JP2018018844A - Magnetic random-access memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a magnetic random-access memory having high radiation resistance.SOLUTION: The magnetic random access memory includes: a magnetoresistance element having a first terminal and a second terminal; and a transistor. The magnetoresistive element and the transistor constitute a memory cell. The second terminal of the magnetoresistive element is connected to a first diffusion layer of the transistor. One of a source electrode and a drain electrode of the transistor is surrounded by a gate electrode.SELECTED DRAWING: Figure 5

Description

  The present invention relates to a magnetic random access memory, and more particularly to radiation resistance of a magnetic random access memory.

  Magnetic random access memory (MRAM) is more resistant to radiation because it stores information in the direction of magnetization compared to SRAM (Static Random Access Memory) and other memories that store information using charges. Expected to be high. However, a deterioration phenomenon due to a TID (Total Ionizing Dose) effect is known for a transistor which is a constituent element of a magnetic random access memory. When radiation enters the oxide film, electron hole pairs are generated. Some of the generated electron hole pairs recombine and disappear. The rest moves through the oxide film. Electrons have higher mobility than holes and are considered to be swept out of the oxide film. The holes are trapped at the defect sites, and positive charges accumulate in the oxide film. The charge accumulated in the gate oxide film of the oxide film of the semiconductor device shifts the threshold voltage of the transistor in the negative direction. On the other hand, the charge accumulated in the field oxide film in the oxide film of the semiconductor device induces a leakage current. As a result, an integrated circuit using a transistor under radiation consumes leakage power due to the TID effect.

  In Patent Document 1, a logic circuit layout technique for improving radiation resistance is proposed. According to Patent Document 1, by using an edgeless transistor, it is possible to reduce the influence of leakage current due to charges accumulated in the field oxide film.

US Pat. No. 6,570,234 JP 2008-47220 A

  However, the magnetic random access memory of the background art has a problem to be solved.

  In the magnetic random access memory, when a leakage current is induced by the TID effect, erroneous reading or erroneous writing may occur. At the time of writing or reading, a read current and a write current are supplied to the selected cell via the bit line. At this time, the leakage current of the transistors of the non-selected cells on the same column increases due to the TID effect. As a result, a desired current cannot be supplied to the selected cell, which may cause a malfunction.

  Hierarchical bit line structure is known to reduce the influence of leakage current of unselected cells on the same column. The hierarchical bit line structure includes a global bit line, a plurality of local bit lines, and transistors that connect the global bit lines and the local bit lines. At the time of writing or reading, the transistor connects the local bit line connected to the selected cell and the global bit line, and supplies a write current or a read current. The hierarchical bit line structure can reduce the leakage current of unselected cells by suppressing the number of cells connected to the local bit line. However, the area overhead of the transistors connecting the global bit lines and the local bit lines and the increase in the number of bit lines arranged on the memory array are problems.

  The technique described in Patent Document 1 is a technique for reducing the leakage current of a logic circuit and is useful. However, from the viewpoint of reducing the leakage current during standby, the magnetic random access memory is not an indispensable technique because the memory cell array can be shut off during standby and the leakage current can be easily eliminated.

  Patent Document 2 proposes a technique for reducing the number of bit lines in a magnetic random access memory and facilitating the manufacturing process. According to Patent Document 2, the bit lines arranged on the memory cell array are shared between adjacent cells, and the bit line voltage is appropriately controlled, thereby reducing the number of bit lines while reducing erroneous writing of unselected cells. It is possible to reduce. The technique described in Patent Document 2 has an effect of alleviating an increase in the number of bit lines when a hierarchical bit line structure is applied. However, a circuit for avoiding erroneous writing of unselected cells is required.

  An object of the present invention is to provide a magnetic random access memory having high radiation resistance.

To achieve the above object, a magnetic random access memory according to the present invention includes a magnetoresistive element having a first terminal and a second terminal, and a transistor.
The magnetoresistive element and the transistor constitute a memory cell,
The second terminal of the magnetoresistive element is connected to the first diffusion layer of the transistor;
One of the source electrode and the drain electrode of the transistor is surrounded by a gate electrode.

  The present invention can provide a magnetic random access memory having high radiation resistance.

(A) is a schematic top view which shows the memory cell array of the transistor layer of a related magnetic random access memory, (b) is sectional drawing along the XX line of (a). It is a schematic diagram which shows the memory cell array of the wiring layer of a related magnetic random access memory. It is a circuit diagram of a related magnetic random access memory. It is a schematic diagram which shows read-out operation | movement of a related magnetic random access memory. It is a schematic diagram showing a memory cell array of a transistor layer of the magnetic random access memory of the first embodiment. (A) is sectional drawing along the AA line of FIG. 5, (b) is sectional drawing along the BB line of FIG. It is a schematic diagram which shows the memory cell array of the wiring layer of the magnetic random access memory of 1st Embodiment. 1 is a circuit diagram of a magnetic random access memory according to a first embodiment. FIG. It is a schematic diagram which shows read-out operation | movement of the magnetic random access memory of 1st Embodiment. It is a schematic diagram which shows the memory cell array of the transistor layer of the magnetic random access memory of 2nd Embodiment. It is a schematic diagram which shows the memory cell array of the wiring layer of the magnetic random access memory of 2nd Embodiment. It is a circuit diagram of the magnetic random access memory of 2nd Embodiment.

  Before describing a preferred embodiment of the present invention, a related magnetic random access memory will be described with reference to the drawings. FIG. 1A is a schematic plan view showing a memory cell array of a transistor layer of a related magnetic random access memory, and FIG. 1B is a cross-sectional view taken along line XX in FIG. The memory cell array is composed of N rows and M columns of memory cells. The memory cell array of FIG. 1A illustrates a case where the memory cell is composed of memory cells C00, C10, C01, C11 of 2 rows and 2 columns. The memory cell array includes an active region where a transistor is formed and an element isolation region that isolates the transistor. Memory cell C00 includes N-type transistors including diffusion layers DIF0, DIF1, and DIF2, a gate electrode 104, and contacts CT0, CT1, and CT2. The gate electrode 104 functions as the word line WL0, and a high voltage is applied when a memory cell is selected. As shown in FIG. 1B, one main surface of the semiconductor substrate 101 is divided into a plurality of active regions by an element isolation region by a field oxide film 103. A gate oxide film 102 is formed on one main surface of the semiconductor substrate 101 in each active region, and a gate electrode 104 is formed on the gate oxide film 102.

  Consider the case where radiation is incident on an oxide film as described in the description of the background art, electron hole pairs are generated, and positive charges are accumulated in the oxide film. At positions E0 and E1 where the boundary between the active region and the element isolation region intersects with the gate electrode 104, a leak current is generated between the diffusion layer DIF0 and the diffusion layer DIF1 due to the charge accumulated in the field oxide film 103. Leakage current between the diffusion layer DIF1 and the diffusion layer DIF2 is generated by charges accumulated in the field oxide film 103 at the positions E2 and E3 where the gate electrode 104 intersects the boundary between the active region and the element isolation region.

  FIG. 2 is a schematic diagram showing a memory cell array of a wiring layer of a related magnetic random access memory. As in FIG. 1A, a memory cell array of 2 rows and 2 columns is shown. The memory cell array includes a first wiring layer 105, a second wiring layer 106, contacts, a magnetoresistive element R, and a bit line pair.

  One of the bit line pairs BLB 0 and BLB 1 is formed in the first wiring layer 105. The other of the bit line pairs BL0 and BL1 is formed in the second wiring layer 106. The magnetoresistive element is formed between the first wiring layer 105 and the second wiring layer 106.

  The bit line pair BL0, BLB0 is connected to the memory cells C00, C10. The bit line pair BL1, BLB1 is connected to the memory cells C01, C11.

  In the memory cell C00, the bit line BLB0 is connected to the diffusion layers DIF0 and DIF2 through contacts. The bit line BL0 is connected to the diffusion layer DIF1 via the magnetoresistive element R and a contact.

  FIG. 3 is a circuit diagram of a related magnetic random access memory. As in FIG. 1A, a memory cell array of 2 rows and 2 columns is shown. The memory cell array includes bit lines BL0, BLB0, BL1, and BLB1, word lines WL0 and WL1, and memory cells C00, C10, C01, and C11. The bit lines BLB0, BLB1, BL0, and BL1 extend in the first direction, and extend in the vertical direction as an example of the first direction. The word lines WL0 and WL1 extend in the second direction, and extend in the horizontal direction as an example of the second direction.

  Bit lines BL0 and BLB0 are connected to memory cells C00 and C10. Bit lines BL1 and BLB1 are connected to memory cells C01 and C11. The word line WL0 is connected to the memory cells C00 and C01. The word line WL1 is connected to the memory cells C10 and C11.

  The memory cell C00 includes a transistor and a magnetoresistive element. One terminal of the magnetoresistive element is connected to one terminal of the source electrode or the drain electrode of the transistor. The other terminal of the magnetoresistive element is connected to the bit line BL0. The other terminal of the source electrode or the drain electrode of the transistor is connected to the bit line BLB0. The gate electrode of the transistor is connected to the word line WL0.

FIG. 4 is a schematic diagram showing a read operation of a related magnetic random access memory. When reading data from the memory cell C00, the high voltage V _HIGH is applied to the word line WL0 to turn on the transistor. A low voltage V _LOW is applied to the word line WL1, and the transistor is turned off. Further, a read voltage V _S is applied to the bit line BL0, and a low voltage V _LOW is applied to the bit lines BLB0, BL1, and BLB1. Read current I _s is via the bit line BL0, flows and the magnetic resistance element R of the memory cell C00 selected, the transistors in the ON state. Read current I _s varies according to the data stored in the selected cell. This is because the resistance value of the magnetoresistive element takes different values depending on the stored data.

Due to the TID effect, a leak current I _leak flows through the non-selected memory cells. The sum of the read current I _s and the leak current I _leak is measured by the sense amplifier determines the data of the magnetoresistive element. Although FIG. 4 shows a case where there is only one non-selected cell, since there are a plurality of non-selected cells on the normal bit line, I _leak becomes a size that cannot be ignored. As a result, the S / N ratio (Signal to Noise ratio) deteriorates, and erroneous reading may occur.

  Similarly, in the write operation of the magnetic random access memory, the write current cannot be sufficiently supplied to the selected cell due to the leakage current of the non-selected cell on the same column as the selected cell, and there is a risk that erroneous writing occurs.

[First Embodiment]
The magnetic random access memory according to the first embodiment will be described. FIG. 5 is a schematic diagram showing a memory cell array of a transistor layer of the magnetic random access memory according to the first embodiment of the present invention. 6A is a cross-sectional view taken along line AA in FIG. 5, and FIG. 6B is a cross-sectional view taken along line BB in FIG. The memory cell array is composed of N rows and M columns of memory cells. The memory cell array of FIG. 5 illustrates a case where the memory cell is composed of memory cells C00, C10, C01 and C11 of 2 rows and 2 columns. The memory cell array includes an active region where a transistor is formed and an element isolation region that isolates the transistor.

  Memory cell C00 includes N-type transistors including diffusion layers DIF0, DIF1, and DIF2, a gate electrode 4, and contacts CT0, CT1, and CT2. One of diffusion layer DIF1 and diffusion layers DIF0 and DIF2 is the source region of the N-type transistor, and the other of diffusion layer DIF1 and diffusion layers DIF0 and DIF2 is the drain region of the N-type transistor. The gate electrode 4 functions as the word line WL0, and a high voltage is applied when a memory cell is selected. As shown in FIGS. 6A and 6B, one main surface of the semiconductor substrate 1 is divided into a plurality of active regions by an element isolation region formed by a field oxide film 3. A gate oxide film 2 is formed on one main surface of the semiconductor substrate 1 in each active region, and a gate electrode 4 is formed on the gate oxide film 2.

  Consider the case where radiation is incident on an oxide film as described in the description of the background art, electron hole pairs are generated, and positive charges are accumulated in the oxide film. Leakage current between the diffusion layer DIF0 and the diffusion layer DIF2 can be generated by charges accumulated in the field oxide film 3 at positions E0 and E1 where the gate electrode 4 intersects with the boundary between the active region and the element isolation region. However, in the present embodiment, the diffusion layer DIF0 and the diffusion layer DIF2 are always given the same potential, so that no leakage current occurs. The diffusion layer DIF1 is surrounded by the gate electrode 4. As shown in FIG. 5, the gate electrode 4 includes a linear portion and an annular portion 4 r, and the diffusion layer DIF <b> 1 is surrounded by the annular portion 4 r of the gate electrode 4. That is, the gate electrode 4 surrounding the diffusion layer DIF1 is isolated from the boundary between the active region and the element isolation region, and is not affected by the charge accumulated in the field oxide film 3. The portion where the gate electrode 4 intersects the boundary between the active region and the element isolation region is a linear portion other than the annular portion 4r.

  FIG. 7 is a schematic diagram showing a memory cell array in the wiring layer of the magnetic random access memory according to the first embodiment of the present invention. Similar to FIG. 5, a memory cell array of 2 rows and 2 columns is shown as an example of the memory cell array. The memory cell array includes a first wiring layer 5, a second wiring layer 6, a contact, a magnetoresistive element R, and a bit line pair.

  One of the bit line pairs BLB 0 and BLB 1 is formed in the first wiring layer 5. The other of the bit line pairs BL0 and BL1 is formed in the second wiring layer 6. The magnetoresistive element R is formed between the first wiring layer 5 and the second wiring layer 6.

  The bit line pair BL0, BLB0 is connected to the memory cells C00, C10. The bit line pair BL1, BLB1 is connected to the memory cells C01, C11.

  In the memory cell C00, the bit line BLB0 is connected to the diffusion layers DIF0 and DIF2 through contacts. The bit line BL0 is connected to the diffusion layer DIF1 through the magnetoresistive element R, the first wiring layer 5a, and the contact.

  FIG. 8 is a circuit diagram of the magnetic random access memory according to the first embodiment. Similar to FIG. 5, a memory cell array of 2 rows and 2 columns is shown as an example of the memory cell array. The memory cell array includes bit lines BL0, BLB0, BL1, and BLB1, word lines WL0 and WL1, and memory cells C00, C10, C01, and C11.

  Bit lines BL0 and BLB0 are connected to memory cells C00 and C10. Bit line BL1 and bit line BLB1 are connected to memory cells C01 and C11. The word line WL0 is connected to the memory cells C00 and C01. The word line WL1 is connected to the memory cells C10 and C11.

  The memory cell C00 includes two transistors and a magnetoresistive element R. One terminal of the magnetoresistive element R is connected to one terminal of the source electrode or the drain electrode of the transistor. The other terminal of the magnetoresistive element R is connected to the bit line BL0. The other terminal of the source electrode or the drain electrode of the transistor is connected to the bit line BLB0. The gate electrode of the transistor is connected to the word line WL0.

(Operation)
FIG. 9 is a schematic diagram showing a read operation of the magnetic random access memory according to the first embodiment. When reading data from the memory cell C00, the high voltage V _HIGH is applied to the word line WL0 to turn on the transistor. A low voltage V _LOW is applied to the word line WL1, and the transistor is turned off. Further, a read voltage V _S is applied to the bit line BL0, and a low voltage V _LOW is applied to the bit lines BLB0, BL1, and BLB1. Read current I _s is via the bit line BL0, flows and the magnetic resistance element R of the memory cell C00 selected, the transistors in the ON state. Read current I _s varies according to the data stored in the selected cell. This is because the resistance value of the magnetoresistive element takes different values depending on the stored data.

(effect)
The magnetic random access memory according to the first embodiment is made paying attention to a malfunction caused by a leakage current during operation, and can reduce a leakage current I _leak flowing in a non-selected memory cell. The sum of the read current I _s and the leak current I _leak is measured by the sense amplifier determines the data of the magnetoresistive element. Since the influence of the TID effect can be reduced, the S / N ratio of the sense amplifier is improved and the possibility of erroneous reading is reduced.

  According to this embodiment, the write current of the magnetic random access memory can similarly reduce the leakage current to the non-selected cell on the same column as the selected cell. As a result, a sufficient write current can be supplied to the selected cell, and the possibility of erroneous writing can be reduced.

  Therefore, the magnetic random access memory of this embodiment can provide high radiation resistance.

[Second Embodiment]
A magnetic random access memory according to the second embodiment will be described. FIG. 10 is a schematic diagram showing a memory cell array of a transistor layer of the magnetic random access memory according to the second embodiment of the present invention. The memory cell array is composed of N rows and M columns of memory cells. The memory cell array of FIG. 10 illustrates a case where the memory cell array is composed of memory cells C00, C10, C01, and C11 in one row and four columns. The memory cell array includes an active region where a transistor is formed and an element isolation region that isolates the transistor.

  Memory cell C00 includes N-type transistors including diffusion layers DIF0, DIF1, and DIF2, a gate electrode 14, and contacts CT0, CT1, and CT2. One of diffusion layer DIF1 and diffusion layers DIF0 and DIF2 is the source region of the N-type transistor, and the other of diffusion layer DIF1 and diffusion layers DIF0 and DIF2 is the drain region of the N-type transistor. The gate electrode 14 functions as the word line WL0, and a high voltage is applied when a memory cell is selected.

  Consider the case where radiation is incident on an oxide film as described in the description of the background art, electron hole pairs are generated, and positive charges are accumulated in the oxide film. At the position E0 where the gate electrode 14 intersects the boundary between the active region and the element isolation region, a leakage current between the diffusion layer DIF0 and the diffusion layer DIF2 can be generated due to the charge accumulated in the field oxide film. However, in the present embodiment, the diffusion layer DIF0 and the diffusion layer DIF2 are always given the same potential, so that no leakage current occurs. The diffusion layer DIF1 is surrounded by the gate electrode. The gate electrode 14 includes an annular portion 14r, and the diffusion layer DIF1 is surrounded by the annular portion 14r of the gate electrode 14. As shown in FIG. 10, the gate electrode 14 includes a linear portion and an annular portion 14 r, and the diffusion layer DIF <b> 1 is surrounded by the annular portion 14 r of the gate electrode 14. That is, the gate electrode 14 surrounding the diffusion layer DIF1 is isolated from the boundary between the active region and the element isolation region, and is not affected by the charge accumulated in the field oxide film. The portion where the gate electrode 14 intersects the boundary between the active region and the element isolation region is a linear portion other than the annular portion 14r.

  Furthermore, the memory cell C00 and the memory cell C10 are arranged adjacent to each other in the word line direction, which is the direction in which the word line extends. Memory cell C00 and memory cell C10 share diffusion layer DIF2. The layout of the gate electrode and diffusion layer of the memory cell C10 is an arrangement obtained by rotating the layout of the gate electrode and diffusion layer of the memory cell C00 by approximately 180 degrees.

  FIG. 11 is a schematic diagram showing a memory cell array in the wiring layer of the magnetic random access memory according to the second embodiment of the present invention. Similar to FIG. 10, a memory cell array of 1 row and 4 columns is shown as an example of the memory cell array. The memory cell array includes a first wiring layer 15, a second wiring layer 16, a contact, a magnetoresistive element R, and a bit line pair.

  Bit lines BLB 0 and BLB 1 of the bit line pair are formed in the first wiring layer 15. Bit lines BL0_L, BL0_R, BL1_L, and BL1_R of the bit line pairs are formed in the second wiring layer 16. The magnetoresistive element R is formed between the first wiring layer 15 and the second wiring layer 16.

  The bit lines BLB0 and BLB1 of the bit line pair are shared between adjacent cells. That is, the bit line BLB0 is shared by the memory cell C00 and the memory cell C10. The bit line BLB1 is shared by the memory cell C01 and the memory cell C11.

  The bit line BL0_R is connected to the memory cell C00. The bit line BL0_L is connected to the memory cell C10. The bit line BL1_R is connected to the memory cell C01. The bit line BL1_L is connected to the memory cell C11.

  In the memory cell C00, the bit line BLB0 is connected to the diffusion layers DIF0 and DIF2 through contacts. The bit line BL0_R is connected to the diffusion layer DIF1 through a contact with the magnetoresistive element R.

  FIG. 12 is a circuit diagram of the magnetic random access memory according to the second embodiment. Similar to FIG. 10, a memory cell array of 1 row and 4 columns is shown as an example of the memory cell array. The memory cell array includes bit lines BL0_R, BL0_L, BLB0, BL1_R, BL1_L, BLB1, word lines WL0, WL1, and memory cells C00, C10, C01, C11. The bit lines BLB0, BL0_L, BL0_R, BLB1, BL1_L, and BL1_R extend in the first direction, and extend in the vertical direction as an example of the first direction. The word lines WL0 and WL1 extend in the second direction, and extend in the horizontal direction as an example of the second direction.

  The bit lines BL0_R and BLB0 are connected to the memory cell C00. The bit lines BL0_L and BLB0 are connected to the memory cell C10. The bit lines BL1_R and BLB1 are connected to the memory cell C01. The bit lines BL1_L and BLB1 are connected to the memory cell C11. The word line WL0 is connected to the memory cells C00 and C01. The word line WL1 is connected to the memory cells C10 and C11.

  The memory cell C00 includes two transistors and a magnetoresistive element R. One terminal of the magnetoresistive element R is connected to one terminal of the source electrode or the drain electrode of the transistor. The other terminal of the magnetoresistive element R is connected to the bit line BL0_R. The other terminal of the source electrode or the drain electrode of the transistor is connected to the bit line BLB0. The gate electrode of the transistor is connected to the word line WL0.

(Operation)
When reading data from the memory cell C00 in FIG. 12, a high voltage V _HIGH is applied to the word line WL0 to turn on the transistor. A low voltage V _LOW is applied to the word line WL1, and the transistor is turned off. Further, the read voltage _{V S} is applied to the bit line BL0_R, the bit line BLB0, BL0_L, BLB1, BL1_L, a low voltage is applied _{V LOW} to BL1_R. Read current _{I s} is via the bit line BL0_R, flows and the magnetic resistance element R of the memory cell C00 selected, the transistors in the ON state. Read current I _s varies according to the data stored in the selected cell. This is because the resistance value of the magnetoresistive element takes different values depending on the stored data.

(effect)
In the magnetic random access memory according to the present embodiment, the leakage current I _leak flowing through the non-selected memory cells can be reduced as in the first embodiment. The sum of the read current I _s and the leak current I _leak is measured by the sense amplifier determines the data of the magnetoresistive element. Since the influence of the TID effect can be reduced, the S / N ratio of the sense amplifier is improved and the possibility of erroneous reading is reduced.

  According to this embodiment, the write current of the magnetic random access memory can similarly reduce the leakage current to the non-selected cell on the same column as the selected cell. As a result, a sufficient write current can be supplied to the selected cell, and the possibility of erroneous writing can be reduced. Therefore, the magnetic random access memory according to the present embodiment can realize high radiation resistance.

  Furthermore, since the magnetic random access memory of this embodiment shares bit lines between adjacent columns, the number of bit lines can be reduced. In the present embodiment, the number of bit lines of the related magnetic random memory is reduced from 2 / column to 3/2 columns = 1.5 / column. Furthermore, the magnetic random access memory according to the present embodiment does not require a circuit for avoiding erroneous writing of unselected cells described in Patent Document 2.

  Therefore, according to this embodiment, it is possible to provide a magnetic random access memory that has high radiation resistance, reduces the number of bit lines, and facilitates the manufacturing process.

  As mentioned above, although preferable embodiment of this invention was described, this invention is not limited to this. It goes without saying that various modifications are possible within the scope of the invention described in the claims, and these are also included in the scope of the present invention.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Gate oxide film 3 Field oxide film 4, 14 Gate electrode 5, 15 1st wiring layer 6, 16 2nd wiring layer

Claims (5)

A magnetoresistive element having a first terminal and a second terminal;
A transistor,
The magnetoresistive element and the transistor constitute a memory cell,
The second terminal of the magnetoresistive element is connected to a first diffusion layer of the transistor;
A magnetic random access memory in which one of a source electrode or a drain electrode of the transistor is surrounded by a gate electrode. The gate electrode includes an annular portion;
The magnetic random access memory according to claim 1, wherein the one of the source electrode and the drain electrode of the transistor is surrounded by the annular portion of the gate electrode. A first memory cell;
A second memory cell;
A plurality of bit line pairs extending in a first direction;
A plurality of word lines extending in a second direction,
The first memory cell and the second memory cell share at least one bit line;
3. The magnetic random access memory according to claim 1, wherein the first memory cell and the second memory cell are arranged along the second direction. 4.   The magnetic random access memory according to claim 3, wherein the first memory cell and the second memory cell share a diffusion layer region.   The magnetic layer according to claim 3 or 4, wherein a layout of the diffusion layer and the gate electrode of the second memory cell is an arrangement obtained by rotating the layout of the diffusion layer and the gate electrode of the first memory cell approximately 180 times. Random access memory.

Images