JP2018011141A - Solid-state imaging device, driving method of solid-state imaging device, and electronic apparatus - Google Patents

Abstract

An object of the present invention is to reduce the accumulation time (exposure time) when reading out charges a plurality of times during one imaging frame, compared to the case where each of a plurality of pixel signals is sequentially converted from analog to digital. A solid-state imaging device according to an embodiment of the present disclosure includes a pixel array unit in which pixels including a photoelectric conversion unit are arranged, a driving unit that reads charges from the photoelectric conversion unit a plurality of times in one imaging frame, and a plurality of times An analog-to-digital conversion unit that performs analog-to-digital conversion on each of the plurality of pixel signals based on reading out the electric charges in parallel. [Selection] Figure 1

Description

  The present disclosure relates to a solid-state imaging device, a driving method of the solid-state imaging device, and an electronic apparatus.

  In the solid-state imaging device, a pixel signal that is substantially linear with respect to the amount of charge accumulated in the photoelectric conversion unit by photoelectric conversion is output from the pixel including the photoelectric conversion unit. The dynamic range of the solid-state imaging device is uniquely determined by the charge amount (saturation charge amount) that can be accumulated in the photoelectric conversion unit and the noise level.

  However, since the amount of charge stored in the photoelectric conversion unit is limited, the signal charge generated after being saturated cannot be stored. For this reason, for example, when photographing at high illuminance, if the amount of charge stored in the photoelectric conversion unit is exceeded, the amount of charge exceeding that amount is not reflected in the pixel signal, so the accumulation time (exposure) The linearity of the pixel signal with respect to time) cannot be ensured.

  The solution is to read out the charge from the photoelectric conversion unit multiple times during one imaging frame, and add a plurality of pixel signals based on the multiple times of readout of the charge to simulate the saturation signal of the photoelectric conversion unit. A technique for increasing the amount has been employed (see, for example, Patent Document 1).

JP2015-109503A

  In the prior art described in Patent Document 1, analog-to-digital conversion is sequentially performed by one analog-to-digital conversion unit with respect to a plurality of pixel signals obtained in time series by reading out charges a plurality of times. Therefore, the accumulation time (exposure time) cannot be made shorter than the time required for analog-to-digital conversion of all the plurality of pixel signals, that is, the analog-to-digital conversion period for one imaging frame.

  In view of this, the present disclosure provides a solid-state imaging device capable of shortening the accumulation time (exposure time), compared with the case of performing analog-digital conversion for each of a plurality of pixel signals in order to read out charges a plurality of times during one imaging frame, It is an object of the present invention to provide a method for driving a solid-state imaging device and an electronic apparatus.

In order to achieve the above object, a solid-state imaging device of the present disclosure includes:
A pixel array unit in which pixels including a photoelectric conversion unit are arranged;
A drive unit that reads out charges from the photoelectric conversion unit a plurality of times during one imaging frame; and
An analog-to-digital conversion unit that performs analog-to-digital conversion on each of a plurality of pixel signals based on a plurality of times of charge readout;
Is provided. In addition, an electronic apparatus according to the present disclosure for achieving the above object includes the solid-state imaging device having the above configuration.

In order to achieve the above object, a method for driving a solid-state imaging device according to the present disclosure includes:
In driving a solid-state imaging device in which pixels including a photoelectric conversion unit are arranged,
Read out the charge multiple times from the photoelectric converter during one imaging frame,
Each of a plurality of pixel signals based on a plurality of charge readouts is analog-to-digital converted in parallel.

  According to the present disclosure, each of a plurality of pixel signals based on a plurality of charge readouts is analog-to-digital converted in parallel, thereby storing each of the plurality of pixel signals sequentially than analog-to-digital conversion. Time (exposure time) can be shortened.

  The effects described here are not necessarily limited, and any of the effects described in the present specification may be used. Moreover, the effect described in this specification is an illustration to the last, Comprising: It is not limited to this, There may be an additional effect.

FIG. 1 is a system configuration diagram illustrating an outline of a system configuration of the solid-state imaging device according to the first embodiment of the present disclosure. FIG. 2 is a wiring diagram showing a connection relationship between one pixel column and two parallel AD converters. FIG. 3 is a block diagram showing an example of the configuration of a single slope type analog-digital converter. FIG. 4 is a timing waveform diagram for explaining an operation involving correlated double sampling processing of a single slope AD converter. FIG. 5 is a circuit diagram illustrating an example of a circuit configuration of a pixel in the solid-state imaging device according to the first embodiment. FIG. 6 is a diagram schematically illustrating a shutter operation, a read operation, a charge accumulation state, and an addition process in the case where charge is read twice from the photodiode PD in one imaging frame. FIG. 7 is a diagram schematically illustrating a shutter operation, a read operation, and a charge accumulation state in the case where charge is read once from the photodiode PD in one imaging frame. FIG. 8 shows the relationship between the shutter timing and the readout timing for each exposure time with respect to the brightness of the photographing environment when the charge is read once from the photodiode PD and when the charge is read twice during one imaging frame. It is a figure which shows an example. FIG. 9A, FIG. 9B, and FIG. 9C are timing waveform diagrams for explaining a specific circuit operation of the pixel when the charge is read twice. FIG. 10 is a diagram schematically illustrating a shutter operation, a read operation, a charge accumulation state, and an addition process in the case where charge is read out from the photodiode PD three times during one imaging frame. FIG. 11 is a wiring diagram showing a connection relationship between one pixel column and four parallel AD converters when reading out charges from the photodiode PD four times during one imaging frame. FIG. 12 is a circuit diagram illustrating an example of a pixel circuit configuration in the case of a 4-parallel configuration. FIG. 13 is a diagram schematically illustrating a shutter operation, a read operation, a charge accumulation state, and an addition process when an addition process is performed by a signal processing unit outside the semiconductor substrate. FIG. 14A, FIG. 14B, and FIG. 14C are diagrams for explaining the relationship between the charge read timing and the analog gain. FIG. 15A, FIG. 15B, and FIG. 15C are diagrams for explaining the relationship among the analog gain, dynamic range, and charge read timing. FIG. 16 is a circuit diagram illustrating an example of a circuit configuration of a pixel in the solid-state imaging device according to the second embodiment. 17A, 17B, and 17C are diagrams illustrating examples of arrangement of a plurality of photoelectric conversion units included in a pixel. 18A and 18B are explanatory diagrams of the conventional method 1 having a pixel structure having a plurality of photoelectric conversion units. 19A and 19B are explanatory diagrams of the conventional method 2 having a pixel structure having a plurality of photoelectric conversion units. 20A and 20B, in the pixel structure having a plurality of photoelectric conversion unit is an explanatory view of the method for reading from photodiodes PD _1, PD ₂ twice charge in one image pick-up frame. FIG. 21 is an exploded perspective view showing an outline of a configuration of a solid-state imaging device having a laminated structure. FIG. 22 is a block diagram illustrating a configuration of an imaging apparatus that is an example of the electronic apparatus of the present disclosure.

Hereinafter, modes for carrying out the technology of the present disclosure (hereinafter referred to as “embodiments”) will be described in detail with reference to the drawings. The technology of the present disclosure is not limited to the embodiments, and various numerical values in the embodiments are examples. In the following description, the same reference numerals are used for the same elements or elements having the same function, and redundant description is omitted. The description will be given in the following order.
1. 1. General description of the solid-state imaging device of the present disclosure, a driving method thereof, and an electronic apparatus First embodiment (an example in which one pixel has one photoelectric conversion unit)
2-1. System configuration 2-2. Single slope type analog-digital converter 2-3. Circuit configuration of pixel 2-4. 2. Circuit operation of the pixel Second Embodiment (Example in which one pixel has a plurality of photoelectric conversion units)
4). Modification 5 5. Electronic device of the present disclosure Configurations that can be taken by the present disclosure

<Description of Solid-State Imaging Device of the Present Disclosure, Method for Driving the Same, and Electronic Device>
In the solid-state imaging device, the driving method of the solid-state imaging device, and the electronic apparatus of the present disclosure, light shot noise is a main cause of noise at high illuminance, and in order to improve this, it is important to capture a large amount of light. It is effective to read out charges from the photoelectric conversion unit a plurality of times during one imaging frame. That is, by adding a plurality of pixel signals based on a plurality of charge readouts, it is possible to artificially increase the saturation signal amount of the photoelectric conversion unit.

  Then, by performing analog-digital conversion on each of the plurality of pixel signals in parallel, the intended purpose, that is, shortening of the accumulation time (exposure time) can be realized. Here, “in parallel” means a case where processing is performed in parallel at the same time, and a case where processing is performed in parallel with a time lag. In the case of the former process, the entire time for processing in parallel will overlap, and in the case of the latter process, a part of the time for processing in parallel will overlap.

  In the solid-state imaging device of the present disclosure including the preferable configuration described above, the driving method thereof, and the electronic device, the pixel may have a plurality of selection transistors corresponding to a plurality of pixel signals. At this time, for a plurality of selection transistors, a plurality of pixel signals can be selected in parallel and supplied to the analog-digital conversion unit through corresponding vertical signal lines.

  Furthermore, in the solid-state imaging device of the present disclosure including the above-described preferable configuration, the driving method thereof, and the electronic apparatus, the first signal that transmits the pixel signal in the first direction for each pixel column with respect to the vertical signal line. A signal line group and a second signal line group that transmits pixel signals in a second direction opposite to the first direction for each pixel column can be employed. The analog-digital conversion unit is provided for each pixel column, and is provided for each pixel column and a set of analog-digital converters that perform analog-digital conversion on pixel signals transmitted by the first signal line group. The pixel signal transmitted by the second signal line group can be constituted by a set of analog-digital converters that perform analog-digital conversion.

  Furthermore, in the solid-state imaging device of the present disclosure including the above-described preferable configuration, the driving method thereof, and the electronic apparatus, a reference voltage generation unit that generates a reference voltage having an inclined waveform for the analog-digital converter, It can be set as the structure which has a comparator and a count part. The comparator compares the pixel signal supplied from the pixel through the vertical signal line with the reference voltage having an inclined waveform, and outputs a pulse signal having a pulse width corresponding to the level of the pixel signal. The count unit performs a count operation in synchronization with a predetermined clock in a comparison period from the start to the end of the comparison operation of the comparator. And let the count value of a count part be the digital value after analog-digital conversion.

  Furthermore, in the solid-state imaging device of the present disclosure including the above-described preferable configuration, the driving method thereof, and the electronic apparatus, a plurality of pixel signals based on a plurality of times of charge readout are selected according to the user's selection. It is possible to set a configuration in which a mode for reading out in time series through the selection transistors and a mode for reading out simultaneously through a plurality of selection transistors can be set.

  Further, in the solid-state imaging device of the present disclosure including the above-described preferred configuration, the driving method thereof, and the electronic apparatus, a plurality of digital data output from the analog-digital conversion unit is obtained based on the plurality of pixel signals. It can be set as the structure provided with the memory part to memorize | store. The plurality of digital data is preferably added in the memory unit.

  Moreover, in the solid-state imaging device of the present disclosure including the preferable configuration described above, the driving method thereof, and the electronic apparatus, a configuration in which a plurality of photoelectric conversion units are included in one pixel can be employed. The plurality of photoelectric conversion units are preferably used for phase difference detection in which the distance from the subject is measured using the phase difference of the subject image.

  Alternatively, in the solid-state imaging device of the present disclosure including the above-described preferable configuration, the driving method thereof, and the electronic apparatus, the pixel array unit and the analog-digital conversion unit are respectively stacked on different semiconductor substrates. It can be set as the structure mounted in.

<First Embodiment>
1st Embodiment of this indication is an example in case one pixel has one photoelectric conversion part. FIG. 1 shows a system configuration diagram of the solid-state imaging device according to the first embodiment. In the first embodiment, as the solid-state imaging device, for example, a CMOS image sensor which is a kind of XY address type solid-state imaging device is illustrated.

[System configuration]
The solid-state imaging device 10 according to the first embodiment includes a pixel array unit 12 formed on a semiconductor substrate (semiconductor chip) 11 and a peripheral circuit unit integrated on the same semiconductor substrate 11 as the pixel array unit 12. It is the composition which has. The peripheral circuit unit includes a vertical drive unit 13, analog-digital conversion (hereinafter referred to as “AD conversion”) units 14 and 15, column processing units 16 and 17, a memory unit 18, a system control unit 19 and the like. Has been.

  The pixel array unit 12 performs photoelectric conversion so that the pixels 20 including the photoelectric conversion unit that generates and accumulates photoelectric charges according to the received light amount are two-dimensionally arranged in the row direction and the column direction, that is, in a matrix form. It has been configured. Here, the row direction refers to the arrangement direction of pixels in the pixel row (that is, the horizontal direction), and the column direction refers to the arrangement direction of pixels in the pixel column (that is, the vertical direction). Details of the specific circuit configuration and pixel structure of the pixel 20 will be described later.

  In the pixel array unit 12, pixel drive lines (not shown) are wired in the row direction for each pixel row with respect to the matrix-like pixel arrangement, and, for example, two vertical signal lines 31 and 32 are provided for each pixel column. Are wired along the column direction. The pixel drive line transmits a drive signal, which will be described later, for performing drive when reading a signal from the pixel 20. One end of the pixel drive line is connected to an output end corresponding to each row of the vertical drive unit 13.

  The vertical drive unit 13 is configured by a shift register, an address decoder, and the like, and drives each pixel 20 of the pixel array unit 12 at the same time or in units of rows. That is, the vertical drive unit 13 constitutes a drive unit that drives each pixel 20 of the pixel array unit 12 together with the system control unit 19 that controls the vertical drive unit 13. Although the vertical drive unit 13 is not shown in detail with respect to its specific configuration, the vertical drive unit 13 generally has two scanning systems, a reading scanning system and a sweeping scanning system.

  In order to read out signals from the pixels 20, the readout scanning system selectively scans the pixels 20 in the pixel array unit 12 in units of rows. A signal read from the pixel 20 is an analog signal. The sweep-out scanning system performs sweep-out scanning on the readout line on which readout scanning is performed by the readout scanning system prior to the readout scanning by the time corresponding to the shutter speed.

  By the sweep scanning by the sweep scanning system, unnecessary charges are swept out from the photoelectric conversion unit of the pixel 20 in the readout row, thereby resetting the photoelectric conversion unit. A so-called electronic shutter operation is performed by sweeping (resetting) unnecessary charges by the sweep scanning system. Here, the electronic shutter operation refers to an operation in which the photoelectric charge of the photoelectric conversion unit is discarded and exposure is newly started (photocharge accumulation is started).

  The signal read by the read operation by the read scanning system corresponds to the amount of light received after the immediately preceding read operation or electronic shutter operation. The period from the read timing by the previous read operation or the sweep timing by the electronic shutter operation to the read timing by the current read operation is the exposure period of the photocharge in the unit pixel.

  Pixel signals output from each pixel 20 in the pixel row selected by the vertical drive unit 13 are input to the AD conversion units 14 and 15 through the two systems of vertical signal lines 31 and 32. Here, the vertical signal line 31 of one system transmits the pixel signal output from each pixel 20 of the selected row in the first direction (one side in the pixel column direction / upward direction in the figure) for each pixel column. Signal line group (first signal line group). The vertical signal line 32 of the other system directs the pixel signal output from each pixel 20 in the selected row in a second direction opposite to the first direction (the other side in the pixel column direction / downward in the figure). It consists of a signal line group (second signal line group) for transmission.

  Each of the AD conversion units 14 and 15 includes a set (AD converter group) of AD converters 141 and 151 provided for each pixel column, and is provided with the pixel array unit 12 interposed therebetween in the pixel column direction. A pixel signal transmitted through the vertical signal lines 31 and 32 of the system is AD converted. That is, the AD conversion unit 14 includes a set of AD converters 141 that are transmitted in the first direction by the vertical signal line 31 for each pixel column and perform AD conversion on input pixel signals. The AD conversion unit 15 includes a set of AD converters 151 that are transmitted in the second direction by the vertical signal line 32 for each pixel column and perform AD conversion on input pixel signals.

  Pixel data (digital data) after AD conversion by the AD conversion units 14 and 15 is supplied to the memory unit 18 via the column processing units 16 and 17. The memory unit 18 temporarily stores pixel data that has passed through the column processing unit 16 and pixel data that has passed through the column processing unit 17. Further, the memory unit 18 also performs a process of adding the pixel data that has passed through the column processing unit 16 and the pixel data that has passed through the column processing unit 17.

  The system control unit 19 includes a timing generator that generates various timing signals, and based on the various timings generated by the timing generator, the vertical drive unit 13, the AD conversion units 14 and 15, and column processing Drive control of the units 16 and 17 is performed. The system control unit 19 further performs switching control of the operation mode of the vertical drive unit 13 in accordance with a mode selection signal input from the outside under the operation of the user.

  The pixel data read from the memory unit 18 is output through the interface 52 after predetermined signal processing is performed by the signal processing unit 51 provided outside the semiconductor substrate 11. In the signal processing unit 51, for example, processing for obtaining the sum and average of pixel data in one imaging frame is performed.

  FIG. 2 shows a connection relationship between one pixel column and AD converters 141 and 151 having two parallel configurations. One end of the vertical signal line 31 is connected to an AD converter 141 and a current source 41 of one system. Then, the pixel signal output from the pixel 20 is transmitted in the first direction (upward in the figure) by the vertical signal line 31 and input to the AD converter 141. Further, the AD converter 151 and the current source 42 of the other system are connected to one end of the vertical signal line 32. The pixel signal output from the pixel 20 is transmitted in the second direction (downward in the figure) by the vertical signal line 32 and input to the AD converter 151.

  As the AD converters 141 and 151, known AD converters can be used. As a known AD converter, a single slope AD converter, a successive approximation AD converter, or a delta-sigma modulation (ΔΣ modulation) AD converter can be exemplified. However, the AD converters 141 and 151 are not limited to these. In the present embodiment, single slope AD converters are used as the AD converters 141 and 151.

[About single slope AD converter]
An example of the configuration of the single slope AD converter is shown in FIG. Here, the AD converter 141 will be described as a single slope AD converter 141, but the AD converter 151 is the same as the AD converter 141.

The single slope AD converter 141 includes a reference voltage generation unit 1411. The reference voltage generation unit 1411 generates a so-called ramp (RAMP) waveform reference voltage V _ref , which is a ramp waveform whose voltage value changes stepwise as time passes, as a reference signal used for AD conversion. . The reference voltage generation unit 1411 can be configured using, for example, a DAC (digital-analog conversion) circuit. The reference voltage generation unit 1411 is not limited to a configuration using a DAC circuit.

In addition to the reference voltage generation unit 1411, the single slope AD converter 141 includes a comparator (comparator) 1412 and a count unit, for example, an up / down counter (in the figure, “U / D CNT” is described. 1413). The comparator 1412 receives the signal voltage _Vout of the vertical signal line 31 corresponding to the pixel signal output from the pixel 20 as a comparison input, and the reference voltage of the ramp wave (gradient waveform) generated by the reference voltage generation unit 1411. _Vref is used as a reference input, and both are compared.

Then, the comparator 1412 may, for example, the output V _co when the reference voltage V _ref is greater than the signal voltage V _out is the first state (e.g., high level) becomes the reference voltage V _ref is less signal voltage V _out At this time, the output V _co is in the second state (for example, low level). Thereby, the output signal of the comparator 1412 becomes a pulse signal having a pulse width corresponding to the level of the pixel signal.

The up / down counter 1413 is given a predetermined clock CK at the same timing as the supply start timing of the reference voltage V _ref to the comparator 1412 under the control of the system control unit 19. The up / down counter 1413 counts down (DOWN) or counts up (UP) in synchronization with a predetermined clock CK, so that the period of the pulse width of the output pulse of the comparator 1412, that is, the comparator 1412. A comparison period from the start of the comparison operation to the end of the comparison operation is measured. The count result (count value) of the up / down counter 1413 becomes a digital value obtained by digitizing an analog pixel signal.

In the solid-state imaging device 10, generally, noise removal processing by correlated double sampling (CDS) is performed in order to remove noise during the reset operation of the pixels 20. For example, the reset level V _rst and the signal level V _sig are read from the pixel 20 in this order. The reset level V _rst corresponds to the potential of the floating diffusion FD when the floating diffusion FD (see FIG. 5) of the pixel 20 is reset. The signal level V _sig corresponds to the potential of the floating diffusion FD when the charge accumulated in the photodiode PD is transferred to the floating diffusion FD.

In the readout method in which the reset level V _rst is read first, random noise generated when resetting is held in the floating diffusion FD. _Therefore , the signal level V _sig read by adding a signal charge includes a reset level. The same amount of noise as V _rst is retained. For this reason, it is possible to obtain a signal from which these noises are removed by performing a correlated double sampling operation in which the reset level V _rst is subtracted from the signal level V _sig .

This correlated double sampling processing can be performed in parallel at the time of AD conversion in the single slope AD converter 141. Specifically, in the single slope AD converter 141, the up / down counter 1413 is, for example, a reset level during the measurement operation in the comparison period from the start of the comparison operation in the comparator 1412 to the end of the comparison operation. A down-count is performed for V _rst and an up-count is performed for the signal level V _sig . By this down count / up count operation, the difference between the signal level V _sig and the reset level V _rst can be obtained. As a result, noise removal processing by correlated double sampling can be performed during AD conversion by the AD converter 1412. FIG. 4 is a timing waveform diagram for explaining the operation of the single slope AD converter 141 with correlated double sampling processing.

[Pixel circuit configuration]
An example of the circuit configuration of the pixel 20 in the solid-state imaging device 10 according to the first embodiment is shown in FIG. The pixel 20 includes a photodiode PD as a photoelectric conversion unit. The pixel 20 includes a transfer transistor 21, a reset transistor 22, an amplification transistor 23, and, for example, two selection transistors 24 ₁ and 24 ₂ in addition to the photodiode PD.

In this example, for example, N-type MOSFETs are used as the transfer transistor 21, the reset transistor 22, the amplification transistor 23, and the selection transistor 24 (24 ₁ , 24 ₂ ). However, the combination of the conductivity types of the transistors 21 to 24 illustrated here is only an example, and the combination of these conductivity types is not limited.

  The photodiode PD has an anode electrode connected to a low-potential-side power source (for example, ground), and photoelectrically converts received light into photocharge (here, photoelectrons) having a charge amount corresponding to the amount of light. Accumulate charge. The cathode electrode of the photodiode PD is electrically connected to the gate electrode of the amplification transistor 23 through the transfer transistor 21. Here, the region where the gate electrode of the amplification transistor 23 is electrically connected is a floating diffusion (floating diffusion region / impurity diffusion region) FD. The floating diffusion FD is a charge-voltage conversion unit that converts charge into voltage.

A transfer signal TRG that activates a high level (for example, V _DD level) is supplied from the vertical drive unit 13 to the gate electrode of the transfer transistor 21. When the transfer transistor 21 becomes conductive in response to the transfer signal TRG, it is photoelectrically converted by the photodiode PD and transfers the photoelectric charge accumulated in the photodiode PD to the floating diffusion FD.

The reset transistor 22 is connected between the high potential side power source V _DD and the floating diffusion FD. A reset signal RST that activates a high level is supplied from the vertical drive unit 13 to the gate electrode of the reset transistor 22. The reset transistor 22 becomes conductive in response to the reset signal RST, thereby discarding the charge of the floating diffusion FD to the node of the power supply V _DD . Thereby, a reset operation for resetting the floating diffusion FD is performed.

The amplification transistor 23 has a gate electrode connected to the floating diffusion FD and a drain electrode connected to the high potential side power source _VDD . The amplification transistor 23 serves as an input part of a source follower that reads out a pixel signal obtained by converting the electric charge photoelectrically converted by the photodiode PD into a voltage by the floating diffusion FD. That is, the source electrode of the amplification transistor 23 is connected to the vertical signal lines 31 and 32 via the selection transistors 24 ₁ and 24 ₂ . The amplification transistor 23 and the current sources 41 and 42 connected to the respective one ends of the vertical signal lines 31 and 32 constitute a source follower that converts the voltage of the floating diffusion FD into the potential of the vertical signal lines 31 and 32. doing.

In the selection transistor 24 ₁ , for example, the drain electrode is connected to the source electrode of the amplification transistor 23, and the source electrode is connected to the vertical signal line 31. A selection signal SEL1 that activates a high level is supplied from the vertical drive unit 13 to the gate electrode of the selection transistor 24 ₁ . The selection transistor 24 ₁ is turned on in response to the selection signal SEL 1, thereby transmitting the pixel signal output from the amplification transistor 23 to the vertical signal line 31 with the pixel 20 selected.

In the selection transistor 24 ₂ , for example, the drain electrode is connected to the source electrode of the amplification transistor 23, and the source electrode is connected to the vertical signal line 32. A selection signal SEL < _b > 2 whose high level is active is supplied from the vertical drive unit 13 to the gate electrode of the selection transistor 242. The selection transistor 24 ₂ is turned on in response to the selection signal SEL 2, thereby transmitting the pixel signal output from the amplification transistor 23 to the vertical signal line 32 with the pixel 20 selected.

  The solid-state imaging device 10 according to the first embodiment having the above configuration reads out charges from the photodiode PD a plurality of times during one imaging frame, and adds a plurality of pixel signals based on the plurality of times of reading out the charges. It is characterized by. Since the amount of saturation signal of the photodiode PD can be increased in a pseudo manner by reading out the charges a plurality of times, the dynamic range can be expanded. In addition, at high illuminance, light shot noise can be improved by capturing a large amount of light.

  The solid-state imaging device 10 according to the first embodiment is further characterized in that each of a plurality of pixel signals based on a plurality of charge readouts is AD-converted in parallel. With this parallel AD conversion processing, when AD conversion processing is performed on each of a plurality of pixel signals in order, the exposure time (accumulation time) that could not be shorter than the AD conversion period for one imaging frame is shortened. The accumulation time can be arbitrarily set within one vertical scanning period.

  As a result, according to the solid-state imaging device 10 according to the first embodiment, the dynamic range can be expanded, so that it is possible to cope with shooting with high illuminance. In addition, since the exposure time can be shortened, for example, occurrence of image blurring when a moving image is taken can be suppressed. The point that the dynamic range can be expanded and the exposure time can be shortened will be described more specifically below.

  In the solid-state imaging device 10 according to the present embodiment, under the control of the system control unit 19, the vertical driving unit 13 performs, for example, read driving of charges twice from the photodiode PD during one imaging frame. FIG. 6 schematically shows a shutter operation, a read operation, a charge accumulation state, and an addition process in the case where charge is read twice from the photodiode PD during one imaging frame. Incidentally, FIG. 7 schematically shows a shutter operation, a read operation, and a charge accumulation state when the charge is read once from the photodiode PD in one imaging frame.

  When reading charge once from the photodiode PD during one imaging frame, the amount of charge stored in the photodiode PD is limited, so that signal charges generated after saturation are stored. I can't. On the other hand, the amount of charge corresponding to the number of times of reading is obtained by performing reading twice at a higher reading speed than in the case of one charge reading, storing in the memory unit 18 and performing addition processing. Can be read out from the photodiode PD.

  At this time, when AD conversion is sequentially performed by one AD conversion unit with respect to two pixel signals obtained in time series by two charge readouts, the charge accumulation time (exposure time) is set to all the two pixel signals. The time required for AD conversion, that is, the AD conversion period for one imaging frame cannot be shortened.

  Therefore, the solid-state imaging device 10 according to the present embodiment employs a configuration in which two AD conversion units are provided in parallel for two pixel signals based on two charge readouts (two parallel configuration). By providing two systems of AD converters in parallel for two pixel signals read out in time series from the pixel 20, two pixel signals read out in time series are paralleled by two systems of AD converters. AD conversion can be performed. In other words, since the AD converters are provided in parallel in two systems, during the AD conversion of the image signal based on the first charge reading, the second charge reading and the AD conversion of the pixel signal based on the second charge reading are performed in parallel. (In parallel).

  Relationship between shutter timing and readout timing for each exposure time (accumulation time) with respect to the brightness of the photographing environment when reading out the charge once from the photodiode PD and reading out the charge twice during one imaging frame An example of this is shown in FIG. The upper side of FIG. 8 shows the shutter timing and readout timing when the charge is read once from the photodiode PD during one imaging frame, and the lower side of FIG. 8 shows 2 from the photodiode PD during one imaging frame. The shutter timing and readout timing in the case where readout of recharged charges is performed are shown.

[Circuit circuit operation]
Here, a specific circuit operation of the pixel 20 having the circuit configuration shown in FIG. 5 in the case of reading out charges twice will be described with reference to timing waveform diagrams of FIGS. 9A, 9B, and 9C.

FIG. 9A is a timing waveform diagram of the horizontal synchronization signal H _sync , the selection signal SEL1, the selection signal SEL2, the reset signal RST, and the transfer signal TRG during shutter. Since the reset signal RST and the transfer signal TRG are simultaneously in an active state (high level), the reset transistor 22 and the transfer transistor 21 are turned on. As a result, a shutter operation is performed in which the charge of the photodiode PD is discarded to the node of the power supply _VDD .

FIG. 9B is a timing waveform diagram of the horizontal synchronization signal H _sync , the selection signal SEL1, the selection signal SEL2, the reset signal RST, and the transfer signal TRG during the first charge reading. When the selection signal SEL1 becomes active, the selection transistor 24 ₁ becomes conductive. During the active period of the selection signal SEL1, the reset signal RST becomes active and the reset transistor 22 becomes conductive, so that the floating diffusion FD is reset. Then, the potential of the floating diffusion FD at the time of resetting is read to the vertical signal line 31 by the selection transistor 24 ₁ as the reset level V _rst and AD-converted by the AD converter 141.

Subsequently, when the transfer signal TRG becomes active and the transfer transistor 21 becomes conductive, the first charge is read from the photodiode PD to the floating diffusion FD. The potential of the floating diffusion FD at the time of the first charge reading is read to the vertical signal line 31 by the selection transistor 24 ₁ as the signal level V _sig based on the first charge reading, and AD conversion is performed by the AD converter 141. Is done. During the AD conversion of the pixel signal based on the first charge read by the AD converter 141, the second charge read is performed.

FIG. 9C is a timing waveform diagram of the horizontal synchronization signal H _sync , the selection signal SEL1, the selection signal SEL2, the reset signal RST, and the transfer signal TRG at the time of the second charge reading. As the selection signal SEL2 becomes active, the selection transistor 24 ₂ becomes conductive. In the active period of the selection signal SEL2, the reset signal RST is in an active state and the reset transistor 22 is in a conductive state, whereby the floating diffusion FD is reset. The potential of the floating diffusion FD when the reset is read out to the vertical signal line 31 by the selection transistor 24 ₂ as a reset level V _rst, is AD converted by the AD converter 141.

Subsequently, when the transfer signal TRG becomes active and the transfer transistor 21 becomes conductive, the second charge is read from the photodiode PD to the floating diffusion FD. Then, the potential of the floating diffusion FD at the time of the second charge reading is read to the vertical signal line 32 by the selection transistor 24 ₂ as the signal level V _sig based on the second charge reading, and AD conversion is performed by the AD converter 151. Is done.

  As described above, since two AD signals are provided in parallel for two pixel signals read out from the pixel 20 in time series, the two pixel signals are AD-converted in parallel by separate AD converters. It can be performed. Accordingly, the charge accumulation time (exposure time) can be shortened as compared with the case where each of the two pixel signals is AD-converted sequentially by one AD conversion unit.

(Example of 3 parallel configuration)
In the solid-state imaging device 10 according to the present embodiment, the case where the charge is read twice from the photodiode PD in one imaging frame has been described as an example, but the number of times of reading the charge from the photodiode PD is 2. The reading is not limited to the number of times, and it is possible to read three times or more. FIG. 10 schematically shows a shutter operation, a read operation, a charge accumulation state, and an addition process when the charge is read from the photodiode PD three times during one imaging frame. In this case, the AD conversion unit has a three-parallel configuration.

(Example of 4 parallel configuration)
Further, FIG. 11 shows the relationship between one pixel column and a 4-parallel configuration AD converter when the charge is read out from the photodiode PD four times during one imaging frame, and the pixel 20 in the 4-parallel configuration is shown. An example of the circuit configuration is shown in FIG.

In the case of the 4-parallel configuration, under the control of the system control unit 19, the vertical driving unit 13 performs driving to read out charges from the photodiode PD four times during one imaging frame. Corresponding to the four charge readouts, the pixel 20 includes four selection transistors 24 _{1 to} 24 ₄ . In addition, four vertical signal lines 31 to 34 are wired for each pixel column. Then, the selection transistor 24 ₁ selects the pixel signal associated with the first reading and outputs it to the vertical signal line 31, and the selection transistor 24 ₂ selects the pixel signal associated with the second reading and outputs it to the vertical signal line 32. To do. In addition, the selection transistor 24 ₃ selects a pixel signal associated with readout for the third time and outputs it to the vertical signal line 33, and the selection transistor 24 ₄ selects the pixel signal associated with readout for the fourth time and outputs it to the vertical signal line 34. To do.

  The vertical signal line 31 and the vertical signal line 33 transmit the pixel signal output from the pixel 20 in the first direction (one side in the pixel column direction / upward in the figure), and the vertical signal line 32 and the vertical signal line 34. Transmits the pixel signal output from the pixel 20 in the second direction (the other side in the pixel column direction / downward in the figure). An AD converter (ADC 1) 141 and a current source 41 are connected to one end of the vertical signal line 31, and an AD converter (ADC 3) 142 and a current source 43 are connected to one end of the vertical signal line 33. An AD converter (ADC 2) 151 and a current source 42 are connected to one end of the vertical signal line 32, and an AD converter (ADC 4) 152 and a current source 44 are connected to one end of the vertical signal line 34. Yes.

(Example of addition processing outside the semiconductor substrate)
In the solid-state imaging device 10 according to the present embodiment, a plurality of pixel data after AD conversion is added in the memory unit 18 mounted on the same semiconductor substrate 11 as the pixel array unit 12. It is not limited to the addition process at 18. That is, it is possible to adopt a configuration in which the memory unit 18 is provided outside the semiconductor substrate 11, and a plurality of pixel data is added in the memory unit 18 outside the semiconductor substrate 11. The signal processing unit 41 (see FIG. 1) can also be configured to add a plurality of pixel data.

  FIG. 13 schematically shows a shutter operation, a read operation, a charge accumulation state, and an addition process when an addition process is performed by the signal processing unit 41 outside the semiconductor substrate 11. Here, the case where the charge is read twice from the photodiode PD in one imaging frame is illustrated, but the semiconductor substrate is also used when the charge is read three times or when the charge is read four times. The signal processing unit 41 outside 11 can perform addition processing.

[Application example]
In the solid-state imaging device 10 according to the first embodiment described above, for example, four readings (Read 1, Read 2, Read 3, Read 4) are not performed in a divided manner, but a partial reading is performed at the same time, whereby the analog gain is increased. The signal level can be controlled as if it were. As a result, in the AD conversion unit that has been read simultaneously, the amount of stored charge increases, so that an effect of noise reduction can be obtained. When the number of charges read from the photodiode PD in one imaging frame increases as Read1, Read2, Read3, Read4, Read5,..., The analog gain resolution increases.

  Here, the charge read timing will be described by taking as an example a case where the number of charge reads is four (the AD conversion unit has four parallel configurations). FIG. 14A shows an example of a mode in which the analog gain is 1.0 times. As shown in FIG. 14A, the first, second, third, and fourth read operations are sequentially performed in time series during one imaging frame (vertical synchronization period), thereby pseudo-saturating the photodiode PD. Since the signal amount can be increased, the dynamic range can be expanded.

  On the other hand, the dynamic range can be narrowed by changing the analog gain by controlling the charge read timing. FIG. 14B shows an example of a mode in which the analog gain is 1.5 times. As shown in FIG. 14B, the first read operation and the second read operation are performed at the same timing, and thereafter the third and fourth read operations are sequentially performed to increase the analog gain by 1.5 times. The dynamic range can be made narrower than when the analog gain is 1.0 times.

  FIG. 14C shows an example of a mode in which the analog gain is 2.0 times. As shown in FIG. 14C, the first read operation and the second read operation are performed at the same timing, and then the third read operation and the fourth read operation are performed at the same timing, whereby the analog gain is increased. The dynamic range can be made narrower than that when the analog gain is 1.5 times.

  Each mode of the mode in which the analog gain is 1.0 times, the mode in which the analog gain is 1.5 times, and the mode in which the analog gain is 2.0 times can be arbitrarily selected by the user. For example, the system control unit 19 is supplied with a mode selection signal for the user to select one of the above modes from an operation unit (not shown). Then, the system control unit 19 receives the mode selection signal and sets the operation mode of the vertical drive unit 13 so as to execute any one of the above modes.

  Next, the relationship among the analog gain, dynamic range, and charge read timing will be described with reference to FIGS. 15A, 15B, and 15C. Here, a case will be described as an example in which the number of times of charge reading is two (the AD conversion unit has two parallel configurations).

  FIG. 15A is an example of a mode in which the analog gain is 1.0 times. As shown in FIG. 15A, the saturation signal amount of the photodiode PD is artificially increased by sequentially performing the first and second read operations in time series during one imaging frame (vertical synchronization period). Therefore, the dynamic range can be expanded.

  FIG. 15B shows an example of a mode in which the analog gain is 2.0 times and the first and second read operations are sequentially performed in time series. When the analog gain is 2.0 times, the dynamic range is halved. Since the dynamic range is halved, a dark subject can be imaged brightly. FIG. 15C shows an example of a mode in which the analog gain is 2.0 times, the first read operation and the second read operation have the same timing (simultaneous read), and AD conversion is performed simultaneously. By making the analog gain 2.0 times and simultaneous readout, the dynamic range is halved, but a dark subject can be imaged brightly, and the time difference between the two pixel signals due to simultaneous readout can be eliminated. it can.

  Each mode is a mode in which the analog gain is 1.0 times, a mode in which the analog gain is 2.0 times, and the readout operation is performed in time series, and a mode in which the analog gain is 2.0 times and simultaneous readout (simultaneous AD conversion) is performed. The mode setting can be arbitrarily selected by the user. For example, the system control unit 19 is supplied with a mode selection signal for the user to select one of the above modes from an operation unit (not shown). Then, the system control unit 19 receives the mode selection signal and sets the operation mode of the vertical drive unit 13 so as to execute any one of the above modes.

Second Embodiment
The second embodiment of the present disclosure is an example in the case where one pixel has a plurality of photoelectric conversion units. FIG. 16 shows a circuit configuration of a pixel in the solid-state imaging device according to the second embodiment. Also in the second embodiment, a CMOS image sensor is exemplified as the solid-state imaging device.

In the solid-state imaging device according to the second embodiment, the pixel 20 includes a plurality of photoelectric conversion units, for example, two photodiodes PD ₁ and PD ₂ , and correspondingly, two transfer transistors 21 ₁ and 21. Has _two . The transfer transistor 21 ₁ is turned on in response to the transfer signal TRG ₁ supplied from the vertical drive unit 13 to transfer the charge of the photodiode PD ₁ to the floating diffusion FD. The transfer transistor 21 ₂ is turned on in response to the transfer signal TRG ₂ supplied from the vertical drive unit 13 to transfer the charge of the photodiode PD ₂ to the floating diffusion FD.

Also in the solid-state imaging device according to the second embodiment, electric charges are read from the photodiodes PD ₁ and PD _{2 a} plurality of times during one imaging frame. The system configuration of the solid-state imaging device according to the second embodiment is basically the same as that of the solid-state imaging device according to the first embodiment shown in FIG. That is, the solid-state imaging device according to the second embodiment also includes a system AD conversion unit corresponding to the number of times of charge readout, and a plurality of system AD conversion units for a plurality of pixel signals based on a plurality of times of charge readout. It has a system configuration for AD conversion in parallel.

The two photodiodes PD ₁ and PD ₂ included in the pixel 20 are used for phase difference autofocusing that automatically focuses in an imaging apparatus such as a camera using the solid-state imaging apparatus according to the second embodiment. Can do. Phase difference autofocus is a method that uses two sensors to make use of the phase difference of a subject image, measures the distance between the subject and the imaging lens, and focuses. Two photodiodes PD ₁ and PD ₂ can be used as two sensors for this phase difference type autofocus.

The phase difference type autofocus using _two photodiodes PD ₁ and PD ₂ will be described more specifically. Since the photodiode PD ₁ and the photodiode PD ₂ are formed at different positions, a subject image obtained by the _two photodiodes PD ₁ and PD ₂ is shifted. A phase shift amount (phase difference) is calculated from the shift of the subject image to obtain a defocus amount. Then, based on this defocus amount, auto focus can be achieved by adjusting the position of the imaging lens in the optical axis direction.

As shown in FIG. 17A, the _two photodiodes PD ₁ and PD ₂ can be arranged in the X direction (left side in FIG. 17A) or in the Y direction (right side in FIG. 17A). . In the arrangement arranged in the X direction, the phase difference in the X direction can be detected by the _two photodiodes PD ₁ and PD ₂ . When arranged in the Y direction, the phase difference in the Y direction can be detected by the _two photodiodes PD ₁ and PD ₂ .

Here, the pixel configuration in which the pixel 20 includes the two photodiodes PD ₁ and PD ₂ is illustrated, but the pixel configuration is not limited thereto. For example, as shown in FIG. 17B, the pixel 20 includes three photodiodes PD ₁ , PD ₂ , and PD ₃ , and as shown in FIG. 17C, four photodiodes PD ₁ , PD ₂ , PD ₃ , A pixel configuration in which PD ₄ is arranged in a square may be used.

Incidentally, in the case of a pixel configuration in which the _four photodiodes PD ₁ , PD ₂ , PD ₃ , and PD ₄ are arranged in a square, the addition result of the photodiode PD ₁ and the photodiode PD ₃ , the photodiode PD ₂ and the photodiode PD _From the addition result of ₄ , the phase difference in the X direction can be detected. Further, the phase difference in the Y direction can be detected from the addition result of the photodiode PD ₁ and the photodiode PD _{2 and} the addition result of the photodiode PD ₃ and the photodiode PD ₄ .

By the way, in the pixel 20 having a plurality of photodiodes, for example, two photodiodes PD ₁ and PD ₂ , as shown in FIG. 18A, for example, when the photodiode PD ₁ is saturated, the exposure time (accumulation time) of the pixel is increased. The linearity of the pixel signal cannot be ensured (conventional method 1). Specifically, as shown in FIG. 18B, when the photodiode PD ₁ is saturated, the linearity of the pixel signal obtained by combining the charge of the photodiode PD _{1 and} the charge of the photodiode PD ₂ is impaired (disintegrated). .

In contrast to the conventional method 1, as shown in FIG. 19A, by providing a blooming path BP between the _two photodiodes PD ₁ and PD ₂ , the linearity of the pixel signal with respect to the exposure time can be ensured (conventional method). 2). However, by providing the blooming path BP, as shown in FIG. 19B, the linearity in the exposure period X can be ensured, but the saturation charge amount of each of the photodiodes PD ₁ and PD ₂ is compared to the case where the blooming path BP is not provided. Therefore, the range that can be used as a single photodiode is limited. That is, the range in which the pixel 20 can be used as a phase difference detection pixel is limited. In addition, it is difficult to accurately process the blooming pass BP for all the pixels.

In the solid-state imaging device according to the second embodiment, as in the case of the solid-state imaging device according to the first embodiment, charges are read from the photodiodes PD ₁ and PD _{2 a} plurality of times during one imaging frame. . Specifically, as shown in FIG. 20A, and to perform the reading from the photodiodes PD _1, PD ₂ in one imaging frame for example, twice the charge.

As shown in FIG. 20B, even if the blooming path BP is not formed between the _two photodiodes PD ₁ and PD ₂ by reading out the charges multiple times, the pixel 20 having the _two photodiodes PD ₁ and PD ₂ is formed. Linearity with respect to the exposure time of the pixel signal can be ensured. Moreover, the absence of the blooming path BP does not limit the range that can be used as the phase difference detection pixel. That is, according to the solid-state imaging device according to the second embodiment, both functions of dynamic range expansion and phase difference detection can be achieved.

<Modification>
As mentioned above, although the technique of this indication was demonstrated based on preferable embodiment, the technique of this indication is not limited to these embodiment. The configuration and structure of the solid-state imaging device described in each of the above embodiments are examples, and can be changed as appropriate.

For example, in each of the above-described embodiments, a so-called 4Tr configuration pixel having four functional transistors (Tr) including a transfer transistor 21, a reset transistor 22, an amplification transistor 23, and a selection transistor 24 (24 ₁ , 24 ₂ ). Although the case where 20 is used as a base has been described as an example, the present invention is not limited to this.

  For example, the technique of the present disclosure can be applied to a case where a pixel 20 having a so-called 3Tr configuration in which the amplification transistor 23 has a function of the selection transistor 24 by controlling the drain potential of the amplification transistor 23 is used as a base. it can. In the case where the pixel 20 having the 3Tr configuration is used as a base, the same number of amplification transistors 23 as the number of charges read out are provided, and the drain potentials of the plurality of amplification transistors 23 are controlled. The effects and effects can be obtained.

  In each of the above embodiments, the case where the present invention is applied to a so-called flat structure solid-state imaging device in which the AD conversion units 14 and 15 and the memory unit 18 are mounted on the semiconductor substrate 11 together with the pixel array unit 12 is taken as an example. Although described above, the present invention is not limited to application to a solid-state imaging device having a flat structure. That is, the present invention can also be applied to a so-called stacked structure solid-state imaging device in which a plurality of semiconductor substrates are stacked on each other. As a solid-state imaging device having a stacked structure, for example, as shown in FIG. 21, a semiconductor substrate 61 in which a pixel array unit 12 is formed, a semiconductor substrate 62 in which a memory unit 18 is formed, AD conversion units 14 and 15 and a column The solid-state imaging device 10 formed by stacking the semiconductor substrates 63 on which the processing units 16 and 17 are formed can be exemplified.

  According to the solid-state imaging device 10 having this stacked structure, the first layer semiconductor substrate 61 needs only to have a size (area) sufficient to form the pixel array unit 12, and thus the size (area) of the first layer semiconductor substrate 61 is sufficient. ) As a result, the size of the entire chip can be reduced. Furthermore, a process suitable for pixel creation can be applied to the first semiconductor substrate 61, and a process suitable for circuit creation can be applied to the second and third semiconductor substrates 62 and 63. In manufacturing the imaging device 10, there is also an advantage that process optimization can be achieved.

  Further, in the solid-state imaging device 10 having a stacked structure, pixel signals read from the pixel array unit 12 are converted into digital data by the AD conversion units 14 and 15 and then controlled by a memory controller (not shown). Data can be written to the memory unit 18 at high speed. The digital data written to the memory unit 18 can be read out to the signal processing units such as the column processing units 16 and 17 at a low speed under the control of the memory controller. As a result, pixel signals can be instantaneously read from the pixel array unit 12 to the memory unit 18 and slowly read from the memory unit 18 to perform signal processing, so that a high-quality image with little distortion can be obtained.

  In addition, although the three-layer laminated structure is illustrated here, the present invention is not limited to this, and a two-layer laminated structure or a four-layer or more laminated structure may be used.

<Electronic device of the present disclosure>
The solid-state imaging device according to the first and second embodiments described above uses an imaging device such as a digital still camera or a video camera, a portable terminal device having an imaging function such as a mobile phone, or a solid-state imaging device for an image reading unit. It can be used as an imaging unit (image capturing unit) in electronic devices such as copying machines. Note that the solid-state imaging device may be formed as a single chip, or may be in a modular form having an imaging function in which an imaging unit and a signal processing unit or an optical system are packaged together. Good. There is a case where the above-mentioned module form mounted on an electronic device, that is, a camera module is used as an imaging device.

[Imaging device]
FIG. 22 is a block diagram illustrating a configuration of an imaging apparatus that is an example of the electronic apparatus of the present disclosure. As shown in FIG. 22, an imaging apparatus 100 according to this example includes an optical system 101 including a lens group and the like, an imaging unit 102, a DSP circuit 103, a frame memory 104, a display device 105, a recording device 106, an operation system 107, and And a power supply system 108 and the like. The DSP circuit 103, the frame memory 104, the display device 105, the recording device 106, the operation system 107, and the power supply system 108 are connected to each other via a bus line 109.

  The optical system 101 captures incident light (image light) from a subject and forms an image on the imaging surface of the imaging unit 102. The imaging unit 102 converts the amount of incident light imaged on the imaging surface by the optical system 101 into an electrical signal for each pixel and outputs the electrical signal as a pixel signal. The DSP circuit 103 performs general camera signal processing, such as white balance processing, demosaic processing, and gamma correction processing.

  The frame memory 104 is appropriately used for storing data during the signal processing in the DSP circuit 103. The display device 105 includes a panel type display device such as a liquid crystal display device or an organic EL (electroluminescence) display device, and displays a moving image or a still image captured by the imaging unit 102. The recording device 106 records the moving image or the still image captured by the imaging unit 102 on a recording medium such as a portable semiconductor memory, an optical disk, or an HDD (Hard Disk Drive).

  The operation system 107 issues operation commands for various functions of the imaging apparatus 100 under the operation of the user. The power supply system 108 appropriately supplies various power supplies serving as operation power for the DSP circuit 103, the frame memory 104, the display device 105, the recording device 106, and the operation system 107 to these supply targets.

  In the imaging device 100 configured as described above, the solid-state imaging device according to the first and second embodiments described above can be used as the imaging unit 102. The solid-state imaging device according to the first and second embodiments can expand the dynamic range and shorten the exposure time. Therefore, by using the solid-state imaging device according to the first and second embodiments as the imaging unit 102, it is possible to cope with shooting with high illuminance and suppress the occurrence of image blurring when shooting a moving image, for example. be able to.

<Configuration that the present disclosure can take>
In addition, this indication can also take the following structures.
[1] A pixel array unit in which pixels including a photoelectric conversion unit are arranged,
A drive unit that reads out charges from the photoelectric conversion unit a plurality of times during one imaging frame; and
An analog-to-digital conversion unit that performs analog-to-digital conversion on each of a plurality of pixel signals based on a plurality of times of charge readout;
A solid-state imaging device.
[2] The pixel has a plurality of selection transistors corresponding to a plurality of pixel signals,
The plurality of selection transistors select a plurality of pixel signals in parallel and supply them to the analog-digital conversion unit through corresponding vertical signal lines.
The solid-state imaging device according to [1] above.
[3] The vertical signal lines include a first signal line group that transmits pixel signals in a first direction for each pixel column, and a second direction opposite to the first direction for each pixel column. A second signal line group transmitting to
The analog-digital conversion unit is provided for each pixel column, and is provided for each pixel column and a set of analog-digital converters that perform analog-digital conversion on pixel signals transmitted by the first signal line group. A set of analog-to-digital converters for analog-to-digital conversion of pixel signals transmitted by two signal line groups;
The solid-state imaging device according to [2] above.
[4] Analog-to-digital converter
A reference voltage generator for generating a reference voltage having an inclined waveform;
A comparator that compares a pixel signal supplied from a pixel through a vertical signal line with a reference voltage having an inclined waveform and outputs a pulse signal having a pulse width corresponding to the level of the pixel signal; and
A counting unit that performs a counting operation in synchronization with a predetermined clock in a comparison period from the start to the end of the comparison operation of the comparator;
The count value of the count unit is a digital value after analog-digital conversion,
The solid-state imaging device according to [3] above.
[5] A mode in which a plurality of pixel signals based on a plurality of charge readouts are read in time series through a plurality of selection transistors and a mode in which reading is simultaneously performed through the plurality of selection transistors can be set according to a user's selection. ,
The solid-state imaging device according to any one of [1] to [4].
[6] A memory unit that stores a plurality of digital data output from the analog-digital conversion unit based on the plurality of pixel signals is provided.
The solid-state imaging device according to any one of [1] to [5].
[7] The plurality of digital data is added in the memory unit.
The solid-state imaging device according to [6] above.
[8] Having a plurality of photoelectric conversion units in one pixel.
The solid-state imaging device according to any one of [1] to [7].
[9] The plurality of photoelectric conversion units are used for phase difference detection that measures the distance to the subject using the phase difference of the subject image.
The solid-state imaging device according to [8] above.
[10] The pixel array unit and the analog-digital conversion unit are respectively mounted on different semiconductor substrates stacked on each other.
The solid-state imaging device according to any one of [1] to [9].
[11] In driving a solid-state imaging device in which pixels including a photoelectric conversion unit are arranged,
Read out the charge multiple times from the photoelectric converter during one imaging frame,
Analog-to-digital conversion of each of a plurality of pixel signals based on a plurality of charge readouts in parallel.
A driving method of a solid-state imaging device.
[12] A pixel array unit in which pixels including a photoelectric conversion unit are arranged,
A drive unit that reads out charges from the photoelectric conversion unit a plurality of times during one imaging frame; and
An analog-to-digital conversion unit that performs analog-to-digital conversion on each of a plurality of pixel signals based on readout of a plurality of charges in parallel;
An electronic apparatus having a solid-state imaging device.

DESCRIPTION OF SYMBOLS 10 ... Solid-state imaging device, 11 ... Semiconductor substrate (semiconductor chip), 12 ... Pixel array part, 13 ... Vertical drive part, 14, 15 ... AD conversion part (Analog-digital conversion part) , 16, 17 ... column processing unit, 18 ... memory unit, 19 ... system control unit, 20 ... pixel, 21 ... photodiode (photoelectric conversion unit), 22 ... transfer Transistor 23... Reset transistor 24... Amplifier transistor 25 ₁ , 25 ₂ ... Select transistor 31 to 34... Vertical signal line 41 to 44. Signal processing unit, 52 ... interface, 141, 142, 151, 132 ... AD converter, 1411 ... reference voltage generation unit, 1412 ... comparator (comparator), 1413 ... up / down Down counter (counting unit)

Claims (12)

A pixel array unit in which pixels including a photoelectric conversion unit are arranged;
A drive unit that reads out charges from the photoelectric conversion unit a plurality of times during one imaging frame; and
An analog-to-digital conversion unit that performs analog-to-digital conversion on each of a plurality of pixel signals based on readout of a plurality of charges in parallel;
A solid-state imaging device. The pixel has a plurality of selection transistors corresponding to a plurality of pixel signals,
The plurality of selection transistors select a plurality of pixel signals in parallel and supply them to the analog-digital conversion unit through corresponding vertical signal lines.
The solid-state imaging device according to claim 1. The vertical signal lines transmit a pixel signal in a first direction for each pixel column in a first direction, and transmit the pixel signal in a second direction opposite to the first direction for each pixel column. A second signal line group,
The analog-digital conversion unit is provided for each pixel column, and is provided for each pixel column and a set of analog-digital converters that perform analog-digital conversion on pixel signals transmitted by the first signal line group. A set of analog-to-digital converters for analog-to-digital conversion of pixel signals transmitted by two signal line groups;
The solid-state imaging device according to claim 2. Analog-to-digital converter
A reference voltage generator for generating a reference voltage having an inclined waveform;
A comparator that compares a pixel signal supplied from a pixel through a vertical signal line with a reference voltage having an inclined waveform and outputs a pulse signal having a pulse width corresponding to the level of the pixel signal; and
A counting unit that performs a counting operation in synchronization with a predetermined clock in a comparison period from the start to the end of the comparison operation of the comparator;
The count value of the count unit is a digital value after analog-digital conversion,
The solid-state imaging device according to claim 3. According to the user's selection, it is possible to set a mode for reading a plurality of pixel signals based on a plurality of charge readouts in time series through a plurality of selection transistors and a mode for simultaneously reading through a plurality of selection transistors.
The solid-state imaging device according to claim 2. A memory unit for storing a plurality of digital data output from the analog-digital conversion unit based on the plurality of pixel signals;
The solid-state imaging device according to claim 1. The plurality of digital data is added in the memory unit.
The solid-state imaging device according to claim 6. Having a plurality of photoelectric conversion units in one pixel;
The solid-state imaging device according to claim 1. The plurality of photoelectric conversion units are used for phase difference detection that measures the distance to the subject using the phase difference of the subject image.
The solid-state imaging device according to claim 8. The pixel array unit and the analog-digital conversion unit are respectively mounted on different semiconductor substrates stacked on each other.
The solid-state imaging device according to claim 1. In driving a solid-state imaging device in which pixels including a photoelectric conversion unit are arranged,
Read out the charge multiple times from the photoelectric converter during one imaging frame,
Analog-to-digital conversion of each of a plurality of pixel signals based on a plurality of charge readouts in parallel.
A driving method of a solid-state imaging device. A pixel array unit in which pixels including a photoelectric conversion unit are arranged;
A drive unit that reads out charges from the photoelectric conversion unit a plurality of times during one imaging frame; and
An analog-to-digital conversion unit that performs analog-to-digital conversion on each of a plurality of pixel signals based on a plurality of times of charge readout;
An electronic apparatus having a solid-state imaging device.