JP2018002291A - Semiconductor integrated circuit tray having notches for binding band - Google Patents

Abstract

PURPOSE: To minimize a gap formed between semiconductor integrated circuit trays when stacked semiconductor integrated circuit trays are bundled with a binding band.SOLUTION: Provided is a semiconductor integrated circuit tray 1 having a substantially quadrangular shape when viewed from the top. In the tray 1, notches 2 for hanging a binding band to bundle a plurality of trays 1 are formed along at least one side of upper and lower sides at four locations within 3.4 cm from each end of two lateral faces extending in a longitudinal direction of the tray 1. In one embodiment, the lateral face of the semiconductor integrated circuit tray 1 recesses from the upper side to the lower side at the position of the notch 2 to form a groove with a width substantially as large as the width of the notch 2.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a tray for housing a semiconductor integrated circuit (PKG) such as an IC. More specifically, in the packaging operation of a plurality of trays, the tray can be bent (deformation) when a binding band is hung on the trays. The present invention relates to minimizing the occurrence of a gap and, in turn, preventing gaps between the trays and horizontal displacement from occurring.

  A tray for a semiconductor integrated circuit used in each process of manufacturing, measuring and shipping an electronic component such as an IC must pass various quality tests including a drop test performed at a delivery destination. As an example of a drop test, a plurality of semiconductor integrated circuit trays on which a plurality of IC components (PKG) are placed are bundled using a binding band, put into an aluminum bag together with a moisture absorbent, and vacuum packed. , Packed in corrugated cardboard, and dropped onto concrete ground 20 times from a height of about 1 m (all 6 sides of tray, dropped on 3 sides, 1 corner down 10 times in total Two sets of drop tests) are performed as a set. If the IC components on the tray are not damaged after receiving the impact due to dropping, they can be delivered as a regular semiconductor integrated circuit tray.

JP2011-238660A JP 2010-189048 A

  When the tray 6 for a conductor integrated circuit of the conventional product is bundled using the binding band 3, a gap 10 is generated between the stacked trays 6 because the tray 6 is bent due to excessive force applied near the center portion. It was easy (see FIG. 6B). Even when the interlock function unit 11 composed of a convex body and a concave body that suppress stacking as disclosed in Patent Document 2 is formed on each tray, the tray 6 is subjected to a large impact in a drop test. The gap between them further opens, and the horizontal displacement between the trays 6 increases. Then, the semiconductor integrated circuit 7 placed on the lower tray 6 is pushed toward the front guide (wall) 5a of the upper tray 6 and is sandwiched between the front guide 5a and the back guide 6a and may be damaged. (See FIG. 7 (a)).

  In order to solve the problem, a semiconductor integrated circuit tray having a substantially quadrangular shape in a plan view, and upper and lower sides at four locations within 3.4 cm from each edge of two side surfaces extending in the longitudinal direction of the tray A semiconductor integrated circuit tray having a notch for a binding band, characterized in that a notch for hanging a binding band for binding a plurality of trays is formed along at least one side of the tray. As a result, even when a plurality of trays bundled with the binding band are subjected to a large impact in a drop test or the like, the state in which the trays are bound is maintained.

  In one embodiment, the side surface of the semiconductor integrated circuit tray is recessed from the upper side to the lower side at the position of the cutout, and a groove having the same width as the width of the cutout is formed.

  In one embodiment, the protrusions extend from both sides of the opening position of the notch in a direction approaching each other.

  According to the semiconductor integrated circuit tray having the binding band cutout of the present invention, at least one of the upper side and the lower side at four locations within 3.4 cm from each edge of the two side surfaces extending in the longitudinal direction of the tray. A notch for hanging a binding band that binds the plurality of trays is formed along the, so that the plurality of trays will not bend even if the binding band is applied. Therefore, even if a large impact is received in the drop test, there is no gap or misalignment between the trays.

  As an incidental effect, in the semiconductor integrated circuit tray having the binding band cutout according to the present invention, it is possible to prevent a semiconductor integrated circuit such as an IC housed in the pocket of each tray from being stolen. In other words, the current IC (PKG) is very thin and small, so even if there is only a slight gap between the trays, it will slide down from the gap, but a binding band is attached to the notch of the tray of the present invention. When hung, there is no gap between the trays, so there is no worry of the IC being stolen from the gap between the trays.

The figure which shows the tray for semiconductor integrated circuits which has the notch for binding bands of this invention. The side view which shows the several tray for semiconductor integrated circuits with which the binding band was hung. The side view which shows four types of notches formed in the tray for semiconductor integrated circuits. The figure which expands and shows four types of notches. The side view which shows the tray in which the notch of Example (a) and Example (b) was formed. The figure which shows schematically the packing process of the tray for semiconductor integrated circuits. Sectional drawing which shows the pocket which mounted the semiconductor integrated circuit ((a) The example of the tray of the conventional goods with a large gap | deviation of a stack | stuck, (b) The example of the tray of this invention without the gap | deviation of a stack | stack). The perspective view which shows one Example of the tray for semiconductor integrated circuits of this invention.

  A semiconductor integrated circuit tray 1 having a notch for a binding band according to the present invention will be described below based on a specific example with reference to the accompanying drawings.

  FIG. 1 is a six-sided view showing a semiconductor integrated circuit tray 1 having a binding band cutout according to the present invention. In the embodiment shown in FIG. 1, notches 2 are formed along only the lower sides at four locations within 3.4 cm from each edge (that is, the corner portion) on the two side surfaces extending in the longitudinal direction of the tray 1. Has been.

  As shown in FIG. 2, when binding a plurality of semiconductor integrated circuit trays 1 using the binding band 3, the packing operator hangs the binding band 3 on the position of the notch 2 of these trays 1. There is no gap 10 between the plurality of trays 1.

  FIG. 3 shows an embodiment of a tray 1 for a semiconductor integrated circuit having various notches 2. In the embodiment shown in FIGS. 3A to 3C, the upper side in the vicinity of the edges (corner portions) of the two side surfaces extending in the longitudinal direction of the semiconductor integrated circuit tray 1 having a substantially rectangular shape in plan view. A cutout 2 for hanging a binding band is formed along at least one of the lower side.

  In the embodiment shown in FIG. 3D, along the at least one of the upper side and the lower side in the vicinity of the edges of the two side surfaces extending in the longitudinal direction of the semiconductor integrated circuit tray 1 having a substantially rectangular shape in plan view. In addition, a notch 2 for hanging the binding band is formed. Further, at the position of the notch 2, the side surface of the tray 1 is recessed from the upper side to the lower side, and is substantially the same as the width of the notch 2. A groove 2a having a width is formed.

  4 (a) to 4 (d) are enlarged views showing the four types of notches shown in FIGS. 3 (a) to 3 (d). In the embodiment shown in FIG. 4A, a binding band is applied along the lower sides at four locations within 3.4 cm from the end edges of the two side surfaces extending in the longitudinal direction of the semiconductor integrated circuit tray 1. The notch 2 is formed. In the embodiment shown in FIG. 4B, a binding band is applied along the upper sides at four locations within 3.4 cm from the end edges of the two side surfaces extending in the longitudinal direction of the semiconductor integrated circuit tray 1. The notch 2 is formed. Further, in the embodiment shown in FIG. 4C, the bundles are formed along the upper and lower sides at four locations within 3.4 cm from the end edges of the two side surfaces extending in the longitudinal direction of the semiconductor integrated circuit tray 1. A notch 2 for forming a band is formed.

  Further, in the embodiment shown in FIG. 4 (d), bundling is performed along the upper and lower sides at four locations within 3.4 cm from the end edges of the two side surfaces extending in the longitudinal direction of the semiconductor integrated circuit tray 1. A notch 2 for forming a band is formed, and the side surface of the semiconductor integrated circuit tray 1 is recessed from the upper side to the lower side at the position of the notch 2, and the width of the notch 2 is substantially the same. A groove 2a is formed. In this way, when the grooves 2a on the side surface of the tray 1 are formed at the positions of the various notches 2 described above, the grooves 2a can be hung so as to accommodate the binding bands. It is possible to bundle the semiconductor integrated circuit trays 1 more firmly.

  In still another embodiment of the present invention shown in FIGS. 5A and 5B, the protrusions 4 extend from both sides of the opening position of the notch 2 of the semiconductor integrated circuit tray 1 in a direction approaching each other. ing.

  In the embodiment shown in FIG. 5A, the two protrusions 4 extending from both sides of the opening position of the notch 2 are formed to the same length. The formation of the two protrusions 4 has an advantage that the binding band 3 can be easily hung on the semiconductor integrated circuit tray 1. These protrusions 4 are preferably formed of a material that is not easily broken.

  In the embodiment shown in FIG. 5B, one of the two protrusions 4a extending from both sides of the opening position of the notch 2 is formed longer than the other protrusion 4b. By being formed in this way, the binding band 3 after being hung on the notch 2 is firmly supported by at least the longer projection 4a, so that it is almost impossible to manually remove the binding band. It becomes possible. Therefore, there is little fear that the IC (PKG) placed on the semiconductor integrated circuit tray 1 will be stolen.

  The packaging process of the semiconductor integrated circuit tray will be described with reference to FIG. It should be noted that FIG. 6 focuses on explanation and differs from the actual dimensions. FIG. 6A is a plan view showing a conventional semiconductor integrated circuit tray 6 in which a plurality of pockets 5 for accommodating a semiconductor integrated circuit 7 such as an IC are formed. A plurality of concave pockets 5 for accommodating a semiconductor integrated circuit 7 such as an IC are formed in the semiconductor integrated circuit tray 6. FIG. 6B is a diagram schematically illustrating a conventional packing process.

  As shown in FIG. 6A, the packing worker first places the semiconductor integrated circuit 7 in the pocket 5 formed in the semiconductor integrated circuit tray 6, and then, as shown in FIG. 6B. In addition to a predetermined number of trays (often 5 or 10) on which the semiconductor integrated circuit 7 is placed, one tray is stacked on the top as a lid, Tie it up with tie band 3. Next, as shown in FIG. 6 (c), the packing operator wraps a cushioning sheet (air packing or the like) 8 around the stacked trays 6 and then puts it in the cardboard box 9 to form a series. Complete the packaging work.

  As shown in FIG. 6B, the arm hanging portion 1a formed on the conventional tray 6 (in the case of a JEDEC standard semiconductor integrated circuit tray, 1 inch wide (about 2.54 cm) wide, depth 0. One inch (about 0.254 cm) is a grip portion when the robot arm or the like grips the tray 6 in the process of manufacturing, measuring, and the like of the semiconductor integrated circuit. The arm hanging portion 1a has a shape that makes it easy to hang the binding band 3. However, in the present very thin semiconductor integrated circuit tray, it is possible to hang the binding band 3 on the arm hanging portion 1a. Since the thickness of the portion 1a is particularly thin and weak, it is not desirable. For example, when a binding band is wound around a tray 6 made of polyphenylene ether (PPE) with a predetermined amount of force (for example, a force of 23 kg weight) using a machine, a force is applied near the center of the stacked tray 6. Is excessively added, and the tray 6 bends, and the gap 10 between the stacked trays 6 is enlarged (see FIGS. 6B and 6C).

  In contrast, in the present invention, a plurality of trays are provided along at least one of the upper and lower sides at four locations within 3.4 cm from the end edges of the two side surfaces extending in the longitudinal direction of the tray 1. By forming the notch for hanging the binding band to be bundled, the deflection (deformation) of the trays 1 bundled using the binding band is minimized. Therefore, even if a large impact is received in the drop test, the occurrence of gaps or deviations between the trays 1 can be minimized, so that the IC or the like on the tray 1 is not damaged ( (Refer FIG.7 (b)).

  In another embodiment of the present invention shown in FIG. 8, notches are only formed along the upper and lower sides at four locations within 3.4 cm from each edge of the side surface of the semiconductor integrated circuit tray 1. Instead, additional notches are formed along the upper and lower sides near the center of the side surface. As shown in FIG. 8, when additional cutouts are formed near the center of the side surface, a plurality of trays 1 are completely brought into close contact with each other by hanging four binding bands on these cutouts. It becomes possible.

DESCRIPTION OF SYMBOLS 1 ... (Invention) semiconductor integrated circuit tray 1a ... Arm hanging part 2 ... Notch 2a ... Groove 3 ... Bundling band 4 ... Projection 4a ... Projection 4b ... Projection 5 ... Pocket 5a ... Front guide (wall)
6 ... (Conventional) Tray for semiconductor integrated circuit 6a ... Back guide (wall)
7 ... Semiconductor integrated circuit 8 ... Buffer sheet 9 ... Cardboard box 10 ... Gap
11 ... Interlock function section

Claims (3)

A tray for a semiconductor integrated circuit having a substantially rectangular shape in plan view,
Notches for hanging a binding band for bundling a plurality of trays along at least one of the upper and lower sides at four locations within 3.4 cm from the edges of the two side surfaces extending in the longitudinal direction of the tray. A tray for a semiconductor integrated circuit having a notch for a binding band, which is formed.   The side surface of the tray for the semiconductor integrated circuit is recessed from the upper side to the lower side at the position of the notch, so that a groove having substantially the same width as the width of the notch is formed on the side surface. Item 12. A semiconductor integrated circuit tray having the binding band cutout according to Item 1. 3. The tray for a semiconductor integrated circuit having a notch for a binding band according to claim 1 or 2, wherein the protrusions extend from both sides of the opening position of the notch so as to approach each other.

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