JP2018085709A - Reading control circuit, solid-state imaging element, and method of driving imaging element - Google Patents

Abstract

【Task】
In the case of reading a large number of pixels at a high frame frequency, it is possible to realize excellent moving image capturing characteristics and resolution characteristics, enabling linear and high S / N signal acquisition without reducing the saturation level at low illumination, At high illuminance, it is possible to obtain a good S / N signal in the linear region and to expand the dynamic range.
[Solution]
The signal from the photodiode (PD) 111 is input via the transfer gate (TX) 112, the floating diffusion capacitor (FD1) 113 having a small capacitance and a large conversion gain, and the signal from the (FD1) 113 is an overflow gate ( Of floating diffusion capacitance (FD2) 123, which is inputted via OFG) 122 and has a large capacitance and a small conversion gain. Both (FD1) 113 and (FD2) 123 have their own pixel output circuits (OUT1, 2). 117 and 127, and each output unit outputs a signal corresponding to a specific signal output line (204A, B).
[Selection] Figure 1

Description

  The present invention relates to a readout control circuit, a solid-state imaging device, and a driving method of the imaging device. The present invention relates to a readout control circuit, a solid-state imaging device, and a driving method of the imaging device that output as possible.

  Conventionally, in a solid-state imaging device, for example, a CMOS image sensor, a substantially linear output signal is obtained according to the value of signal charge accumulated in a unit pixel by photoelectric conversion. The dynamic range is determined from the noise ratio.

  In such a solid-state image sensor, when the camera lens aperture is adjusted to a low-luminance subject, the signal of the high-luminance subject is saturated, and conversely, when the camera lens aperture is adjusted to a high-luminance subject, the low-luminance subject is Therefore, an image element having a sufficiently wide dynamic range capable of obtaining a good image with either high luminance or low luminance has been demanded.

In addition to simply expanding the dynamic range, it has been required to expand the dynamic range after satisfying the following items (1) to (4). That is, (1) the resolution characteristics can be improved without dividing the photoelectric conversion unit, (2) the moving image imaging characteristics can be improved without dividing the exposure time, (3) high sensitivity, There is a need to be able to eliminate the trade-off between high S / N and wide dynamic range, and (4) to be able to read high frame frequencies in super-multiple pixels.

  Here, in order to expand the dynamic range of the output signal amount with respect to the incident light quantity, two signals obtained by the long exposure and the short exposure from the same pixel are read out a plurality of times, and the read out sensitivity is different. Is known by a signal processing unit downstream of the image sensor (see Patent Document 1 and Non-Patent Document 1).

  Further, in the prior art shown in FIG. 22, each pixel includes a photodiode PD that receives light to generate a photocharge, a transfer transistor T that transfers a photocharge provided adjacent to the PD, A floating diffusion FD provided connected to the PD via T, and a first storage capacitor CSa and a second storage capacitor CSb for storing photocharges overflowing from the PD during the exposure accumulation operation through the T; . In addition to the storage capacitors CSa and CSb, a reset transistor R for discharging signal charges in the FD, a first storage transistor Ca provided between the FD and the CSa, and the CSa A second storage transistor Cb provided between the CSb, an amplification transistor SF for reading out signal charges of the FD, the CSa, and the CSb as voltages, and a pixel or a pixel block provided in connection with the SF And a selection transistor X for selecting.

In the conventional technology configured as described above, a plurality of pixels having the above-described configuration are integrated in a two-dimensional or one-dimensional array. In each pixel, the transfer transistor T, the first storage transistor Ca, the second Each drive line is connected to the gate electrodes of the storage transistor Cb and the reset transistor R, the pixel selection line driven from the row shift register is connected to the gate electrode of the selection transistor X, and the output of the selection transistor X One output line OUT is connected to the side source and controlled by the column shift register, and any signal is output through this one output line OUT (see Patent Document 2).
Japanese Patent No. 3680366 Japanese Patent No. 5066704 Orly Yadid-Pecht and Eric R. Fossum, “Wide Intrascene Dynamic Range CMOS APS Using Dual Sampling”, IEEE TRANSACTIONS ON ELECTRON DEVICES, Vol.44, No.10, pp.1721-1723, Oct., 1997.

However, in the conventional technique described in Patent Document 1 and the like, the signal amount is not doubled in the method of synthesizing the signals by the long exposure and the short exposure, but the readout noises are each integrated. Since it becomes twice, the S / N deteriorates particularly at low illuminance.
In addition, since the long exposure and the short exposure are imaged at different timings, there is a problem that the imaging time is shifted and subjects moving at high speed appear to be shifted from each other. In addition, since the number of readings per pixel is a plurality of times, the maximum frame frequency is lowered.

  Further, the conventional technique described in Patent Document 2 is a method of reading a pre-saturation signal and a supersaturation signal using a storage capacitor element. Since the number of times of readout per pixel is a plurality of times, the maximum frame frequency is lowered. .

  The present invention has been made in view of the above circumstances, and can realize excellent moving image capturing characteristics and resolution characteristics, and enables linear and high S / N signal acquisition without reducing the saturation level at low illuminance. In a high illuminance, a readout control circuit, a solid-state imaging device, which can enable a good S / N in the linear region, can increase the dynamic range, and can suppress a decrease in the maximum frame frequency, It is another object of the present invention to provide a method for driving an image sensor.

The read control circuit of the present invention comprises:
In the readout control circuit of the solid-state imaging device, a first floating diffusion capacitance unit that accumulates signals from the photoelectric conversion unit and has a small capacitance and a large conversion gain;
A second floating diffusion capacitor means having a large capacitance and a small conversion gain, in which a signal from the first floating diffusion capacitor means is inputted and stored via an overflow gate;
The first floating diffusion capacitance means and the second floating diffusion capacitance means both have a unique pixel output circuit.
Further, each of the first floating diffusion capacitance means is configured by using four transistors including a transfer transistor, and each of the second floating diffusion capacitance means is configured by using four transistors including an overflow gate. be able to.
Further, each of the first floating diffusion capacitor means is configured by using three transistors not including a transfer transistor, and each of the second floating diffusion capacitor means is configured by using four transistors including an overflow gate. can do. In this case, it is preferable that the photoelectric conversion part is composed of a photoelectric conversion film.

Moreover, the solid-state imaging device of the present invention is
A read control circuit as described above;
And an output unit provided in accordance with the pixel output circuit for outputting an output signal from each of the unique pixel output circuits to a corresponding output signal line.

Further, the driving method of the image sensor of the present invention is as follows:
A driving method for driving the solid-state imaging device described above,
When the first floating diffusion capacitance means and the second floating diffusion capacitance means are reset and photoelectrons move from the photoelectric conversion unit to the first floating diffusion capacitance means during a signal accumulation period,
When the gate voltage of the overflow gate is set to a predetermined value, the saturation capacity of the first floating diffusion capacitor means is set, and when photoelectrons overflow from the first floating diffusion capacitor means, the overflow electrons are transferred to the first floating diffusion capacitor means. Each of the first floating diffusion capacitance means and the second floating diffusion capacitance means, the signal voltage determined by the amount of photoelectrons and the conversion gain for each pixel output signal by the corresponding source follower element. Thereafter, the two pixel output signals are output to the corresponding output signal lines.

  According to the readout control circuit and the solid-state imaging device of the present invention, the first floating diffusion capacitance means has a small capacitance and a large conversion gain, so that a linear and high S / N signal can be obtained without reducing the saturation level at low illuminance. Can be obtained. The signal charge overflowing from the first floating diffusion capacitor means flows to the second floating diffusion capacitor means through the overflow gate. Since the second floating diffusion capacitance means has a large capacitance and a small conversion gain, the dynamic range can be expanded while realizing a good S / N in the linear region even at high illuminance.

By synthesizing the two signals output from the solid-state imaging device by a signal processing unit at the subsequent stage, a signal having a high S / N in a low illuminance state and a wide dynamic range in a high illuminance state can be obtained.
These two signals are excellent in moving image capturing characteristics and resolution characteristics because an optical signal is acquired by the same photoelectric conversion unit at the same time.
It should be noted that a plurality of pixel output circuits and signal output lines are provided, and one column signal processing circuit can be provided for each output line, thereby suppressing a decrease in the maximum frame frequency.
The effects of the invention described above can be similarly achieved by the method for driving the image sensor of the present invention.

1 is an equivalent circuit diagram of a unit pixel according to Embodiment 1. FIG. 1 shows a system configuration diagram of a solid-state imaging device having a pixel array of unit pixels according to Embodiment 1. FIG. 3 is a time chart of an input signal to the pixel circuit when signal readout is performed using the pixel circuit of Example 1 illustrated in FIG. 1. 1 illustrates an example of a schematic plan view of a unit pixel according to Embodiment 1. FIG. Regarding Example 1, (A) shows a potential diagram at the time of exposure at low illuminance, and (B) shows a potential diagram at the time of movement of a signal charge at low illuminance. Regarding Example 1, (A) shows a potential diagram at the time of exposure at high illuminance, and (B) shows a potential diagram at the time of movement of a signal charge at high illuminance. Regarding Example 1, (A) shows a signal output from the pixel circuit via the first floating diffusion capacitor (FD1) with a high conversion gain and a pixel circuit via a second floating diffusion capacitor (FD2) with a low conversion gain. It is a figure which shows the relationship with respect to incident light intensity | strength with the signal output, (B) is a figure which shows the relationship with respect to incident light intensity of the output signal after a synthesis | combination after synthesize | combining in the signal processing part of a back | latter stage. FIG. 6 is a plan view showing a result of unit pixel potential simulation according to the first embodiment. FIG. 9 is a sectional view taken along line B-B ′ in FIG. 8. FIG. 9 is a sectional view taken along line C-C ′ of FIG. 8. FIG. 6 is an equivalent circuit diagram of a unit pixel according to the second embodiment. FIG. 3 is a system configuration diagram of a solid-state imaging device having a pixel array of unit pixels according to a second embodiment. 12 is a time chart of an input signal to a pixel circuit when signal readout is performed using the second embodiment shown in FIG. FIG. 5 shows an example of a schematic plan view of a unit pixel according to Embodiment 2. FIG. Regarding Example 2, (A) shows a potential diagram when signal charges move at low illuminance, and (B) shows a potential diagram when signal charges move at high illuminance. FIG. 10 is a plan view showing a result of unit pixel potential simulation according to the second embodiment. FIG. 17 is a sectional view taken along line B-B ′ of FIG. 16. FIG. 17 is a sectional view taken along line C-C ′ of FIG. 16. FIG. 10 is an equivalent circuit diagram of a unit pixel according to the third embodiment. FIG. 20 is a time chart of an input signal to a pixel circuit when signal readout is performed using the third embodiment illustrated in FIG. 19. FIG. FIG. 7 shows an example of a schematic plan view and a schematic cross-sectional view of a unit pixel according to Example 3. FIG. FIG. 2 is an equivalent circuit diagram of a single pixel of a solid-state imaging device according to a conventional technique.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
<Example 1>
FIG. 2 is a system configuration diagram of a solid-state imaging device having a pixel array of unit pixels, specifically, a CMOS image sensor. The CMOS image sensor 200 has a pixel array 201 in which unit pixels 202 including photoelectric conversion elements are two-dimensionally arranged in an array and connected to a pixel drive wiring 203 and a vertical signal line 204, and a column signal as a peripheral circuit. The processing circuit 205, output circuit 206, control circuit 207, horizontal scanning circuit 208, and vertical scanning circuit 209 are configured.
Here, the reason why the column signal processing circuit 205 and the horizontal scanning circuit 208 are arranged above and below in the drawing is that the frame frequency can be doubled compared to the case where they are arranged on one side. Because.

FIG. 1 is an equivalent circuit diagram of a pixel circuit (reading control circuit) used in the CMOS image sensor according to the first embodiment.
As shown in FIG. 1, the read control circuit in this embodiment includes two signal paths, a first signal path and a second signal path.

  As shown in FIG. 1, a photodiode (PD) 111 that is a photoelectric conversion element is connected to a first floating diffusion capacitor (FD1) 113 via a transfer transistor (TX) 112. The first floating diffusion capacitor (FD1) 113 is connected to the second floating diffusion capacitor (FD2) 123 via the overflow gate (OFG) 122.

  The pixel output circuit of the first floating diffusion capacitor (FD1) 113, which is the first signal path, includes a reset transistor 1 (RT1) 114, a source follower transistor 1 (SF1) 115, and a selection transistor 1 (SL1) 116. The pixel output 1 (OUT1) 117 is connected to the vertical signal line 204A.

On the other hand, the pixel output circuit of the second floating diffusion capacitor (FD2) 123, which is the second signal path, includes a reset transistor 2 (RT2) 124 and a source follower transistor 2 (SF2).
125 and the selection transistor 2 (SL2) 126, and the pixel output 2 (OUT2) 127 is connected to a vertical signal line 204B different from the above.

  The drain electrodes of the reset transistor 1 (RT1) 114, the source follower transistor 1 (SF1) 115, the reset transistor 2 (RT2) 124, and the source follower transistor 2 (SF2) 125 are connected to a pixel power supply (VDD) 118. .

  The gates of the transfer transistor (TX) 112, the overflow gate (OFG) 122, the reset transistor 1 (RT1) 114, the reset transistor 2 (RT2) 124, the selection transistor 1 (SL1) 116, and the selection transistor 2 (SL2) 126 The electrode is connected to each pixel drive wiring 203.

  In the pixel circuit (reading control circuit) of the unit pixel 202 shown in FIG. 1, the photodiode (PD) 111 accumulates an amount of negative charge corresponding to the intensity of incident light. The anode of the photodiode (PD) 111 is grounded, and the cathode is connected to the gate of the source follower transistor 1 (SF1) 115 via the transfer transistor (TX) 112 and the first floating diffusion capacitor (FD1) 113. . The gate of the transfer transistor (TX) 112 is connected to the pixel drive wiring 203 (TX) from the vertical operation circuit 209, and a transfer signal is input thereto.

  In the first signal path, the source follower transistor 1 (SF1) 115 and the selection transistor 1 (SL1) 116 are connected in series between the pixel power supply (VDD) 118 and the pixel output 1 (OUT1) 117. The gate of the selection transistor 1 (SL1) 116 is connected to the pixel drive wiring 203 (SL1) from the vertical operation circuit 209, and a selection signal is input thereto. The reset transistor 1 (RT1) 114 is connected between the pixel power supply (VDD) 118 and the gate of the source follower transistor 1 (SF1) 115. The gate of the reset transistor 1 (RT1) 114 is connected to the pixel drive wiring 203 (RT1) from the vertical operation circuit 209 and receives a reset signal.

The first floating diffusion capacitor (FD1) 113 is connected to the gate of the source follower transistor 1 (SF1) 115.
As described above, the second floating diffusion capacitor (FD2) 123 is connected to the first floating diffusion capacitor (FD1) 113 via the overflow gate (OFG) 122, and the first floating diffusion capacitor (FD1). When the charge accumulated in 113 overflows from the overflow gate (OFG) 122, it is input to the second floating diffusion capacitor (FD 2) 123.

  In the second signal path, the source follower transistor 2 (SF2) 125 and the selection transistor 2 (SL2) 126 are connected in series between the pixel power supply (VDD) 118 and the pixel output 2 (OUT2) 127. The gate of the selection transistor 2 (SL2) 126 is connected to the pixel drive wiring 203 (SL2) from the vertical operation circuit 209, and a selection signal is input thereto. The reset transistor 2 (RT2) 124 is connected between the pixel power supply (VDD) 118 and the gate of the source follower transistor 2 (SF2) 125. The gate of the reset transistor 2 (RT2) 124 is connected to the pixel drive wiring 203 (RT2) from the vertical operation circuit 209 and receives a reset signal.

The second floating diffusion capacitor (FD2) 123 is connected to the gate of the source follower transistor 2 (SF2) 125.
FIG. 3 is a time chart showing an input signal of each transistor when signal reading is performed using the pixel circuit (reading control circuit) 202 shown in FIG.

In FIG. 3, each chart shows select transistors 1, 2 (SL1, 2) 116, 126.
, Reset transistors 1 and 2 (RT1 and 2) 114 and 124, first transfer transistor (TX) 112, and overflow gate (OFG) 122 are shown in signal waveforms, and SL, RT, TX and OFG are shown in the subsequent stage. The numbers ((1) to (n)) in the parentheses indicated indicate unit pixels from the first row to the n-th row on the corresponding line (row).

As shown in FIG. 3, when the selection transistors 1, 2 (SL1, 2) 116, 126 are in the on state (SL1 and SL2 are at “H” level), the reset transistors 1, 2 (RT1, 2) 114, 124 are turned on. The first and second floating diffusion capacitors (FD1, 2) 113 and 123 are reset by turning on (RT1 and RT2 are at “H” level). This is the same for all rows.
When the transfer transistor (TX) 112 is turned on (TX (1) is at “H” level), the signal charge of the photodiode (PD) 111 passes through the transfer transistor (TX) 112 and the first floating diffusion capacitance ( It moves to (FD1) 113 and is converted into a signal voltage by the first floating diffusion capacitor (FD1) 113. When signal charges exceeding the saturation capacity of the first floating diffusion capacitor (FD1) 113 flow in, the signal charge moves to the second floating diffusion capacitor (FD2) 123 via the overflow gate (OFG) 122, and this second The floating diffusion capacitance (FD2) 123 is converted into a signal voltage.

Here, the conversion gain is set high by reducing the capacitance of the first floating diffusion capacitor (FD1) 113, and the conversion gain is set low by increasing the capacitance of the second floating diffusion capacitance (FD2) 123.
The gate voltage (threshold value) of the overflow gate (OFG) 122 is fixed to a predetermined constant value after adjusting the voltage value in order to set the saturation capacitance of the first floating diffusion capacitor (FD1) 113 to a predetermined value. . The signal voltages of the first floating diffusion capacitor (FD1) 113 and the second floating diffusion capacitor (FD2) 123 are applied to the gate electrodes of the source follower transistor 1 (SF1) 115 and the source follower transistor 2 (SF2) 125, respectively. Output currents from the source follower transistor 1 (SF1) 115 and the source follower transistor 2 (SF2) 125 are output from the pixel output 1 (OUT1) and the pixel output 2 (OUT2) to separate vertical signal lines 204A and 204B.

FIG. 4 shows an example of a schematic plan view of a unit pixel according to the first embodiment, which corresponds to the equivalent circuit diagram of the unit pixel of FIG.
That is, in this schematic plan view, the photodiode (PD) 111 is connected via the transfer transistor (TX) 112, the first floating diffusion capacitor (FD1) 113, the reset transistor 1 (RT1) 114, and the pixel power supply (VDD) 118. The source follower transistor 1 (SF1) 115 is connected to the gate. The source follower transistor 1 (SF1) 115 is connected to the pixel output 1 (OUT1) 117 via the selection transistor 1 (SL1) 116.

  On the other hand, in this schematic plan view, the photodiode (PD) 111 includes a transfer transistor (TX) 112, an overflow gate (OFG) 122, a second floating diffusion capacitor (FD2) 123, a reset transistor 2 (RT2) 124, a pixel. It is shown that it is connected to the gate of the source follower transistor 2 (SF2) 125 via a power supply (VDD) 118. The source follower transistor 2 (SF2) 125 is connected to the pixel output 2 (OUT2) 127 via the selection transistor 2 (SL2) 126.

FIG. 5 shows a cross section taken along the line AA ′ in the schematic plan view of FIG. 4 for the case of low illuminance. (A) is for exposure, and (B) is for movement of signal charge. It is shown.
In addition, the name of the site | part in which each potential is shown is shown by the symbol above the site | part (same in FIG. 6).
In addition, the portion indicated by cross-hatching in the drawing originally shows the amount of electrons existing in the first floating diffusion capacitance (FD1) 113 and the second floating diffusion capacitance (FD2) 123, and is shown in satin. The portion indicates the amount of photoelectrons flowing into or from the photodiode (PD) 111 (same in FIG. 6).
As is clear from these figures, when the illuminance is low, the amount of photoelectrons in the photodiode (PD) 111 is small. Therefore, when the transfer transistor (TX) 112 is on, the photoelectrons are in the first floating diffusion. It moves only to the capacitor (FD1) 113 and does not move to the second floating diffusion capacitor (FD2) 123. Therefore, the second floating diffusion capacitor (FD2) 123 remains at the original voltage VDD.

On the other hand, FIG. 6 shows a cross section taken along the line AA ′ in the schematic plan view of FIG. 4 in the case of high illuminance. (A) is for exposure, and (B) is for movement of signal charge. , Respectively.
As is clear from these figures, when the illumination is high, the amount of photoelectrons in the photodiode (PD) 111 is large, so that when the transfer transistor (TX) 112 is on, the photoelectrons are in the first floating diffusion. Simultaneously with the movement to the capacitor (FD1) 113, the first floating diffusion capacitor (FD1) 113 overflows and moves to the second floating diffusion capacitor (FD2) 123. For this reason, in the second floating diffusion capacitor (FD2) 123, the amount of photoelectrons is increased from the original voltage VDD.

FIG. 7A shows a high conversion gain signal output from the pixel output circuit via the first floating diffusion capacitor FD1 (113) and output from the pixel output circuit via the second floating diffusion capacitor FD2 (123). It is a figure which shows the relationship with respect to the incident light intensity | strength of the signal of the low conversion gain performed.
In FIG. 7B, the signal of the high conversion gain (FD1) and the signal of the low conversion gain (FD2) are combined in a signal processing unit (not shown) at the subsequent stage outside the solid-state imaging device. It is a figure which shows a signal (output signal after a synthesis | combination) in relation to incident light intensity.
As can be seen from FIG. 7A, the signal of the high conversion gain (FD1) is saturated at a constant output value (saturation point), and at this incident light intensity, just the low conversion gain (FD2). Therefore, the two signals may be combined at the rising point of the low conversion gain (FD2) signal.
As shown in the figure, the combined signal has a large slope at low illuminance and high S / N, while the slope is small at high illuminance and has a wide dynamic range. Therefore, two contradictory characteristics can be exhibited by one signal. Therefore, the signal of a high-brightness subject is saturated by matching to a low-brightness subject, or the signal of a low-brightness subject is buried in noise by matching to a high-brightness subject. It can be avoided.
Furthermore, in this embodiment, the resolution characteristics can be made excellent without dividing the photoelectric conversion unit, the moving image pickup characteristics can be made excellent without dividing the exposure time, and the sensitivity and the high The trade-off between S / N and wide dynamic range can be eliminated.

Next, FIG. 8 is a plan view showing the result of the potential simulation of the unit pixel. The gate electrode of the transfer transistor (TX) 112 is 2.5 V, the gate electrode of the overflow gate (OFG) 122 is 1.9 V, the reset transistor 1 (RT1) 114, the reset transistor 2 (RT2) 124, and the source follower transistor 1 0 V is applied to the gate electrodes of (SF1) 115, source follower transistor 2 (SF2) 125, selection transistor 1 (SL1) 116, and selection transistor 2 (SL2) 126.
In FIG. 8, the numbers of the respective parts in FIG. 8 are omitted in order to avoid difficulty in seeing lines and the like representing the respective parts due to the complexity of inserting characters.

FIG. 9 is a sectional view taken along line BB ′ in FIG. In the example of FIG. 9, a photoelectron is empty in the photodiode (PD) 111.
That is, in the cross section taken along the line BB ′, it is shown that the photodiode (PD) 111 is in an empty state because no electrons are accumulated at the bottom of the conduction band. On the other hand, under the first floating diffusion capacitor (FD1) 113 and the transfer transistor (TX) 112, a state in which a predetermined amount of electrons are contained is shown.

On the other hand, FIG. 10 is a cross-sectional view taken along the line CC ′ in FIG. In the example of FIG. 10, the first floating diffusion capacitor (FD1) 113 shows a state where electrons are saturated.
That is, the first floating diffusion capacitor (FD1) 113 is in a saturated state (the overflow gate (OFG) 122 is full), and no more photoelectrons enter the first floating diffusion capacitor (FD1) 113. Then, the photoelectrons flow into the second floating diffusion capacitor (FD2) 123. In the state shown in FIG. 10, the second floating diffusion capacitor (FD2) 123 is in the state of VDD = 3.3V and is in the original electron state, and is from the first floating diffusion capacitor (FD1) 113. The photoelectrons have not yet flowed in.
<Example 2>

Hereinafter, Example 2 of the present invention will be described with reference to the drawings.
In addition, since the thing of Example 2 has many parts in common with the thing of Example 1, in the following description, the number which added 200 to the number attached | subjected to each part of Example 1 respond | corresponded to each part of Example 1. It attaches | subjects to each part of Example 2, and the detailed description may be abbreviate | omitted.
FIG. 12 shows a system configuration of a solid-state imaging device having a pixel array of unit pixels according to the second embodiment, specifically, a CMOS image sensor, and corresponds to FIG. 2 showing the first embodiment. . The CMOS image sensor 400 includes a pixel array 401 in which unit pixels 402 including photoelectric conversion elements are two-dimensionally arranged in an array and connected to a pixel drive wiring 403 and a vertical signal line 404, and a column signal as a peripheral circuit. It comprises a processing circuit 405, an output circuit 406 connected to the digital CDS circuit 410 outside the sensor, a control circuit 407, a horizontal scanning circuit 408, and a vertical scanning circuit 409.
Here, the reason why the column signal processing circuit 405 and the horizontal scanning circuit 408 are arranged above and below in the drawing is that the frame frequency can be doubled compared to the case where they are arranged on one side. Because.

FIG. 11 is an equivalent circuit diagram of a pixel circuit (reading control circuit) used in the CMOS image sensor according to the second embodiment. In this equivalent circuit, the pixel circuit that reads the signal charge from the photoelectric conversion unit is provided for the first floating diffusion capacitor means, and since no transfer transistor is provided, the three transistors and the second floating diffusion capacitor means are provided. It is composed of four transistors including an overflow gate, and is configured to generate a signal in a high S / N state in a low illuminance state and a wide dynamic range state in a high illuminance state.
As shown in FIG. 11, the read control circuit according to the second embodiment includes two signal paths, ie, a first signal path and a second signal path.

  As shown in FIG. 11, a photodiode (PD) 311 that is a photoelectric conversion element is connected to a first floating diffusion capacitor (FD1) 313. The first floating diffusion capacitor (FD1) 313 is connected to the second floating diffusion capacitor (FD2) 323 via the overflow gate (OFG) 322.

The pixel output circuit of the first floating diffusion capacitor (FD1) 313, which is the first signal path, includes a reset transistor 1 (RT1) 314, a source follower transistor 1 (SF1) 315, and a selection transistor 1 (SL1) 316. The pixel output 1 (OUT1) 317 is connected to the vertical signal line 404A.

  On the other hand, the pixel output circuit of the second floating diffusion capacitor (FD2) 323, which is the second signal path, includes a reset transistor 2 (RT2) 324, a source follower transistor 2 (SF2) 325, and a selection transistor 2 (SL2) 326. The pixel output 2 (OUT2) 327 is connected to a vertical signal line 404B different from the above.

  The drain electrodes of the reset transistor 1 (RT1) 314, the source follower transistor 1 (SF1) 315, the reset transistor 2 (RT2) 324, and the source follower transistor 2 (SF2) 325 are connected to a pixel power supply (VDD) 318. .

  The gate electrodes of the overflow gate (OFG) 322, the reset transistor 1 (RT1) 314, the reset transistor 2 (RT2) 324, the selection transistor 1 (SL1) 316, and the selection transistor 2 (SL2) 326 are driven by the respective pixels. It is connected to the wiring 403.

  In the pixel circuit (reading control circuit) of the unit pixel 402 shown in FIG. 11, the photodiode (PD) 311 generates an amount of negative charge corresponding to the intensity of incident light. The anode of the photodiode (PD) 311 is grounded, and the cathode is connected to the gate of the source follower transistor 1 (SF1) 315 via the first floating diffusion capacitor (FD1) 313.

  In the first signal path, the source follower transistor 1 (SF1) 315 and the selection transistor 1 (SL1) 316 are connected in series between the pixel power supply (VDD) 318 and the pixel output 1 (OUT1) 317. The gate of the selection transistor 1 (SL1) 316 is connected to the pixel drive wiring 403 (SL1) from the vertical operation circuit 409, and a selection signal is input thereto. The reset transistor 1 (RT1) 314 is connected between the pixel power supply (VDD) 318 and the gate of the source follower transistor 1 (SF1) 315. The gate of the reset transistor 1 (RT1) 314 is connected to the pixel drive wiring 403 (RT1) from the vertical operation circuit 409 and receives a reset signal.

The first floating diffusion capacitor (FD1) 313 is connected to the gate of the source follower transistor 1 (SF1) 315.
As described above, the second floating diffusion capacitor (FD2) 323 is connected to the first floating diffusion capacitor (FD1) 313 via the overflow gate (OFG) 322, and the first floating diffusion capacitor (FD1). When the charge accumulated in 313 overflows from the overflow gate (OFG) 322, the charge is input to the second floating diffusion capacitor (FD 2) 323.

  In the second signal path, the source follower transistor 2 (SF2) 325 and the selection transistor 2 (SL2) 326 are connected in series between the pixel power supply (VDD) 318 and the pixel output 2 (OUT2) 327. The gate of the selection transistor 2 (SL2) 326 is connected to the pixel drive wiring 403 (SL2) from the vertical operation circuit (numbered 409 in FIG. 12; the same applies hereinafter), and a selection signal is input thereto. The reset transistor 2 (RT2) 324 is connected between the pixel power supply (VDD) 318 and the gate of the source follower transistor 2 (SF2) 325. The gate of the reset transistor 2 (RT2) 324 is connected to the pixel drive wiring 403 (RT2) from the vertical operation circuit 409 and receives a reset signal.

The second floating diffusion capacitor (FD2) 323 is connected to the gate of the source follower transistor 2 (SF2) 325.
FIG. 13 is a time chart showing the input signal of each transistor when signal reading is performed using the pixel circuit (reading control circuit) 402 shown in FIG.

  In FIG. 13, each chart shows signal waveforms of the selection transistors 1, 2 (SL1, 2) 316, 326, the reset transistors 1, 2 (RT1, 2) 314, 324, and the overflow gate (OFG) 322. , SL, RT, and the numbers in parentheses after the OFG ((1) to (n)) indicate unit pixels in the first to nth rows on the corresponding line (row). Yes. ADC indicates the sampling timing of the AD converter. In the prior art, when the pixel circuit is composed of three transistors, the reset noise is removed from the driving waveform by digital correlation double sampling (digital CDS) of the post-reset method. Since this method is an improvement over the case where the pixel circuit is composed of three transistors, reset noise is removed from the drive waveform by a digital CDS of a post-reset method.

As shown in FIG. 13, when the selection transistors 1, 2 (SL1, 2) 316, 326 are in the ON state (SL1 and SL2 are at “H” level), the reset transistors 1, 2 (RT1, 2) 314, 324 are turned on. The first and second floating diffusion capacitors (FD1, 2) 313, 323 are reset by turning on (RT1 and RT2 are at “H” level). This is the same for all rows.
The signal charge of the photodiode (PD) 311 moves to the first floating diffusion capacitor (FD1) 313 and is converted into a signal voltage by the first floating diffusion capacitor (FD1) 313. When signal charges exceeding the saturation capacity of the first floating diffusion capacitor (FD1) 113 flow in, the signal charge moves to the second floating diffusion capacitor (FD2) 323 via the overflow gate (OFG) 322, and this second The floating diffusion capacitance (FD2) 323 is converted into a signal voltage.

Here, the conversion gain is set high by reducing the capacitance of the first floating diffusion capacitance (FD1) 313, and the conversion gain is set low by increasing the capacitance of the second floating diffusion capacitance (FD2) 323.
The gate voltage (threshold value) of the overflow gate (OFG) 322 is fixed to a predetermined constant value after adjusting the voltage value in order to set the saturation capacity of the first floating diffusion capacitor (FD1) 313 to a predetermined value. . The signal voltages of the first floating diffusion capacitor (FD1) 313 and the second floating diffusion capacitor (FD2) 323 are applied to the gate electrodes of the source follower transistor 1 (SF1) 315 and the source follower transistor 2 (SF2) 325, respectively. Output currents from the source follower transistor 1 (SF1) 315 and the source follower transistor 2 (SF2) 325 are output from the pixel output 1 (OUT1) and the pixel output 2 (OUT2) to separate vertical signal lines 404A and 404B.

FIG. 14 shows an example of a schematic plan view of a unit pixel according to the second embodiment, which corresponds to the equivalent circuit diagram of the unit pixel of FIG.
That is, in this schematic plan view, the photodiode (PD) 311 includes the source follower transistor 1 (SF1) via the first floating diffusion capacitor (FD1) 313, the reset transistor 1 (RT1) 314, and the pixel power supply (VDD) 318. ) Connected to the gate of 315. The source follower transistor 1 (SF1) 315 is connected to the pixel output 1 (OUT1) 317 via the selection transistor 1 (SL1) 316.

  On the other hand, in this schematic plan view, the photodiode (PD) 311 includes an overflow gate (OFG) 322, a second floating diffusion capacitor (FD2) 323, a reset transistor 2 (RT2) 324, and a pixel power supply (VDD) 318. The source follower transistor 2 (SF2) 325 is connected to the gate. The source follower transistor 2 (SF2) 325 is connected to the pixel output 2 (OUT2) 327 via the selection transistor 2 (SL2) 326.

FIG. 15A shows a cross-sectional view taken along the line AA ′ of FIG. 14, which is a schematic plan view, in the case of low illuminance, and shows when signal charges move.
In addition, the name of the site | part in which each potential is shown is shown by the symbol above the site | part.
In addition, the portion indicated by cross hatching in the figure indicates the amount of electrons existing in the first floating diffusion capacitance (FD1) 313 and the second floating diffusion capacitance (FD2) 323, and the portion indicated by satin is This shows the amount of photoelectrons flowing from the photodiode (PD) 311.
As is clear from these figures, when the illumination is low, the amount of photoelectrons generated in the photodiode (PD) 311 is small, so that the photoelectrons only move to the first floating diffusion capacitor (FD1) 313. It does not move to the second floating diffusion capacitor (FD2) 323. Therefore, the second floating diffusion capacitance (FD2) 323 remains at the original voltage VDD.

On the other hand, FIG. 15B shows a cross section taken along the line AA ′ of the potential diagram in FIG. 14 in the case of high illuminance, and shows the movement of the signal charge.
As is clear from these figures, when the illuminance is high, the amount of photoelectrons generated in the photodiode (PD) 311 is large, so that the photoelectrons move to the first floating diffusion capacitor (FD1) 313 at the same time. The first floating diffusion capacitor (FD1) 313 overflows and moves to the second floating diffusion capacitor (FD2) 323. For this reason, in the second floating diffusion capacitor (FD2) 323, the amount of photoelectrons is increased from the original voltage VDD.

In this embodiment, a high conversion gain signal output from the pixel output circuit via the first floating diffusion capacitor FD1 (313) and an output from the pixel output circuit via the second floating diffusion capacitor FD2 (323). Since the relationship between the low conversion gain signal and the incident light intensity is the same as that described with reference to FIG. 7 in the first embodiment, the description thereof is omitted here.

Next, FIG. 16 is a plan view showing the result of the potential simulation of the unit pixel. The gate electrode of the overflow gate (OFG) 322 is 1.9 V, the reset transistor 1 (RT1) 314, the reset transistor 2 (RT2) 324, the source follower transistor 1 (SF1) 315, the source follower transistor 2 (SF2) 325, the selection 0 V is applied to the gate electrodes of the transistor 1 (SL1) 316 and the selection transistor 2 (SL2) 326.
Compared to FIG. 8, which is a similar diagram in the first embodiment, the difference is that the transfer transistor (TX) 112 is not provided between the photodiode (PD) 311 and the first floating diffusion capacitor (FD1) 313. (Same for FIG. 17).

FIG. 17 is a sectional view taken along line BB ′ in FIG. In the example of FIG. 17, a photoelectron is empty in the photodiode (PD) 311.
That is, in the cross section taken along the line BB ′, it is shown that the photodiode (PD) 311 is in an empty state because no electrons are accumulated at the bottom of the conduction band. On the other hand, a state where a predetermined amount of electrons are contained is shown below the first floating diffusion capacitor (FD1) 313.

On the other hand, FIG. 18, which is a cross-sectional view taken along the line CC ′ in FIG. 16, is the same as the cross-sectional view taken along the line CC ′ in FIG.
In the second embodiment formed as described above, there are many configurations common to those of the first embodiment, but there are also portions that are different from each other. Hereinafter, this difference will be mainly described in an enumerated form.

<Differences between Example 1 and Example 2>
The first embodiment is assumed to have a wide dynamic range function on the premise of a four-transistor pixel circuit, whereas the second embodiment is assumed to have a wide dynamic range function on the premise of a three-transistor pixel circuit. . Therefore, the first embodiment and the second embodiment are different from each other in that the premise is a pixel circuit with four transistors and a pixel circuit with three transistors (difference 1 below).
In the first embodiment, a four-transistor pixel circuit is provided with a wide dynamic range function. In the second embodiment, a three-transistor pixel circuit is provided with a wide dynamic range function. The difference is in the difference in action and effect due to the wide dynamic range function provided to different pixel circuits (difference 2 below).

[1] Difference 1
(1) Equivalent circuit and layout In the first embodiment, the transfer transistor (TX), the reset transistor 1 (RT1), the source follower transistor 1 (SF1), and the selection transistor 1 (SL1) for the first floating diffusion capacitor 4 transistors (4-transistor type), and for the second floating diffusion capacitance, an overflow gate (OFG), a reset transistor 2 (RT2), a source follower transistor 2 (SF2), and a selection transistor 2 (SL2) 4).
On the other hand, in the second embodiment, the transfer transistor (TX) is not provided, and the reset transistor 1 (RT1), the source follower transistor 1 (SF1), and the selection transistor 1 are provided for the first floating diffusion capacitance. (SL1) is composed of three transistors (three-transistor type), and for the second floating diffusion capacitance, an overflow gate (OFG), a reset transistor 2 (RT2), a source follower transistor 2 (SF2), and a selection transistor 2 (SL2) four transistors.
However, in the first embodiment, the driving method for three transistors as in the second embodiment can be applied by holding the transfer transistor (TX) in the ON state.
(2) Drive waveform In the first embodiment of the four-transistor method, the pre-reset method is adopted in which the signal is read after resetting, so the analog CDS is arranged between the pixel and the AD converter and reset. Noise can be removed.
On the other hand, in the second embodiment of the three-transistor method, a post-reset method is adopted in which a reset is performed after reading a signal. Therefore, even if an analog CDS is arranged between the pixel and the AD converter, the reset is performed. Noise cannot be removed. Since there is a correlation regarding reset noise between the reset noise and the signal after one frame (signal + reset noise) (the reset noise is approximately the same level), the digital CDS can be applied to remove the reset noise. The digital CDS (see the digital CDS 410 in FIG. 12) can be configured by arranging a frame memory outside the sensor chip.
(3) Maximum frame frequency In the case of adopting the digital CDS in the 3-transistor embodiment 2, the reset noise and the signal after one frame (signal + reset noise) are read out by the AD converter. Since the difference is obtained and the reset noise is canceled to obtain an image signal for one frame (see FIG. 13), when the circuit configuration other than the pixel is the same, when the three-transistor method is adopted, the four-transistor method The maximum frame frequency is ½ compared to the case of adopting.
(4) Noise The correlation between the reset noise of the 4-transistor system and the reset noise between the signal (signal + reset noise) is based on the correlation of the reset noise between the 3-transistor system reset noise and the signal (signal + reset noise). Therefore, the 4-transistor method has a larger canceling effect of reset noise in CDS.
(5) Saturation signal amount The saturation signal amount of the 4-transistor system is defined by the saturation electron amount of the photodiode (PD). Electrons overflowing from the photodiode (PD) at the time of exposure move to the floating diffusion capacitance (FD), and are discharged to the pixel power supply (VDD) at the time of reset. Electrons overflowing from the photodiode (PD) during the accumulation period of each frame are not used.
On the other hand, the saturation signal amount of the three-transistor method is defined by the saturation electron amount of the floating diffusion capacitance (FD). The photodiode (PD) is n-type and has a low impurity concentration, whereas the floating diffusion capacitance (FD) is n + and has a high impurity concentration, so that the floating diffusion capacitance (FD) has a high state density and a small area. However, the amount of saturated electrons is larger than that of the photodiode (PD). Electrons overflowing from the floating diffusion capacitance (FD) during the accumulation period of each frame are not used.
(6) Photodiode (PD) Sensitivity When no microlens is attached to each pixel, the sensitivity of the photodiode (PD) is defined by the area of the photodiode (PD). On the other hand, when a microlens is attached to each pixel, incident light is collected on the pixel, so the sensitivity of the photodiode (PD) is higher than that of the photodiode (PD). It is greatly influenced by. The sensitivity of the photodiode (PD) is not greatly affected by the 4-transistor system or the 3-transistor system.

[2] Difference 2
(1) A device having a wide dynamic range function on the premise of the 4-transistor pixel circuit according to the first embodiment (hereinafter sometimes referred to as a 4Tr. System with a wide DR function) and a 3-transistor pixel according to the second embodiment. Before comparing with a circuit provided with a wide dynamic range function (hereinafter sometimes referred to as a 3Tr. System with a wide DR function), the effect of adding the wide DR function will be described.
The effects are as follows: (A) Even if the photoelectric conversion unit is not divided, the resolution characteristics are excellent; (B) Even when the exposure time is not divided, the moving image imaging characteristics are excellent; and (C) In the pixel output signal The trade-off between high sensitivity, high S / N ratio, and wide dynamic range can be eliminated, and (D) high frame frequency can be achieved in super-multiple pixels.
(2) Specific configuration and effect of wide DR function First floating diffusion capacitance (FD1) and second floating diffusion capacitance (FD2) are connected by an overflow gate (OFG), and the first floating diffusion is formed. The saturation electron amount of the capacitor (FD1) is adjusted by the gate voltage of the overflow gate (OFG), and the electrons overflowing from the first floating diffusion capacitor (FD1) are moved to the second floating diffusion capacitor (FD2). The first floating diffusion capacitor (FD1) and the second floating diffusion capacitor (FD2) output different signals from the output units OUT1 and OUT2 through the respective pixel circuits. The area of the first floating diffusion capacitor (FD1) is small and the charge voltage conversion coefficient is high, while the area of the second floating diffusion capacitor (FD2) is large and the charge voltage conversion coefficient is low. On the low illuminance side, only the first floating diffusion capacitor (FD1) is used to obtain high sensitivity and a high S / N signal, while on the high illuminance side, the first floating diffusion capacitor (FD1) and the second floating diffusion capacitor are used. A diffusion capacitor (FD2) is used to obtain a high sensitivity and wide DR signal, and the above two signals are synthesized outside the sensor chip to obtain a wide DR signal.
Note that 4Tr. System and 3Tr. The wide DR function itself of the system is the same.
(3) About the maximum frame frequency Since two types of pixel outputs are provided, the AD converter is provided for each of them, so that the decrease in the maximum frame frequency is suppressed and the frame equivalent to the conventional technology is provided. It can be a frequency.
(4) Noise, saturation signal amount, and sensitivity of photodiode (PD) Noise, saturation signal amount, and sensitivity of photodiode (PD) are the same as in difference 1 above.
(5) 3Tr. With wide DR function When using a photoelectric conversion film for the system 3Tr. The system has the following advantages by laminating photoelectric conversion films (see Example 3 below). In this case, the film material of the photoelectric conversion film is not particularly limited.
3Tr. With wide DR function with laminated photoelectric conversion film. In the method, since the n + -type Si of the floating diffusion capacitance (FD) and the metal of VIA are connected without a barrier, the reset operation time and the signal readout time can be shortened (in the prior art). It can be equivalent to the case of 3Tr.
Note that 4Tr. With wide DR function in which photoelectric conversion films are stacked. In the method, a photoelectric conversion film can be stacked as a structure, but the n − type Si of the photodiode (PD) and the metal of VIA are connected, and the n + type Si of the floating diffusion capacitance (FD) and the metal of VIA are connected. In between, photodiode (P
Since the n-type Si of D) enters and functions as a barrier, there is a problem because the reset operation time and the signal readout time become long.
Further, as shown in the second embodiment, 3Tr. With a wide DR function using a general photodiode (PD). In the method, since there are seven transistors in the pixel, the area ratio occupied by these transistors is large, and the aperture ratio of the photodiode (PD) becomes low. As shown in Example 3 described later, 3Tr. In the system, the aperture ratio can be made substantially 100% without a microlens.

<Example 3>
In the second embodiment, since the photodiode (PD) 311 can be replaced with the photoelectric conversion film (PF) 511, only the portion of the photodiode (PD) 311 is replaced with the photoelectric conversion film (PF) 511 in this way. This will be described as Example 3 below.

  FIG. 19 shows an equivalent circuit diagram of a pixel circuit (reading control circuit) used in a solid-state imaging device having a pixel array of unit pixels 602 according to the third embodiment, specifically, a CMOS image sensor. is there. Since the thing of Example 3 has many parts in common with the thing of Example 2, in the following description, the number which added 200 to each part of Example 2 corresponds to each part of Example 2. It attaches to each part of the Example 3 which was done, and the detailed description may be abbreviate | omitted.

As shown in FIG. 19, the photoelectric conversion unit in Example 3 is a photoelectric conversion film (PF) 511. The photoelectric conversion film (PF) 511 is stacked on each unit pixel 602 and connected to the first floating diffusion capacitor (FD1) 513.
As described above, by stacking the photoelectric conversion film on each unit pixel 602, a space for arranging each unit pixel 602 can be used effectively, and the density of the pixels can be increased.

  In the pixel circuit (reading control circuit) of the unit pixel 602 shown in FIG. 19, the photoelectric conversion film (PF) 511 generates a negative charge of an amount corresponding to the intensity of incident light. The upper electrode (UE) 511A of the photoelectric conversion film (PF) 511 is connected to the pixel drive wiring (UE) 603, and the lower electrode (LE) 511B is a source follower transistor via the first floating diffusion capacitor (FD1) 513. 1 (SF1) 515 is connected to the gate.

  FIG. 20 is a time chart showing the input signal of each transistor when signal reading is performed using the pixel circuit (reading control circuit) shown in FIG.

Since each chart in FIG. 20 is the same as each chart in FIG. 13 described in the second embodiment (other than the chart of the uppermost upper electrode (UE)), description of each chart is omitted.
Note that the upper electrode (UE) is configured such that the photoelectric conversion film is maintained in an ON state by constantly inputting an L signal.

FIG. 21 shows an example of a schematic plan view and a schematic cross-sectional view of a unit pixel, and corresponds to the equivalent circuit diagram of the unit pixel 602 in FIG.
That is, in the schematic plan view and the schematic cross-sectional view, the photoelectric conversion film (PF) 511 is sandwiched between the upper electrode (UE) 511A and the lower electrode (LE) 511B, as shown in FIG. The upper electrode (UE) 511A is connected to the pixel drive wiring (UE) 603, and the lower electrode (LE) 511B is connected to the first floating diffusion capacitor (FD1) 513. Compared with FIG. 14 of the second embodiment, since there is no photodiode (PD) 311 occupying a large area, the pixel size can be reduced.

  Further, in the schematic plan view and the schematic cross-sectional view, the lower electrode (LE) 511B is connected to the first floating diffusion capacitor (FD1) 513, and the first floating diffusion capacitor (FD1) 513 is the overflow gate (OFG) 522. It is shown that it is connected to the second floating diffusion capacitor (FD2) 523 via

  Although the case where the carrier of the photoelectric conversion film (PF) 511 is an electron and a negative voltage is applied to the upper electrode (UE) 511A is described here, the carrier is a hole and the positive voltage is applied to the upper electrode (UE). The same effect can be obtained even when is applied.

In the imaging apparatus, driving method, and readout control circuit of the present embodiment, the above-described configuration enables linear and high S / N signal acquisition without reducing the saturation level in a low illuminance state. In a high illuminance state, the dynamic range can be expanded while ensuring a good S / N in the linear region.
In particular, for low illuminance state and high illuminance state, each has a pixel output circuit and signal output line, so the optical signal obtained by the same photoelectric conversion unit at the same time is read at high frame frequency Therefore, it is possible to cope with an imaging device that reads an extremely large number of pixels at a high frame frequency while having excellent moving image imaging characteristics and resolution characteristics.
Such an operational effect is obtained when, for example, a super-multi-pixel is read at a high frame frequency, such as Super Hi-Vision, as compared with that described in Patent Document 2 (Patent No. 5066704) described in the related art. Very advantageous.

  Furthermore, the readout control circuit, the solid-state imaging device, and the driving method of the imaging device of the present invention are not limited to those of the above-described embodiment, and other various modes can be adopted. For example, in the above-described embodiment, two sets of image output circuit units and two output signal lines are provided, but three or more sets of image output circuit units and three or more output signal lines are provided instead. May be. When there are three sets of image output circuit units and three output signal lines, it is possible to cope with each exposure of high illuminance, medium illuminance, and low illuminance.

Also, the equivalent circuit configuration of each unit pixel is not limited to the circuit shown in FIGS. 1, 11, and 19, and can be changed to other various modes. It is also possible to increase the number of transistors in the circuit portion.
Further, the saturation state voltages (gate set values of the overflow gate (OFG)) of the floating diffusion capacitors (FD1, 2) 113, 123, 313, 323, 513, and 523 and the gate voltages of various transistors are also described in the above embodiment. It is not restricted to a thing, It is possible to set to an appropriate value.

111,311 Photodiode (PD)
112 Transfer transistor (TX)
113, 313, 513 First floating diffusion capacitance (FD1)
114, 314, 514 Reset transistor 1 (RT1)
115, 315, 515 Source follower transistor 1 (SF1)
116, 316, 516 Select transistor 1 (SL1)
117, 317, 517 Pixel output 1 (OUT1)
118, 318, 518 Pixel power supply (VDD)
122, 322, 522 Overflow gate (OFG)
123, 323, 523 Second floating diffusion capacitance (FD2)
124, 324, 524 Reset transistor 2 (RT2)
125, 325, 525 Source follower transistor 2 (SF2)
126, 326, 526 Select transistor 2 (SL2)
127, 327, 527 Pixel output 2 (OUT2)
200, 400 CMOS image sensor 201, 401 Pixel array 202, 402, 602 Unit pixel 203, 403, 603 Pixel drive wiring 204, 204A, B, 404A, B, 604A, B Vertical signal line 205, 405 Column signal processing circuit 206 , 406 Output circuit 207, 407 Control circuit 208, 408 Horizontal scanning circuit 209, 409 Vertical scanning circuit 410 Digital CDS
511 Photoelectric conversion film (PF)
511A Upper electrode (UE)
511B Lower electrode (LE)

Claims (6)

In the readout control circuit of the solid-state imaging device, a first floating diffusion capacitance unit that accumulates signals from the photoelectric conversion unit and has a small capacitance and a large conversion gain;
A second floating diffusion capacitor means having a large capacitance and a small conversion gain, in which a signal from the first floating diffusion capacitor means is inputted and stored via an overflow gate;
Both the first floating diffusion capacitance means and the second floating diffusion capacitance means include a unique pixel output circuit.   Each of the first floating diffusion capacitance means is configured by using four transistors including a transfer transistor, and each of the second floating diffusion capacitance means is configured by using four transistors including an overflow gate. The read control circuit according to claim 1, wherein:   Each of the first floating diffusion capacitance means is configured by using three transistors that do not include a transfer transistor, and each of the second floating diffusion capacitance means is configured by using four transistors that include an overflow gate. The read control circuit according to claim 1, wherein:   The read control circuit according to claim 3, wherein the photoelectric conversion unit includes a photoelectric conversion film. A read control circuit according to any one of claims 1 to 4,
A solid-state imaging device, comprising: an output unit provided in accordance with each pixel output circuit that outputs a signal output from each of the unique pixel output circuits to a corresponding output signal line. A driving method for driving the solid-state imaging device according to claim 5,
When the first floating diffusion capacitance means and the second floating diffusion capacitance means are reset and photoelectrons move from the photoelectric conversion unit to the first floating diffusion capacitance means during a signal accumulation period,
When the gate voltage of the overflow gate is set to a predetermined value, the saturation capacity of the first floating diffusion capacitor means is set, and when photoelectrons overflow from the first floating diffusion capacitor means, the overflow electrons are transferred to the first floating diffusion capacitor means. Each of the first floating diffusion capacitance means and the second floating diffusion capacitance means, the signal voltage determined by the amount of photoelectrons and the conversion gain for each pixel output signal by the corresponding source follower element. A driving method for driving a solid-state imaging device, wherein the two pixel output signals are output to corresponding output signal lines.