JP2018082009A - Semiconductor module - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technique for relieving stress concentrated on a principal surface electrode near a location where a gate runner is provided. A semiconductor module includes a semiconductor substrate, a main surface electrode provided on one main surface of the semiconductor substrate, and a gate runner arranged on a part of the main surface electrode. A gate runner having a gate wire and a protective film covering the gate wire, a solder layer provided on at least a part of the main surface electrode other than the range where the gate runner is provided, and An adhesion layer provided on at least a part of the protective film of the gate runner, and the adhesion layer is a material different from the solder layer, and the protective film with the solder layer than the solder layer. It is a material with high adhesion. [Selection diagram] Fig. 3

Description

  The technology disclosed in this specification relates to a semiconductor module.

  Patent Document 1 discloses a semiconductor module having a structure in which a principal surface electrode provided on one principal surface of a semiconductor substrate is joined to a lead frame via a solder layer.

Japanese Patent Laid-Open No. 2015-233035

  In this type of semiconductor module, each member repeats expansion and contraction due to thermal cycles such as self-heating when the semiconductor element formed in the semiconductor substrate is energized and / or application of external thermal stress. Stress concentrates on the principal surface electrode due to the thermal expansion difference. There is a need for a technique for relieving such stress concentrated on the principal surface electrode.

  By the way, in this type of semiconductor module, a gate runner is often disposed on the main surface electrode. The gate runner has a gate wiring covered with a protective film, and the gate wiring is configured to be connected to a gate electrode formed in the semiconductor substrate. Thereby, a gate signal is uniformly applied to the gate electrode formed in the semiconductor substrate.

  In a conventional semiconductor module in which a gate runner is provided, a solder layer applied on the main surface electrode is also applied on such a gate runner. However, as a result of studies by the present inventors, it has been found that the adhesion between the protective film of the gate runner and the solder layer is poor. For this reason, when a thermal cycle is applied to the semiconductor module, the solder layer applied on the protective film is not strongly constrained by the protective film, and thus moves with repeated expansion and contraction. Such movement (expansion and contraction) of the solder layer on the protective film particularly concentrates stress on the principal surface electrode in the vicinity of the location where the gate runner is disposed. The present specification provides a technique for relieving stress concentrated on a main surface electrode in the vicinity of an arrangement location of a gate runner.

  One embodiment of a semiconductor module disclosed in the present specification includes a semiconductor substrate, a main surface electrode, a gate runner, a solder layer, and an adhesion layer. The main surface electrode is provided on one main surface of the semiconductor substrate. The gate runner is disposed on a part of the main surface electrode. The gate runner includes a gate wiring and a protective film that covers the gate wiring. The solder layer is provided on at least a part of the main surface electrode outside the range where the gate runner is provided. The adhesion layer is provided on at least a part of the protective film of the gate runner. The adhesion layer is a material different from the solder layer, and has a higher adhesion force to the protective film than the solder layer. In addition, the adhesion strength here is measured by a pudding cup test.

  In the semiconductor module of the above embodiment, an adhesion layer is provided on at least a part of the protective film of the gate runner. The adhesion layer is a material having higher adhesion with the protective film than the solder layer. For this reason, since the movement of the adhesion layer provided on the protective film is suppressed, the stress concentrated on the main surface electrode in the vicinity of the location where the gate runner is disposed is relieved.

The longitudinal cross-sectional view of a semiconductor module is shown. It is a top view of a semiconductor substrate and shows the state where a solder layer and an adhesion layer were formed. FIG. 3 is a cross-sectional view of a main part of the semiconductor module, showing a cross-sectional view of the main part corresponding to the line III-III in FIG. 2. FIG. 3 is a cross-sectional view of a main part of a conventional semiconductor module, showing a cross-sectional view of the main part corresponding to the line III-III in FIG. 2. It is a top view of the semiconductor substrate in the semiconductor module of a modification, and shows the state where the solder layer and the adhesion layer were formed. It is a top view of the semiconductor substrate in the semiconductor module of a modification, and shows the state where the solder layer and the adhesion layer were formed.

  A semiconductor module 10 shown in FIG. 1 includes an upper lead frame 12, a copper block 16, a semiconductor substrate 20, a lower lead frame 24, and a resin layer 26. The semiconductor substrate 20 is mainly composed of silicon. Although not shown in FIG. 1, an electrode layer, an insulating protective film, and the like are provided on the upper surface of the semiconductor substrate 20. Although not shown in FIG. 1, an electrode layer is provided on the lower surface of the semiconductor substrate 20. The electrode layer provided on the lower surface of the semiconductor substrate 20 is bonded to the upper surface of the lower lead frame 24 via the solder layer 22. The electrode layer provided on the upper surface of the semiconductor substrate 20 is bonded to the lower surface of the copper block 16 via the solder layer 18. The upper surface of the copper block 16 is joined to the upper lead frame 12 via the solder layer 14. The upper lead frame 12 and the lower lead frame 24 function as electrode plates for energizing the semiconductor substrate 20 and also function as heat dissipation plates for radiating heat from the semiconductor substrate 20. The side surface of the laminate composed of the upper lead frame 12, the copper block 16, the semiconductor substrate 20 and the lower lead frame 24 is covered with a resin layer 26.

  FIG. 2 is a plan view of the semiconductor substrate 20 and shows a state where the solder layer 18 is applied. As shown in FIG. 2, a gate runner 30 is disposed on the semiconductor substrate 20, and a region where the solder layer 18 is applied by the gate runner 30 is divided into three in this example.

  FIG. 3 is an enlarged cross-sectional view corresponding to line III-III in FIG. As shown in FIG. 3, the upper surface of the semiconductor substrate 20 is covered with a main surface electrode 42. The material of the main surface electrode 42 is AlSi (alloy containing aluminum and silicon). The main surface electrode 42 is electrically connected to a semiconductor region (for example, a source and an anode) formed on the semiconductor substrate 20.

  As shown in FIGS. 2 and 3, the gate runner 30 is disposed on a part of the upper surface of the main surface electrode 42. As shown in FIG. 2, the gate runner 30 has a first gate runner portion 32 and a second gate runner portion 34. The first gate runner portion 32 extends in one direction across the element region where the semiconductor element is formed in the semiconductor substrate 20. The second gate runner part 34 branches from the first gate runner part 32 and extends in a direction orthogonal to the first gate runner part 32. The second gate runner portion 34 extends from the first gate runner portion 32 toward the position where the gate pad is provided. The first gate runner portion 32 and the second gate runner portion 34 are configured to be connected at the center of the element region. In this example, the gate runner 30 has three end portions 30A located on the peripheral side of the element region.

  As shown in FIG. 3, the gate runner 30 (the first gate runner part 32 and the second gate runner part 34 have the same configuration) includes a gate wiring 30a and a protective film 30b covering the gate wiring 30a. Have The gate wiring 30 a is configured to be connected to the gate electrode in the semiconductor substrate 20. Thereby, a gate signal can be uniformly applied to the gate electrode formed in the semiconductor substrate 20. The material of the protective film 30b is an insulating polyimide.

  A nickel layer 44 is provided on the upper surface of the main surface electrode 42 where the gate runner 30 is not provided. The upper surface of the nickel layer 44 is bonded to the solder layer 18. The upper surface of the solder layer 18 is joined to the copper block 16. The nickel layer 44 is provided to improve the wettability of the solder layer 18. The solder layer 18 is applied between the nickel layer 44 and the copper block 16 after the adhesion layer 52 described later is bonded between the protective film 30 b and the copper block 16. The material of the solder layer 18 is SnCuNiP.

  An adhesion layer 52 is provided on the upper surface of the gate runner 30. As shown in FIG. 2, the adhesion layer 52 is provided in the entire range of the upper surface of the gate runner 30. The material of the adhesion layer 52 is CuMo. Since CuMo, which is the material of the adhesion layer 52, contains Cu, it is a material that can be satisfactorily bonded to the polyimide protective film 30b. The adhesion force of the adhesion layer 52 to the protective film 30b is higher than the adhesion force of the solder layer 18 to the protection film 30b. The upper surface of the adhesion layer 52 is bonded to the copper block 16.

  The adhesion layer 52 is formed on the upper surface of the protective film 30b after the upper surface of the protective film 30b is subjected to oxygen plasma treatment. Thereby, the contact | adhesion power of the contact | adherence layer 52 and the protective film 30b further improves. The adhesion layer 52 and the copper block 16 are bonded using an ultrasonic bonding technique. Thereby, the adhesion layer 52 and the copper block 16 can be firmly bonded. The thickness of the adhesion layer 52 is adjusted to be approximately the same as the thickness of the solder layer 18.

  FIG. 4 shows a cross-sectional view of a main part of a conventional semiconductor module. Parts corresponding to the respective parts of the semiconductor module 10 are denoted by the same reference numerals as in FIG. The conventional semiconductor device shown in FIG. 4 does not include the adhesion layer 52, and the solder layer 18 is also applied to the upper surface of the gate runner 30. Since the adhesion force of the solder layer 18 to the protective film 30b is weak, the solder layer 18 provided on the upper surface of the gate runner 30 is not strongly restrained.

  The temperature of the semiconductor module 10 rises by energizing the semiconductor elements formed in the semiconductor substrate 20. Further, the temperature of the semiconductor module 10 may rise due to an external temperature rise. Thus, the semiconductor module 10 is exposed to a thermal cycle. Hereinafter, a case where the semiconductor module 10 is exposed to a thermal cycle will be described. First, the conventional semiconductor module shown in FIG. 4 will be described. In the conventional semiconductor module shown in FIG. 4, since the adhesion between the protective film 30b and the solder layer 18 is poor, the solder layer 18 applied to the upper surface of the protective film 30b greatly expands and contracts when a thermal cycle is applied. Repeat and move freely. Since the semiconductor module 10 is covered with the resin layer 26, the solder layer 18 applied on the protective film 30b presses the resin layer 26 at the end 30A (see FIG. 2) of the gate runner 30 (see FIG. 1). (See “A”). The stress is particularly concentrated on the main surface electrode 42 in the vicinity immediately below the end 30A of the gate runner 30 due to the external force accompanying this pressing. In particular, immediately below the end 30A of the gate runner 30 is a triple point where the main surface electrode 42, the nickel layer 44, and the resin layer 26 are in contact with each other, and is a place where stress is likely to concentrate. Since the end portion 30A of the gate runner 30 and the triple point are close to each other, stress is particularly concentrated on the main surface electrode 42 in the vicinity of the triple point.

  On the other hand, in the semiconductor module 10 of the present embodiment shown in FIG. 3, an adhesion layer 52 is provided on the upper surface of the protective film 30 b of the gate runner 30 instead of the solder layer 18. The adhesion layer 52 is a material having higher adhesion with the protective film 30 b than the solder layer 18. For this reason, since the movement of the adhesion layer 52 provided on the upper surface of the protective film 30b is suppressed, the main surface electrode 42 in the vicinity of the location where the gate runner 30 is disposed, particularly directly below the end 30A of the gate runner 30. The stress of the main surface electrode 42 is relaxed.

  The linear expansion coefficient of CuMo, which is the material of the adhesion layer 52, is smaller than the linear expansion coefficient of the solder layer 18, and is closer to the linear expansion coefficient of the polyimide protective film 30b. For this reason, in the semiconductor module 10, stress due to a difference in thermal expansion between the adhesion layer 52 and the protective film 30 b is relieved as compared with the conventional semiconductor module.

  Furthermore, the thermal conductivity of CuMo which is the material of the adhesion layer 52 is larger than the thermal conductivity of the solder layer 18. For this reason, the heat generated when the semiconductor element in the semiconductor substrate 20 operates is favorably transferred to the copper block 16 and the upper lead frame 12 through the adhesion layer 52, and the temperature rise of the semiconductor substrate 20 is suppressed. Can do.

  In the semiconductor module 10 described above, the adhesion layer 52 is provided over the entire upper surface of the gate runner 30. However, in order to relieve the stress of the main surface electrode 42 in the vicinity of the location where the gate runner 30 is provided, it is only necessary that the adhesion layer 52 be provided on at least a part of the upper surface of the gate runner 30.

  For example, as shown in FIG. 5, the adhesion layer 52 may be selectively provided at the connection portion between the first gate runner portion 32 and the second gate runner portion 34, that is, at the center portion of the element region. In this example, since the solder layer 18 provided on the upper surface of the gate runner 30 is divided into three, the stress of the main surface electrode 42 in the vicinity of the location where the gate runner 30 is disposed is relieved. Further, the central portion of the element region is a portion where the temperature is highest, and the adhesive layer 52 having high thermal conductivity is provided in the central portion of the element region, so that the maximum temperature of the semiconductor substrate 20 can be suppressed. .

  As shown in FIG. 6, the adhesion layer 52 may be selectively provided corresponding to the end 30 </ b> A of the gate runner 30. Even in this case, the stress of the main surface electrode 42 immediately below the end 30A of the gate runner 30 is relaxed.

  Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology illustrated in the present specification or the drawings achieves a plurality of objects at the same time, and has technical utility by achieving one of the objects.

10: Semiconductor module 12: Upper lead frame 14: Solder layer 16: Copper block 18: Solder layer 20: Semiconductor substrate 22: Solder layer 24: Lower lead frame 26: Resin layer 30: Gate runner 30a: Gate wiring 30b: Protective film 32: 1st gate runner part 34: 2nd gate runner part 42: Main surface electrode 44: Nickel layer 52: Adhesion layer

Claims (1)

A semiconductor substrate;
A main surface electrode provided on one main surface of the semiconductor substrate;
A gate runner disposed on a part of the main surface electrode, the gate runner having a gate wiring and a protective film covering the gate wiring,
A solder layer provided on at least a part of the main surface electrode other than the range in which the gate runner is provided;
An adhesion layer provided on at least a part of the protective layer of the gate runner,
The adhesion layer is a semiconductor module that is a material different from the solder layer and has a higher adhesion to the protective film than the solder layer.

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