JP2014032985A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

Provided is a semiconductor device in which process temperature is lowered, pressurization pressure is reduced, and process time is shortened by surface activated bonding.
A first insulating substrate, a first semiconductor substrate and a source pad electrode and a gate pad electrode disposed on a surface of the first semiconductor substrate. The first semiconductor devices 10T ₁ and 10T ₂ having drain pad electrodes disposed on the back surface of the first semiconductor substrate 26T, the second semiconductor substrate 26D, and the second semiconductor disposed on the first insulating substrate 70 A second semiconductor device 10D ₁ having an anode electrode A disposed on the front surface of the substrate 26D and a cathode electrode disposed on the back surface of the second semiconductor substrate 26D. The drain pad electrode and the first insulating substrate 70 are provided. The cathode electrode and the first insulating substrate 70 are surface-activated bonded.
[Selection] Figure 2

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device using surface activated bonding and a manufacturing method thereof.

  Currently, many research institutions are conducting research and development of silicon carbide (SiC) devices. Characteristics of the SiC device include low on-resistance, high-speed switching, and high-temperature operation.

  Conventionally, in an Si device such as an insulated gate bipolar transistor (IGBT) used in the field of semiconductor power modules, the operable temperature range is up to about 150 ° C., so the conventional Sn-Ag system It was possible to drive even using low melting point solder such as.

  However, the SiC device can theoretically operate up to about 400 ° C. When the conventional low melting point solder is used, when the SiC device is driven at a high temperature, the joint portion by the low melting point solder is melted, and the gap between the electrodes is melted. Short-circuiting, peeling between the SiC device and the base plate, and the like have occurred, impairing the reliability of the SiC device.

  For this reason, the SiC device cannot be driven at a high temperature, and the characteristics of the SiC device cannot be fully utilized.

  At present, this high melting point bonding is actively developed, but considering mass production, the process time is not suitable for mass production and the process temperature is high. Due to the difference in thermal expansion coefficient of each material used, extra stress is applied to the material, and reliability cannot be ensured.

  A method for interconnecting SiC devices and a low thermal resistance package have already been disclosed (see, for example, Patent Document 1 and Patent Document 2). Patent Document 1 and Patent Document 2 disclose a method of forming a package that accommodates a SiC device, and the SiC device is liquid phase diffusion (TLP: Transient Liquid Phase) with respect to other components or conductive surfaces. Bonded using bonding technology.

  On the other hand, a composite solder article comprising Sn and / or Pb and having a relatively low melting point, for example, 430 ° C. or lower has already been disclosed (for example, see Patent Document 3). Patent Document 3 is characterized in that the solder alloy has a smaller temperature difference between the liquid phase and the solid phase than the basic solder.

  Further, a metal transfer MEMS package using a wafer level solder transfer technology has already been disclosed (for example, see Non-Patent Document 1). In Non-Patent Document 1, a device wafer and a package cap are bonded by TLP technology using a relatively thin Ni—Sn layer.

  An apparatus that cools a semiconductor element from the back surface via a cooler is also disclosed (for example, see Patent Document 4).

  Further, a semiconductor element module formed by using a room temperature bonding method is also disclosed (for example, see Patent Document 5).

International Publication No. WO2006 / 074165 US Patent Application Publication No. US2006 / 0151871 Special table hei 04-503480 JP 2010-245329 A JP 2008-47736 A

“Metal Transfer MEMS Package Using Wafer Level Solder Transfer Technology” by Valenci Welsch III, Junseok Chae, Carlil Najafi, American Electrical and Electronics Association Transactions on Advanced Packaging, Vol. 28, No. 4, November 2005 643-649 (Warren C. Welch, III, Junseok Chae, and Khalil Najafi, “Transfer of Metal MEMS Packages Using a Wafer-Level Solder Transfer Technique”, IEEE TRANSACTION ON ADVANCED PACKAGING, VOL, 28, NO.4, NOVEMBER 2005, pp. 643-649)

  Currently, Sn-Ag solder, which is a low melting point solder, is generally used to satisfy the Pb-free requirement. However, as described above, the low melting point solder has a melting temperature as low as about 230 ° C., and cannot be used in a device capable of high temperature driving such as SiC.

  An object of the present invention is to provide a semiconductor device in which a process temperature is lowered, a pressurizing pressure is reduced, and a process time is shortened by surface activated bonding, and a manufacturing method thereof.

  According to one aspect of the present invention for achieving the above object, the first insulating substrate is disposed on the first insulating substrate, and the first semiconductor substrate is disposed on the surface of the first semiconductor substrate. A first semiconductor device having a source pad electrode and a gate pad electrode, and a drain pad electrode disposed on the back surface of the first semiconductor substrate; a second semiconductor substrate disposed on the first insulating substrate; A second semiconductor device having an anode electrode disposed on the surface of the second semiconductor substrate and a cathode electrode disposed on the back surface of the second semiconductor substrate, the drain pad electrode and the first insulating substrate; A semiconductor device is provided in which the cathode electrode and the first insulating substrate are surface-activated bonded.

  According to another aspect of the present invention, a first insulating substrate, a flip-chip disposed on the first insulating substrate, a first semiconductor substrate, and a source pad electrode disposed on the back surface of the first semiconductor substrate. And a first semiconductor device having a gate pad electrode and a drain pad electrode disposed on the surface of the first semiconductor substrate, a second semiconductor substrate disposed on the first insulating substrate, and the second semiconductor. A second semiconductor device having an anode electrode disposed on the back surface of the substrate and a cathode electrode disposed on the surface of the second semiconductor substrate, the gate pad electrode, the first insulating substrate, A semiconductor device is provided in which the source pad electrode and the first insulating substrate, and the anode electrode and the first insulating substrate are surface-activated bonded.

  According to another aspect of the present invention, an insulating substrate, a signal wiring electrode disposed on the insulating substrate, a power wiring electrode disposed on or through the insulating substrate, and the insulating substrate A semiconductor device disposed on a substrate in a flip chip and having a semiconductor substrate, a source pad electrode and a gate pad electrode disposed on a back surface of the semiconductor substrate, and a drain pad electrode disposed on a surface of the semiconductor substrate There is provided a semiconductor device in which the signal wiring electrode and the gate pad electrode, the source pad electrode and the power wiring electrode are surface-activated bonded.

  According to another aspect of the present invention, an insulating substrate, a signal wiring electrode disposed on the insulating substrate, a power wiring electrode disposed on or through the insulating substrate, and the insulating substrate A semiconductor device disposed on a substrate in a flip chip and having a semiconductor substrate, a source pad electrode and a gate pad electrode disposed on a back surface of the semiconductor substrate, and a drain pad electrode disposed on a surface of the semiconductor substrate A gate connector disposed on the gate pad electrode, and a source connector disposed on the source pad electrode, the gate connector, the gate pad electrode and the signal wiring electrode, the source connector and the source. A semiconductor device in which the pad electrode and the power wiring electrode are surface-activated bonded is provided.

  According to another aspect of the present invention, under vacuum or inert gas, a semiconductor device and a metal to be bonded opposed to the semiconductor device are passed through the metal applied to the semiconductor device or the semiconductor. A surface activation process is performed on the surface of the device together with the surface of the metal to be bonded, and a first pressure is applied between the semiconductor device and the metal to be bonded in a vacuum or under an inert gas. And applying a second pressure between the semiconductor device and the metal to be bonded and applying a low temperature to the surface between the semiconductor device and the metal to be bonded under atmospheric pressure. There is provided a method of manufacturing a semiconductor device including a step of forming an activated junction.

  According to the present invention, it is possible to provide a semiconductor device in which a process temperature is lowered, a pressurizing pressure is reduced, and a process time is shortened by surface activated bonding, and a manufacturing method thereof.

FIG. 2 is a schematic plan pattern configuration diagram of the semiconductor device according to the first embodiment. FIG. 2 is a schematic cross-sectional structure diagram taken along line II in FIG. 1. FIG. 9 is a schematic cross-sectional structure diagram illustrating a semiconductor device according to Modification Example 1 of the first embodiment, taken along line II in FIG. 1. FIG. 10 is a schematic cross-sectional structure diagram of the semiconductor device according to the second modification of the first embodiment, taken along line II in FIG. 1. FIG. 10 is a schematic cross-sectional structure diagram illustrating a semiconductor device according to Modification 3 of the first embodiment, taken along line II in FIG. 1. FIG. 3 is a schematic cross-sectional structure diagram for explaining a process of the method for manufacturing the semiconductor device according to the first embodiment. BRIEF DESCRIPTION OF THE DRAWINGS It is description of the surface activation joining process applied to the manufacturing method of the semiconductor device which concerns on 1st Embodiment, Comprising: (a) Two metal materials oppose each other in a chamber, Either or both of the opposing surfaces Fig. 2 is a schematic cross-sectional structure diagram showing how the surface activation process is performed, (b) a schematic diagram showing how the two metal materials are in contact with each other in the chamber and the contact interface is deformed under low pressure. (C) Under atmospheric pressure, two metal materials contact each other, and under low temperature heating and low pressure, the contact interface disappears completely and only one interface is formed. FIG. 4 is a schematic cross-sectional structure diagram showing a state, and (d) a schematic cross-sectional structure diagram showing a state in which a boundary surface is removed and a seamless surface activated bonding is formed. In the method of manufacturing a semiconductor device according to the first embodiment, a temperature profile example and a pressure profile example in the surface activation bonding process, a temperature profile example in a relatively high pressure and high heating solid phase diffusion bonding process, and Comparison example with pressure profile example. FIG. 3 is a schematic cross-sectional structure diagram of a mounting substrate applied to the semiconductor device according to the first embodiment. FIG. 3 is a schematic cross-sectional structure diagram of a semiconductor substrate applied to the semiconductor device according to the first embodiment. FIG. 3 is a schematic cross-sectional structure diagram of a SiC • MOSFET, which is an example of a semiconductor device applied to the semiconductor device according to the first embodiment. FIG. 4 is a schematic cross-sectional structure diagram of an SiC MOSFET that includes a source pad electrode SP and a gate pad electrode GP, which is an example of a semiconductor device applied to the semiconductor device according to the first embodiment. The typical circuit block diagram of the three-phase alternating current inverter comprised by applying the semiconductor device which concerns on 1st Embodiment. The typical plane pattern block diagram of the semiconductor device which concerns on 2nd Embodiment. FIG. 15 is a schematic sectional view taken along line II-II in FIG. 14. FIG. 15 is a schematic cross-sectional structure diagram taken along the line II-II in FIG. 14, which is a semiconductor device according to Modification 1 of the second embodiment. FIG. 15 is a schematic cross-sectional structure diagram of a semiconductor device according to Modification 2 of the second embodiment, taken along line II-II in FIG. 14. FIG. 10 is a schematic cross-sectional structure diagram for explaining one process of a method for manufacturing a semiconductor device according to a second embodiment. The typical plane pattern block diagram of the semiconductor device mounted in the semiconductor device which concerns on 3rd Embodiment. The typical bird's-eye view structure figure of the semiconductor device mounted in the semiconductor device concerning a 3rd embodiment. The typical cross-section figure which follows the III-III line | wire of FIG. The typical plane pattern block diagram of the insulated substrate which mounts the semiconductor device which concerns on 3rd Embodiment. The typical plane pattern block diagram explaining a mode that the several semiconductor device was mounted in the flip chip on the insulated substrate of FIG. FIG. 23 is a schematic planar pattern configuration diagram of a semiconductor device according to an embodiment in which a plurality of semiconductor devices are mounted on a flip chip on the insulating substrate of FIG. 22. FIG. 25 is a schematic sectional view taken along line IV-IV in FIG. 24. FIG. 25 is a schematic cross-sectional structure diagram of the semiconductor device according to the third embodiment, which is a schematic cross-sectional structure taken along line IV-IV in FIG. 24 and mounted on a heat spreader. (A) Schematic bird's-eye view structure diagram of semiconductor device according to modification 1 of third embodiment, (b) Schematic cross-sectional structure diagram along line VV in FIG. 27 (a). FIG. 25 is a schematic cross-sectional structure diagram of a semiconductor device according to Modification 2 of the third embodiment, taken along line IV-IV in FIG. 24. FIG. 25 is a schematic cross-sectional structure diagram of a semiconductor device according to Modification 3 of the third embodiment, taken along line IV-IV in FIG. 24. FIG. 16 is a schematic cross-sectional structure diagram of a semiconductor device according to Modification 4 of the third embodiment. The typical cross-section figure of the semiconductor device which concerns on the modification 4 of 3rd Embodiment mounted on the heat spreader. (A) A typical bird's-eye view structure diagram of a semiconductor device concerning modification 5 of a 3rd embodiment, (b) A typical section structure figure which meets a VI-VI line of Drawing 32 (a). The typical cross-section figure of the semiconductor device which concerns on the modification 6 of 3rd Embodiment mounted on the heat spreader. The typical cross-section figure of the semiconductor device which concerns on the modification 7 of 3rd Embodiment mounted on the heat spreader.

  Next, embodiments will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  Further, the embodiments described below exemplify apparatuses and methods for embodying the technical idea of the present invention, and the embodiments of the present invention include the material, shape, structure, The layout is not specified as follows. Various modifications can be made to the embodiment of the present invention within the scope of the claims.

[First embodiment]
A schematic planar pattern configuration of the semiconductor device according to the first embodiment is expressed as shown in FIG. 1, and a schematic cross-sectional structure taken along line II in FIG. 1 is expressed as shown in FIG. The

As shown in FIG. 1, the semiconductor device according to the first embodiment includes two MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors) 10T ₁ and 10T ₂ and one Schottky barrier diode (SBD: Schottky). Barrier Diode) has a two-in-one configuration in which a semiconductor device composed of 10D ₁ and two MOSFETs 10T ₃ and 10T ₄ and one SBD 10D ₂ are mounted in one package. In addition, the semiconductor device has a Standard (Face Up Chip) configuration in which the source pad electrode SP, the gate pad electrode GP, and the anode electrode A of the semiconductor device are arranged on the surface side.

  The semiconductor device according to the first embodiment can be formed in a four-in-one configuration, a six-in-one configuration, or the like. Furthermore, the structure combined with the DC-DC converter is also possible.

As shown in FIGS. 1 and 2, the semiconductor device according to the first embodiment is disposed on a first insulating substrate 8, a first insulating substrate 8, a first semiconductor substrate 26T, and a first semiconductor substrate. and the source pad electrode SP and the gate pad electrode GP disposed on the surface of the 26T, the first semiconductor device 10T ₁ · 10T ₂ having a drain pad electrode disposed on the back surface of the first semiconductor substrate 26T (not shown) And a second semiconductor substrate 26D, an anode electrode A disposed on the surface of the second semiconductor substrate 26D, and a cathode electrode disposed on the back surface of the second semiconductor substrate 26D. and a second semiconductor device 10D has a (not shown) and _1. Here, the drain pad electrode and the first insulating substrate 8 and the cathode electrode and the first insulating substrate 8 are surface-activated bonded.

  Further, as shown in FIGS. 1 and 2, the semiconductor device according to the first embodiment has a bonding wire BL1 that connects the signal wiring electrode 12G disposed on the first insulating substrate 8 and the gate pad electrode GP. -Provided with BL2.

  Moreover, as shown in FIGS. 1 and 2, the semiconductor device according to the first embodiment further includes a heat spreader 100 on which the first insulating substrate 8 is mounted. The first insulating substrate 8 and the heat spreader 100 have surface activation. Bonded.

  1 and 2, the semiconductor device according to the first embodiment includes metal layers 14D and 14K disposed on the surface of the first insulating substrate 8, and includes the metal layers 14D and 14K. A drain surface activated bonding layer 48D and a cathode surface activated bonding layer 48K formed by surface activated bonding may be provided between the drain pad electrode and the cathode electrode.

  Further, as shown in FIGS. 1 and 2, the semiconductor device according to the first embodiment includes a metal layer 6 disposed on the back surface of the first insulating substrate 8, and includes a metal layer 6 and a heat spreader 100. A heat spreader surface activated bonding layer 48H formed by surface activated bonding is provided therebetween. Therefore, the semiconductor device according to the first embodiment has a single-side cooling configuration.

  The drain surface activated bonding layer 48D, the cathode surface activated bonding layer 48K, and the heat spreader surface activated bonding layer 48H may be any one or more selected from a combination of Cu, Ag, Au, Ti, Ni, or Al. It can be formed by surface activated bonding between metals.

The first semiconductor devices 10T ₁ , 10T ₂ , 10T ₃ , 10T ₄ and the second semiconductor devices 10D ₁ , 10D ₂ are formed of any one of SiC, GaN, AlN, diamond, or Si power devices. Is possible.

Further, a semiconductor having a band gap energy of 1.1 eV to 8 eV can be used for the first semiconductor devices 10T ₁ , 10T ₂ , 10T ₃ , 10T ₄ and the second semiconductor devices 10D ₁ , 10D ₂ .

The first insulating substrate 70 can be formed of a ceramic substrate made of AlN, Al ₂ O ₃ , Si ₃ N ₄ or the like. On the front and back surfaces of the first insulating substrate 8, metal layers 6 and 14 formed of, for example, copper foil or the like are provided.

  The semiconductor device according to the first embodiment shown in FIG. 2 is case-sealed after molding.

(Modification 1)
In the semiconductor device according to the first modification of the first embodiment, a schematic cross-sectional structure taken along line II of FIG. 1 is represented as shown in FIG.

As shown in FIG. 3, the semiconductor device according to the first modification of the first embodiment includes a source connector 20T ₁ disposed on the source pad electrode SP, and an anode connector 20A disposed on the anode electrode A. comprising a, between the source pad electrode SP and the source connector 20T _1, and between the anode electrode a and the anode connector 20A is bonded surface activation.

Further, as shown in FIG. 3, the semiconductor device according to the first modification of the first embodiment includes a first upper surface plate electrode 22 disposed flush with the source connector 20T ₁ and the anode connector 20A.

Further, in the semiconductor device according to the first modification of the first embodiment, as shown in FIG. 3, the surface activation is performed between the source connector 20T ₁ and the source pad electrode SP and between the anode connector 20A and the anode electrode A. A source surface activated bonding layer 48S and an anode surface activated bonding layer 48A formed by bonding may be provided.

  In addition, as shown in FIG. 3, the semiconductor device according to the first modification of the first embodiment is a bonding wire that connects the signal wiring electrode 12 </ b> G and the gate pad electrode GP disposed on the first insulating substrate 8. BL1 and BL2.

  Further, as shown in FIG. 3, the semiconductor device according to Modification 1 of the first embodiment further includes a heat spreader 100 on which the first insulating substrate 8 is mounted, and the first insulating substrate 8 and the heat spreader 100 are provided on the surface. Activated joining.

  Further, as shown in FIG. 3, the semiconductor device according to Modification 1 of the first embodiment includes a metal layer 6 disposed on the back surface of the first insulating substrate 8, and includes the metal layer 6 and the heat spreader 100. In the meantime, a heat spreader surface activated bonding layer 48H formed by surface activated bonding is provided.

  The semiconductor device according to the first modification of the first embodiment has a double side cooling configuration.

  The drain surface activated bonding layer 48D, the cathode surface activated bonding layer 48K, and the heat spreader surface activated bonding layer 48H may be any one or more selected from a combination of Cu, Ag, Au, Ti, Ni, or Al. It can be formed by surface activated bonding between metals.

  The semiconductor device according to the first modification of the first embodiment shown in FIG. 3 is case-sealed after molding.

  In the semiconductor device according to the first modification of the first embodiment, the source surface activated bonding layer 48S, the drain surface activated bonding layer 48D, the cathode surface activated bonding layer 48K, and the anode surface activated bonding layer 48A are made of Cu. , Ag, Au, Ti, Ni, or a combination of one or a plurality of metals selected from a combination of Al and surface activated bonding.

  The heat spreader surface activated bonding layer 48H is formed by surface activated bonding of one or more metals selected from a combination of Cu, Ag, Au, Ti, Ni or Al.

The source connectors 20T ₁ and 20T ₂ and the anode connector 20A are formed of any one of Al, Cu, CuMo, CuW, and AlSiC. Other configurations are the same as those of the first embodiment.

(Modification 2)
4 is a semiconductor device according to Modification 2 of the first embodiment, and a schematic cross-sectional structure taken along line II of FIG. 1 is represented as shown in FIG.

  As shown in FIG. 4, the semiconductor device according to the second modification of the first embodiment includes the second insulating substrate 8 disposed on the source pad electrode SP, the gate pad electrode GP, and the anode electrode A, and the source The pad electrode SP and the second insulating substrate 8, the gate pad electrode GP and the second insulating substrate 8, and the anode electrode A and the second insulating substrate 8 are surface-activated bonded.

  As shown in FIG. 4, the semiconductor device according to Modification 2 of the first embodiment includes metal layers 14G, 14S, and 14A disposed on the back surface of the second insulating substrate 8, and includes the metal layer 14S and the source pad. Source surface activated bonding layer 48S, gate surface activated bonding layer 48G and anode surface formed by surface activated bonding between electrode SP, metal layer 14G and gate pad electrode GP, and metal layer 14A and anode electrode A An activated bonding layer 48A may be provided.

  As shown in FIG. 4, the semiconductor device according to the second modification of the first embodiment has a double-side cooling configuration and a wireless insulation module configuration.

  In the semiconductor device according to the second modification of the first embodiment, the source surface activation bonding layer 48S, the gate surface activation bonding layer 48G, and the anode surface activation bonding layer 48A are Cu, Ag, Au, Ti, Ni Alternatively, it is formed by surface activated bonding of one or more metals selected from a combination of Al. Other configurations are the same as those of the first embodiment.

(Modification 3)
FIG. 5 is a schematic cross-sectional structure of the semiconductor device according to the third modification of the first embodiment, taken along the line I-I in FIG. 1.

  As shown in FIG. 5, the semiconductor device according to the third modification of the first embodiment includes the second upper surface plate electrode 22 disposed on the source pad electrode SP, the gate pad electrode GP, and the anode electrode A, The source pad electrode SP and the second upper surface plate electrode 22, the gate pad electrode GP and the second upper surface plate electrode 22G, and the anode electrode A and the second upper surface plate electrode 22 are surface-activated bonded. Here, the second upper surface plate electrode 22G is embedded in the second upper surface plate electrode 22 so as to be insulated from the second upper surface plate electrode 22 via the insulating layer 22I.

  As shown in FIG. 5, the semiconductor device according to the third modification of the first embodiment includes metal layers 14G, 14S, and 14A disposed on the back surfaces of the second upper surface plate electrodes 22G and 22, and the metal layer 14S. And source pad electrode SP, source layer activated bonding layer 48S, gate surface activated bonding layer 48G formed by surface activated bonding between metal layer 14G and gate pad electrode GP, and metal layer 14A and anode electrode A. And an anode surface activation bonding layer 48A. The metal layers 14G, 14S, and 14A are not necessarily essential, and may be omitted from the configuration. In this case, the second upper surface plate electrode 22 and the source pad electrode SP, the second upper surface plate electrode 22G and the gate pad electrode GP, and the second upper surface plate electrode 22 and the anode electrode A are formed by surface activation bonding. The source surface activated bonding layer 48S, the gate surface activated bonding layer 48G, and the anode surface activated bonding layer 48A may be provided.

  As shown in FIG. 5, the semiconductor device according to the third modification of the first embodiment has a double-side cooling configuration and a wireless module configuration.

  In the semiconductor device according to the third modification of the first embodiment, the source surface activation bonding layer 48S, the gate surface activation bonding layer 48G, and the anode surface activation bonding layer 48A are Cu, Ag, Au, Ti, Ni Alternatively, it is formed by surface activated bonding of one or more metals selected from a combination of Al. Other configurations are the same as those of the first embodiment.

(Surface activated bonding process)
A schematic cross-sectional structure for explaining one step of the method of manufacturing the semiconductor device according to the first embodiment is expressed as shown in FIG.

  As one step of the method of manufacturing the semiconductor device according to the first embodiment, the surface activated bonding step is a step in which a semiconductor device and a metal to be bonded opposed to the semiconductor device are subjected to a semiconductor in a vacuum or under an inert gas. Surface activation treatment with the metal applied to the device or the surface of the semiconductor device itself, together with the surface of the metal to be bonded, and bonding with the semiconductor device under vacuum or inert gas A step of applying a first pressure P between the metal parts and temporarily bonding, and applying a second pressure P1 between the semiconductor device and the metal part to be joined under atmospheric pressure and heating at a low temperature, Forming a surface activated bond between the metal to be bonded.

  The second pressure for forming the surface activated bond is not less than atmospheric pressure and not more than 10 MPa.

  The temperature for forming the surface activated bonding is from room temperature to 150 ° C.

As one step of the method of manufacturing the semiconductor device according to the first embodiment, the surface activation bonding step includes an insulating substrate 8 attached to the chuck 400 and a chip pocket 500 as shown in FIG. The first semiconductor devices 10T ₁ and 10T ₂ and the second semiconductor device 10D ₁ that are formed are opposed to each other in the chamber 300, and the surfaces of the metal layers 14D, 14K, and 14D disposed on the back surface of the insulating substrate 8 are , Surface activation treatment. Further, it is desirable that the chip pocket 500 be formed of an elastic and stretchable material in order to form the surface activated bonding.

As a surface activation bonding (SAB) method, for example, plasma processing, ion beam processing such as FIB (Focused Ion Beam), laser beam processing, photochemical reaction processing, or the like can be applied. In the first embodiment, plasma processing using Ar ⁺ ions is performed.

That is, surface activation treatment is performed on the surfaces of the metal layers 14D, 14K, and 14D using Ar ⁺ ions.

Next, to face the cathode surface, a first drain surface of the semiconductor device 10T ₁ of the drain surface, the second semiconductor device 10D ₁ of the first semiconductor device 10T _1, arranged surface of the metal layer 14D-14K-14D, A first pressure P is applied to form a temporary bond.

Then, under atmospheric pressure, the second pressure P1 is applied between the metal layer 14D · 14K · 14D and the first semiconductor device 10T ₁ · second semiconductor device 10D ₁ · first semiconductor device 10T _1, and a low temperature heating Te, to form a surface activated bonding between the metal layer 14D · 14K · 14D and the first semiconductor device 10T ₁ · second semiconductor device 10D ₁ · first semiconductor device 10T _1.

As a result, as shown in FIG. 2, the drain surface activated bonding layer 48D, the cathode surface activated bonding layer 48K, the drain surface activated bonding layer 48D, and the first metal layers 14D, 14K, and 14D are formed by surface activated bonding. A strong junction is formed between the semiconductor device 10T ₁ , the second semiconductor device 10D _1, and the first semiconductor device 10T ₁ .

  In addition, after forming Cu, Ag, Au, Ti, Ni, Al, etc. on the surface of the opposing metal material which forms a surface activation joining, using a plating technique, a sputtering technique, or a vacuum evaporation technique, it is actual. A surface activation treatment may be performed.

  Alternatively, the surface activation treatment may be performed on the surface of the opposing metal material forming the surface activated bonding.

In the surface activated bonding process, the surfaces to be bonded are exposed to Ar ⁺ plasma in the chamber 300 to activate the surfaces.

  Next, in the chamber 300, the surfaces to be bonded are brought into contact with each other to form a temporary bond with a relatively low pressure.

  Next, under atmospheric pressure, a relatively low pressure (for example, about atmospheric pressure to about 10 MPa) and a heat of, for example, room temperature to about 150 ° C. are applied to the temporary bonding surface, and the two materials are surface-activated bonded. Let

  FIG. 4 is a description of a surface activation bonding process applied to the method for manufacturing a semiconductor device according to the first embodiment, in which two metal materials M1 and M2 face each other in the chamber 300 and either one of the facing surfaces or In both cases, a schematic cross-sectional structure showing a state of performing the surface activation treatment step is expressed as shown in FIG.

  Further, a schematic cross-sectional structure showing a state in which the two metal materials M1 and M2 are in contact with each other in the chamber 300 and the contact interface BF is plastically deformed under a low pressure P is shown in FIG. It is expressed as shown in

  Furthermore, under the atmospheric pressure, the two metallic materials M1 and M2 are in contact with each other, and under low temperature heating and low pressure of P1, the contact interface is completely lost, and only one boundary surface BS is formed. A schematic cross-sectional structure showing the appearance is expressed as shown in FIG.

  Furthermore, a schematic cross-sectional structure showing a state in which the boundary surface is removed and a seamless surface activated bonding is formed is expressed as shown in FIG.

(A) First, as shown in FIG. 7A, two metal materials M1 and M2 are opposed to each other in a chamber 300, and a surface activation treatment process is performed on one or both of the opposed surfaces. Here, in the surface activation treatment step, plasma treatment using Ar ⁺ ions is performed.

(B) Next, in the chamber 300, the two metal materials M1 and M2 are brought into contact with each other and, for example, a pressure having a relatively low pressure P is applied. As a result, the contact interface BF is plastically deformed.

(C) Next, as shown in FIG. 7C, the two metal materials M1 and M2 are brought into contact with each other while being subjected to the heating process with the heater 600 or the like under atmospheric pressure. A low pressurization of the pressure P1 is performed. As a result, the contact interface BF disappears completely and only one boundary surface BS is formed. The heating temperature at this time is, for example, room temperature or higher and about 150 ° C. or lower. The pressure is not less than atmospheric pressure and not more than about 10 MPa.

(D) If the heating process is continued while further applying the pressure P1, the boundary surface BS between the two metal materials M1 and M2 is removed as shown in FIG. Formed.

(Comparison of surface activated bonding and solid phase diffusion bonding conditions)
In the method of manufacturing a semiconductor device according to the first embodiment, the temperature profile example and the pressure profile example in the surface activation bonding process of relatively low pressure and low heating, and the temperature in the solid phase diffusion bonding process as a comparative example An example profile and an example pressure profile are represented as shown in FIG.

  In the temperature profile example and the pressure profile example in the solid phase diffusion bonding process, as shown in FIG. 8, in the initial state, a pressure of about 90 MPa is applied, and the pressure is maintained and the temperature is maintained within about 5 minutes. The temperature is raised to ° C. Thereafter, a pressure of about 90 MPa and a heating temperature of about 350 ° C. are maintained for about 20 minutes. Thereafter, in about 25 minutes, the pressure is decreased from about 90 MPa to atmospheric pressure, and the heating temperature is decreased from about 350 ° C. to about 200 ° C. Thereafter, the heating temperature is lowered from about 200 ° C. to room temperature in about 25 minutes. As is apparent from FIG. 8, the pressurizing / heating process time is completed in about 1 hour.

  On the other hand, in the example of the temperature profile and the example of the pressure profile in the surface activation bonding process of relatively low pressure and low heating as the method for manufacturing the semiconductor device according to the first embodiment, as shown in FIG. The temperature is, for example, room temperature or higher and about 150 ° C. or lower. The pressure is not less than atmospheric pressure and not more than about 10 MPa. The pressurizing / heating process time is about 5 minutes.

  A schematic cross-sectional structure of the mounting substrate 70 applied to the semiconductor device according to the first embodiment is represented as shown in FIG. 9, and a schematic cross-sectional structure of the applied semiconductor substrate 7 is shown in FIG. It is expressed as

  The schematic cross-sectional structure of the mounting substrate 70 applied in the semiconductor device according to the first embodiment has a structure in which metal layers 14 and 6 are formed on the front and back surfaces of the insulating substrate 8 as shown in FIG. May be. Here, the metal layers 14 and 6 may be formed of a Cu electrode or an Al electrode on the surface of the mounting substrate 70 such as a DBC (Direct Bonding Copper) substrate or a DBA (Direct Brazed Aluminum). The signal wiring electrode 12 and the power wiring electrode 16 may be formed on the insulating substrate 8 by patterning these Cu electrodes and Al electrodes. Alternatively, the signal wiring electrode 12 and the power wiring electrode 16 may be pattern-formed on the insulating substrate 8 using a plating technique, a sputtering technique, a vacuum deposition technique, or the like.

  In order to form the drain surface activation junction, flatness of the substrate is required. Therefore, instead of the mounting substrate 70, a semiconductor substrate 7 such as a silicon wafer can be applied as shown in FIG. In the example of FIG. 10, the metal layer 5 is formed on the semiconductor substrate 7.

  The metal layers 14, 6 and 5 can be formed of Cu, Ag, Au, Ti, Ni, Al, or the like using a plating technique, a sputtering technique, or a vacuum evaporation technique.

  According to the semiconductor device and the manufacturing method thereof according to the first embodiment, a high-melting point surface activation bonding layer can be formed by a low temperature process, so that damage to the material can be reduced during the manufacturing process. it can.

  According to the semiconductor device according to the first embodiment, it is also possible to realize a structure in which a plurality of semiconductor devices are arranged in parallel by a simultaneous process, thereby increasing capacity, mass production, shortening process time, Simplification of the process is easy.

  In the semiconductor device according to Modifications 2 and 3 of the first embodiment, wire bonding is possible because the electrode connection is performed by surface activated bonding. For this reason, the reliability at the time of manufacture can be improved, the parasitic inductance which a bonding wire has is reduced, and high-speed switching performance and high frequency drive performance can be achieved.

  According to the semiconductor device according to the first to third modifications of the first embodiment, it is possible to realize a double-sided cooling structure that cools the semiconductor device from both the mounting substrate side and the upper surface plate electrode 22 or the second insulating substrate side. It has excellent heat dissipation performance.

(Configuration example of semiconductor device)
As an example of the semiconductor device 10 applied to the semiconductor device 1 according to the first embodiment, as shown in FIG. 11, a schematic cross-sectional structure of an SiC MOSFET includes a semiconductor substrate 26 made of an n ⁻ high resistance layer, A p base region 28 formed on the surface side of the semiconductor substrate 26, a source region 30 formed on the surface of the p base region 28, and a gate insulating film disposed on the surface of the semiconductor substrate 26 between the p base regions 28. 32, a gate electrode 38 disposed on the gate insulating film 32, a source electrode 34 connected to the source region 30, an n ⁺ drain region 24 disposed on the back surface opposite to the surface of the semiconductor substrate 26, and a drain pad electrode 36 connected to the n ⁺ drain region 24.

  In FIG. 11, the semiconductor device 10 is composed of a planar gate type n-channel vertical SiC • MOSFET, but may be composed of a trench gate type n-channel vertical SiC • MOSFET.

  Further, a GaN-based FET or the like can be applied to the semiconductor device 10 applied to the semiconductor device 1 according to the first embodiment instead of the SiC • MOSFET.

  As the semiconductor device 10 applied to the semiconductor device 1 according to the first embodiment, any of SiC-based, GaN-based, AlN-based, diamond-based, or Si-based power devices can be applied.

  Furthermore, the semiconductor device 10 applied to the semiconductor device 1 according to the first embodiment can use a semiconductor having a band gap energy of 1.1 eV to 8 eV, for example.

  According to the semiconductor device according to the first embodiment, the surface activated bonding layers 48G, 48S, 48D, and 48H have, for example, high heat resistance such as the melting point of metallic silver of about 960 ° C. By applying the activated bonding layers 48G, 48S, 48D, and 48H to power devices such as SiC FETs and GaN FETs, the power devices can be driven at high temperatures.

  12 is an example of the semiconductor device 10 applied according to the first embodiment, and a schematic cross-sectional structure of a SiC MOSFET including a source pad electrode SP and a gate pad electrode GP is expressed as shown in FIG. . The gate pad electrode GP is connected to the gate electrode 38 disposed on the gate insulating film 32, and the source pad electrode SP is connected to the source electrode 34 connected to the source region 30.

  Further, as shown in FIG. 12, the gate pad electrode GP and the source pad electrode SP are arranged on an interlayer insulating film 44 for passivation covering the surface of the semiconductor device 10. In the semiconductor substrate 26 below the gate pad electrode GP and the source pad electrode SP, in the configuration example of FIG. 26, illustration is omitted, but as in the central portion of FIG. 11 or FIG. A transistor structure having a structure may be formed.

  Further, as shown in FIG. 12, the source pad electrode SP may be extended and disposed on the passivation interlayer insulating film 44 also in the transistor structure at the center. Alternatively, in the transistor structure in the central portion of FIG. 26, the gate pad electrode GP may be extended and disposed on the passivation interlayer insulating film 44.

(Application examples using semiconductor devices)
Next, a three-phase AC inverter configured using the semiconductor device 1 according to the first embodiment will be described with reference to FIG.

  As shown in FIG. 13, the three-phase AC inverter includes a gate drive unit 50, a power module unit 52 connected to the gate drive unit 50, and a three-phase AC motor unit 54. The power module unit 52 is connected to U, V, and W phase inverters corresponding to the U phase, V phase, and W phase of the three-phase AC motor unit 54.

  In FIG. 13, the gate drive unit 50 is connected only to the gate electrodes of the transistors Q1 and Q2, but is similarly connected to the gate electrodes of the transistors Q3 and Q4 and the gate electrodes of the transistors Q5 and Q6. Has been.

  In the power module 52, the inverter-structured SiC MOSFETs Q1 and Q2, Q3 and Q4, and Q5 and Q6 are connected between the plus terminal (+) and the minus terminal (−) to which the capacitor C is connected. Furthermore, diodes D1 to D6 are connected in antiparallel between the sources and drains of the SiC MOSFETs Q1 to Q6, respectively.

  As described above, the SiC MOSFETs Q1 to Q6 corresponding to the semiconductor device 10 applied to the semiconductor device 1 according to the first embodiment are mounted via the surface activation bonding layers 48G, 48S, 48D, and 48H. 70 or electrically connected to the heat spreader 100.

  According to the first embodiment and the first to third modifications thereof, the semiconductor device in which the process temperature is lowered, the pressurizing pressure is reduced, and the process time is shortened by surface activated bonding, and the process A manufacturing method can be provided.

[Second Embodiment]
A schematic planar pattern configuration of the semiconductor device according to the second embodiment is expressed as shown in FIG. 14, and a schematic cross-sectional structure taken along line II-II in FIG. 14 is expressed as shown in FIG. The

As shown in FIG. 14, the semiconductor device according to the second embodiment includes a semiconductor device composed of two MOSFETs 10T ₁ and 10T ₂ and one SBD 10D _1, two MOSFETs 10T ₃ and 10T ₄ and one semiconductor device. It has a _two- in-one configuration in which a semiconductor device composed of SBD 10D ₂ is mounted in one package. In addition, the semiconductor device has a Flip (Face Down Chip) configuration in which the source pad electrode SP, the gate pad electrode GP, and the anode electrode A of the semiconductor device are arranged on a flip chip.

  Note that the semiconductor device according to the second embodiment can be formed in a Four in One configuration, a Six in One configuration, or the like. Furthermore, the structure combined with the DC-DC converter is also possible.

As shown in FIGS. 14 and 15, the semiconductor device according to the second embodiment is disposed on the first insulating substrate 8 and the first insulating substrate 8 in a flip chip, and includes a first semiconductor substrate 26T ₁ , the first semiconductor device 10T has a source pad electrode SP and the gate pad electrode GP disposed on the first semiconductor substrate 26T ₁ on the back surface, and a drain pad electrode D disposed on the first semiconductor substrate 26T ₁ on the surface ₁ When disposed on the first insulating substrate 8, a second semiconductor substrate 26D _1, and the anode electrode a disposed in the second semiconductor substrate 26D ₁ on the back surface is disposed on the second semiconductor substrate 26D ₁ on the surface A second semiconductor device 10D ₁ having a cathode electrode K, a gate pad electrode GP and a first insulating substrate 8, a source pad electrode SP and a first insulating substrate 8, an anode electrode A and a first insulating substrate 8 Are surface activated bonded.

  In addition, as shown in FIG. 15, the semiconductor device according to the second embodiment further includes a heat spreader 100 on which the first insulating substrate 8 is mounted, and the first insulating substrate 8 and the heat spreader 100 are surface-activated bonded. The

  Further, as shown in FIG. 15, the semiconductor device according to the second embodiment includes metal layers 14G, 14S, and 14A disposed on the surface of the first insulating substrate 8, and the metal layers 14G, 14S, and 14A. And gate pad electrode GP / source pad electrode SP / anode electrode A, gate surface activated bonding layer 48G / source surface activated bonding layer 48S / cathode surface activated bonding layer 48K formed by surface activated bonding. May be provided.

  Further, as shown in FIG. 15, the semiconductor device according to the second embodiment includes a metal layer 6 disposed on the back surface of the first insulating substrate 8, and between the metal layer 6 and the heat spreader 100, A heat spreader surface activated bonding layer 48H formed by surface activated bonding is provided. Therefore, the semiconductor device according to the second embodiment has a single-side cooling configuration.

  The gate surface activated bonding layer 48G, the source surface activated bonding layer 48S, the cathode surface activated bonding layer 48K, and the heat spreader surface activated bonding layer 48H are selected from a combination of Cu, Ag, Au, Ti, Ni, or Al. It can be formed by surface activated bonding of one or more metals.

The first semiconductor devices 10T ₁ , 10T ₂ , 10T ₃ , 10T ₄ and the second semiconductor devices 10D ₁ , 10D ₂ are formed of any one of SiC, GaN, AlN, diamond, or Si power devices. Is possible.

Further, a semiconductor having a band gap energy of 1.1 eV to 8 eV can be used for the first semiconductor devices 10T ₁ , 10T ₂ , 10T ₃ , 10T ₄ and the second semiconductor devices 10D ₁ , 10D ₂ .

The first insulating substrate 8 can be formed of a ceramic substrate made of AlN, Al ₂ O ₃ , SiN or the like. On the front and back surfaces of the first insulating substrate 8, metal layers 6 and 14 formed of, for example, copper foil or the like are provided.

  Note that the semiconductor device according to the second embodiment shown in FIG. 15 is case-sealed after molding.

(Modification 1)
In the semiconductor device according to the first modification of the second embodiment, a schematic cross-sectional structure taken along line II-II in FIG. 14 is expressed as shown in FIG.

  As shown in FIG. 16, the semiconductor device according to the first modification of the second embodiment includes a third upper surface plate electrode 22 disposed on the drain pad electrode D and the cathode electrode K, The third upper surface plate electrode 22, the cathode electrode K, and the third upper surface plate electrode 22 are surface-activated bonded.

  As shown in FIG. 16, the semiconductor device according to the first modification of the second embodiment includes a third upper surface plate electrode 22 and a drain pad electrode D, and a third upper surface plate electrode 22 and a cathode electrode K. A drain surface activated bonding layer 48D and a cathode surface activated bonding layer 48K formed by surface activated bonding may be provided.

  As shown in FIG. 16, the semiconductor device according to the first modification of the second embodiment has a double-side cooling configuration and a wireless module configuration.

  In the semiconductor device according to the first modification of the second embodiment, the drain surface activated bonding layer 48D and the cathode surface activated bonding layer 48K are selected from a combination of Cu, Ag, Au, Ti, Ni, or Al. It is formed by surface activated bonding between any one or a plurality of metals. Other configurations are the same as those of the second embodiment.

(Modification 2)
In the semiconductor device according to the second modification of the second embodiment, a schematic cross-sectional structure taken along line II-II in FIG. 14 is expressed as shown in FIG.

  As shown in FIG. 17, the semiconductor device according to the second modification of the second embodiment includes a second insulating substrate 8 disposed on the drain pad electrode D and the cathode electrode K. The two insulating substrate 8, the cathode electrode K and the second insulating substrate 8 are surface-activated bonded.

  As shown in FIG. 17, the semiconductor device according to the second modification of the second embodiment includes metal layers 14D and 14K disposed on the back surface of the second insulating substrate 8, and includes the metal layer 14D and the drain pad electrode D. In addition, a drain surface activated bonding layer 48D and a cathode surface activated bonding layer 48K formed by surface activated bonding may be provided between the metal layer 14K and the cathode pad electrode K.

  As shown in FIG. 17, the semiconductor device according to the second modification of the second embodiment has a double-side cooling configuration and a wireless insulating module configuration.

  In the semiconductor device according to the second modification of the second embodiment, the drain surface activated bonding layer 48D and the cathode surface activated bonding layer 48K are selected from a combination of Cu, Ag, Au, Ti, Ni, or Al. It is formed by surface activated bonding between any one or a plurality of metals. Other configurations are the same as those of the second embodiment.

(Surface activated bonding process)
A schematic cross-sectional structure for explaining one step of the method of manufacturing a semiconductor device according to the second embodiment is expressed as shown in FIG.

As one step of the method of manufacturing the semiconductor device according to the second embodiment, the surface activation bonding step includes the insulating substrate 8 attached to the chuck 400 and the chip pocket 500 as shown in FIG. The first semiconductor devices 10T ₁ and 10T ₂ and the second semiconductor device 10D ₁ that are formed are arranged in the chamber 300, and the metal layers 14G, 14S, 14A, 14S, and the like disposed on the back surface of the insulating substrate 8. The surface of 14G is subjected to surface activation treatment. Further, it is desirable that the chip pocket 500 be formed of an elastic and stretchable material in order to form the surface activated bonding.

As a surface activation treatment (SAB) method, for example, plasma treatment, ion beam treatment such as FIB, laser beam treatment, photochemical reaction treatment, or the like can be applied. In the second embodiment, plasma processing using Ar ⁺ ions is performed.

That is, surface activation treatment is performed on the surfaces of the metal layers 14G, 14S, and 14A using Ar ⁺ ions.

Next, the surfaces of the metal layers 14G, 14S, and 14A are arranged so as to face the gate pad electrode GP / source pad electrode SP of the first semiconductor device 10T ₁ and the anode electrode A of the second semiconductor device 10D ₁ , A pressure P is applied to form a temporary bond.

  Next, under atmospheric pressure, the second pressure P1 is applied between the metal layer 14G / 14S / 14A and the anode electrode A of the gate pad electrode GP / source pad electrode SP / and heated at a low temperature, and the metal layer 14G / A surface activated junction is formed between the anode electrode A of the gate pad electrode GP and the source pad electrode SP.

As a result, as shown in FIG. 15, the gate surface activated bonding layer 48G, the source surface activated bonding layer 48S, the anode surface activated bonding layer 48A, and the first metal layers 14G, 14S, and 14A are formed by the surface activated bonding. A strong junction is formed between the semiconductor device 10T ₁ and the second semiconductor device 10D ₁ .

  In addition, after forming Cu, Ag, Au, Ti, Ni, Al, etc. on the surface of the opposing metal material which forms a surface activation joining, using a plating technique, a sputtering technique, or a vacuum evaporation technique, it is actual. A surface activation treatment may be performed.

  Alternatively, the surface activation treatment may be performed on the surface of the opposing metal material forming the surface activated bonding.

In the surface activated bonding process, the surfaces to be bonded are exposed to Ar ⁺ plasma in the chamber 300 to activate the surfaces.

  Next, in the chamber 300, the surfaces to be bonded are brought into contact with each other to form a temporary bond with a relatively low pressure.

  Next, under atmospheric pressure, a relatively low pressure (for example, about atmospheric pressure to about 10 MPa) and a heat of, for example, room temperature to about 150 ° C. are applied to the temporary bonding surface, and the two materials are surface-activated bonded. Let

  According to the second embodiment and the first and second modifications thereof, the semiconductor device in which the process temperature is lowered, the pressurizing pressure is reduced, and the process time is shortened by surface activated bonding, and the process A manufacturing method can be provided.

[Third embodiment]
A schematic planar pattern configuration of the semiconductor device 10 mounted on the semiconductor device 1 according to the third embodiment is expressed as shown in FIG. 19, and a schematic bird's-eye view structure is expressed as shown in FIG. A schematic cross-sectional structure taken along line III-III in FIG. 19 is expressed as shown in FIG.

  The semiconductor device 10 mounted on the semiconductor device 1 according to the third embodiment is disposed on the semiconductor substrate 26 and the interlayer insulating film 44 formed on the surface of the semiconductor substrate 26 as shown in FIGS. Gate pad electrode GP and source pad electrode SP, gate connector 18 disposed on gate pad electrode GP via gate surface activation bonding layer 48G, and source surface activation bonding layer 48S on source pad electrode SP. And a drain pad electrode 36 disposed on the drain region 24 formed on the back surface of the semiconductor substrate 26. The gate connector 18 has a T-shape. Since the detailed structure of the semiconductor device 10 is described in detail in FIGS. 25 to 26, the detailed structure is not shown in FIG.

  In FIG. 19, copper (Cu), silver (Ag), gold (Au), titanium (Ti), nickel (Ni), or the like may be formed on the surfaces of the source pad electrode SP and the gate pad electrode GP. . That is, a metal layer made of Cu, Ag, Au, Ti, Ni or the like is formed on the surface of the semiconductor device 10 on the source pad electrode SP / gate pad electrode GP by using a plating technique, a sputtering technique, a vacuum deposition technique, or the like. The surface activated bonding layers 48S and 48G may be formed between the source connector 20 and the gate connector 18.

  As shown in FIG. 22, the mounting substrate 70 on which the semiconductor device 1 according to the third embodiment is mounted includes an insulating substrate 8, and signal wiring electrodes 12 and power wiring electrodes 16 disposed on the insulating substrate 8. .

A schematic planar pattern configuration for explaining a state in which a plurality of semiconductor devices 10 ₁ , 10 ₂ , 10 _3, and 10 ₄ are mounted on a flip chip on the mounting substrate 70 of FIG. 22 is expressed as shown in FIG. A schematic planar pattern configuration of the semiconductor device 1 according to the embodiment in which a plurality of semiconductor devices 10 ₁ , 10 ₂ , 10 _3, and 10 ₄ are mounted on a flip chip on the mounting substrate 70 of FIG. 24, the schematic cross-sectional structure taken along the line IV-IV in FIG. 24 is represented as shown in FIG. 25, is the schematic cross-sectional structure taken along the line IV-IV in FIG. A schematic cross-sectional structure of the semiconductor device 1 according to the third embodiment mounted on is represented as shown in FIG. Although a configuration example in which a plurality of semiconductor devices 10 are arranged in parallel is disclosed here, only one semiconductor device 10 may be arranged. Here, in FIGS. 25 and 26, the interlayer insulating film 44 formed on the surface of the semiconductor substrate 26 is not shown.

As shown in FIGS. 19 to 26, the semiconductor device 1 according to the third embodiment is disposed on the insulating substrate 8, the signal wiring electrode 12 disposed on the insulating substrate 8, and the insulating substrate 8. On the surface of the semiconductor substrate 26, the power wiring electrode 16, flip-chip disposed on the insulating substrate 8, the semiconductor substrate 26, the source pad electrode SP and the gate pad electrode GP disposed on the back surface of the semiconductor substrate 26, and Semiconductor devices 10 ₁ , 10 ₂ , 10 ₃ , 10 ₄ having drain pad electrodes 36 ₁ , 36 ₂ , 36 ₃ , 36 ₄ disposed thereon and gate connectors 18 ₁ , 18 disposed on the gate pad electrode GP ₂ · 18 ₃ · 18 ₄ and source connectors 20 ₁ , 20 ₂ , 20 _3, and 20 ₄ disposed on the source pad electrode SP. Here, the gate connectors 18 ₁ , 18 ₂ , 18 ₃ , 18 ₄ , the gate pad electrode GP and the signal wiring electrode 12, the source connectors 20 ₁ , 20 ₂ , 20 ₃ , 20 ₄ , the source pad electrode SP and the power wiring electrode 16 Are surface activated bonded.

  In the semiconductor device 1 according to the third embodiment, the surface activation junction by the surface activation technique is formed on all of the gate pad electrode GP, the source pad electrode SP, and the drain pad electrode 36 of the semiconductor device 10. The source pad electrode SP is arranged face down so that the source pad electrode SP is on the back side. A flip-chip structure is realized by a face-down arrangement in which the gate pad electrode GP and the source pad electrode SP are arranged on the back surface and the drain pad electrode 36 is arranged on the surface. Since the surface activation junction by the surface activation technique is formed on all of the gate pad electrode GP, the source pad electrode SP, and the drain pad electrode 36 of the semiconductor device 10, complete wire bonding can be realized.

  In addition, as shown in FIG. 26, the semiconductor device 1 according to the third embodiment further includes a heat spreader 100 on which the mounting substrate 70 is mounted, and the mounting substrate 70 and the heat spreader 100 are surface-activated bonded. good.

The semiconductor device 1 according to the third embodiment includes the drain connector DC disposed on the drain pad electrodes 36 ₁ , 36 ₂ , 36 _3, and 36 ₄ as shown in FIGS. The drain pad electrodes 36 ₁ , 36 ₂ , 36 _3, and 36 ₄ and the drain connector DC are surface-activated bonded.

The gate connector 18 _1, 18 _2, 18 _3, 18 _4, as shown in FIG. 20, gate connector 18 _1, 18 _2, 18 _3, 18 ₄ of the T shape is in contact with the gate pad electrode GP The area where the gate connectors 18 ₁ , 18 ₂ , 18 _3, and 18 ₄ are in contact with the signal wiring electrode 12 may be larger than the area. Furthermore, the T-shaped shape of the gate connectors 18 ₁ , 18 ₂ , 18 _3, and 18 ₄ may have a bee-shaped shape that widens toward the end, or a tapered shape. The strength of the gate connectors 18 ₁ , 18 ₂ , 18 _3, and 18 ₄ can be increased by providing such a diverging bee shape or a tapered shape.

Further, the semiconductor device 1 according to the third embodiment, as shown in FIGS. 23 24, a plurality of semiconductor devices 10 _1, 10 _2, 10 _3, 10 _{4, 2,} semiconductor device 10 ₁ - 10 The plurality of gate connectors 18 ₁ , 18 ₂ , 18 _3, and 18 ₄ of 10 ₃ and 10 ₄ can be surface-activated bonded simultaneously with the gate pad electrode GP.

Further, the semiconductor device 1 according to the third embodiment, as shown in FIGS. 23 24, a plurality of semiconductor devices 10 _1, 10 _2, 10 _3, 10 _{4, 2,} semiconductor device 10 ₁ - 10 The plurality of source connectors 20 ₁ , 20 ₂ , 20 _3, and 20 ₄ of 10 ₃ and 10 ₄ can be surface-activated bonded simultaneously with the source pad electrode SP.

Further, the semiconductor device 1 according to the third embodiment, as shown in FIGS. 23 24, a plurality of semiconductor devices 10 _1, 10 _2, 10 _3, 10 _{4, 2,} semiconductor device 10 ₁ - 10 The plurality of drain pad electrodes 36 ₁ , 36 ₂ , 36 _3, and 36 ₄ of 10 ₃ and 10 ₄ can be surface-activated bonded simultaneously with the drain connector DC.

As shown in FIGS. 24 to 26, the semiconductor device 1 according to the third embodiment includes gate connectors 18 ₁ , 18 ₂ , 18 ₃ , 18 ₄ , gate pad electrodes GP, and signal wiring electrodes 12. A gate surface activation bonding layer 48G and a gate connector surface activation bonding layer 48GC formed by surface activation bonding may be provided therebetween.

Similarly, as shown in FIGS. 24 to 26, a source formed by surface activation bonding between the source connector 20 ₁ , 20 ₂ , 20 ₃ , 20 ₄ and the source pad electrode SP and the power wiring electrode 16 is used. A surface activated bonding layer 48S and a source connector surface activated bonding layer 48SC may be provided.

Similarly, as shown in FIGS. 24 to 26, a drain surface activation bonding layer formed by surface activation bonding between the drain connector DC and the drain pad electrodes 36 ₁ , 36 ₂ , 36 _3, and 36 _4. 48D may be provided.

  In the semiconductor device 1 according to the third embodiment, the mounting substrate 70 includes the metal layer 6 disposed on the back surface of the insulating substrate 8, and surface activation is performed between the metal layer 6 and the heat spreader 100. A heat spreader surface activated bonding layer 48H formed by bonding may be provided.

  The gate surface activation bonding layer 48G, the gate connector surface activation bonding layer 48GC, the source surface activation bonding layer 48S, the source connector surface activation bonding layer 48SC, the drain surface activation bonding layer 48D, and the heat spreader surface activation bonding layer 48H are , Cu, Ag, Au, Ti, Ni or Al can be formed by surface activated bonding of one or more metals selected from a combination. Here, one or more metals selected from a combination of Cu, Ag, Au, Ti, Ni, or Al can be formed using a plating technique, a sputtering technique, or a vacuum deposition technique.

The drain connector DC, the source connectors 20 ₁ , 20 ₂ , 20 _3, and 20 ₄ and the gate connectors 18 ₁ , 18 ₂ , 18 _3, and 18 ₄ are made of aluminum (Al), copper (Cu), and copper molybdenum (CuMo). An alloy, a copper tungsten (CuW) alloy, or Al—SiC can be used.

  In the semiconductor device 1 according to the third embodiment, when the surface activation bonding layers 48G, 48GC, 48S, 48SC, 48D, and 48H are formed, the pressure applied to the bonding portion is about atmospheric pressure or higher. It is desirable that the heating temperature is 10 MPa or less and the heating temperature is room temperature to about 150 ° C. or less.

(Modification 1)
A schematic bird's-eye view structure of the semiconductor device 1 according to the first modification of the third embodiment is represented as shown in FIG. 27A, and is a schematic cross-sectional structure taken along line VV in FIG. Is expressed as shown in FIG. In the semiconductor device 1 according to the first modification of the third embodiment, the plurality of semiconductor devices 10 ₁ , 10 _2, and 10 ₃ are arranged on the insulating substrate 8, respectively, as the signal wiring electrode 12 and the power wiring electrode 16. On the other hand, the drain connector DC is disposed in a flip chip and is commonly disposed on the drain pad electrodes 36 ₁ , 36 _2, and 36 ₃ . In the semiconductor device 1 according to the first modification of the third embodiment, the gate pad electrode GP and the source pad electrode SP are arranged in parallel, and the gate connectors 18 ₁ , 18 ₂ , which are arranged on the gate pad electrode GP. 18 ₃ and the source connectors 20 ₁ , 20 _2, and 20 ₃ disposed on the source pad electrode SP are disposed in parallel with each other in a stripe shape. In the semiconductor device 1 according to the first modification of the third embodiment, the gate pad electrode GP and the gate connectors 18 ₁ , 18 _2, and 18 ₃ disposed on the gate pad electrode GP are the third embodiment. In comparison, it is formed with a relatively large area to increase the bonding strength.

  Also in the first modification of the third embodiment, although not shown, the surface activation bonding layers 48G, 48GC, 48S, 48SC, 48D, and 48H are the same as the configuration of the third embodiment. Is arranged.

  Also in the semiconductor device 1 according to the first modification of the third embodiment, the pressure applied to the junction when forming the surface activation junction layers 48G, 48GC, 48S, 48SC, 48D, and 48H. Is about atmospheric pressure or more and about 10 MPa or less, and the heating temperature is desirably room temperature to about 150 ° C. or less.

(Modification 2)
In the semiconductor device according to the second modification of the third embodiment, a schematic cross-sectional structure taken along line IV-IV in FIG. 24 is expressed as shown in FIG.

In the semiconductor device according to the second modification of the third embodiment, as shown in FIG. 28, the gate connectors 18 ₁ , 18 ₂ , 18 _3, and 18 ₄ are omitted, and the gate pad electrode GP and the signal wiring electrode 12 are omitted. The gate surface activation bonding layer 48G formed by surface activation bonding is provided.

Similarly, as shown in FIG. 28, the source connectors 20 ₁ , 20 ₂ , 20 _3, and 20 ₄ are omitted, and the source formed by surface activation bonding between the source pad electrode SP and the power wiring electrode 16. A surface activated bonding layer 48S is provided. Other configurations are the same as those of the third embodiment.

(Modification 3)
In the semiconductor device according to the third modification of the third embodiment, a schematic cross-sectional structure taken along line IV-IV in FIG. 24 is represented as shown in FIG.

In the semiconductor device according to the third modification of the third embodiment, a direct surface activation junction is provided between the gate connectors 18 ₁ , 18 ₂ , 18 _3, and 18 ₄ and the gate pad electrode GP and the signal wiring electrode 12. doing.

Similarly, as shown in FIG. 29, the surface connectors 20 ₁ , 20 ₂ , 20 _3, and 20 ₄ and the source pad electrode SP and the power wiring electrode 16 are directly surface-activated joined.

Further, as shown in FIG. 29, the surface activation bonding is directly performed between the drain connector DC and the drain pad electrodes 36 ₁ , 36 ₂ , 36 _3, and 36 ₄ .

As shown in the semiconductor device according to the third modification of the third embodiment, the surface activation bonding is directly performed between the electrode layer of the semiconductor device and the opposing metal layer, thereby reducing the number of manufacturing steps and the manufacturing cost. Can be reduced. Other configurations are the same as those of the third embodiment. Note that FIG. 29 shows an example in which the heat spreader surface activation bonding layer 48H is disposed between the metal layer 6 and the heat spreader 100. The metal layer 6 and the heat spreader 100 may be directly surface activated bonded.

(Modification 4)
As shown in FIG. 30, the semiconductor device 1 according to the fourth modification of the third embodiment is disposed through the insulating substrate 8, the signal wiring electrode 12 disposed on the insulating substrate 8, and the insulating substrate 8. The power wiring electrode 16a, the flip-chip disposed on the insulating substrate 8, the source pad electrode SP and the gate pad electrode GP disposed on the back surface of the semiconductor substrate 26, and the surface of the semiconductor substrate 26 includes a semiconductor device 10 ₁ having the drain pad electrode 36 disposed above the gate pad electrode GP gate connector 18 ₁ disposed on, the source pad electrode SP source connector disposed on 20 _1. The gate connector 18 ₁ and the gate pad electrode GP and the signal wiring electrode 12 and the source connector 20 ₁ and the source pad electrode SP and power wiring electrode 16, is bonded surface activation. The configuration in FIG. 30 corresponds to the configuration in FIG. 25 in the third embodiment.

In the semiconductor device 1 according to the fourth modification of the third embodiment, the power wiring electrode 16a is disposed through the insulating substrate 8. Here, the power wiring electrode 16a is formed of, for example, a thick copper plate having a thickness of about 0.5 mm to about 1.0 mm. On power wiring electrodes 16a, for example, by forming a silver plating layer 19, it may facilitate the connection between the source connector 20 _1.

  With the power wiring electrode 16a, a large current of, for example, about several hundred amperes can be applied in the thickness direction of the insulating substrate 8 through a thick copper plate having low resistance and excellent heat dissipation.

  Further, as shown in FIG. 31, the semiconductor device 1 according to the fourth modification of the third embodiment further includes a heat spreader 100 on which the mounting substrate 70 is mounted, and the mounting substrate 70 and the heat spreader 100 are surface activated bonded. May be. The other configuration is the same as that of the third embodiment, and a duplicate description is omitted.

(Modification 5)
A schematic bird's-eye view structure of the semiconductor device 1 according to Modification 5 of the third embodiment is represented as shown in FIG. 32A, and is a schematic cross-sectional structure taken along line VI-VI in FIG. Is expressed as shown in FIG. In the semiconductor device 1 according to the fifth modification of the third embodiment, a plurality of semiconductor devices 10 ₁ , 10 _2, and 10 ₃ are passed through the signal wiring electrodes 12 and the insulating substrate 8 arranged on the insulating substrate 8. Thus, the power connector electrode 16a is arranged on a flip chip, and the drain connector DC is arranged on the drain pad electrodes 36 ₁ , 36 ₂ , 36 ₃ in common. In the semiconductor device 1 according to the fifth modification of the third embodiment, the gate pad electrode GP and the source pad electrode SP are arranged in parallel, and the gate connectors 18 ₁ , 18 ₂ , and the like arranged on the gate pad electrode GP. 18 ₃ and the source connectors 20 ₁ , 20 _2, and 20 ₃ disposed on the source pad electrode SP are disposed in parallel with each other in a stripe shape.

Also in the semiconductor device 1 according to the fifth modification of the third embodiment, as in the fourth modification, the power wiring electrode 16 a is disposed through the insulating substrate 8. For example, a silver plating layer 19 may be formed on the power wiring electrode 16a to facilitate connection with the source connectors 20 ₁ , 20 _2, and 20 ₃ . The other configuration is the same as that of the first modification of the third embodiment, and a duplicate description is omitted.

(Modification 6)
FIG. 33 shows a schematic cross-sectional structure taken along line IV-IV in FIG. 24, which is a semiconductor device according to Modification 6 of the third embodiment.

In the semiconductor device according to Modification 6 of the third embodiment, the gate connectors 18 ₁ , 18 ₂ , 18 _3, and 18 ₄ are omitted as shown in FIG. 33 as compared with Modification 4 (FIG. 30). In addition, a gate surface activation bonding layer 48G formed by surface activation bonding is provided between the gate pad electrode GP and the signal wiring electrode 12.

Similarly, as shown in FIG. 33, the source connectors 20 ₁ , 20 ₂ , 20 _3, and 20 ₄ are omitted, and the source pad electrode SP and the power wiring electrode 16 are not compared with the fourth modification (FIG. 30). Are provided with a source surface activated bonding layer 48S formed by surface activated bonding. Other configurations are the same as those of the third embodiment.

(Modification 7)
FIG. 34 shows a schematic cross-sectional structure taken along line IV-IV in FIG. 24, which is a semiconductor device according to Modification 7 of the third embodiment.

In the semiconductor device according to Modification 7 of the third embodiment, as shown in FIG. 34, gate connectors 18 ₁ , 18 ₂ , 18 ₃ , 18 ₄ , gate pad electrode GP and signal wiring electrode 12 Directly surface-activated bonding between them.

Similarly, as shown in FIG. 34, the source connectors 20 ₁ , 20 ₂ , 20 _3, and 20 ₄ and the source pad electrode SP and the power wiring electrode 16 are directly surface-activated joined.

Further, as shown in FIG. 34, the drain connector DC and the drain pad electrodes 36 ₁ , 36 ₂ , 36 ₃ and 36 ₄ are directly surface-activated joined.

As shown in the semiconductor device according to the modified example 7 of the third embodiment, the surface activation bonding is directly performed between the electrode layer of the semiconductor device and the opposing metal layer, thereby reducing the number of manufacturing steps and the manufacturing cost. Can be reduced. Other configurations are the same as those of the third embodiment. Note that FIG. 34 shows an example in which the heat spreader surface activation bonding layer 48H is disposed between the metal layer 6 and the heat spreader 100. The metal layer 6 and the heat spreader 100 may be directly surface activated bonded.

(Method for manufacturing semiconductor device)
As shown in FIG. 25, the manufacturing method of the semiconductor device 1 according to the third embodiment includes a gate surface activation junction by surface activation joining a gate connector 18 ₁ , a gate pad electrode GP and a signal wiring electrode 12. forming a layer 48G and the gate connector surface activated bonding layer 48GC, the source connector 20 ₁ and the source pad electrode SP and power wiring electrodes 16a and joined surface activation, the source surface activated bonding layer 48S and a source connector surface Forming an activated bonding layer 48SC.

A method of manufacturing a semiconductor device 1 according to the third embodiment, as shown in FIG. 25, a drain connector DC and the drain pad electrode 36 ₁ and joined surface activation, the drain surface activated bonding layer 48D You may have the process to form.

  The step of forming the gate surface activation bonding layer 48G and the gate connector surface activation bonding layer 48GC and the step of forming the source surface activation bonding layer 48S and the source connector surface activation bonding layer 48SC are performed simultaneously. Also good.

  Further, the step of forming the drain surface activation bonding layer 48D and the step of forming the source surface activation bonding layer 48S and the source connector surface activation bonding layer 48SC may be performed simultaneously.

  Further, in the method of manufacturing the semiconductor device 1 according to the third embodiment, as shown in FIG. 26, the metal layer 6 disposed on the back surface of the insulating substrate 8 and the heat spreader 100 are surface-activated bonded to form a heat spreader. You may have the process of forming the surface activation joining layer 48H.

  In the method for manufacturing the semiconductor device 1 according to the third embodiment, the pressure for forming the surface activation junction is, for example, about atmospheric pressure to about 10 MPa, and the heating temperature is, for example, room temperature to about 150. It is below ℃.

(Drain surface activated bonding)
Cu, Ag, Au, Ti, Ni, Al, or the like is formed on the drain side surface of the semiconductor device 10 using a plating technique, a sputtering technique, or a vacuum deposition technique. For example, a structure of the drain pad electrode 36 in which Ti / Ni / Au / Ag is sequentially stacked on the drain region 24 may be formed. When the source electrode 34 of the semiconductor device 10 is formed of Al, an electrode structure in which Ni / Ag is sequentially stacked on the Al may be formed.

  Further, Cu, Ag, Au, Ti, Ni, Al, or the like may be formed on the back surface of the drain connector DC by using a plating technique, a sputtering technique, or a vacuum deposition technique.

Both / one surface of Ti / Ni / Au / Ag formed on the drain side surface of the semiconductor device 10 and Cu, Ag, Au, Ti, Ni, etc. formed on the back surface of the drain connector DC In the chamber, the surface is activated by exposure to Ar ⁺ plasma.

  Next, Ti / Ni / Au / Ag formed on the drain side surface of the semiconductor device 10 and the surface of Cu, Ag, Au, Ti, Ni, etc. formed on the back surface of the drain connector DC are brought into contact with each other. At this time, a relatively low pressure P is applied to make contact.

  Next, under atmospheric pressure, Ti / Ni / Au / Ag formed on the drain side surface of the semiconductor device 10 and Cu, Ag, Au, Ti, Ni, etc. formed on the back surface of the drain connector DC. A surface activated bond is formed by applying a relatively low pressure P1 while heating the surface at a relatively low temperature. The pressure for forming the surface activated bonding is, for example, about atmospheric pressure or more and about 10 MPa or less, and the heating temperature is, for example, room temperature to about 150 ° C. or less.

  The holding time of the heating temperature (about 150 ° C. or less) is about 1 minute, the cooling time from the heating temperature to room temperature and the temperature rising time from the room temperature to the heating temperature are about several minutes in total. , Within a few minutes.

(Heat spreader surface activated bonding)
Bonding between the insulating substrate 8 and a base plate such as the heat spreader 100 can be similarly formed. That is, metal layers 100a and 100b made of Cu, Ag, Au, Ti, Ni, Al, or the like are formed on the surface of the heat spreader 100 using a plating technique, a sputtering technique, or a vacuum deposition technique. Further, the metal layers 14 and 6 made of Cu, Ag, Au, Ti, Ni or the like are formed on the surface of the insulating substrate 8 by using a plating technique, a sputtering technique, or a vacuum evaporation technique.

Thereafter, the back surface of the insulating substrate 8 and the surface of the heat spreader 100 are exposed to Ar ⁺ plasma in the chamber to activate the surface.

  Next, under atmospheric pressure, pressure and heat are applied in the same manner as described above to form the heat spreader surface activation bonding layer 48H.

  Next, a gate surface activation bonding layer 48G is formed between the gate connector 18 on the back side of the semiconductor device 10 and the gate pad electrode GP, and a source surface activation bonding layer 48S is formed between the source connector 20 and the source pad electrode SP. You may do it.

  Next, the drain surface activation bonding layer 48D may be formed by bringing the surface of the drain pad electrode 36 of the semiconductor device 10 into contact with the back surface of the drain connector DC and applying pressure and heat in the same manner as described above.

  The order in which the surface activated bonding layers are formed is limited to the order of the heat spreader surface activated bonding layer 48H, the gate surface activated bonding layer 48G, the source surface activated bonding layer 48S, and the drain surface activated bonding layer 48D. The order can be selected as appropriate. For example, the drain surface activated bonding layer 48D, the source surface activated bonding layer 48S, and the gate surface activated bonding layer 48G may be formed in the same process, and finally the heat spreader surface activated bonding layer 48H may be formed.

(Source surface activated junction / gate surface activated junction)
In the method for manufacturing the semiconductor device 1 according to the third embodiment, first, as shown in FIG. 20, a source connector 20 and a gate connector 18 for bonding to the source pad electrode SP and the gate pad electrode GP are prepared. As materials for the source connector 20 and the gate connector 18, basically, a material having high electrical conductivity and high thermal conductivity, and a material having a thermal expansion coefficient close to that of the semiconductor device 10 to be mounted are selected. For example, a material such as Al or Cu can be selected as the material having high electrical conductivity and thermal conductivity. Alternatively, from the viewpoint of a material having a thermal expansion coefficient close to that of the semiconductor device 10 to be mounted, a material such as CuMo, CuW, or Al—SiC can be selected. On the surface of the material of the source connector 20 and the gate connector 18, Cu, Ag, Au, Ti, and Ni may be formed using a plating technique, a sputtering technique, or a vacuum deposition technique.

  Next, although not shown on the surfaces of the gate pad electrode GP and the source pad electrode SP, a metal layer made of Cu, Ag, Au, Ti, Ni or the like is applied with a plating technique, a sputtering technique, or a vacuum evaporation technique. You may form using.

  Here, the material of the metal layer can be changed depending on the material of the source connector 20 and the gate connector 18 that are surface-activated bonded to them. For example, when the gate connector / 18 source connector 20 is covered with an Ag plating layer, a metal layer made of Ag is formed on the gate pad electrode GP / source pad electrode SP using a plating technique, a sputtering technique, or a vacuum deposition technique. It is possible to form and facilitate surface activated bonding between Ags.

  When the gate pad electrode GP and the source pad electrode SP are made of Al, the gate connector 18 and the source connector 20 are preferably plated with Ni in order to prevent oxidation of Al. Since Al is a very soft metal, plastic deformation easily occurs in the surface activation joining process, but Ni plating is performed on the gate connector 18 and the source connector 20 to realize a state where there is little oxide film. Thus, surface activated bonding can be facilitated.

  The configuration of the semiconductor device 1 according to the third embodiment after the manufacturing process is expressed as shown in FIGS.

  As shown in FIGS. 25 to 26, a drain surface activation bonding layer 48 </ b> D is formed between the drain pad electrode 36 and the drain connector DC of the semiconductor device 10, and between the gate connector 18 and the gate pad electrode GP / signal wiring electrode 12. Then, the gate surface activation bonding layer 48G and the gate connector surface activation bonding layer 48GC are formed.

  Similarly, as shown in FIGS. 25 to 26, a source surface activation bonding layer 48 </ b> S and a source connector surface activation bonding layer 48 </ b> SC are formed between the source connector 20 and the source pad electrode SP / power wiring electrode 16.

  In the method for manufacturing the semiconductor device 1 according to the third embodiment, in the drain surface activation bonding step between the drain pad electrode 36 of the semiconductor device 10 and the drain connector DC, the surface of the drain pad electrode 36 is, for example, Since the rear surface of the drain connector DC is formed of Ag, for example, Ag plating is performed, a surface activation bonding layer 48D by Ag-Ag bonding is formed. The melting temperature of the surface activated bonding layer 48D is also about 960 ° C., which is the melting point of Ag.

  In the semiconductor device 1 according to the third embodiment, the surface activation bonding layer 48D having a high melting point is obtained by a relatively low heating step of room temperature to about 150 ° C. and a low pressurization step of about atmospheric pressure to about 10 MPa. · 48S · 48SC · 48H · 48G · 48GC can be obtained.

  In the semiconductor device 1 according to the third embodiment, the source pad electrode SP and the gate pad electrode GP are surface-activated joined to the source connector 20 and the gate connector 18, and the power wiring electrode 16 and the signal wiring electrode 12 are connected. Surface activated bonding to the source connector 20 and the gate connector 18 and surface activated bonding of the drain pad electrode 36 to the drain connector DC realize a complete wire bondless structure and a double-sided cooling structure of the semiconductor device 10 can do.

  Furthermore, by performing surface activation bonding of the mounting substrate 70 to the heat spreader 100, the double-sided cooling performance of the semiconductor device 10 can be further improved.

  In addition, since the manufacturing method of the semiconductor device 1 according to the first to seventh modifications of the third embodiment is the same as that of the embodiment, the duplicate description is omitted.

  According to the third embodiment and modifications 1 to 7 thereof, the semiconductor device in which the process temperature is lowered, the pressurizing pressure is reduced, and the process time is shortened by surface activated bonding, and the process A manufacturing method can be provided.

  According to the present invention, it is possible to provide a semiconductor device in which the process temperature is lowered and the process time is shortened by surface activated bonding, and a manufacturing method thereof.

[Other embodiments]
As described above, the embodiments have been described. However, it should be understood that the descriptions and drawings constituting a part of this disclosure are illustrative and do not limit the present invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  As described above, the present invention includes various embodiments not described herein.

  The semiconductor device of the present invention can be used for all power devices such as a power semiconductor module and an intelligent power module.

DESCRIPTION OF SYMBOLS 1 ... Semiconductor device 5, 6, 14, 14D, 14K, 100a, 100b ... Metal layer 7 ... Semiconductor substrate 8 ... Insulating substrate 10, 10 ₁ , 10 ₂ , 10 ₃ , 10 ₄ , 10T ₁ , 10T ₂ , 10T ₃ 10T ₄ , 10D ₁ , 10D ₂ ... Semiconductor device 12, 12 G... Signal wiring electrode 16, 16 a, 16 S... Power wiring electrode 18, 18 ₁ , 18 ₂ , 18 ₃ , 18 ₄ . , 20 ₁ , 20 ₂ , 20 ₃ , 20 ₄ , 20T ₁ , 20T ₂ ... source connector 20A ... anode connector 22 ... upper surface plate electrode 24 ... drain region 26, 26T, 26D ... high resistance substrate 28 ... base region 30 ... source Region 32 ... Gate insulating film 34 ... Source electrode 36 ... Drain pad electrode 38 ... Gate electrode 44 ... Interlayer insulating film 48G ... Gate surface activation bonding layer 48K ... Kaso Surface activated bonding layer 48A ... Anode surface activated bonding layer 48GC ... Gate connector surface activated bonding layer 48S ... Source surface activated bonding layer 48SC ... Source connector surface activated bonding layer 48D ... Drain surface activated bonding layer 48H ... Heat spreader Surface activated bonding layer 50 ... gate drive unit 52 ... power module unit 54 ... three-phase AC motor unit 70 ... mounting substrate 100 ... heat spreader 300 ... chamber 400 ... chuck 500 ... chip pocket C ... capacitors D1-D6 ... diode GP ... gate Pad electrode SP ... Source pad electrode DC ... Drain connector BL1, BL2 ... Bonding wire

Claims (45)

A first insulating substrate;
A first semiconductor substrate, a source pad electrode and a gate pad electrode arranged on the surface of the first semiconductor substrate, and a drain arranged on the back surface of the first semiconductor substrate. A first semiconductor device having a pad electrode;
A second semiconductor substrate disposed on the first insulating substrate, having a second semiconductor substrate, an anode electrode disposed on the front surface of the second semiconductor substrate, and a cathode electrode disposed on the back surface of the second semiconductor substrate. With two semiconductor devices,
The drain pad electrode and the first insulating substrate, and the cathode electrode and the first insulating substrate are surface activated bonded. A signal wiring electrode disposed on the first insulating substrate;
The semiconductor device according to claim 1, further comprising: a bonding wire that connects the gate pad electrode and the signal wiring electrode. A source connector disposed on the source pad electrode;
3. The method according to claim 2, further comprising an anode connector disposed on the anode electrode, wherein the source pad electrode and the source connector, and between the anode electrode and the anode connector are surface activated. The semiconductor device described.   The semiconductor device according to claim 3, further comprising a first upper surface plate electrode disposed flush with the source connector and the anode connector.   A second insulating substrate disposed on the source pad electrode, the gate pad electrode and the anode electrode; the source pad electrode and the second insulating substrate; the gate pad electrode and the second insulating substrate; and the anode electrode. The semiconductor device according to claim 1, wherein the second insulating substrate is surface-activated bonded.   A second upper surface plate electrode disposed on the source pad electrode, the gate pad electrode and the anode electrode; the source pad electrode and the second upper surface plate electrode; the gate pad electrode and the second upper surface plate electrode; The semiconductor device according to claim 1, wherein the anode electrode and the second upper surface plate electrode are surface-activated bonded.   First and second metal layers disposed on the surface of the first insulating substrate, and surface activation between the first metal layer and the drain pad electrode and between the second metal layer and the cathode electrode. 2. The semiconductor device according to claim 1, further comprising a drain surface activated bonding layer and a cathode surface activated bonding layer formed by bonding.   A source connector surface activation bonding layer and an anode connector surface activation bonding layer formed by surface activation bonding are provided between the source connector, the source pad electrode, and the anode connector and the anode electrode. The semiconductor device according to claim 4.   A source surface activated bonding layer formed by surface activated bonding between the second insulating substrate and the source pad electrode, the second insulating substrate and the gate pad electrode, and the second insulating substrate and the anode electrode. 7. The semiconductor device according to claim 6, further comprising a gate surface activated bonding layer and an anode surface activated bonding layer.   Source surface activity formed by surface activated bonding between the second upper surface plate electrode and the source pad electrode, the second upper surface plate electrode and the gate pad electrode, and the second upper surface plate electrode and the anode electrode. The semiconductor device according to claim 7, further comprising an activation junction layer, a gate surface activation junction layer, and an anode surface activation junction layer. A first insulating substrate;
A flip chip is disposed on the first insulating substrate, and a first semiconductor substrate, a source pad electrode and a gate pad electrode disposed on the back surface of the first semiconductor substrate, and a surface of the first semiconductor substrate. A first semiconductor device having a drain pad electrode formed;
A second semiconductor substrate disposed on the first insulating substrate, having a second semiconductor substrate, an anode electrode disposed on the back surface of the second semiconductor substrate, and a cathode electrode disposed on the surface of the second semiconductor substrate. With two semiconductor devices,
The gate pad electrode and the first insulating substrate, the source pad electrode and the first insulating substrate, the anode electrode and the first insulating substrate are surface-activated bonded.   A third upper surface plate electrode disposed on the drain pad electrode and the cathode electrode; the drain pad electrode and the third upper surface plate electrode; and the cathode electrode and the third upper surface plate electrode are surface-activated bonded. The semiconductor device according to claim 11.   A second insulating substrate disposed on the drain pad electrode and the cathode electrode; the drain pad electrode and the second insulating substrate; and the cathode electrode and the second insulating substrate insulating substrate are surface-activated bonded. The semiconductor device according to claim 11.   A gate surface activation bonding layer formed by surface activation bonding between the first insulating substrate and the gate pad electrode, the first insulating substrate and the source pad electrode, and the first insulating substrate and the anode electrode. The semiconductor device according to claim 11, further comprising a source surface activated bonding layer and an anode surface activated bonding layer.   A drain surface activation bonding layer and a cathode surface activation bonding layer formed by surface activation bonding are provided between the third upper surface plate electrode, the drain pad electrode, and the third upper surface plate electrode, and the cathode electrode. The semiconductor device according to claim 12.   A drain surface activated bonding layer and a cathode surface activated bonding layer formed by surface activated bonding are provided between the second insulating substrate, the drain pad electrode, and the second insulating substrate and the cathode electrode. The semiconductor device according to claim 13.   The semiconductor device according to claim 1, further comprising a heat spreader on which the first insulating substrate is mounted, wherein the first insulating substrate and the heat spreader are surface-activated bonded.   A metal layer disposed on a back surface of the first insulating substrate, and a heat spreader surface activation bonding layer formed by surface activation bonding between the metal layer and the heat spreader. Item 18. The semiconductor device according to Item 17.   The gate surface activated bonding layer, the source surface activated bonding layer, and the anode surface activated bonding layer may be any one or a plurality of metals selected from a combination of Cu, Ag, Au, Ti, Ni, or Al. 15. The semiconductor device according to claim 10, wherein the semiconductor device is formed by surface activated bonding.   The heat spreader surface activated bonding layer is formed by surface activated bonding of one or more metals selected from a combination of Cu, Ag, Au, Ti, Ni, or Al. Item 19. A semiconductor device according to Item 18.   The semiconductor device according to claim 3, wherein the source connector and the anode connector are formed of any one of Al, Cu, CuMo, CuW, and AlSiC.   The first semiconductor device and the second semiconductor device are any of SiC-based, GaN-based, AlN-based, diamond-based, or Si-based power devices. The semiconductor device according to item.   The semiconductor device according to any one of claims 1 to 22, wherein the first semiconductor device and the second semiconductor device use a semiconductor having a band gap energy of 1.1 eV to 8 eV.   The said 1st semiconductor device and the said 2nd semiconductor device are applied to any one module of a one-in-one, a two-in-one, a four-in-one, and six-in-one, The one of Claims 1-21 characterized by the above-mentioned. Semiconductor device. An insulating substrate;
A signal wiring electrode disposed on the insulating substrate;
A power wiring electrode disposed on or through the insulating substrate;
A flip chip is disposed on the insulating substrate, and includes a semiconductor substrate, a source pad electrode and a gate pad electrode disposed on the back surface of the semiconductor substrate, and a drain pad electrode disposed on the surface of the semiconductor substrate. A semiconductor device, wherein the signal wiring electrode and the gate pad electrode, the source pad electrode and the power wiring electrode are surface-activated bonded. An insulating substrate;
A signal wiring electrode disposed on the insulating substrate;
A power wiring electrode disposed on or through the insulating substrate;
A flip chip is disposed on the insulating substrate, and includes a semiconductor substrate, a source pad electrode and a gate pad electrode disposed on the back surface of the semiconductor substrate, and a drain pad electrode disposed on the surface of the semiconductor substrate. A semiconductor device;
A gate connector disposed on the gate pad electrode;
A source connector disposed on the source pad electrode, wherein the gate connector, the gate pad electrode and the signal wiring electrode, and the source connector, the source pad electrode and the power wiring electrode are surface-activated bonded. A semiconductor device.   27. The semiconductor device according to claim 25, further comprising a heat spreader on which the insulating substrate is mounted, wherein the insulating substrate and the heat spreader are surface-activated bonded.   27. The semiconductor device according to claim 26, further comprising a drain connector disposed on the drain pad electrode, wherein the drain pad electrode and the drain connector are surface-activated bonded.   27. The gate connector according to claim 26, wherein the gate connector has an inverted T shape, and an area where the gate connector contacts the signal wiring electrode is larger than an area where the gate connector contacts the gate pad electrode. The semiconductor device described.   27. The semiconductor device according to claim 26, comprising a plurality of the semiconductor devices, wherein the plurality of gate connectors of the semiconductor devices can be surface-activated bonded simultaneously with the gate pad electrode.   27. The semiconductor device according to claim 26, comprising a plurality of the semiconductor devices, wherein the plurality of source connectors of the semiconductor devices can be surface-activated bonded simultaneously with the source pad electrodes.   29. The semiconductor device according to claim 28, comprising a plurality of the semiconductor devices, wherein the plurality of drain pad electrodes of the semiconductor devices can be surface-activated bonded simultaneously with the drain connector.   27. A gate surface activation bonding layer and a gate connector surface activation bonding layer formed by surface activation bonding are provided between the gate connector and the gate pad electrode and the signal wiring electrode. A semiconductor device according to 1.   27. A source surface activation bonding layer and a source connector surface activation bonding layer formed by surface activation bonding are provided between the source connector, the source pad electrode, and the power wiring electrode. A semiconductor device according to 1.   27. The semiconductor device according to claim 26, further comprising a drain surface activation bonding layer formed by surface activation bonding between the drain connector and the drain pad electrode.   28. A metal layer disposed on the back surface of the insulating substrate, and a heat spreader surface activated bonding layer formed by surface activated bonding between the metal layer and the heat spreader. A semiconductor device according to 1.   The gate surface activated bonding layer and the gate connector surface activated bonding layer are formed by surface activated bonding of one or more metals selected from a combination of Cu, Ag, Au, Ti, Ni, or Al. 34. The semiconductor device according to claim 33, wherein:   The source surface activated bonding layer and the source connector surface activated bonding layer are formed by surface activated bonding of one or more metals selected from a combination of Cu, Ag, Au, Ti, Ni, or Al. 35. The semiconductor device according to claim 34, wherein:   The drain surface activated bonding layer is formed by surface activated bonding of one or more metals selected from a combination of Cu, Ag, Au, Ti, Ni, or Al. 35. The semiconductor device according to 35.   The heat spreader surface activated bonding layer is formed by surface activated bonding of one or more metals selected from a combination of Cu, Ag, Au, Ti, Ni or Al. 37. The semiconductor device according to claim 36.   27. The semiconductor device according to claim 26, wherein the gate connector and the source connector are formed of any one of Al, Cu, CuMo, CuW, or AlSiC.   27. The semiconductor device according to claim 25, wherein the semiconductor device is a power device of any one of a SiC system, a GaN system, an AlN system, a diamond system, and a Si system.   27. The semiconductor device according to claim 25, wherein the semiconductor device uses a semiconductor having a band gap energy of 1.1 eV to 8 eV. Under vacuum or inert gas, a semiconductor device and a metal to be bonded opposed to the semiconductor device are passed through the metal applied to the semiconductor device or to the surface of the semiconductor device itself. A step of surface activation treatment with the surface of the joint metal,
A step of applying a first pressure between the semiconductor device and the metal to be bonded under vacuum or inert gas, and temporarily bonding;
Under atmospheric pressure, applying a second pressure between the semiconductor device and the metal to be bonded and heating at a low temperature to form a surface activated bond between the semiconductor device and the metal to be bonded; A method for manufacturing a semiconductor device, comprising:   45. The method according to claim 44, wherein the surface activation treatment is performed to prevent reattachment after removing an oxide film or an adsorbed molecule on the surface of the semiconductor device or the surface of the metal to be bonded. A method for manufacturing a semiconductor device.

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