JP2018046163A - Semiconductor device and semiconductor device manufacturing method - Google Patents

Abstract

A semiconductor device and a method for manufacturing the semiconductor device that can be easily manufactured and can be set to a predetermined gate threshold voltage while maintaining a withstand voltage. A MOS gate having a trench gate structure is provided on the front surface side of a silicon carbide substrate. The gate trench 8 constituting the trench gate structure penetrates the n + type source region 6 and the p type base region 3 and reaches the n − type drift region 2. Between the adjacent gate trenches 8, apart from the gate trench 8, a first p + -type region 4 that penetrates the p-type base region 3 in the depth direction and reaches the n − -type drift region 2 is provided. The first p + type region 4 is provided immediately below the p + + type contact region 7. The width p 2 of the first p + -type region 4 is narrower than the width w 1 of the gate trench 8. A second p + -type region 5 is provided at the bottom of the gate trench 8. First and second p + type regions 4 and 5 are silicon carbide epitaxial growth layers. [Selection] Figure 1

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

  Silicon carbide (SiC) has excellent physical properties such as a band gap that is about three times wider than that of silicon (Si), a breakdown electric field strength that is nearly an order of magnitude higher, and a high saturation drift velocity of electrons. . For this reason, silicon has been widely used as a material for power semiconductor devices, but in order to exceed the performance of power semiconductor devices using silicon, it is effective to use silicon carbide as a material for power semiconductor devices. .

  Conventionally, a vertical MOSFET (Metal Oxide Field Effect Transistor), which is a switching device, has a planar gate structure in which a MOS gate is provided in a flat plate shape on a semiconductor substrate, and the semiconductor substrate is formed on a semiconductor substrate. Two types of MOS gate structures are widely known: a trench gate structure in which a MOS gate is embedded in a trench.

  In recent vertical power semiconductor devices, a trench gate structure has attracted attention. In the trench gate structure, since the channel is formed perpendicular to the front surface of the substrate, the cell width can be reduced as compared with the planar gate structure in which the channel is formed parallel to the front surface of the substrate. This is because the cell density per unit area can be increased and the current density per unit area can be increased, which is advantageous in terms of cost.

  For this reason, vertical MOSFETs using silicon also have a history of shifting from a planar gate structure to a trench gate structure. For this reason, also in the vertical MOSFET using silicon carbide, a trench gate structure is finally required, as in the vertical MOSFET using silicon.

  However, in the vertical MOSFET using silicon carbide, due to the adverse effect of residual carbon (C) near the channel and the difficulty in processing the trench gate structure, when the trench gate structure is adopted, the vertical MOSFET using silicon is different from the vertical MOSFET using silicon. However, the channel mobility is greatly reduced. For this reason, channel resistance becomes high and the predominance with respect to silicon falls. In order to reduce the channel resistance, measures such as shortening the channel length or reducing the impurity concentration of the base region along the trench sidewall where the channel is formed to make the channel polarity easier to reverse are taken. To do. However, when the channel length is shortened, the distance between the drift region and the source region becomes closer, so punch-through (a phenomenon in which a current flows between the drain and the source without applying a gate voltage) is likely to occur, and the withstand voltage (withstand voltage) There is concern about the decline.

  In addition, when the impurity concentration in the base region is lowered, a depletion layer (channel) of majority carriers easily spreads from the boundary between the gate insulating film and the base region into the base region when a gate voltage is applied. As a result, the electric field strength applied to the channel is weakened, so the minority carrier density in the channel is difficult to increase, and it is necessary to apply a high gate voltage to increase the minority carrier density in the channel and reverse the polarity of the channel. The effect of lowering the gate threshold voltage obtained by lowering the impurity concentration of the base region is small. That is, when the gate threshold voltage is used as a reference, if the gate threshold voltage is to be increased, the impurity concentration of the base region must be sufficiently increased, so that the channel resistance is excessively increased. Is unnecessarily lowered, and there is a concern about a decrease in pressure resistance. The breakdown voltage is a voltage at which avalanche breakdown occurs.

  As a vertical MOSFET having a trench gate structure using silicon carbide, an n-channel MOSFET having a reduced channel resistance by providing an n-type region having a high electron mobility along the inner wall of the trench has been proposed (for example, (See the following Patent Document 1 (paragraph 0032, FIG. 1).) In Patent Document 1 below, the channel resistance is reduced by making the portion of the p-type base region along the trench sidewall, which is a factor for determining the gate threshold voltage, n-type.

  Further, as another vertical MOSFET having a trench gate structure using silicon carbide, silicon carbide is used as a semiconductor material, the width of the p-type base region sandwiched between adjacent trenches is reduced, and the impurity concentration is reduced. An apparatus has been proposed (see, for example, Patent Document 2 below (paragraphs 0033 to 0034, FIGS. 1 to 3)). In Patent Document 2 below, the width of the p-type base region is narrowed to suppress the spread of the depletion layer of majority carriers and suppress the decrease in breakdown voltage.

Japanese Patent No. 4678902 JP 2011-023675 A

  However, when a portion of the p-type base region along the sidewall of the trench is made to have a low impurity concentration or an n-type structure as in Patent Document 1 is formed by ion implantation, it is perpendicular to the front surface of the substrate. In the ion implantation of n-type impurities from the direction, there are problems that the amount of n-type impurities implanted into the trench sidewall is small and the depth of implantation of the n-type impurities is small. Therefore, in order to ensure the implantation amount and implantation depth of the n-type impurity, it is necessary to ion-implant the n-type impurity into the trench sidewall from a direction oblique to the front surface of the substrate. Since it is necessary to perform ion implantation at every implantation angle, a new problem of increasing the number of ion implantations occurs.

  Moreover, in the said patent document 1, the n-type impurity density | concentration in a trench bottom part becomes high because an n-type area | region is provided along the trench bottom part. For this reason, when the MOSFET is turned off, the electric field concentration at the bottom of the trench becomes strong, and there is a possibility that the breakdown voltage is reduced due to the dielectric breakdown of the gate insulating film at the portion along the bottom of the trench. In Patent Document 2, it is difficult to form a MOS gate structure at a portion where the trench interval is narrowed. In addition, since the bottom of the trench is located on the drain side of the pn junction between the base region and the drift region, the electric field concentration at the bottom of the trench becomes strong when the MOSFET is turned off, and the breakdown voltage due to the dielectric breakdown of the gate insulating film at the bottom of the trench There is a risk of decline.

  The present invention eliminates the problems caused by the prior art described above, and can be easily manufactured and can be set to a predetermined gate threshold voltage while maintaining a withstand voltage, and a method of manufacturing the semiconductor device The purpose is to provide.

  In order to solve the above-described problems and achieve the object of the present invention, a semiconductor device according to the present invention has the following characteristics. A first semiconductor layer of the first conductivity type is provided on the front surface of a semiconductor substrate made of a semiconductor having a wider band gap than silicon. A second semiconductor layer of the second conductivity type is provided on the surface of the first semiconductor layer opposite to the semiconductor substrate side. A first conductivity type first semiconductor region is selectively provided in the second semiconductor layer. The trench penetrates the first semiconductor region and the second semiconductor layer in the depth direction and reaches the first semiconductor layer. A gate electrode is provided inside the trench via a gate insulating film. A second semiconductor region of a second conductivity type that penetrates the second semiconductor layer in the depth direction and reaches the first semiconductor layer is provided apart from the trench. The second semiconductor region has a higher impurity concentration than the second semiconductor layer. A third semiconductor region of a second conductivity type is provided inside the first semiconductor layer, separated from the second semiconductor layer and the second semiconductor region. The third semiconductor region covers the bottom of the trench. The third semiconductor region has an impurity concentration higher than that of the second semiconductor layer. The first electrode is electrically connected to the first semiconductor region and the second semiconductor layer. The second electrode is provided on the back surface of the semiconductor substrate.

  The semiconductor device according to the present invention is characterized in that, in the above-described invention, the width of the second semiconductor region is narrower than the width of the trench.

  In the semiconductor device according to the present invention, the end of the second semiconductor region on the second electrode side is located closer to the second electrode than the bottom of the trench in the above-described invention. .

  The semiconductor device according to the present invention further includes a second conductivity type fourth semiconductor region selectively provided inside the second semiconductor layer in the above-described invention. The fourth semiconductor region has a higher impurity concentration than the second semiconductor region. The first electrode is in contact with the first semiconductor region and the fourth semiconductor region. The second semiconductor region is provided on the second electrode side of the fourth semiconductor region and is in contact with the fourth semiconductor region.

  The semiconductor device according to the present invention may further include a second conductivity type fifth semiconductor region provided on the second electrode side of the second semiconductor region inside the first semiconductor layer. It is characterized by providing.

  In the semiconductor device according to the present invention as set forth in the invention described above, the width of the fifth semiconductor region is wider than the width of the second semiconductor region.

  In the semiconductor device according to the present invention as set forth in the invention described above, the fifth semiconductor region covers an end portion of the second semiconductor region on the second electrode side.

  In the semiconductor device according to the present invention, the trench is provided in a linear layout extending in parallel with the front surface of the semiconductor substrate. The second semiconductor region and the fifth semiconductor region are provided in a linear layout parallel to a direction in which the trench extends linearly.

  In the semiconductor device according to the present invention, the trench is provided in a linear layout extending in parallel with the front surface of the semiconductor substrate. The second semiconductor region is provided in a linear layout parallel to a direction in which the trench extends linearly. A plurality of the fifth semiconductor regions are arranged at a predetermined interval in a direction in which the second semiconductor regions extend linearly.

  In the semiconductor device according to the present invention as set forth in the invention described above, the impurity concentration of the fifth semiconductor region is higher than the impurity concentration of the second semiconductor region.

  In the semiconductor device according to the present invention as set forth in the invention described above, the second semiconductor region is an epitaxially grown layer.

  In the semiconductor device according to the present invention as set forth in the invention described above, the third semiconductor region is an epitaxial growth layer.

  In the semiconductor device according to the present invention, the semiconductor having a wider band gap than silicon is silicon carbide in the above-described invention.

  In the semiconductor device according to the present invention, in the above-described invention, a surface of the second semiconductor layer opposite to the first semiconductor layer side is a (0001) surface, and a side wall of the trench is {1 It is a -100} plane.

  In the semiconductor device according to the present invention, in the above-described invention, the second semiconductor layer has a Gaussian distribution type second conductivity type impurity concentration profile having a height difference in a depth direction from a position having the highest impurity concentration. It is characterized by that.

  In order to solve the above-described problems and achieve the object of the present invention, a semiconductor device manufacturing method according to the present invention has the following characteristics. First, a first step of epitaxially growing a first semiconductor layer of the first conductivity type on the front surface of a semiconductor substrate made of a semiconductor having a wider band gap than silicon is performed. Next, a second step of epitaxially growing a second conductivity type second semiconductor layer on the first semiconductor layer is performed. Next, a first trench that penetrates the second semiconductor layer in the depth direction and reaches the first semiconductor layer, and a depth that penetrates the second semiconductor layer and reaches the first semiconductor layer, A third step of forming a second trench having a width smaller than that of the first trench apart from each other is performed. Next, a second conductive type third semiconductor layer having an impurity concentration higher than that of the second semiconductor layer is epitaxially grown along the surface of the second semiconductor layer and the inner wall of the first trench, and the second trench is formed. A fourth step of completely filling the inside with the third semiconductor layer is performed. Next, a fifth step of removing the portion of the third semiconductor layer on the side wall of the first trench and exposing the first semiconductor layer and the second semiconductor layer on the side wall of the first trench is performed. Next, the first semiconductor region of the first conductivity type exposed to the side wall of the first trench and reaching the second semiconductor layer is selectively formed on the third semiconductor layer remaining between the adjacent first trenches. A sixth step of forming is performed. Next, a seventh step of forming a gate insulating film along the surface of the third semiconductor layer remaining at the bottom of the first trench and the side wall of the first trench is performed. Next, an eighth step of forming a gate electrode on the gate insulating film is performed inside the first trench. Next, a ninth step of forming a first electrode electrically connected to the first semiconductor region and the third semiconductor layer is performed. Next, a tenth step of forming a second electrode on the back surface of the semiconductor substrate is performed.

  In the method of manufacturing a semiconductor device according to the present invention, in the above-described invention, in the third step, the first trench having a crystal plane whose oxidation rate is faster than a front surface of the semiconductor substrate as a side wall is formed. To do. In the fifth step, an oxide film is formed by oxidizing a portion of the third semiconductor layer on the side wall of the first trench, and the oxide film is removed to remove the oxide film on the side wall of the first trench. The layer and the second semiconductor layer are exposed.

  The method for manufacturing a semiconductor device according to the present invention uses the semiconductor substrate having the (0001) plane as the front surface in the above-described invention. In the third step, the first trench having a {1-100} plane as a side wall is formed.

  In addition, in the above-described invention, the method for manufacturing a semiconductor device according to the present invention includes the third semiconductor layer remaining between the adjacent first trenches after the fifth step and before the seventh step. An eleventh step of selectively forming a second conductivity type fourth semiconductor region reaching the second semiconductor layer is performed. In the eleventh step, the fourth semiconductor region is formed in the third semiconductor layer at a position facing the second trench in the depth direction. In the ninth step, the first electrode in contact with the first semiconductor region and the fourth semiconductor region is formed.

  According to the semiconductor device manufacturing method of the present invention, in the above-described invention, the second conductivity type fifth layer is formed on the surface layer of the first semiconductor layer after the first step and before the second step. A twelfth step of selectively forming the semiconductor region is performed. In the third step, the second trench reaching the fifth semiconductor region through the second semiconductor layer in the depth direction is formed.

  In the semiconductor device manufacturing method according to the present invention as set forth in the invention described above, the width of the fifth semiconductor region is wider than the width of the second trench.

  In the semiconductor device manufacturing method according to the present invention, the semiconductor having a wider band gap than silicon is silicon carbide in the above-described invention.

  According to the above-described invention, since the extension of the channel is suppressed when the gate voltage is applied, a predetermined gate threshold voltage corresponding to the impurity concentration of the base region (second semiconductor layer) can be appropriately set. Further, the electric field at the bottom of the gate trench can be relaxed by the second semiconductor region between the gate trenches and the third semiconductor region at the bottom of the gate trench. Moreover, according to the above-described invention, the second and third semiconductor regions having high crystallinity can be easily formed without using ion implantation.

  According to the semiconductor device and the method for manufacturing the semiconductor device of the present invention, it is possible to easily manufacture the semiconductor device and to set the predetermined gate threshold voltage while maintaining the withstand voltage.

1 is a cross-sectional view showing a structure of a semiconductor device according to a first embodiment; FIG. 6 is a cross-sectional view showing a state in the middle of manufacturing the semiconductor device according to the first embodiment; FIG. 6 is a cross-sectional view showing a state in the middle of manufacturing the semiconductor device according to the first embodiment; FIG. 6 is a cross-sectional view showing a state in the middle of manufacturing the semiconductor device according to the first embodiment; FIG. 6 is a cross-sectional view showing a state in the middle of manufacturing the semiconductor device according to the first embodiment; FIG. 6 is a cross-sectional view showing a state in the middle of manufacturing the semiconductor device according to the first embodiment; 6 is a cross-sectional view showing a structure of a semiconductor device according to a second embodiment; FIG.

  Exemplary embodiments of a semiconductor device and a method for manufacturing the semiconductor device according to the present invention will be explained below in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, it means that electrons or holes are majority carriers in layers and regions with n or p, respectively. Further, + and − attached to n and p mean that the impurity concentration is higher and lower than that of the layer or region where it is not attached. Note that, in the following description of the embodiments and the accompanying drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted. In the present specification, in the Miller index notation, “−” means a bar attached to the index immediately after that, and “−” is added before the index to indicate a negative index.

(Embodiment 1)
The semiconductor device according to the present invention is configured using a semiconductor having a wider band gap than silicon (Si) (hereinafter referred to as a wide band gap semiconductor) as a semiconductor material. Here, an enhancement (normally-off) type vertical MOSFET (hereinafter referred to as SiC-vertical MOSFET) manufactured (manufactured) using silicon carbide (SiC) as a wide band gap semiconductor is shown in FIG. 1 as an example. The structure of the semiconductor device according to the first embodiment will be described. FIG. 1 is a cross-sectional view illustrating the structure of the semiconductor device according to the first embodiment.

The semiconductor device according to the first embodiment shown in FIG. 1 is a SiC-vertical MOSFET having a trench gate structure MOS gate on the front surface side of a silicon carbide substrate (semiconductor chip) 10. Silicon carbide substrate 10 epitaxially grows silicon carbide layers (first to third semiconductor layers) 21 to 23 having predetermined conductivity type and impurity concentration on the front surface of n ⁺ type starting substrate (semiconductor substrate) 1 in order. This is an epitaxial substrate. The n ⁺ type starting substrate 1 is an n ⁺ type drain region. N ⁻ type silicon carbide layer 21 is n ⁻ type drift region 2. The p-type silicon carbide layer 22 is the p-type base region 3.

  FIG. 1 shows two unit cells (functional unit of an element) 20 in the active region, and other unit cells adjacent to the unit cell and an edge termination region surrounding the active region are not shown. The active region is a region through which current flows in the on state. The edge termination region is a region between the active region and the end of the chip, and relaxes the electric field on the front surface of the silicon carbide substrate 10 (hereinafter referred to as the substrate front surface) to maintain a withstand voltage. . In the edge termination region, a guard ring, a junction termination (JTE) structure, a RESURF, and a field voltage structure such as a field plate are arranged.

In the active region, the MOS gate of the unit cell 20 is provided on the substrate front surface (surface on the silicon carbide layer 23 side) side. The MOS gate of the unit cell 20 includes a p-type base region 3, first and second p ⁺ -type regions (second and third semiconductor regions) 4 and 5, an n ⁺ -type source region (first semiconductor region) 6, and a p ⁺⁺ type. A contact region (fourth semiconductor region) 7, a trench (hereinafter referred to as a gate trench) 8, a gate insulating film 9 and a gate electrode 11 are formed. P type base region 3 is p type silicon carbide layer 22 epitaxially grown on n ⁻ type silicon carbide layer 21 as described above. The p-type base region 3 has a p-type Gaussian distribution in the depth direction formed by ion implantation of p-type impurities (having a height difference from the depth position where the p-type impurity concentration is maximum). It may have an impurity concentration profile.

A p ⁺ type silicon carbide layer 23 is epitaxially grown on p type silicon carbide layer 22 to form first and second p ⁺ type regions 4 and 5 as will be described later. Inside this p ⁺ type silicon carbide layer 23, an n ⁺ type source region 6 and a p ⁺⁺ type contact region 7 are selectively provided. The n ⁺ -type source region 6 and the p ⁺⁺ -type contact region 7 penetrate the p ⁺ -type silicon carbide layer 23 in the depth direction (direction from the substrate front surface to the substrate back surface: vertical direction) and p-type carbonization. The silicon layer 22 is reached. The n ⁺ type source region 6 and the p ⁺⁺ type contact region 7 are in contact with each other. The p ⁺⁺ type contact region 7 has a function of reducing contact resistance with the source electrode (first electrode) 13.

Gate trench 8 passes through n ⁺ type source region 6 and p type base region 3 and reaches n ⁻ type drift region 2. One unit cell 20 is located between the centers of the portions (mesa portions) between the gate trenches 8. The gate insulating film 9 is provided along the inner wall of the gate trench 8. The gate electrode 11 is provided on the gate insulating film 9 inside the gate trench 8. The gate electrode 11 faces the n ⁺ -type source region 6, the p-type base region 3 and the n ⁻ -type drift region 2 across the gate insulating film 9 on the side wall of the gate trench 8. Gate electrode 11 is electrically insulated from n ⁻ type drift region 2, p type base region 3, second p ⁺ type region 5 and n ⁺ type source region 6 by gate insulating film 9. An end of the gate electrode 11 on the substrate front surface side may protrude outside the gate trench 8.

The gate electrode 11 (that is, the gate trench 8) is arranged in a stripe (straight line) planar layout extending in parallel to the front surface of the substrate, for example. In this case, each region between the adjacent gate trenches 8 (p-type base region 3, first p ⁺ -type region 4, n ⁺ -type source region 6 and p ⁺⁺ -type contact region 7) or directly under the gate trench 8 (drain) The second p ⁺ -type region 5 on the side) is also arranged in a linear planar layout parallel to the direction in which the gate electrodes 11 extend in a stripe shape (the depth direction in FIG. 1). The planar layout is a planar shape and arrangement configuration of each part viewed from the front surface side of the silicon carbide substrate 10.

First p ⁺ -type region 4 penetrates p-type silicon carbide layer 22 in the depth direction from the substrate front surface side and reaches n ⁻ -type drift region 2. The first p ⁺ type region 4 is provided immediately below the p ⁺⁺ type contact region 7. The first p ⁺ type region 4 is preferably in contact with the p ⁺⁺ type contact region 7. The first p ⁺ type region 4 may be in contact with the n ⁺ type source region 6. Further, the first p ⁺ -type region 4 is arranged away from the gate trench 8. The first p ⁺ -type region 4 may be disposed, for example, near the center between adjacent gate trenches 8. The width w2 of the first p ⁺ -type region 4 is narrower than the width w1 of the gate trench 8 (w2 <w1). The widths w1 and w2 are the widths in the direction (short direction) perpendicular to the direction in which the gate trenches 8 extend in a stripe shape (the same applies to the cell width and widths w3 and w4 described later).

The end on the drain side of the first p ⁺ -type region 4 only needs to be located on the drain side with respect to the bottom of the gate trench 8. For example, the end on the drain side of the second p ⁺ -type region 5 is located on the drain side. You may do it. FIG. 1 shows a case where the depth positions of the end portions on the drain side of the first and second p ⁺ type regions 4 and 5 are the same. Since the end of the first p ⁺ type region 4 on the drain side is located on the drain side of the bottom of the gate trench 8, the drain of the first p ⁺ type region 4 is more than the bottom of the gate trench 8 when the MOSFET is off. The electric field tends to concentrate on the end portion on the side, and the withstand voltage (withstand voltage) is maintained.

The first p ⁺ type region 4 is constituted by, for example, an epitaxial growth layer (p ⁺ type silicon carbide layer 23). The impurity concentration of the first p ⁺ -type region 4 is higher than the impurity concentration of the p-type base region 3. The impurity concentration of the first p ⁺ -type region 4 is set to an impurity concentration that is, for example, about an order of magnitude higher than the impurity concentration of the p-type base region 3, and is within the impurity concentration range that can be realized in the epitaxial growth layer (for example, 1 × 10 ¹⁸ or less). Degree). By making the impurity concentration of the first p ⁺ -type region 4 higher than the impurity concentration of the p-type base region 3, the gate threshold voltage can be adjusted by the impurity concentration of the p-type base region 3.

Specifically, in the first p ⁺ -type region 4, a voltage higher than the gate threshold voltage is applied to the gate electrode 11 with a positive voltage applied to the drain electrode (second electrode) 15 with respect to the source electrode 13. When this occurs, it has a function of suppressing the growth of a depletion layer of majority carriers (holes) spreading from the boundary between the gate insulating film 9 and the p-type base region 3 into the p-type base region 3. This hole depletion layer (region in which holes are depleted) is a channel formed in a portion of the p-type base region 3 along the side wall of the gate trench 8. In a thermal equilibrium state where no gate voltage is applied, the channel contains only a few minority carriers (electrons) and is in a very low conductivity state.

This channel spreads in the p-type base region 3 when a positive gate voltage is applied, but its elongation is suppressed by the first p ⁺ -type region 4. As a result, the electric field strength applied to the channel is stronger than in the conventional structure in which the first p ⁺ -type region 4 is not provided, and the lower end of the conduction band on the semiconductor surface of the MOS gate (channel portion of the p-type base region 3) is at the Fermi level. Since it tends to approach, the electron density in the channel is likely to increase, and the conductivity of the channel is likely to increase (the polarity of the channel is easily reversed to n-type). Therefore, even if the impurity concentration of the p-type base region 3 is lowered, the polarity of the channel can be inverted to the n-type with the gate threshold voltage theoretically obtained with the impurity concentration of the p-type base region 3.

Thus, the gate threshold voltage can be set as appropriate depending on the impurity concentration of the p-type base region 3. For example, even if the impurity concentration of the p-type base region 3 is lowered, the breakdown voltage can be prevented from being lowered by the first p ⁺ -type region 4 as described above and by the second p ⁺ -type region 5 as described later. For this reason, it is possible to set the impurity concentration of the p-type base region 3 appropriately as described above and to a predetermined gate threshold voltage while maintaining the breakdown voltage. Specifically, the gate threshold voltage includes, for example, the impurity concentration of the p-type base region 3, the impurity concentration of the first p ⁺ -type region 4, and the width w 3 from the sidewall of the gate trench 8 to the first p ⁺ -type region 4. And the thickness of the gate insulating film.

The second p ⁺ type region 5 is provided inside the n ⁻ type drift region 2 and covers the entire bottom surface of the gate trench 8. The second p ⁺ type region 5 is arranged apart from the p type base region 3 and the first p ⁺ type region 4. Second p ⁺ -type region 5 may partially contact p-type base region 3. The second p ⁺ type region 5 is formed of, for example, an epitaxial growth layer (p ⁺ type silicon carbide layer 23). The impurity concentration of the second p ⁺ -type region 5 is higher than the impurity concentration of the p-type base region 3. Impurity concentration of the 2p ⁺ -type region 5 is set, for example, to the same extent as the impurity concentration of the 1p ⁺ -type region 4. The second p ⁺ -type region 5 has a function of relaxing the electric field applied to the bottom of the gate trench 8 and maintaining the breakdown voltage when the MOSFET is turned off.

The interlayer insulating film 12 is provided on the entire surface of the substrate from the active region to the edge termination region, and covers the gate electrode 11. The source electrode 13 is in contact with the n ⁺ type source region 6 and the p ⁺⁺ type contact region 7 through a contact hole opened in the interlayer insulating film 12, and is connected to the p type base region 3, the first p ⁺ type region 4, and the n ⁺ type. It is electrically connected to type source region 6 and p ⁺⁺ type contact region 7. The source electrode 13 is electrically insulated from the gate electrode 11 by the interlayer insulating film 12. The source electrode 13 may be provided only inside the contact hole.

The source pad (electrode pad) 14 is provided on the interlayer insulating film 12 and the source electrode 13 so as to fill the inside of the contact hole. The source pad 14 electrically connects the source electrodes 13 of all the unit cells 20. A drain electrode 15 is provided over the entire back surface of silicon carbide substrate 10 (the back surface of n ⁺ -type starting substrate 1). A drain pad (electrode pad) 16 is provided on the surface of the drain electrode 15.

Next, a method for manufacturing the semiconductor device according to the first embodiment will be described. 2-6 is sectional drawing which shows the state in the middle of manufacture of the semiconductor device concerning Embodiment 1. FIGS. First, an n ⁺ type single crystal substrate doped with an n type impurity such as nitrogen (N) is prepared as an n ⁺ type starting substrate (starting wafer) 1. The front surface of the n ⁺ -type starting substrate 1 may be, for example, a (0001) plane, a so-called Si plane. Next, an n ⁻ type silicon carbide layer 21 doped with an n type impurity such as nitrogen is epitaxially grown on the front surface of the n ⁺ type starting substrate 1. The thickness of n ⁻ type silicon carbide layer 21 may be, for example, 10 μm.

Next, a p-type silicon carbide layer 22 doped with a p-type impurity such as aluminum (Al) is epitaxially grown on the surface of the n ⁻ -type silicon carbide layer 21. The thickness and impurity concentration of p-type silicon carbide layer 22 may be, for example, about 1.5 μm and about 5 × 10 ¹⁵ / cm ³ , respectively. The state up to this point is shown in FIG.

Next, an etching mask (not shown) having openings corresponding to the formation regions of the gate trench 8 and the first p ⁺ -type region 4 is formed on the surface of the p-type silicon carbide layer 22 by photolithography. As this etching mask, for example, an oxide film (SiO ₂ ) mask may be used. Next, etching is performed using this etching mask as a mask to form first and second trenches 31 and 32 that penetrate p-type silicon carbide layer 22 in the depth direction and reach n ⁻ -type silicon carbide layer 21. This etching may be, for example, dry etching. A portion of n ⁻ type silicon carbide layer 21 other than first and second trenches 31 and 32 becomes n ⁻ type drift region 2. A portion of the p-type silicon carbide layer 22 other than the first and second trenches 31 and 32 becomes the p-type base region 3.

These first and second trenches 31 and 32 are alternately repeated in a direction (lateral direction) parallel to the front surface of the substrate, and are arranged apart from each other. The width w11 of the first trench 31 is the same as the width w1 of the gate trench 8, and may be about 1.5 μm, for example. The width w12 of the second trench 32 is the same as the width w2 of the first p ⁺ -type region 4, and may be, for example, about 0.5 μm. The first and second trenches 31 and 32 are formed, for example, such that the m-plane is exposed on the side wall. The m-plane is a general term for the (1-100) plane perpendicular to the (000-1) plane, the so-called C-plane. Specifically, the m-plane is a (10-10) plane, a (-1010) plane, a (1-100) plane, a (-1100) plane, a (01-10) plane, and a (0-110) plane. is there. Then, the etching mask used to form the first and second trenches 31 and 32 is removed. The state up to here is shown in FIG.

Next, along the surface of the p-type silicon carbide layer 22 and the inner wall of the first trench 31, a p ⁺ -type silicon carbide layer 23 doped with a p-type impurity such as aluminum is epitaxially grown. At this time, the thickness t1 of the p ⁺ -type silicon carbide layer 23 is set to be not less than half the width w12 of the second trench 32 (w12 / 2 ≦ t1), so that the inside of the second trench 32 is a p ⁺ -type silicon carbide layer. 23 completely embed. The thickness t1 and the impurity concentration of the p ⁺ type silicon carbide layer 23 may be about 0.3 μm and about 5 × 10 ¹⁷ / cm ³ , respectively. The silicon carbide substrate (semiconductor) in which the n ⁻ type silicon carbide layer 21, the p type silicon carbide layer 22, and the p ⁺ type silicon carbide layer 23 are sequentially laminated on the front surface of the n ⁺ type starting substrate 1 through the steps so far. Wafer) 10 is manufactured. The state up to this point is shown in FIG.

Next, the p ⁺ -type silicon carbide layer 23 is selectively oxidized using the feature that the oxidation rate varies depending on the crystal plane of silicon carbide. Specifically, the side wall (m-plane) portion of the first trench 31 of the p ⁺ -type silicon carbide layer 23 is completely oxidized by wet oxidation, for example. The portion embedded in the second trench 32 of the p ⁺ -type silicon carbide layer 23 is not oxidized because it is not exposed to an atmosphere (water vapor) containing, for example, water (H ₂ O) used in wet oxidation. The portion of the p ⁺ -type silicon carbide layer 23 on the surface of the p-type silicon carbide layer 22 and the portion on the bottom surface of the first trench 31 are oxidized according to the oxidation rate of the crystal plane (Si surface). In silicon, the m-plane oxidation proceeds faster than the Si-plane oxidation, so that an unoxidized p ⁺ -type silicon carbide layer 23 remains on the Si surface.

Next, the oxidized portion (namely, oxide film) of p ⁺ type silicon carbide layer 23 is removed by, for example, etching. Thereby, p ⁺ -type silicon carbide layer 23 remains only on the surface of p-type silicon carbide layer 22, on the bottom surface of first trench 31, and inside second trench 32. A portion of p ⁺ type silicon carbide layer 23 remaining on the bottom surface of first trench 31 is first p ⁺ type region 4. A portion of p ⁺ type silicon carbide layer 23 remaining on the bottom surface of first trench 31 is second p ⁺ type region 5. In addition, the n ⁻ -type drift region 2 and the p-type base region 3 are exposed on the side wall of the first trench 31. The surface of the second p ⁺ -type region 5 becomes the bottom surface of the gate trench 8, and the exposed side wall of the first trench 31 becomes the side wall of the gate trench 8.

Next, a portion corresponding to the formation region of the n ⁺ type source region 6 is opened on the front surface of the silicon carbide substrate 10 (the surface of the p ⁺ type silicon carbide layer 23) by a photolithography technique. An ion implantation mask is formed. An ion implantation mask is embedded in the first trench 31. For example, an oxide film mask may be used as the ion implantation mask. Next, n-type impurities such as phosphorus (P) are ion-implanted using this ion implantation mask as a mask. At this time, countering dose of the n-type impurity in this ion implantation was set higher than the p-type impurity concentration of the p ⁺ -type silicon carbide layer 23, a portion of the conductivity type of the p ⁺ -type silicon carbide layer 23 to n-type . The n-type impurity implantation depth for ion implantation is set to a depth equal to or greater than the thickness t1 of the portion of the p ⁺ -type silicon carbide layer 23 remaining on the surface of the p-type silicon carbide layer 22. Thereby, n ⁺ type source region 6 is selectively formed in the portion of p ⁺ type silicon carbide layer 23 remaining on the surface of p type silicon carbide layer 22. Then, the ion implantation mask used to form the n ⁺ -type source region 6 is removed.

Next, a portion corresponding to the region where the p ⁺⁺ type contact region 7 is formed is opened on the front surface of the silicon carbide substrate 10 (the surface of the p ⁺ type silicon carbide layer 23) by photolithography. An ion implantation mask is formed. An ion implantation mask is embedded in the first trench 31. For example, an oxide film mask may be used as the ion implantation mask. Next, a p-type impurity such as aluminum is ion-implanted using the ion implantation mask as a mask. At this time, the implantation depth of the p-type impurity for ion implantation is set to a depth equal to or greater than the thickness t1 of the portion of the p ⁺ -type silicon carbide layer 23 remaining on the surface of the p-type silicon carbide layer 22. To further p-type impurity to the p ⁺ -type silicon carbide layer 23 is ion-implanted, part of the p-type impurity concentration of the p ⁺ -type silicon carbide layer 23 is increased. Thereby, p ⁺⁺ type contact region 7 is selectively formed in a portion of p ⁺ type silicon carbide layer 23 remaining on the surface of p type silicon carbide layer 22. Then, the ion implantation mask used to form the p ⁺⁺ type contact region 7 is removed. The order of forming the n ⁺ type source region 6 and the p ⁺⁺ type contact region 7 can be interchanged.

Next, the n ⁺ type source region 6 and the p ⁺⁺ type contact region 7 are activated by heat treatment (activation annealing). In this heat treatment, for example, the temperature may be about 1700 ° C. and the heat treatment time may be about 2 minutes. Activation annealing may be performed every time ion implantation is performed. The state up to here is shown in FIG.

Next, the front surface of silicon carbide substrate 10 (the surfaces of n ⁺ type source region 6 and p ⁺⁺ type contact region 7) and the inner wall of gate trench 8 (the surface of second p ⁺ type region 5 and the first surface A gate insulating film 9 is formed along the side wall of the trench 31. For example, the gate insulating film 9 may be formed by thermal oxidation by heat treatment at a temperature of about 1000 ° C. in an oxygen (O ₂ ) atmosphere. The gate insulating film 9 may be a deposited oxide film deposited by a chemical reaction such as high temperature oxidation (HTO).

  Next, a polycrystalline silicon (poly-Si) layer doped with an n-type impurity such as phosphorus is deposited on the gate insulating film 9 so as to be embedded in the gate trench 8. Next, the polycrystalline silicon layer is patterned by a photolithography technique, and a portion to be the gate electrode 11 of the polycrystalline silicon layer is left inside the gate trench 8. A part of the gate electrode 11 may protrude outward (upward) from the gate trench 8.

  Next, an interlayer insulating film 12 is formed so as to cover the gate insulating film 9 and the gate electrode 11. The interlayer insulating film 12 is formed of, for example, PSG (Phospho Silicate Glass), BPSG (Boro Phospho Silicate Glass), or a combination thereof. The thickness t2 of the portion of the interlayer insulating film 12 on the gate electrode 11 may be 1 μm, for example.

Next, the interlayer insulating film 12 and the gate insulating film 9 are patterned by photolithography to form contact holes, and the n ⁺ -type source region 6 and the p ⁺⁺ -type contact region 7 are exposed in the contact holes. Next, the interlayer insulating film 12 is planarized by heat treatment (reflow).

  Next, a metal film to be the source electrode 13 is formed along the surface of the interlayer insulating film 12 and the contact hole by sputtering, for example. The metal film that becomes the source electrode 13 may be a nickel (Ni) film, for example. Next, the metal film is selectively removed by photolithography and etching to leave the source electrode 13 only in the contact hole, for example.

Next, for example, a nickel (Ni) film to be the drain electrode 15 is formed on the back surface of the silicon carbide substrate 10 (the back surface of the n ⁺ -type starting substrate 1). Next, the silicon carbide substrate 10 and the metal films on both sides thereof are reacted by heat treatment to form the source electrode 13 and the drain electrode 15 that are in ohmic contact with the silicon carbide substrate 10. The state up to this point is shown in FIG.

  Next, an aluminum film, for example, serving as the source pad 14 is deposited to a thickness of about 5 μm so as to cover the source electrode 13 and the interlayer insulating film 12 by, for example, sputtering. Next, the aluminum film is selectively removed to leave a portion that becomes the source pad 14.

  The source pad 14 may be formed and a part of the aluminum film may be left as a gate pad (electrode pad) (not shown). Each gate electrode 11 of the unit cell 20 is electrically connected to the gate pad.

  Next, a drain pad 16 is formed by sequentially laminating, for example, a titanium (Ti) film, a nickel film, and a gold (Au) film on the surface of the drain electrode 15 by sputtering, for example. Thereafter, the semiconductor wafer is diced (cut) into chips, thereby completing the SiC-vertical MOSFET shown in FIG.

As described above, according to the semiconductor device according to the first embodiment, by providing the first p ⁺ -type region penetrating the p-type base region in the depth direction apart from the gate trench, the positive gate voltage At the time of application, the extension of the hole depletion layer (channel) extending from the boundary between the gate insulating film and the p-type base region into the p-type base region is suppressed. Therefore, for example, even if the impurity concentration of the p-type base region is lowered in order to reduce the channel resistance, the channel polarity is more easily reversed than in the conventional structure in which the first p ⁺ -type region is not provided, and the impurity in the p-type base region The MOSFET can be turned on with a gate threshold voltage that is theoretically obtained from the concentration. Therefore, a predetermined gate threshold voltage depending on the impurity concentration of the p-type base region can be set as appropriate, and the on-resistance can be reduced.

In addition, according to the semiconductor device according to the first embodiment, even if the impurity concentration of the p-type base region is lowered in order to set the gate threshold voltage to a predetermined value (for example, about 5 V), the first p ⁺ -type region As a result, the effective impurity concentration of the base region is increased. For this reason, punch-through and leakage current due to the short channel effect (deterioration phenomenon) can be prevented, and a decrease in breakdown voltage can be suppressed. Further, according to the semiconductor device of the first embodiment, the end of the first p ⁺ -type region on the drain side is located closer to the drain side than the bottom of the gate trench, or the second p ⁺ -type region is located at the bottom of the gate trench. Thus, it is possible to suppress electric field concentration at the bottom of the gate trench when the MOSFET is turned off. Thereby, a pressure | voltage resistant fall can be prevented.

According to the manufacturing method of the semiconductor device according to the first embodiment, and the 1p ⁺ -type region between the gate trenches, and the 2p ⁺ -type region of the gate trench bottom, it can be formed by epitaxial growth layer. For this reason, the impurity concentration distribution of these first and second p ⁺ -type regions can be made uniform as compared with the case of forming by ion implantation. Further, according to the method of manufacturing the semiconductor device according to the first embodiment, the first p ⁺ type region is formed by embedding the p ⁺ type epitaxial growth layer in the second trench, so that it is more than the case of forming by ion implantation. The width of the first p ⁺ type region can be reduced. For example, the width of the first p ⁺ -type region can be 1 μm or less. Thereby, each cell width can be narrowed, so that the current capability can be improved or the semiconductor chip can be downsized.

Further, if the case where the first 1,2P ⁺ -type region is formed by ion implantation, n ^- -type a drift region n ^- part and the 2p ⁺ -type region of the 1p ⁺ -type region by ion implantation into type silicon carbide layer Form. Next, a p-type silicon carbide layer serving as a p-type base region is epitaxially grown on the n ⁻ -type silicon carbide layer, and the remaining portion of the first p ⁺ -type region is formed by ion implantation into the p-type silicon carbide layer. . In the formation of the remaining portion of the first p ⁺ -type region, the p-type base region is thick with respect to the ion implantation depth into the silicon carbide, so that the epitaxial growth of the p-type silicon carbide layer and the ion implantation are combined. Repeat the process at least twice. Thereafter, etching for forming a gate trench is performed. For this reason, in order to form the first and second p ⁺ -type regions and the gate trench, a total of six steps of epitaxial growth of the p-type silicon carbide layer twice, ion implantation three times, and formation of the gate trench are required.

On the other hand, according to the manufacturing method of the semiconductor device according to the first embodiment, the first and second p ⁺ type regions having high crystallinity can be easily formed without using ion implantation. Specifically, epitaxial growth of p-type silicon carbide layer serving as the p-type base region, formed of the first and second trenches, the epitaxial growth of the p ⁺ -type silicon carbide layer serving as the first 1,2P ⁺ -type region, and, p ⁺ -type A step of removing a part of the silicon carbide layer is performed. For this reason, the number of steps can be reduced as compared with the case where the first and second p ⁺ -type regions are formed by ion implantation. Further, the width of the second trench is made narrower than the width of the first trench, and a crystal plane having a higher oxidation rate than the front surface of the substrate is exposed on the side wall of the first trench, whereby high-speed oxidation and oxide film removal are performed. only it can remove a portion of the p ⁺ -type silicon carbide layer, leaving the p ⁺ -type silicon carbide layer serving as the respective first 2,1P ⁺ -type region at a predetermined position of the first and second trench easily it can.

(Embodiment 2)
Next, the structure of the semiconductor device according to the second embodiment will be described. FIG. 7 is a cross-sectional view illustrating the structure of the semiconductor device according to the second embodiment. The semiconductor device according to the second embodiment is different from the semiconductor device according to the first embodiment in that it is separated from the second p ⁺ type region 5 immediately below the first p ⁺ type region 4 inside the n ⁻ type drift region 2. The third p ⁺ -type region (fifth semiconductor region) 41 is provided.

Specifically, the third p ⁺ type region 41 is provided immediately below the first p ⁺ type region 4. The 3p ⁺ -type region 41 is preferably in contact with the first 1p ⁺ -type region 4, the better many parts in contact with the first 1p ⁺ -type region 4. More preferably, the p ⁺ type region 41 may cover the end of the first p ⁺ type region 4 on the drain side. The third p ⁺ type region 41 may be in contact with the p type base region 3. The thickness t3 of the portion immediately below the first p ⁺ type region 4 of the third p ⁺ type region 41 may be, for example, about 0.1 μm or more and 1.0 μm or less.

By providing the third p ⁺ -type region 41 immediately below the first p ⁺ -type region 4, the breakdown voltage in the second p ⁺ -type region 5 is higher than the breakdown voltage at the end of the first p ⁺ -type region 4 on the drain side. For this reason, an avalanche breakdown is likely to occur at the end of the first p ⁺ -type region 4 on the drain side, and an avalanche breakdown at the bottom of the gate trench 8 can be suppressed.

Further, it is preferable that the drain-side end portion of the third p ⁺ -type region 41 is located closer to the drain side than the drain-side end portion of the second p ⁺ -type region 5. Thereby, when the MOSFET is turned off, the electric field concentration on the third p ⁺ -type region 41 becomes stronger than the electric field concentration on the second p ⁺ -type region 5, thereby further suppressing the occurrence of avalanche breakdown at the bottom of the gate trench 8. Can do.

The impurity concentration of the third p ⁺ type region 41 is preferably higher than the impurity concentration of the first p ⁺ type region 4. This suppresses the extension of the depletion layer extending from the pn junction between the third p ⁺ type region 41 and the n ⁻ type drift region 2 into the third p ⁺ type region 41, so that the drain of the first p ⁺ type region 4 The withstand pressure at the side end is further reduced. For this reason, generation | occurrence | production of the avalanche breakdown in the bottom part of the gate trench 8 can further be suppressed.

The width w4 of the third p ⁺ -type region 41 is preferably wider than the width w2 of the first p ⁺ -type region 4 (w4> w2). This is because, even if the positional deviation of the mask pattern during the formation of the 1,3P ⁺ -type region 4, 41 occurs, the first 1p ⁺ -type region end of the drain side of the 4 reliably by the 3p ⁺ -type region 41 This is because it can be covered.

The third p ⁺ -type region 41 is arranged, for example, with a uniform thickness t3 in a linear planar layout parallel to the direction in which the first p ⁺ -type region 4 extends linearly (the depth direction in FIG. 7). That is, the third p ⁺ type region 41 covers the entire end portion on the drain side of the first p ⁺ type region 4.

Further, the third p ⁺ type regions 41 may be arranged in a plurality of points at predetermined intervals in the direction in which the first p ⁺ type regions 4 extend linearly. That is, the end of the first p ⁺ type region 4 on the drain side may be partially covered with the third p ⁺ type region 41.

Next, a method for manufacturing the semiconductor device according to the second embodiment will be described. First, similarly to the first embodiment, an n ⁺ type starting substrate (starting wafer) 1 is prepared, and an n ⁻ type silicon carbide layer 21 is epitaxially grown on the front surface of the n ⁺ type starting substrate 1. Next, an ion implantation mask (not shown) having an opening corresponding to the formation region of the third p ⁺ type region 41 is formed on the surface of the n ⁻ type silicon carbide layer 21 by photolithography. For example, an oxide film mask may be used as the ion implantation mask.

Next, a p-type impurity such as aluminum is ion-implanted using the ion implantation mask as a mask. At this time, the implantation depth of the p-type impurity for ion implantation is made deeper than the position of the bottom of the first trench 31 formed in a later step. Thereby, third p ⁺ -type region 41 is selectively formed in the surface layer of n ⁻ -type silicon carbide layer 21. At this time, the depth of the third p ⁺ -type region 41 may be about 0.5 μm from the surface of the n ⁻ -type silicon carbide layer 21, for example. Then, the ion implantation mask used to form the third p ⁺ -type region 41 is removed.

Thereafter, similarly to the first embodiment, the steps after epitaxial growth of p-type silicon carbide layer 22 are sequentially performed. At this time, when forming the first and second trenches 31 and 32 (see FIG. 3), the first and second trenches 31 and 32 are arranged so that the bottom of the second trench 32 is located inside the third p ⁺ -type region 41. 32 may be formed. The second trench 32 may be formed so as to penetrate the p-type silicon carbide layer 22 in the depth direction and reach the third p ⁺ -type region 41. Thereby, the SiC-vertical MOSFET shown in FIG. 7 is completed.

As described above, according to the second embodiment, the same effect as in the first embodiment can be obtained. Further, according to the second embodiment, by providing the third p ⁺ -type region apart from the end of the first p ⁺ -type region on the drain side, it is possible to further reduce the electric field concentration at the bottom of the gate trench.

The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. For example, in the manufacturing method according to each of the above-described embodiments, the case where the front surface of the silicon carbide substrate is the Si surface has been described as an example, but the first trench in which the second p ⁺ type region is formed is described. It suffices if a crystal plane having a higher oxidation rate than the front surface of the silicon carbide substrate is exposed on the side wall. For this reason, for example, the front surface of the silicon carbide substrate may be the m-plane, and the sidewalls of the second and first trenches in which the first and second p ⁺ -type regions are formed may be the C-plane. Further, the side walls of the first and second trenches may have an inclination with respect to the front surface of the substrate so that the width of the first and second trenches becomes wider from the bottom toward the opening side.

In the manufacturing method according to each embodiment described above, of the 2p ⁺ -type region become p ⁺ -type silicon carbide layer, the case of removing by oxidizing the portion of the side wall of the first trench faster than other portions As described in the example, the p ⁺ type silicon carbide layer to be the second p ⁺ type region may be removed by selectively etching the side wall portion of the first trench. In this case, the front surface of the silicon carbide substrate may be a C surface. In each of the above-described embodiments, the MOSFET has been described as an example. However, the present invention is not limited to this, and the present invention is also applicable to a MOS semiconductor device such as an IGBT (Insulated Gate Bipolar Transistor). It is.

  In each of the above-described embodiments, the case where silicon carbide is used as the wide band gap semiconductor has been described as an example. However, it can be applied to a wide band gap semiconductor such as gallium nitride (GaN) other than silicon carbide. It is. Further, the present invention can be similarly realized even when the conductivity type (n-type, p-type) is inverted.

  As described above, the semiconductor device and the method for manufacturing the semiconductor device according to the present invention are useful for a vertical MOS semiconductor device having a trench gate structure using a wide band gap semiconductor, and in particular, a vertical MOS semiconductor device using a silicon carbide layer. Suitable for type MOSFET.

1 n ⁺ type starting substrate 2 n ⁻ type drift region 3 p type base region 4 1st p ⁺ type region (p ⁺ type region between gate trenches)
5 Second p ⁺ type region (p ⁺ type region at the bottom of the gate trench)
41 3rd p ⁺ type region (p ⁺ type region covering the drain side end of the first p ⁺ type region)
6 n ⁺ type source region 7 p ⁺⁺ type contact region 8 gate trench 9 gate insulating film 10 silicon carbide substrate 11 gate electrode 12 interlayer insulating film 13 source electrode 14 source pad 15 drain electrode 16 drain pad 20 unit cell 21 to 23 carbonization Silicon layer (epitaxial growth layer)
31, 32 Trench w1 Width of gate trench w2 Width of first p ⁺ type region w3 Width from sidewall of gate trench to first p ⁺ type region w4 Width of third p ⁺ type region w11, 12 Width of trench

Claims (22)

A semiconductor substrate made of a semiconductor having a wider band gap than silicon;
A first semiconductor layer of a first conductivity type provided on the front surface of the semiconductor substrate;
A second semiconductor layer of a second conductivity type provided on the surface of the first semiconductor layer opposite to the semiconductor substrate side;
A first semiconductor region of a first conductivity type selectively provided in the second semiconductor layer;
A trench that penetrates through the first semiconductor region and the second semiconductor layer in a depth direction and reaches the first semiconductor layer;
A gate electrode provided inside the trench via a gate insulating film;
A second conductivity type second semiconductor region which is provided apart from the trench and penetrates the second semiconductor layer in the depth direction to reach the first semiconductor layer and has a higher impurity concentration than the second semiconductor layer; ,
A second conductivity type second impurity layer having a higher impurity concentration than the second semiconductor layer, which is provided inside the first semiconductor layer and is separated from the second semiconductor layer and the second semiconductor region and covers the bottom of the trench. 3 semiconductor regions;
A first electrode electrically connected to the first semiconductor region and the second semiconductor layer;
A second electrode provided on the back surface of the semiconductor substrate;
A semiconductor device comprising:   The semiconductor device according to claim 1, wherein a width of the second semiconductor region is narrower than a width of the trench.   3. The semiconductor device according to claim 1, wherein an end of the second semiconductor region on the second electrode side is located closer to the second electrode than a bottom of the trench. A fourth semiconductor region of a second conductivity type selectively provided inside the second semiconductor layer and having a higher impurity concentration than the second semiconductor region;
The first electrode is in contact with the first semiconductor region and the fourth semiconductor region,
The semiconductor device according to claim 1, wherein the second semiconductor region is provided on the second electrode side of the fourth semiconductor region and is in contact with the fourth semiconductor region.   5. The semiconductor device according to claim 1, further comprising a fifth semiconductor region of a second conductivity type provided on the second electrode side of the second semiconductor region inside the first semiconductor layer. The semiconductor device described in one.   6. The semiconductor device according to claim 5, wherein the width of the fifth semiconductor region is wider than the width of the second semiconductor region.   The semiconductor device according to claim 5, wherein the fifth semiconductor region covers an end portion of the second semiconductor region on the second electrode side. The trench is provided in a linear layout extending parallel to the front surface of the semiconductor substrate,
The said 2nd semiconductor region and the said 5th semiconductor region are provided in the linear layout parallel to the direction where the said trench extends linearly, The Claim 5 characterized by the above-mentioned. Semiconductor device. The trench is provided in a linear layout extending parallel to the front surface of the semiconductor substrate,
The second semiconductor region is provided in a linear layout parallel to a direction in which the trench extends linearly,
The semiconductor device according to claim 5, wherein a plurality of the fifth semiconductor regions are arranged at a predetermined interval in a direction in which the second semiconductor regions extend linearly.   The semiconductor device according to claim 5, wherein an impurity concentration of the fifth semiconductor region is higher than an impurity concentration of the second semiconductor region.   The semiconductor device according to claim 1, wherein the second semiconductor region is an epitaxial growth layer.   The semiconductor device according to claim 1, wherein the third semiconductor region is an epitaxial growth layer.   The semiconductor device according to claim 1, wherein the semiconductor having a wider band gap than silicon is silicon carbide. The surface of the second semiconductor layer opposite to the first semiconductor layer side is a (0001) plane,
The semiconductor device according to claim 1, wherein a side wall of the trench is a {1-100} plane.   15. The second semiconductor layer according to claim 1, wherein the second semiconductor layer has a second conductivity type impurity concentration profile having a Gaussian distribution having a height difference in a depth direction from a position having the highest impurity concentration. A semiconductor device according to 1. A first step of epitaxially growing a first semiconductor layer of a first conductivity type on a front surface of a semiconductor substrate made of a semiconductor having a wider band gap than silicon;
A second step of epitaxially growing a second semiconductor layer of a second conductivity type on the first semiconductor layer;
A first trench penetrating the second semiconductor layer in the depth direction and reaching the first semiconductor layer; and a first trench penetrating the second semiconductor layer in the depth direction and reaching the first semiconductor layer. A third step of forming the second trench having a narrower width apart from each other;
A second conductivity type third semiconductor layer having an impurity concentration higher than that of the second semiconductor layer is epitaxially grown along the surface of the second semiconductor layer and the inner wall of the first trench, and the inside of the second trench is formed. A fourth step of completely filling with the third semiconductor layer;
A fifth step of removing a portion of the sidewall of the first trench of the third semiconductor layer to expose the first semiconductor layer and the second semiconductor layer on the sidewall of the first trench;
A first semiconductor region of a first conductivity type that is exposed on a sidewall of the first trench and reaches the second semiconductor layer is selectively formed in the third semiconductor layer remaining between the adjacent first trenches. 6 steps,
A seventh step of forming a gate insulating film along the surface of the third semiconductor layer remaining at the bottom of the first trench and the side wall of the first trench;
An eighth step of forming a gate electrode on the gate insulating film inside the first trench;
A ninth step of forming a first electrode electrically connected to the first semiconductor region and the third semiconductor layer;
A tenth step of forming a second electrode on the back surface of the semiconductor substrate;
A method for manufacturing a semiconductor device, comprising: In the third step, the first trench having a crystal plane whose oxidation rate is faster than a front surface of the semiconductor substrate as a side wall is formed,
In the fifth step, an oxide film is formed by oxidizing a portion of the third semiconductor layer on the side wall of the first trench, and the oxide film is removed to remove the oxide film on the side wall of the first trench. 17. The method of manufacturing a semiconductor device according to claim 16, wherein the layer and the second semiconductor layer are exposed. Using the semiconductor substrate having a (0001) plane as a front surface,
The method of manufacturing a semiconductor device according to claim 17, wherein in the third step, the first trench having a {1-100} plane as a side wall is formed. After the fifth step, before the seventh step, a fourth semiconductor region of the second conductivity type that reaches the second semiconductor layer is selected as the third semiconductor layer remaining between the adjacent first trenches An eleventh step of automatically forming,
In the eleventh step, the fourth semiconductor region is formed in the third semiconductor layer at a position facing the second trench in the depth direction,
The method of manufacturing a semiconductor device according to claim 16, wherein in the ninth step, the first electrode in contact with the first semiconductor region and the fourth semiconductor region is formed. After the first step, before the second step, further includes a twelfth step of selectively forming a second conductive type fifth semiconductor region on the surface layer of the first semiconductor layer,
20. The second trench according to claim 16, wherein, in the third step, the second trench reaching the fifth semiconductor region through the second semiconductor layer in the depth direction is formed. Semiconductor device manufacturing method.   21. The method of manufacturing a semiconductor device according to claim 20, wherein the width of the fifth semiconductor region is wider than the width of the second trench.   The semiconductor device manufacturing method according to any one of claims 16 to 21, wherein the semiconductor having a wider band gap than silicon is silicon carbide.

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