JP2017228761A - Semiconductor device and manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a high radiation tolerance such as SEGR tolerance. A semiconductor substrate, a first body region and a second body region provided on the upper surface side of the semiconductor substrate, and a neck portion provided between the first body region and the second body region. , The first gate electrode facing the first body region between the first source region and the second source region and the first source region and the neck portion, and the second source region and the neck portion. A second gate electrode facing the second body region between the two, and a separation electrode provided facing the neck portion and separately from the first gate electrode and the second gate electrode. And provides a semiconductor device. [Selection diagram] Fig. 1

Description

  The present invention relates to a semiconductor device and a manufacturing method.

When a MOS semiconductor device is used in a radiation environment such as in space or a nuclear facility, radiation may affect the semiconductor device. Known effects of radiation on semiconductor devices include TID (Total Ionizing Dose) and SEGR (Single Event Gate Rapture). Related prior art documents include the following documents.
[Prior art documents]
[Patent Literature]
Patent Document 1 Japanese Patent Application Laid-Open No. 2008-182191

  The semiconductor device preferably has high radiation tolerance such as SEGR tolerance.

  In a first aspect of the present invention, a semiconductor device is provided. The semiconductor device may have a first conductivity type semiconductor substrate. The semiconductor device may have a second conductivity type, and may include a first body region and a second body region provided on the upper surface side of the semiconductor substrate. The semiconductor device may have a neck portion of the first conductivity type provided between the first body region and the second body region. The semiconductor device has a first conductivity type, and includes a first source region formed in the first body region and a second source region formed in the second body region. Good. The semiconductor device may include a first gate electrode facing the first body region between the first source region and the neck portion. The semiconductor device may include a second gate electrode facing the second body region between the second source region and the neck portion. The semiconductor device may include a separation electrode provided to face the neck portion. The separation electrode may be provided separately from the first gate electrode and the second gate electrode.

  The semiconductor device may include a source electrode formed above the upper surface of the semiconductor substrate. The separation electrode may be electrically connected to the source electrode.

  The semiconductor device may include a gate connection portion that is formed above the separation electrode and electrically connects the first gate electrode and the second gate electrode. An opening for electrically connecting the source electrode and the separation electrode may be formed in the gate connection portion.

  The separation electrode may have a first extension formed by extending upward from the first gate electrode so as to cover a gap between the separation electrode and the first gate electrode. The separation electrode may have a second extension formed by extending upward from the second gate electrode so as to cover a gap between the separation electrode and the second gate electrode. The first extension may be formed so as to cover the first gate electrode. The second extension may be formed so as to cover the second gate electrode. The source electrode may be in contact with the first extension and the second extension.

  On the upper surface of the semiconductor substrate, the end portion of the first body region and the end portion of the first gate electrode may be provided to face each other. On the upper surface of the semiconductor substrate, the end portion of the second body region and the end portion of the second gate electrode may be provided to face each other.

  The first body region and the second body region may have a protruding portion that protrudes closer to the neck portion than the end portion on the upper surface of the semiconductor substrate. The end portion of the separation electrode may be disposed closer to the gate electrode than the tip end of the protruding portion. The semiconductor device has a second conductivity type, and further includes a third body region provided on the upper surface side of the semiconductor substrate. The first body region and the second body region are formed in the third body region. May be connected.

  In a second aspect of the present invention, a method for manufacturing a semiconductor device is provided. In the manufacturing method, a second conductivity type impurity is implanted into the upper surface side of the first conductivity type semiconductor substrate, the second conductivity type first body region and second body region, and the first Forming a neck portion of the first conductivity type provided between the body region and the second body region. The manufacturing method may include forming a first source region of a first conductivity type in the first body region. The manufacturing method may include a step of forming a second source region of the first conductivity type in the second body region. The manufacturing method may include a step of forming an insulating film on the upper surface of the semiconductor substrate. The manufacturing method may include a step of forming a first gate electrode facing the first body region between the first source region and the neck portion on the upper surface side of the insulating film. The manufacturing method may include a step of forming a second gate electrode facing the second body region between the second source region and the neck portion. The manufacturing method may include a step of forming a separation electrode separated from the first gate electrode and the second gate electrode, facing the neck portion.

  In the step of forming the first gate electrode and the second gate electrode, the end portion of each gate electrode may be formed inside the body region rather than the end portion of each body region on the upper surface of the semiconductor substrate. After forming the first gate electrode, the second gate electrode, and the separation electrode, the upper surface of the semiconductor substrate is oxidized to absorb impurities in the body region in the insulating film not covered with the respective gate electrode and separation electrode There may be provided a step.

  The summary of the invention does not enumerate all the features of the present invention. In addition, a sub-combination of these feature groups can also be an invention.

1 is a cross-sectional view showing an example of a semiconductor device 100 according to a first embodiment of the present invention. FIG. 6 is a diagram illustrating another cross-sectional example of the semiconductor device 100. 6 is a diagram showing an example of an electric field intensity distribution in the X-axis direction in the gate insulating film 27. FIG. An example of the electric field strength in the gate insulating film of the comparative example is shown. An example of the electric field strength in the gate insulating film 27 of the semiconductor device 100 is shown. An example of the electric field strength in the gate insulating film of the comparative example is shown. An example of the electric field strength in the gate insulating film 27 of the semiconductor device 100 is shown. It is sectional drawing which shows an example of the semiconductor device 200 concerning 2nd Example of this invention. It is sectional drawing which shows an example of the semiconductor device 300 which concerns on 3rd Example of this invention. FIG. 10 is a diagram showing another cross-sectional example of the semiconductor device 300. It is sectional drawing which shows an example of the semiconductor device 400 which concerns on 4th Example of this invention. 5 is a diagram illustrating an example of a manufacturing method of the semiconductor device 100. FIG. 6 is a diagram illustrating another example of the method for manufacturing the semiconductor device 100. FIG. 6 is a diagram illustrating another example of the method for manufacturing the semiconductor device 100. FIG. 6 is a diagram illustrating an example of a manufacturing method of the semiconductor device 200. FIG. It is sectional drawing which shows an example of the semiconductor device 500 concerning 5th Example of this invention. 4 is an enlarged cross-sectional view in which a periphery of a body region 12 in a semiconductor device 500 is enlarged. FIG. 6 is a diagram illustrating an example of a method for manufacturing the semiconductor device 500. FIG. 6 is a diagram showing another example of a method for manufacturing the semiconductor device 500. FIG. 3 is a plan view showing a cross section taken along the line AA ′ of the semiconductor device 100. 12 is another example of a plan view showing a cross section taken along the line AA ′ of the semiconductor device 100.

  Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. In addition, not all the combinations of features described in the embodiments are essential for the solving means of the invention.

(First embodiment)
FIG. 1 is a sectional view showing an example of a semiconductor device 100 according to the first embodiment of the present invention. Although FIG. 1 illustrates a MOSFET as an example of the semiconductor device 100, the semiconductor device 100 may be another semiconductor device having a gate structure. As a more specific example, the semiconductor device 100 may be an insulated gate bipolar transistor (IGBT).

  The semiconductor device 100 of this example includes a semiconductor substrate 10 of a first conductivity type. In this example, the first conductivity type is N type and the second conductivity type is P type. However, the first conductivity type may be P type and the second conductivity type may be N type. The semiconductor substrate 10 is a silicon substrate to which a predetermined N-type impurity is added, for example. The semiconductor substrate 10 may be a compound semiconductor such as silicon carbide or a nitride semiconductor.

  A drain electrode 24 is provided on one main surface side of the semiconductor substrate 10, and a source electrode 26 is provided on the other main surface side. Note that when the semiconductor device 100 is a bipolar element such as an IGBT, the source electrode 26 may function as an emitter electrode, and the drain electrode 24 may function as a collector electrode.

  In this specification, a direction connecting the source electrode 26 and the drain electrode 24 is defined as a Y-axis direction. In this specification, the Y-axis direction may be referred to as the depth direction. In addition, one side in the Y-axis direction may be referred to as “upper” and the other side as “lower”. In this specification, the direction from the drain electrode 24 to the source electrode 26 is referred to as a Y-axis positive direction, and the relative positive side in the Y-axis is referred to as “upper” and the relative negative side is referred to as “lower”. For example, the surface on the drain electrode 24 side of the main surface of the semiconductor substrate 10 is referred to as a lower surface, and the surface on the source electrode 26 side is referred to as an upper surface.

  The drain electrode 24 is formed in contact with the entire predetermined active region on the lower surface of the semiconductor substrate 10. The source electrode 26 is formed in selective contact with a part of the active region on the upper surface of the semiconductor substrate 10. For example, the source electrode 26 is formed so as to be in contact with the source region 14 in the active region on the upper surface of the semiconductor substrate 10. The source electrode 26 may be in contact with a body region 12 described later. The drain electrode 24 and the source electrode 26 are made of a metal such as aluminum.

  The semiconductor substrate 10 of this example has a drain region 22, an intermediate region 20, and a drift region 16 in order from the lower surface side. The drain region 22 in this example is an N ++ type region. The intermediate region 20 in this example is an N + type region having an impurity concentration lower than that of the drain region 22 and higher than that of the drift region 16. The drift region 16 in this example is an N-type region having a lower impurity concentration than the intermediate region 20. Although the semiconductor substrate 10 of this example includes the intermediate region 20, the intermediate region 20 may not be included.

  A first body region 12-1 and a second body region 12-2 are formed on the drift region 16 on the upper surface side of the semiconductor substrate 10. In this example, each body region 12 is a P-type region. The body regions 12 are provided apart from each other in a cross section perpendicular to the upper surface of the semiconductor substrate 10. In this specification, the direction connecting the first body region 12-1 and the second body region 12-2 is defined as the X-axis direction. Each body region 12 is exposed on the upper surface of the semiconductor substrate 10.

  In this specification, a direction perpendicular to both the X axis and the Y axis is taken as a Z axis direction. Although FIG. 1 shows an XY cross section, each configuration shown in the cross section may be formed by extending in the Z-axis direction. Moreover, each structure shown to the said cross section may be formed cyclically | annularly in the XZ plane. Further, the configuration shown in the cross section of FIG. 1 may be repeatedly formed in the X-axis direction.

  The N-type region of the drift region 16 remains between the first body region 12-1 and the second body region 12-2. In the present specification, an N-type region between the first body region 12-1 and the second body region 12-2 is referred to as a neck portion 18.

  A first source region 14-1 is formed in the first body region 12-1. A second source region 14-2 is formed in the second body region 12-2. Each source region 14 is exposed on the upper surface of the semiconductor substrate 10. Further, the source region 14 is covered with the body region 12 except for the upper surface of the semiconductor substrate 10. In this example, the source region 14 is N-type. The impurity concentration of the source region 14 is higher than the impurity concentration of the drift region 16.

  A first gate electrode 30-1 and a second gate electrode 30-2 are provided above the upper surface of the semiconductor substrate 10. The first gate electrode 30-1 is provided to face the first body region 12-1 between the first source region 14-1 and the neck portion 18. The first gate electrode 30-1 is preferably formed over the entire length between the first source region 14-1 and the neck portion 18.

  The second gate electrode 30-2 is provided to face the second body region 12-2 between the second source region 14-1 and the neck portion 18. The second gate electrode 30-2 is preferably formed over the entire length between the second source region 14-2 and the neck portion 18. A gate insulating film 27 is provided between each gate electrode 30 and the semiconductor substrate 10.

  The body region 12 facing each gate electrode 30-2 functions as a channel. An inversion region is formed on the surface of the body region 12 facing the gate electrode 30 by applying a predetermined voltage to each gate electrode 30. As a result, the source region 14 and the neck portion 18 are electrically connected. By applying a predetermined voltage to the gate electrode 30 in a state where a predetermined voltage is applied between the source electrode 26 and the drain electrode 24, a current flows between the source and drain.

  A separation electrode 60 is further provided above the upper surface of the semiconductor substrate 10. The isolation electrode 60 is provided to face the neck portion 18 with the gate insulating film 27 interposed therebetween. The separation electrode 60 is preferably formed so as to cover the entire region where the neck portion 18 is exposed on the upper surface of the semiconductor substrate 10. However, some of the neck portions 18 may not be covered with the separation electrode 60. The separation electrode 60 may cover more than half of the neck portion 18 on the upper surface of the semiconductor substrate 10 and may cover 3/4 or more.

  The separation electrode 60 is separated from both the first gate electrode 30-1 and the second gate electrode 30-2. The separation electrode 60 may be formed of the same conductive material as that of the gate electrode 30 or may be formed of a different conductive material.

  When the lower surface of the gate insulating film 27 and the drain electrode 24 are electrically connected to the separation electrode 60, a voltage is applied to relax the electric field applied to the gate insulating film 27 on the neck portion 18. Is done. For example, when heavy particles are incident on the semiconductor substrate 10, a plasma filament (electron-hole pair) is generated along the path through which the heavy particles have passed. Therefore, when heavy particles enter the neck portion 18, the lower surface of the gate insulating film 27 on the neck portion 18 and the drain electrode 24 are electrically connected via the plasma filament generated in the N-type region.

  When the gate electrode 30 is provided at a position facing the neck portion 18, a drain-gate voltage is applied to the gate insulating film 27 on the neck portion 18. Since the drain-gate voltage is a relatively large voltage in the initial stage, the gate insulating film 27 on the neck portion 18 may be destroyed when heavy particles enter.

  On the other hand, according to the semiconductor device 100, the separation electrode 60 is provided in a region facing the neck portion 18. If a voltage between the lower limit value (or upper limit value) of the gate voltage fluctuation range and the drain voltage is applied to the separation electrode 60, the electric field applied to the gate insulating film 27 on the neck portion 18 is relaxed. Can do.

  For example, the source electrode 26 is grounded, a drain voltage of about several tens to several hundreds V is applied to the drain electrode 24, a gate voltage of about 10V to 15V is applied to the gate electrode 30 when turned on, and the gate electrode 30 is turned off when turned off. A semiconductor device to be grounded will be described. At turn-off, the gate voltage may temporarily be a negative voltage. At this time, the drain-gate voltage becomes relatively large.

  On the other hand, by applying a voltage between the drain voltage and the negative voltage to the separation electrode 60, the voltage applied to the gate insulating film 27 on the neck portion 18 can be reduced. it can. For this reason, it can suppress that the gate insulating film 27 on the neck part 18 is destroyed, and can improve SEGR tolerance.

  Note that a voltage that allows the semiconductor device 100 to perform an on / off operation in a normal state is applied to the separation electrode 60. As an example, the separation electrode 60 may be electrically connected to the source electrode 26. That is, the ground potential may be applied to the separation electrode 60. As a result, since a constant drain-source voltage is applied to the gate insulating film 27 on the neck portion 18, even if the gate voltage temporarily changes to a negative voltage, the gate insulation on the neck portion 18. The electric field applied to the film 27 can be relaxed.

  Further, a voltage between the source voltage and the lower limit value of the gate voltage may be applied to the separation electrode 60. Further, a positive voltage higher than the source potential may be applied to the separation electrode 60 on condition that the semiconductor device 100 can be turned on / off.

  In this example, a gate insulating film 27 is formed under the separation electrode 60. That is, the insulating film below the separation electrode 60 and the insulating film below the gate electrode 30 are equal in thickness. In another example, the insulating film below the separation electrode 60 and the insulating film below the gate electrode 30 may have different thicknesses.

  When improving the breakdown voltage between the source and the drain, the insulating film below the isolation electrode 60 may be thicker than the insulating film below the gate insulating film 27. In order to improve the breakdown voltage between the gate and the source, the insulating film below the gate insulating film 27 may be thicker than the insulating film below the isolation electrode 60.

  The semiconductor device 100 of this example further includes a gate connection portion 62 that is formed above the separation electrode 60 and electrically connects the first gate electrode 30-1 and the second gate electrode 30-2. An insulating film 29 is formed between the gate connection portion 62 and the separation electrode 60.

  The gate connection part 62 may be formed of the same conductive material as the gate electrode 30 or may be formed of a different conductive material. The gate connection portion 62 and the gate electrode 30 in this example are formed of polysilicon doped with impurities.

  The gate connection portion 62 of this example is formed so as to cover the separation electrode 60 from the first gate electrode 30-1 to the second gate electrode 30-2. Further, the gate connection portion 62 is formed so as to cover the gap 64 between the separation electrode 60 and each gate electrode 30. An insulating film is formed in the gap 64.

  By providing the gate connection portion 62, it is possible to suppress ions or the like incident from above the semiconductor device 100 from reaching the semiconductor substrate 10 through the gap 64. Thereby, the semiconductor device 100 can be protected.

  The insulating film 29 may have the same thickness as the gate insulating film 27 or may have a different thickness. Since a relatively small voltage is applied to the insulating film 29, the insulating film 29 may be thinner than the gate insulating film 27. A gate voltage is applied to the gate connection portion 62. However, the separation electrode 60 is provided between the gate connection portion 62 and the semiconductor substrate 10. For this reason, for example, a gate-source voltage is applied to the insulating film 29. Further, the width of the gap 64 in the X-axis direction may be smaller than the thickness of the gate insulating film 27 in the Y-axis direction.

  The semiconductor device 100 of this example further includes an interlayer insulating film 28 that covers the gate electrode 30 and the gate connection portion 62. The interlayer insulating film 28 may be formed by depositing BPSG (Boron Phosphorus Silicate Glass) or PSG (Phosphorus Silicate Glass).

  As described above, according to the semiconductor device 100 of the first embodiment, the SEGR resistance can be improved. Moreover, the trade-off between TID tolerance and SEGR tolerance can also be improved.

  When radiation enters the gate insulating film 27, electron-hole pairs are generated in the gate insulating film 27. The mobility in the gate insulating film 27 is smaller than that of electrons than that of electrons. For example, when the gate insulating film 27 is a silicon oxide film, the mobility is six digits or more. A fixed charge is generated between the gate electrode 30 and the semiconductor substrate 10 when holes are captured by defects in the gate insulating film 27. In addition, an interface state is generated by the holes reaching the interface. The threshold value of the MOS transistor varies depending on the fixed charge and the interface state. Such a phenomenon is called TID.

  On the other hand, generation of defects in the gate insulating film 27 can be suppressed by generating the gate insulating film 27 by a low temperature process. The gate insulating film 27 is formed by oxidizing the surface of the semiconductor substrate 10 at, for example, 1000 degrees or less. The oxidation temperature may be 900 degrees or less. Thereby, TID tolerance can be improved.

  When heavy particles are incident on the semiconductor substrate 10, plasma filaments (electron hole pairs) are generated along the path through which the heavy particles have passed. For this reason, when heavy particles enter the neck portion 18, the back surface of the gate insulating film 27 and the drain electrode 24 are electrically connected via the plasma filament generated in the N-type region. When the gate electrode 30 is provided at a position facing the neck portion 18, a large drain voltage is applied between the front and back surfaces of the gate insulating film 27 facing the neck portion 18, and the gate insulating film 27 is destroyed. End up. Such a phenomenon is called SEGR.

  In order to increase the SEGR resistance, the thickness of the gate insulating film 27 may be increased. However, when the thickness of the gate insulating film 27 functioning as a gate oxide film is increased, the amount of charge generated when the gate insulating film 27 is irradiated with electron radiation increases, and the TID resistance is deteriorated.

  On the other hand, by providing the separation electrode 60, the semiconductor device 100 can improve the SEGR resistance without deteriorating the TID resistance or suppressing the deterioration of the TID resistance.

  FIG. 2 is a diagram illustrating another cross-sectional example of the semiconductor device 100. The cross section shown in FIG. 2 differs from the cross section shown in FIG. 1 in the position in the Z-axis direction. The semiconductor device 100 has the structure shown in FIG. 1 extended in the Z-axis direction, and has the structure shown in FIG. 2 in a partial region in the Z-axis direction. The structure shown in FIG. 2 is preferably provided at the end of the semiconductor substrate 10 in the Z-axis direction.

  In the cross section, the gate connection portion 62 has an opening 66 for electrically connecting the source electrode 26 and the separation electrode 60. The source electrode 26 has a source connection portion 68 that passes through the opening 66 and is connected to the separation electrode 60. The source connection portion 68 may be formed of the same material as the source electrode 26 or may be formed of a different material. The source connection 68 may be formed of a material containing tungsten.

  The source connection portion 68 is electrically insulated from the gate connection portion 62. An insulating film is formed between the source connection portion 68 and the gate connection portion 62 in this example.

  With such a structure, the source potential can be easily applied to the separation electrode 60. For this reason, SEGR tolerance can be improved.

  FIG. 3 is a diagram illustrating an example of the electric field intensity distribution in the X-axis direction in the gate insulating film 27. FIG. 3 shows an electric field intensity distribution in a state where heavy particles or the like are not incident. The origin in the X-axis direction corresponds to the center position of the neck portion 18. In addition, a rated voltage is applied as the drain-source voltage, and -15 V is applied as the gate-source voltage.

  3 shows the electric field intensity distribution in the comparative example in which the gate electrode 30 is formed also on the neck portion 18 without the separation electrode 60 and the electric field intensity distribution in the semiconductor device 100. A source potential is applied to the separation electrode 60 of the semiconductor device 100 of this example.

  As shown in FIG. 3, by providing the separation electrode 60, the electric field strength at the neck portion 18 can be relaxed before the entrance of heavy particles or the like. Since the electric field in the gate insulating film 27 on the neck portion 18 can be relaxed in the initial stage, the electric field in the gate insulating film 27 on the neck portion 18 can be relaxed even when heavy particles are incident. For this reason, SEGR tolerance improves.

  FIG. 4A shows an example of the electric field strength in the gate insulating film of the comparative example. FIG. 4B shows an example of the electric field strength in the gate insulating film 27 of the semiconductor device 100. In the examples of FIGS. 4A and 4B, the electric field strength is calculated by changing the gate-source voltage. The drain-source voltage is the rated voltage. 4A and 4B show the electric field strengths of the gate insulating film on the neck portion 18 and the gate insulating film on the body region 12, respectively.

  The electric field strength characteristics in the gate insulating film on the body region are almost the same in the two examples of FIGS. 4A and 4B. In the comparative example shown in FIG. 4A, a gate electrode is also provided above the neck portion. For this reason, as the absolute value of the gate-source voltage VGS increases, the electric field strength in the gate insulating film on the neck portion increases.

  In contrast, in the example of the semiconductor device 100 illustrated in FIG. 4B, the separation electrode 60 is provided above the neck portion 18. For this reason, even if the absolute value of the gate-source voltage VGS is increased, the electric field strength in the gate insulating film 27 on the neck portion 18 hardly changes. For this reason, SEGR tolerance improves.

  FIG. 5A shows an example of the electric field strength in the gate insulating film of the comparative example. FIG. 5B shows an example of the electric field strength in the gate insulating film 27 of the semiconductor device 100. In the examples of FIGS. 5A and 5B, the electric field strength is calculated by changing the drain-source voltage. The gate-source voltage is -15V.

  In both the comparative example shown in FIG. 5A and the semiconductor device 100 shown in FIG. 5B, even if the drain-source voltage VDS is changed, the electric field strength in the gate insulating film (electric field strength in the body region) hardly changes. However, in the comparative example shown in FIG. 5A, an electric field corresponding to a gate voltage of −15 V is applied in addition to VDS to both the gate insulating film corresponding to the neck portion and the gate insulating film corresponding to the body region. . Therefore, in the comparative example shown in FIG. 5A, the electric field strength of the neck portion is higher than that of the body portion.

  On the other hand, in the semiconductor device 100 shown in FIG. 5B, an electric field corresponding to a gate voltage of −15 V in addition to the drain-source voltage VDS is applied to the gate insulating film 27 corresponding to the body region 12. Only an electric field corresponding to the drain / source voltage VDS is applied to the gate insulating film 27 on the portion 18. Therefore, in the semiconductor device 100 shown in FIG. 5B, the electric field strength of the neck portion is lower than that of the body region, and the electric field strength of the gate insulating film on the neck portion is relaxed. For this reason, when heavy particles are incident, a plasma filament is generated between the drain electrode 24 and the upper surface of the semiconductor substrate 10, and the electric field applied to the insulating film tends to increase. The applied electric field can be relaxed. For this reason, SEGR tolerance improves.

(Second embodiment)
FIG. 6 is a sectional view showing an example of a semiconductor device 200 according to the second embodiment of the present invention. The semiconductor device 200 differs from the semiconductor device 100 in the structure of the gate connection portion 62. Other structures may be the same as those of the semiconductor device 100. The cross section shown in FIG. 6 corresponds to the cross section shown in FIG. That is, the semiconductor device 200 may have the structure shown in FIG. 6 extending in the Z-axis direction, and may have the same structure as FIG. 2 at the end of the semiconductor substrate 10.

  The gate connection portion 62 of this example has an opening 70. By the opening 70, the gate connection portion 62 is divided into a portion connected to the first gate electrode 30-1 and a portion connected to the second gate electrode 30-2. The opening 70 has the same shape as the opening 66 illustrated in FIG. 2, and the position on the X axis may be the same as the opening 66. Thereby, the semiconductor device 200 can be manufactured easily.

  The opening 70 is preferably not formed at a position facing the gap 64. That is, it is preferable that the respective gaps 64 on both sides of the separation electrode 60 are covered with the corresponding gate connection portions 62. Thereby, the manufacturing of the semiconductor device 200 can be facilitated, and ions and the like can be prevented from entering the semiconductor substrate 10 through the gap 64.

(Third embodiment)
FIG. 7 is a sectional view showing an example of a semiconductor device 300 according to the third embodiment of the present invention. The semiconductor device 300 differs from the semiconductor device 100 in that it does not have the gate connection portion 62 and the shape of the separation electrode 60. Other structures may be the same as those of the semiconductor device 100. The cross section shown in FIG. 7 corresponds to the cross section shown in FIG.

  The first gate electrode 30-1 and the second gate electrode 30-2 in this example are provided separately from each other. The first gate electrode 30-1 and the second gate electrode 30-2 may be plate-shaped.

  The separation electrode 60 extends to the upper side of the first gate electrode 30-1 and the first extension part 72-1, which is formed to extend upward from the first gate electrode 30-1. And a second extension 72-2 formed. The separation electrode 60 may have only one of the first extension part 72-1 and the second extension part 72-2.

  Each extension 72 may be formed of the same material as that of the separation electrode 60. Each extension 72 and the gate electrode 30 are insulated by an insulating film. Each extension 72 is covered with the interlayer insulating film 28.

  The first extension portion 72-1 is formed so as to cover the gap 64 between the separation electrode 60 and the first gate electrode 30-1. The first extension part 72-1 may extend to a position that covers a part of the first gate electrode 30-1, or may extend to a position that covers the entire first gate electrode 30-1. .

  The second extension portion 72-2 is formed so as to cover the gap 64 between the separation electrode 60 and the second gate electrode 30-2. The second extension part 72-2 may extend to a position that covers a part of the second gate electrode 30-2, or may extend to a position that covers the entire second gate electrode 30-2. .

  Also with such a configuration, the incidence of ions or the like to the semiconductor substrate 10 can be suppressed. Further, according to the semiconductor device 300, since the extension 72 of the separation electrode 60 is formed above the gate electrode 30, the source electrode 26 and the separation electrode 60 can be easily connected.

  FIG. 8 is a diagram illustrating another cross-sectional example of the semiconductor device 300. The cross section shown in FIG. 8 differs from the cross section shown in FIG. 7 in the position in the Z-axis direction. The cross section shown in FIG. 8 corresponds to the cross section shown in FIG. That is, the semiconductor device 300 may have the structure shown in FIG. 7 extending in the Z-axis direction, and may have the structure shown in FIG.

  In the cross section, an opening for electrically connecting the source electrode 26 and the extension 72 is formed in the interlayer insulating film 28. The source electrode 26 has a source connection part 68 that contacts the separation electrode 60 through the opening.

  In this example, it is not necessary to form the opening 66 in the gate connection portion 62, so that the source potential can be easily applied to the separation electrode 60. Note that another example of the semiconductor device 300 may have the structure illustrated in FIG. 8 over the entire Z-axis direction. That is, the source connection portion 68 may be formed over the entire separation electrode 60 in the Z-axis direction.

(Fourth embodiment)
FIG. 9 is a cross-sectional view showing an example of a semiconductor device 400 according to the fourth embodiment of the present invention. The semiconductor device 400 is different from the semiconductor device 100 in that the gate connection portion 62 is not provided. Other structures may be the same as those of the semiconductor device 100.

  In the semiconductor device 400, the gate connection portion 62 is not provided. Even in such a configuration, since the separation electrode 60 is provided, the electric field in the gate insulating film 27 on the neck portion 18 can be relaxed, and the SEGR resistance can be improved.

  The gate electrode 30 and the separation electrode 60 may be plate-like electrodes. The gate electrode 30 and the separation electrode 60 may have the same thickness. The gate electrode 30 and the separation electrode 60 may be formed of the same material. However, the shape, thickness, and material of the gate electrode 30 and the separation electrode 60 are not limited to the above examples.

  FIG. 10A is a diagram illustrating an example of a method for manufacturing the semiconductor device 100. First, in step S1000, a semiconductor substrate having a drain region, an intermediate region, and a drift region 16 is prepared. The semiconductor substrate is a substrate in which an N ++ type epitaxial layer (functioning as an intermediate region) and an N type epitaxial layer (functioning as a drift region 16) are formed on an N ++ type substrate (functioning as a drain region). Good. In another example, the semiconductor substrate may be an N-type substrate (functioning as a drift region). In this case, an intermediate region and a drain region are formed by implanting impurities on the lower surface side of the substrate.

Next, P-type impurities such as boron are selectively implanted from the upper surface side of the semiconductor substrate to form P-type first and second body regions 12. As an example, the doping amount of the P-type impurity is 1.0 × 10 ¹³ / cm ² or more and 4.0 × 10 ¹⁴ / cm ² or less. After the impurity is implanted, the semiconductor substrate is heat-treated to diffuse the P-type impurity to a predetermined depth, thereby forming the body region 12. The depth of the body region 12 in this example is 2 μm or more and 6 μm or less. The drift region 16 remaining between the first and second body regions 12 becomes the neck portion 18.

Further, N + type first and second source regions 14 are formed by selectively implanting N type impurities such as arsenic into the first and second body regions 12. As an example, the doping amount of the N-type impurity is 1.0 × 10 ¹⁴ / cm ² or more and 1.0 × 10 ¹⁶ / cm ² or less. After the impurities are implanted, the semiconductor substrate is heat-treated to form the source region 14.

  Next, in step S1002, an insulating film 74 is formed on the upper surface of the semiconductor substrate. The insulating film 74 may be formed by thermally oxidizing a semiconductor substrate. As an example, the insulating film 74 of 600 to 1500 mm is formed by thermal oxidation of 800 to 950 degrees.

  Next, a conductive layer 77 is formed on the insulating film 74. For the conductive layer 77, a conductive material such as polysilicon to which impurities are added may be formed by a CVD method or the like.

  Next, in step S1004, the conductive layer 77 and the insulating film 74 are patterned into a predetermined shape. In this example, a photoresist is applied on the conductive layer 77, and the photoresist is exposed to a shape corresponding to the gate electrode 30 and the separation electrode 60 and developed. Thereby, an opening having a predetermined shape is formed in the photoresist. The conductive layer 77 and the insulating film 74 that are not covered with the photoresist are removed by etching, and the gate electrode 30 and the separation electrode 60 are formed.

Next, in step S1006, an insulating film 76 such as SiO ₂ is deposited with a thickness of 1000 to 4000 by a CVD method or the like. Next, in step S1008, the insulating film 76 is patterned into a predetermined shape. In this example, a photoresist is applied on the insulating film 76, and is exposed and developed. Further, the insulating film 76 not covered with the photoresist is removed by etching. Thereby, at least a part of each gate electrode 30 is exposed. The separation electrode 60 is covered with an insulating film 76. In S1008, the entire gate electrode 30 may be exposed.

  Next, in step S <b> 1010, a conductive layer 78 is formed on the insulating film 76 and the gate electrode 30. The conductive layer 78 may be formed of a conductive material such as polysilicon to which impurities are added by a CVD method or the like. Next, in step S1012, the conductive layer 78 is patterned into a predetermined shape. In step S <b> 1012, a photoresist is applied on the conductive layer 78, and the photoresist is patterned into a shape corresponding to the gate connection portion 62. The gate connection 62 is formed by removing the conductive layer 78 not covered with the photoresist by etching. FIG. 10A shows the gate electrode 30 and the separation electrode 60 having the same thickness. In another example, since the conductive layer 78 is further formed on the gate electrode 30 in S1010, the gate electrode 30 may be formed thicker than the separation electrode 60.

  Next, in step S1014, the interlayer insulating film 28 that covers the gate electrode 30 and the gate connection portion 62 is formed. Further, the source electrode 26, the drain electrode 24, and the like are formed. Thereby, the semiconductor device 100 is completed.

  FIG. 10B is a diagram illustrating another example of the method for manufacturing the semiconductor device 100. In the manufacturing method of this example, first, steps S1000 and S1002 similar to the example of FIG. 10A are performed.

  Next, in step S <b> 1016, the conductive layer 77 and the insulating film 74 are patterned into a shape corresponding to the separation electrode 60. The patterning method is the same as that in step S1004 in the example of FIG. 10A. Thereby, the separation electrode 60 is formed.

  Next, in step S <b> 1018, an insulating film 76 is deposited on the semiconductor substrate 10 and the separation electrode 60. The insulating film 76 is formed by the same method as the insulating film 76 in the example of FIG. 10A.

  Next, in step S <b> 1020, the conductive layer 78 is formed on the insulating film 76. Thereby, the conductive layer 78 is formed above the body region 12 and above the separation electrode 60. The conductive layer 78 is formed by a method similar to that of the conductive layer 78 in the example of FIG. 10A.

  Next, in step S1022, the conductive layer 78 and the insulating film 76 are patterned into a predetermined shape. Thereby, the gate electrode 30, the gate connection portion 62, and the gate insulating film 27 are formed.

  Next, in step S1024, the interlayer insulating film 28 that covers the gate electrode 30 and the gate connection portion 62 is formed. Further, the source electrode 26, the drain electrode 24, and the like are formed. Thereby, the semiconductor device 100 is completed.

  FIG. 10C is a diagram illustrating another example of the method for manufacturing the semiconductor device 100. In this example, first, in step S <b> 1026, an insulating film 74 and a conductive layer 77 are formed on the semiconductor substrate 10. The insulating film 74 and the conductive layer 78 are formed by the same method as the insulating film 74 and the conductive layer 77 in the example of FIG. 10A.

  Next, in step S1028, the conductive layer 77 and the insulating film 74 are patterned into a shape corresponding to the separation electrode 60. The patterning method is the same as that in step S1004 in the example of FIG. 10A. Thereby, the separation electrode 60 is formed.

  In step S1030, a P-type impurity such as boron is implanted into the semiconductor substrate 10 using the separation electrode 60 as a mask, and heat treatment is performed after the implantation. Thereby, the body region 12 is selectively formed. Next, a mask having an opening corresponding to the source region 14 is formed on the body region 12 with a photoresist or the like. Then, an N-type impurity such as arsenic is implanted, and heat treatment is performed after the implantation. Thereby, the source region 14 is selectively formed.

  The processes after S1030 are the same as the processes after step S1018 shown in FIG. 10B. The semiconductor device 100 can also be manufactured by such a method.

  FIG. 11 is a diagram illustrating an example of a method for manufacturing the semiconductor device 200. First, steps S1100 to S1106 similar to steps S1000 to S1006 in the example of FIG. 10A are performed. Next, in step S1108, a part of the insulating film 76 is etched to expose a part of the upper surface of the separation electrode 60.

  Next, in step S1110, the conductive layer 80 is formed on the insulating film 76 and in the opening of the insulating film 76 by a CVD method or the like. The conductive layer 80 may be made of the same material as that of the separation electrode 60.

  Next, in step S1112, the conductive layer 80 and the insulating film 76 are etched. Thereby, the extension part 72-1 and the extension part 72-2 are formed.

  Next, in step S1114, the interlayer insulating film 28 that covers the extension 72 is formed. Further, the source electrode 26, the drain electrode 24, and the like are formed. Thereby, the semiconductor device 200 is completed.

(5th Example)
FIG. 12 is a sectional view showing an example of a semiconductor device 500 according to the fifth embodiment of the present invention. The semiconductor device 500 of this example is different in the shape of the body region 12 from the semiconductor device according to any one of the embodiments described with reference to FIGS. Other structures may be the same as any of the semiconductor devices described in FIGS. FIG. 12 shows an example in which the shape of the body region 12 in the semiconductor device 100 according to the first example is changed.

  In this example, on the upper surface of the semiconductor substrate 10, the end portion 38 of the first body region 12-1 and the end portion 36 of the first gate electrode 30-1 are provided at positions facing each other. In addition, the end 38 of the second body region 12-2 and the end 36 of the second gate electrode 30-2 are provided at opposing positions. The end portion 38 of the body region 12 and the end portion 36 of the gate electrode 30 indicate end portions on the neck portion 18 side. Further, the end portion 38 of the body region 12 and the end portion 36 of the gate electrode 30 indicate end portions in the layer closest to the upper surface of the semiconductor substrate 10.

  Further, the fact that the end portions face each other means that the positions of the end portion 38 and the end portion 36 in the plane parallel to the upper surface of the semiconductor substrate 10 are substantially the same. As an example, when the position error of the end 38 and the end 36 in the plane is within 0.2 μm, the end 38 and the end 36 may be regarded as facing each other.

  However, in the case of having the above-described position error, it is preferable that the end portion 36 of the gate electrode 30 protrudes closer to the neck portion 18 than the end portion 38 of the body region 12. By disposing the end portion 38 of the body region 12 and the end portion 36 of the gate electrode 30 to face each other, SEGR resistance can be improved while ensuring controllability of the channel in the body region 12.

  Each body region 12 has a protruding portion 32 that protrudes toward the neck portion 18 with respect to the end portion 38 on the upper surface of the semiconductor substrate 10. An N-type neck portion 18 extends between the protruding portion 32 and the upper surface of the semiconductor substrate 10.

  By providing the projecting portion 32, when the positional error between the end portion 36 of the gate electrode 30 and the end portion 38 of the body region 12 is formed in a range larger than 0 to 0.2 μm (that is, the end portion 36 is formed). The gate insulating film 27 sandwiched between the gate electrodes 30 facing the neck portion 18 is protected by the protruding portion 32 when the tip portion 38 is displaced from the end portion 38 toward the tip 34 side. For this reason, even if heavy particles are incident and a plasma filament is formed, it is possible to prevent a large drain voltage from being applied to the gate insulating film 27 sandwiched between the gate electrode 30 and the neck portion 18. Moreover, the neck part 18 can be made thin by providing the protrusion part 32. FIG. For this reason, when heavy particles enter the semiconductor substrate 10, it is difficult to form a plasma filament path that penetrates the N-type region. Therefore, SEGR tolerance can be improved.

  FIG. 13 is an enlarged cross-sectional view in which the periphery of the body region 12 in the semiconductor device 500 is enlarged. Although FIG. 13 shows the periphery of the first body region 12-1, the structure of the periphery of the second body region 12-2 is the same.

  The protruding portion 32 has a tip 34 located on the neck portion 18 side of the end portion 38 on the upper surface of the semiconductor substrate 10 inside the semiconductor substrate 10. The tip 34 indicates the portion of the protrusion 32 that is closest to the neck 18 in a plane parallel to the upper surface of the semiconductor substrate 10.

  The end portion 61 of the separation electrode 60 in this example is disposed closer to the gate electrode 30 than the tip end 34 of the protruding portion 32. The end 61 of the separation electrode 60 refers to the end of the separation electrode 60 in the layer closest to the upper surface of the semiconductor substrate 10. That is, the separation electrode 60 terminates above the protruding portion 32. Further, a part of the separation electrode 60 is disposed at a position overlapping the protruding portion 32.

  With such a structure, the separation electrode 60 can cover the space between the tip 34 of the first body region 12-1 and the tip 34 of the second body region 12-2. For this reason, the region where the drain electrode 24 and the upper surface of the semiconductor substrate 10 easily conduct when heavy particles are incident can be covered with the separation electrode 60.

  However, the end 61 of the separation electrode 60 may be disposed on the opposite side of the gate electrode 30 from the tip 34 of the body region 12. Further, the end portion 61 of the separation electrode 60 may be arranged at a position overlapping the tip 34 of the body region 12.

  FIG. 14 is a diagram illustrating an example of a method for manufacturing the semiconductor device 500. First, in the same process as steps S1000 and S1002 of FIG. 10A, the body region 12 and the source region 14 are formed in the semiconductor substrate 10, and the insulating film 74 and the conductive layer 77 are formed on the semiconductor substrate 10.

  Next, in step S1404, the conductive layer 77 and the insulating film 74 are patterned into a predetermined shape. The patterning method is the same as that in step S1004 in FIG. 10A. However, in the plane parallel to the upper surface of the semiconductor substrate 10, the end portion of each gate electrode 30 on the side of the separation electrode 60 is more in the body region 12 than the end portion in the upper surface of the semiconductor substrate 10 of each body region 12. The conductive layer 77 and the insulating film 74 are patterned so as to be disposed inside. Thereby, the two gate electrodes 30 and the separation electrode 60 are formed.

  Next, in step S1405, the upper surface of the semiconductor substrate 10 is thermally oxidized. In S1405, an oxide film is formed mainly in a region not covered with the gate electrode 30 and the separation electrode 60. In this example, an oxide film grows mainly below the gap 64. In FIG. 14, the insulating film 74 and the oxide film are combined to form an insulating film 75. The oxidation temperature in step S1405 is lower than 900 degrees, for example. As an example, the oxidation temperature is about 850 degrees.

  When the insulating film 75 is formed, impurities contained in the body region 12 that are not covered with the gate electrode 30 and the separation electrode 60 are absorbed by the insulating film 75. For this reason, the shape of the body region 12 is a shape in which a boundary portion with the neck portion 18 is wound around the gate electrode 30 side (that is, the source region 14 side) in the vicinity of the upper surface of the semiconductor substrate 10. The body region 12 is implanted with a kind of impurity that is extracted into the insulating film 75 when the semiconductor substrate 10 is oxidized. In this example, the semiconductor substrate 10 is silicon, and the impurity implanted into the body region 12 is boron.

  In step S1405, impurities in each body region 12 are absorbed by the insulating film 75 until the end portion 38 of each body region 12 and the end portion 36 of each gate electrode 30 face each other. However, in the region covered with the gate electrode 30, the impurity contained in the body region 12 is hardly absorbed by the insulating film 75. When the end portion 38 of the body region 12 moves to a position facing the end portion 36 of the gate electrode 30, the end portion 38 hardly moves to the source region 14 side even if oxidation is further advanced.

  Therefore, the position of the end portion 38 of the body region 12 can be aligned with the end portion 36 of the gate electrode 30 by self-alignment. Further, the position of the end portion 38 of each body region 12 can be accurately matched with the position of the end portion 36 of the gate electrode 30 in the same process.

  The process after step S1405 is the same as that after step S1006 in FIG. 10A, for example. Moreover, the process after step S1405 may be the same as that after step S1106 in FIG.

  In the example shown in FIG. 14, the end 61 of the separation electrode 60 is also disposed inside the body region 12. As a result, the end 61 of the separation electrode 60 can be disposed closer to the gate electrode 30 than the tip 34 of the body region 12.

  However, if the area of the body region 12 covered with the separation electrode 60 becomes too large, impurities in the region covered with the separation electrode 60 may not be efficiently sucked out. For this reason, the distance between the end 61 of the separation electrode 60 and the tip 34 of the body region 12 is preferably about 0.2 μm or less.

  Further, if the width of the gap 64 is too small, the impurities at the end of the body region 12 may not be efficiently sucked out when the gap 64 is uneven. On the other hand, if the width of the gap 64 is excessively increased, the width of the separation electrode 60 is reduced, so that the area of the neck portion 18 that can be covered with the separation electrode 60 is reduced. For this reason, the width of the gap 64 is preferably about 0.2 μm or more and 0.8 μm or less. The width of the gap 64 may be 0.3 μm or more. Further, the width of the gap 64 may be 0.5 μm or less.

  FIG. 15 is a diagram illustrating another example of the method for manufacturing the semiconductor device 500. The manufacturing method of this example has a process of step S1505 instead of the process of step S1405 of the manufacturing method shown in FIG. Other steps are the same as those in the manufacturing method shown in FIG.

  In step S1505, a counter impurity of the first conductivity type is implanted into the upper surface of the semiconductor substrate 10 using the first gate electrode 30-1, the second electrode 30-2, and the separation electrode 60 as a mask. In this example, a counter impurity of the first conductivity type is implanted from the gap 64. The counter impurity is an impurity having a conductivity type opposite to that of the body region 12. That is, when a P-type impurity is already implanted into the body region 12, the counter impurity is an N-type impurity. The counter impurity is implanted with a dose sufficient to make a part of the body region 12 have the first conductivity type.

As an example, when the semiconductor device 100 is a silicon N-channel MOS transistor, the counter impurity may be arsenic ions or phosphorus ions. As an example, the dose amount of the counter impurity is about 1.0 × 10 ¹⁴ / cm ² or more and 1.0 × 10 ¹⁶ / cm ² or less. When the semiconductor device 100 is a silicon P-channel MOS transistor, the counter impurity may be boron ions.

  In step S1505, a resist may be formed on the surface of the semiconductor substrate 10 before the counter impurity is implanted. The resist covers the upper surface of the semiconductor substrate 10 except for the region exposed by the gap 64.

  In step S1505, the semiconductor substrate 10 is heat-treated after implanting counter impurities. Thereby, the implanted counter impurity is activated. The heat treatment temperature is about 800 to 950 degrees. Due to the activated counter impurity, the end of the body region 12 on the upper surface of the semiconductor substrate 10 is retracted to a position facing the end of the gate electrode 30. Note that the end of the body region 12 may be disposed closer to the source region 14 than the end of the gate electrode 30 according to the diffusion length of the counter impurity.

  When the semiconductor device 100 is a silicon P-channel MOS transistor, it may be difficult to absorb the impurities in the body region 12 by the method shown in FIG. On the other hand, according to the manufacturing method of this example, the protruding portion 32 can be easily formed in the body region 12 even when the semiconductor device 100 is a silicon P-channel MOS transistor.

(Sixth embodiment)
FIG. 16 is an example of a plan view of a plane parallel to the AA ′ cross section of the semiconductor device 100 shown in FIG. The planar shapes of the first body region 12-1 and the second body region 12-2 are stripes. A stripe-shaped neck portion 18 is provided between the first body region 12-1 and the second body region 12-2. Also in this example, the separation electrode 60 is disposed above the neck portion 18. The separation electrode 60 of this example has the same planar shape as the neck portion 18. For example, the separation electrode 60 has a striped planar shape. The first body region 12-1 and the second body region 12-2 are connected to the third body region 12-3. The first body region 12-1 and the second body region 12-2 are surrounded by the third body region 12-3, and a pressure-resistant structure 90 is provided on the outer periphery of the third body region 12-3. You may arrange. For example, a guard ring, a field plate, or the like is disposed in the pressure-resistant structure 90.

  This example is an example of a plan view of the semiconductor device 100 taken along the line AA ′, but may be applied to the semiconductor devices 200, 300, 400, and 500. Although the planar shapes of the first body region 12-1 and the second body region 12-2 in this example are stripes, the planar shapes of the first body region 12-1 and the second body region 12-2 are used. May be latticed. Further, the first body region 12-1 and the second body region 12-2 in this example are connected to the third body region 12-3, but the first body region 12-1 and the second body region 12-2 are connected to the third body region 12-3. The body region 12-2 may not be connected to the third body region 12-3. The semiconductor device 100 may not have the third body region 12-3.

(Seventh embodiment)
FIG. 17 is another example of a plan view in a plane parallel to the AA ′ cross section of the semiconductor device 100. In the present example, the plurality of first body regions 12-1 are discretely arranged along the X-axis direction and the Z-axis direction. Similarly, the plurality of second body regions 12-2 are discretely arranged along the X-axis direction and the Z-axis direction. In addition, the first body region 12-1 and the second body region 12-2 are alternately arranged in each of the X-axis direction and the Z-axis direction.

  The neck portion 18 of this example is formed around each of the first body regions 12-1 and each of the second body regions 12-2. That is, the planar shape of the neck portion 18 is a lattice shape.

  The positions in the Z-axis direction of the first body region 12-1 and the second body region 12-2 that are adjacent in the X-axis direction may be the same or different. Further, the positions in the X-axis direction of the first body region 12-1 and the second body region 12-2 adjacent in the Z-axis direction may be the same or different. In the example of FIG. 17, each first body region 12-1 is disposed at an intermediate position in the Z-axis direction between two second body regions 12-2 adjacent in the X-axis direction. In addition, each first body region 12-1 is disposed at an intermediate position in the X-axis direction between two second body regions 12-2 adjacent in the Z-axis direction.

  The third body region 12-3 is disposed so as to surround the plurality of first body regions 12-1 and the plurality of second body regions 12-2. Third body region 12-3 may be separated from first body region 12-1 and second body region 12-2. A pressure-resistant structure 90 may be arranged on the outer periphery of the third body region 12-3. The semiconductor device 100 may not have the third body region 12-3.

  Also in this example, the separation electrode 60 is disposed above the neck portion 18. The separation electrode 60 of this example has the same planar shape as the neck portion 18. For example, the separation electrode 60 may have a lattice-like planar shape surrounding each first body region 12-1 and each second body region 12-2. The structures of the gate electrode 30, the gate connection portion 62, and the like are the same as any of the semiconductor devices 100, 200, 300, 400, and 500.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

  The order of execution of each process in the methods shown in the claims, the description, and the drawings is not clearly indicated as “before”, “prior”, etc., and the output of the previous process is not specified. It should be noted that they can be implemented in any order unless used in later processing. Regarding the operation flow in the claims, the description, and the drawings, even if it is described using “first”, “next”, etc. for convenience, it means that it is essential to carry out in this order. It is not a thing.

DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate, 12 ... Body region, 14 ... Source region, 16 ... Drift region, 18 ... Neck part, 20 ... Middle region, 22 ... Drain region, 24 ... Drain electrode, 26 ... Source electrode, 27 ... Gate insulating film, 28 ... Interlayer insulating film, 29 ... Insulating film, 30 ... Gate electrode, 32 ... Protrusion, 34 ... tip, 36 ... end, 38 ... end, 60 ... separation electrode, 61 ... end, 62 ... gate connection, 64 ... gap, 66 ... ..Opening portion 68... Source connection portion 70... Opening portion 72 .. Extension portion 74 .. Insulating film 75 .. Insulating film 76 .. Insulating film 77. ..Conductive layer, 78... Conductive layer, 80... Conductive layer, 90 .. withstand voltage structure, 100, 200, 300, 400 500 ... semiconductor device

Claims (14)

A semiconductor substrate of a first conductivity type;
A first body region and a second body region having a second conductivity type and provided on an upper surface side of the semiconductor substrate;
A neck portion of the first conductivity type provided between the first body region and the second body region;
A first source region having the first conductivity type and formed in the first body region; and a second source region formed in the second body region;
A first gate electrode opposed to the first body region between the first source region and the neck portion; and the second body between the second source region and the neck portion. A second gate electrode facing the region;
A semiconductor device comprising: an isolation electrode provided opposite to the neck portion and provided separately from the first gate electrode and the second gate electrode. A source electrode formed above the upper surface of the semiconductor substrate;
The semiconductor device according to claim 1, wherein the separation electrode is electrically connected to the source electrode. The semiconductor device according to claim 2, further comprising a gate connection portion that is formed above the isolation electrode and electrically connects the first gate electrode and the second gate electrode. The semiconductor device according to claim 3, wherein an opening for electrically connecting the source electrode and the separation electrode is formed in the gate connection portion. The separation electrode has a first extension formed to extend upward from the first gate electrode so as to cover a gap between the separation electrode and the first gate electrode. A semiconductor device according to 1. The separation electrode further includes a second extension formed to extend upward from the second gate electrode so as to cover a gap between the separation electrode and the second gate electrode. 5. The semiconductor device according to 5. The first extension is formed to cover the first gate electrode,
The semiconductor device according to claim 6, wherein the second extension portion is formed to cover the second gate electrode. The semiconductor device according to claim 7, wherein the source electrode is in contact with the first extension portion and the second extension portion. On the upper surface of the semiconductor substrate, an end of the first body region and an end of the first gate electrode are provided at opposing positions, the end of the second body region, and the first The semiconductor device according to claim 1, wherein an end portion of the two gate electrodes is provided at a position facing the gate electrode. The semiconductor device according to claim 9, wherein the first body region and the second body region have a protruding portion that protrudes closer to the neck portion than an end portion of the upper surface of the semiconductor substrate. The semiconductor device according to claim 10, wherein an end portion of the separation electrode is disposed closer to a gate electrode than a tip end of the protruding portion. The semiconductor device has a second conductivity type, and further includes a third body region provided on the upper surface side of the semiconductor substrate,
The semiconductor device according to claim 1, wherein the first body region and the second body region are connected to a third body region. A method for manufacturing a semiconductor device, comprising:
Impurities of the second conductivity type are implanted into the upper surface side of the first conductivity type semiconductor substrate, so that the first body region and the second body region of the second conductivity type, and the first body region And forming a neck portion of the first conductivity type provided between the second body regions,
Forming a first source region of a first conductivity type in the first body region, and a second source region of a first conductivity type in the second body region;
Forming an insulating film on the upper surface of the semiconductor substrate;
A first gate electrode facing the first body region between the first source region and the neck portion, and the second source region and the neck portion on the upper surface side of the insulating film. Forming a second gate electrode opposed to the second body region therebetween, and a separation electrode opposed to the neck portion and separated from the first gate electrode and the second gate electrode. A manufacturing method provided. In the step of forming the first gate electrode and the second gate electrode, an end portion of each gate electrode is formed inside the body region rather than an end portion of each body region on the upper surface of the semiconductor substrate. And
After forming the first gate electrode, the second gate electrode, and the separation electrode, the upper surface of the semiconductor substrate is oxidized to form the insulating film that is not covered with the gate electrode and the separation electrode. The manufacturing method according to claim 13, further comprising the step of absorbing impurities in the body region.

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