JP2017228644A - Wiring board, composite wiring board including the wiring board, and method for their manufacturing - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring board, in mounting an electronic component to form an electronic device, capable of preventing the thickness of the entire electronic device from being badly balanced, a composite wiring board including the wiring board, and methods for their manufacturing.SOLUTION: In a substrate 10 for a device of the present invention, a first substrate 11 and a second substrate 20 are joined. The first substrate 11 has two metal portions 18, 18 which connect between front and rear conductive circuit layers 13, 13, which are exposed to both front and rear surfaces, and which are electrically connected via a common pat 17A that is provided to the conductive circuit layer 13 on a B surface 12B side. The two metal portions 18, 18 are formed of a base material of welding.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a wiring board in which conductive layers and insulating layers are alternately laminated, a composite wiring board having the wiring board, and a method for manufacturing the same.

  As this type of wiring board, one in which an electronic component is mounted on a conductive layer on the outermost insulating resin layer is known (for example, see Patent Document 1).

Japanese Unexamined Patent Publication No. 2006-015433 (paragraph [0017], FIG. 12)

  In the above-described wiring board, when a plurality of electronic components having different sizes are mounted to form an electronic device, the balance of the thickness of the entire electronic device may be deteriorated.

  The wiring board according to the present invention is a wiring board in which a conductive layer having a plating layer and an insulating layer are alternately laminated, and at least a part thereof is formed integrally with the plating layer of the conductive layer. Connecting the outermost conductive layers on the front and back sides, and being exposed on both sides of the front and back sides, and having two metal portions that are electrically connected to each other via at least one conductive layer, the two metal portions being It consists of a base material for welding.

1 is a side sectional view of a device substrate according to a first embodiment of the present invention. (A) Side sectional view of the second substrate, (B) Side sectional view of the first substrate Cross section of common pad Side sectional view showing the manufacturing process of device substrate Side sectional view showing the manufacturing process of device substrate Side sectional view showing the manufacturing process of device substrate Side sectional view showing the manufacturing process of device substrate Side sectional view showing the manufacturing process of device substrate Side sectional view showing the manufacturing process of device substrate Side sectional view showing the manufacturing process of device substrate Side sectional view showing the manufacturing process of device substrate Side sectional view showing the manufacturing process of device substrate Side cross-sectional view showing usage example of device substrate Perspective view showing usage example of device substrate Side sectional view of the device substrate according to the second embodiment. Side sectional view of a device substrate according to a third embodiment.

[First Embodiment]
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 shows a device substrate 10 (corresponding to the “composite wiring board” of the present invention) on which a plurality of electronic components 90 and 91 are mounted and used as an electronic device 100 (see FIG. 13). ing. The device substrate 10 of this embodiment is formed by bonding a first substrate 11 (corresponding to a “wiring board” of the present invention) and a second substrate 20.

  As shown in FIG. 2B, the first substrate 11 has an insulating substrate 12 (corresponding to “insulating layer” and “first central insulating layer” of the present invention) in the center in the plate thickness direction. . The insulating substrate 12 is made of, for example, a reinforcing material such as epoxy resin and glass cloth. The conductive circuit layers 13 and 13 (the “conductive layer” of the present invention) are formed on the F surface 12F which is the front side surface and the B surface 12B which is the back side surface. Respectively). The conductive circuit layers 13 and 13 have copper foil layers 13A and 13A on the insulating substrate 12 and plating layers 13B and 13B thereon.

  A plurality of conductive through holes 14 are formed in the insulating substrate 12. The conductive through-holes 14 communicated with each other at the small-diameter side end portions of the tapered holes 14A and 14A, which are perforated from both the F surface 12F and the B surface 12B of the insulating substrate 12 and gradually reduced in diameter toward the back side. Has an intermediate constricted shape. The through hole 14 for conduction is filled with plating to form a through-hole conductor 15, and the through-hole conductor 15 connects between the conductive circuit layer 13 on the F surface 12 F and the conductive circuit layer 13 on the B surface 12 B. ing. The through-hole conductor 15 is formed integrally with the plating layers 13B and 13B of the conductive circuit layers 13 and 13. The shape of the conductive through hole 14 may be a straight cylindrical shape with no intermediate portion, or may be a tapered shape having a diameter reduced from one surface to the other surface.

  Solder resist layers 16 and 16 are laminated on the conductive circuit layers 13 and 13 on the front and back sides of the insulating substrate 12. A plurality of pad holes 16H and 16H are formed in the solder resist layers 16 and 16, and portions of the conductive circuit layers 13 and 13 exposed from the pad holes 16H and 16H are pads 17 and 17, respectively.

  Further, a receiving portion 19 formed by removing the solder resist layer 16 is formed in a portion overlapping the second substrate 20 in the thickness direction on the F surface 11F side of the first substrate 11. A portion of the conductive circuit layer 13 exposed from the receiving portion 19 is also a pad 17.

  As shown in FIG. 2A, the second substrate 20 has a build-up layer 30 laminated on both sides of the core substrate 21 (corresponding to “insulating layer” and “second central insulating layer” of the present invention). Being done. Similar to the insulating substrate 12 in the first substrate 11, the core substrate 21 is made of an insulating member, and the conductive circuit layers 23 and 23 are formed on the F surface 21 </ b> F that is the front side surface and the B surface 21 </ b> B that is the back side surface. (Corresponding to the “conductive layer” of the present invention) is formed.

  The core substrate 21 is also formed with a plurality of conductive through holes 24. The through-hole 24 for conduction made the small-diameter side end portions of the tapered holes 24A and 24A, which are perforated from both the F surface 21F and the B surface 21B of the core substrate 21 and gradually reduced in diameter toward the back side, communicate with each other. Has an intermediate constricted shape. The through hole 24 for conduction is filled with plating to form a through-hole conductor 25, and the through-hole conductor 25 forms a gap between the conductive circuit layer 23 on the F surface 21 F and the conductive circuit layer 23 on the B surface 21 B. It is connected.

  Both the build-up layer 30 on the F surface 21F side and the build-up layer 30 on the B surface 21B side of the core substrate 21 are formed from the core substrate 21 side with an insulating resin layer 31 (corresponding to the “insulating layer” of the present invention). A conductive layer 32 is laminated.

  The insulating resin layer 31 is made of, for example, a prepreg (a B-stage resin sheet obtained by impregnating a core material with a resin), and the insulating resin layer 31 has a plurality of via holes 31H. The via hole 31H has a tapered shape with a diameter gradually reduced toward the core substrate 21, and the via hole 31H is filled with plating to form a plurality of via conductors 31D. The conductive circuit layer 23 and the conductive layer 32 are connected by the via conductor 31 </ b> D of the insulating resin layer 31. The conductive circuit layer 23 and the conductive layer 32 include copper foil layers 23A and 32A on the insulating substrate 12 or the insulating resin layer 31, and plating layers 23B and 32B thereon.

  Solder resist layers 33 and 33 are laminated on the conductive layers 32 and 32 of the build-up layers 30 and 30 on the front and back sides of the core substrate 21. A plurality of pad holes 33H, 33H are formed in the solder resist layers 33, 33, and portions of the conductive layers 32, 32 exposed from the pad holes 33H, 33H are pads 34, 34.

  In the present embodiment, the “pad” refers to a portion for connecting between layers, a portion for connecting to another component or another substrate in the conductive layer.

  Now, since the first substrate 11 and the second substrate 20 are bonded to each other, they have the following configuration. That is, as shown in FIG. 2B, in the first substrate 11, two through-hole conductors 15 are arranged in parallel within, for example, 0.2 to 2 mm. Then, common pads 17A and 17A to which the two through-hole conductors 15 are commonly connected are provided on the conductive circuit layer 13 on the F surface 12F side and the conductive circuit layer 13 on the B surface 12B side. The planar shape of the common pad 17A may be a quadrangular shape as shown in FIG. 3A, or may be an array shape as shown in FIGS. 3B and 3C. However, as shown in FIG. 3D, an oval shape may be used.

  In addition, the metal parts 18 and 18 of this invention are comprised from these through-hole conductors 15 and 15 and the part located on the through-hole conductors 15 and 15 among the common pads 17A and 17A. Further, as shown in FIG. 3, a plurality of common pads 17 </ b> A are arranged side by side in one first substrate 11. At this time, as shown in FIG. 3 (A), the metal portions 18 and 18 connected by the common pads 17A may be arranged so as to be arranged side by side, or FIGS. 3 (B) to (D). As shown in FIG. In the latter case, the diameter of the metal portions 18 and 18 can be increased to increase the joint portion with the second substrate 20.

  As shown in FIG. 2A, the second substrate 20 has a bonding pad in which the common pad 17A on the F surface 12F side of the first substrate 11 can come into contact with the conductive layer 32 on the B surface 21B side. 34B (corresponding to the “third connection portion” of the present invention) is provided.

  As shown in FIG. 1, the two metal portions 18 and 18 of the first substrate 11 are directly resistance-welded to the bonding pads 34 </ b> B of the second substrate 20, so that the first substrate 11 and the second substrate 20. And are joined. That is, the two metal portions 18 and 18 are resistance welding base materials. Further, the first substrate 11 corresponds to the first mounting portion 38 of the present invention on which the electronic component 90 (corresponding to the “first component” of the present invention) on which the pad 17 on the F surface 11F side of the first substrate 11 is relatively large is mounted. The pad 34 on the F surface 20F side of the second substrate 20 corresponds to the second mounting portion 39 of the present invention on which an electronic component 91 (corresponding to the “second component” of the present invention) is mounted.

  Next, a method for manufacturing the device substrate 10 of the present embodiment will be described. First, the first substrate 11 is manufactured as follows.

  (1) As shown to FIG. 4 (A), what laminated | stacked copper foil 12C on both the front and back of the insulated substrate 12 is prepared.

  (2) As shown in FIG. 4B, a tapered hole 14A for forming a conductive through hole 14 (see FIG. 2B) by irradiating the insulating substrate 12 with, for example, CO2 laser from the F surface 12F side. Is perforated.

  (3) As shown in FIG. 4C, CO2 laser is irradiated to a position directly behind the tapered hole 14A on the F surface 12F side of the B surface 12B of the insulating substrate 12 to form the tapered hole 14A. The conductive through-hole 14 is formed from the tapered holes 14A and 14A.

  (4) An electroless plating process is performed, and an electroless plating film (not shown) is formed on the copper foil 12C and in the conductive through hole 14.

  (5) An electrolytic plating process is performed, and as shown in FIG. 4D, the electroplating is filled in the conductive through-holes 14 to form the through-hole conductors 15 and the electroless on the copper foil 12C. An electrolytic plating film 40 is formed on the plating film. Hereinafter, the copper foil 12C, the electroless plating film, and the electrolytic plating film 40 are collectively referred to as a conductor film 41.

  (6) As shown in FIG. 5A, an etching resist 42 having a predetermined pattern is formed on the conductor film 41.

  (7) Etching is performed, and the portion of the conductor film 41 exposed from the etching resist 42 is removed as shown in FIG.

  (8) The etching resist 42 is peeled off, and the conductive circuit layer 13 is formed by the remaining conductor film 41 as shown in FIG. Thereby, the conductive circuit layers 13 on the front and back sides of the insulating substrate 12 are connected by the through-hole conductor 15. In addition, the plating layer 13B mentioned above is comprised from the part left from the electroless plating film | membrane and the electrolytic plating film | membrane 40 among the conductive circuit layers 13. FIG. This plating layer 13B is integrated with the through-hole conductor 15.

  (9) As shown in FIG. 6A, solder resist layers 16 and 16 are laminated on the conductive circuit layers 13 and 13 on the front and back sides of the insulating substrate 12. At that time, the space between the conductive circuit layers 13 and 13 is filled with the solder resist layers 16 and 16.

  (10) As shown in FIG. 6B, tapered pad holes 16H and 16H and receiving portions 19 are formed at predetermined positions of the solder resist layers 16 and 16 on the front and back of the insulating substrate 12, and the insulating substrate 12 Of the front and back conductive circuit layers 13, 13, portions exposed from the pad holes 16 </ b> H, 16 </ b> H and the receiving portion 19 become the pads 17.

  (11) On the pad 17, a nickel layer, a palladium layer, and a gold layer are laminated in this order to form a metal film (not shown). Thus, the first substrate 11 shown in FIG. 2B is completed. Note that surface treatment with OSP (preflux) may be performed instead of the metal film.

  Next, the second substrate 20 is manufactured as follows.

  (1) As shown to FIG. 7 (A), what laminated | stacked copper foil 21C on both the front and back of the core board | substrate 21 is prepared.

  (2) As shown in FIG. 7B, the core substrate 21 is irradiated with, for example, a CO 2 laser from the F surface 21F side to form a tapered hole 24A for forming a conductive through hole 24 (see FIG. 1). The

  (3) As shown in FIG. 7C, CO2 laser is irradiated to a position directly behind the taper hole 24A on the F surface 21F side of the B surface 21B of the core substrate 21 to drill the taper hole 24A. The conductive through hole 24 is formed from the tapered holes 24A and 24A.

  (4) An electroless plating process is performed, and an electroless plating film (not shown) is formed on the copper foil 21 </ b> C and in the conductive through hole 24.

  (5) An electrolytic plating process is performed, and as shown in FIG. 7D, the electroplating is filled in the conductive through holes 24 to form the through-hole conductors 25, and the electroless on the copper foil 12C. An electrolytic plating film 45 is formed on the plating film. Hereinafter, the copper foil 21 </ b> C, the electroless plating film, and the electrolytic plating film 45 are collectively referred to as a conductor film 46.

  (6) As shown in FIG. 8A, an etching resist 47 having a predetermined pattern is formed on the conductor film 46.

  (7) Etching is performed, and the portion of the conductor film 46 exposed from the etching resist 47 is removed as shown in FIG.

  (8) The etching resist 47 is peeled off, and the conductive circuit layer 23 is formed by the remaining conductor film 46 as shown in FIG. 8C. As a result, the conductive circuit layers 23 on the front and back sides of the core substrate 21 are connected by the through-hole conductors 25. In addition, the plating layer 23 </ b> B described above is configured from a portion left of the electroless plating film and the electrolytic plating film 45 in the conductive circuit layer 23.

  (9) As shown in FIG. 9A, the prepreg as the insulating resin layer 31 and the copper foil 50 are laminated on the conductive circuit layers 23, 23 on the front and back of the core substrate 21, and then heated and pressed. . At that time, the space between the conductive circuit layers 23 and 23 is filled with the prepreg.

  (10) As shown in FIG. 9B, a plurality of via holes 31H, 31H are formed by irradiating the insulating resin layers 31, 31 on both sides of the core substrate 21 formed by the prepreg with CO2 laser. Is done.

  (11) An electroless plating process is performed, and an electroless plating film (not shown) is formed on the insulating resin layers 31 and 31 and in the via holes 31H and 31H.

  (12) An electrolytic plating process is performed, and as shown in FIG. 9C, the electrolytic plating is filled in the via hole 31H to form the via conductor 31D, and on the electroless plating film on the copper foil 50 An electrolytic plating film 51 is formed. Hereinafter, the copper foil 50, the electroless plating film, and the electrolytic plating film 51 are collectively referred to as a conductor film 52.

  (13) As shown in FIG. 10A, an etching resist 53 having a predetermined pattern is formed on the conductor film 52.

  (14) Etching is performed, and the portion of the conductor film 52 exposed from the etching resist 53 is removed as shown in FIG.

  (15) The etching resist 53 is peeled off, and the conductive layer 32 is formed by the remaining conductor film 52 as shown in FIG. As a result, the conductive layer 32 and the conductive circuit layer 23 are connected by the via conductor 31D. In addition, the plating layer 32B mentioned above is comprised from the part left from the electroless plating film | membrane and the electrolytic plating film | membrane 51 among the conductive layers 32. FIG.

  (16) As shown in FIG. 11A, solder resist layers 33 and 33 are laminated on the conductive layers 32 on the front and back sides of the core substrate 21.

  (17) As shown in FIG. 11B, tapered pad holes 33H and 33H are formed at predetermined positions on the solder resist layers 33 and 33 on the front and back sides of the core substrate 21, and the respective conductive surfaces on the front and back sides of the core substrate 21 are electrically connected. A portion of the layer 32 exposed from the pad hole 33 </ b> H becomes a pad 34.

  (18) On the pad 34, a nickel layer, a palladium layer, and a gold layer are laminated in this order to form a metal film (not shown). Thus, the second substrate 20 shown in FIG. 2A is completed. Note that surface treatment with OSP (preflux) may be performed instead of the metal film.

  The first substrate 11 and the second substrate 20 are bonded as follows.

  (1) The second substrate 20 is placed with the F surface 20F facing down.

  (2) On the B surface 20B of the second substrate 20, the common pad 17A on the F surface 12F side of the first substrate 11 (that is, the surface on the F surface 12F side of the metal portion 18) is a bonding pad for the second substrate 20. The first substrate 11 is placed so as to be in contact with 34B.

  (3) As shown in FIG. 12, among the common pads 17A of the first substrate 11, electrodes 95 are respectively formed on portions located on the through-hole conductors 15 and 15 (that is, the surface on the B surface 12B side of the metal portion 18). 96 (corresponding to the “welding tool” of the present invention).

  (4) In the state where the first substrate 11 and the second substrate 20 are pressurized with each other, a current is passed between the electrodes 95 and 96, so that the F surface 12F side of the metal portion 18 of the first substrate 11 and the first substrate 11 The bonding pads 34B of the two substrates 20 are resistance welded, and the first substrate 11 and the second substrate 20 are bonded. Thus, the device substrate 10 is completed. FIG. 12 shows the current flow at this time. The resistance welding method in which a plurality of electrodes are arranged on one member side in this way is called a series method.

  This completes the description of the structure and manufacturing method of the device substrate 10 of the present embodiment. Next, usage examples and operational effects of the device substrate 10 will be described. As shown in FIGS. 13 and 14, the device substrate 10 of this embodiment has solder bumps 80 on the first mounting portion 38 on the first substrate 11 and the second mounting portion 39 on the second substrate 20. Once formed, electronic components 90 and 91 such as a CPU are mounted thereon and soldered to be used as the electronic device 100.

  Here, electronic components having different sizes may be mounted on the device substrate. In this embodiment, the device substrate 10 is manufactured by joining two substrates 11 and 20 in the thickness direction. Since the height of the first mounting portion 38 on the first substrate 11 is different from the height of the second mounting portion 39 on the second substrate 20, the relatively large electronic component 90 is mounted on the first substrate 11. By mounting the relatively small electronic component 91 on the second mounting portion 39 of the second substrate 20 by mounting on the portion 38, the thickness balance of the entire electronic device 100 can be improved, and the entire electronic device 100 can be improved. The thickness can be reduced.

  In addition, since the first substrate 11 and the second substrate 20 are directly joined by resistance welding, a connection connector or the like becomes unnecessary, and the number of components can be reduced. In addition, the thickness of the device substrate 10 as a whole can be made smaller than a configuration in which connection is made by a connector or the like.

  By the way, in the manufacture of a device substrate, generally, a plurality of products are created simultaneously in one collective substrate, and the collective substrate is cut into each product region, thereby being divided into a plurality of products. Here, when the planar shape of the device substrate is complicated, it is conceivable that a blank portion in one aggregate substrate becomes large and the number of products to be obtained decreases.

  On the other hand, in the present embodiment, the first substrate 11 and the second substrate 20 are separately formed, and the device substrate 10 is formed by bonding them, so that the planar shape of the device substrate 10 is complicated. Even so, the planar shape of each of the substrates 11 and 20 created in the collective substrate can be simplified, and the number of products can be increased.

  Moreover, since the wiring pattern of each board | substrate 11 and 20 is not restricted except a welding part, the effect mentioned above can be acquired, suppressing the influence which affects pattern design.

  In addition, since the first substrate 11 includes the two metal portions 18 and 18 and the common pads 17A and 17A, the first substrate 11 can be directly bonded to the second substrate 20, and the device substrate 10 described above can be manufactured. Is possible. Moreover, in this embodiment, since the 1st board | substrate 11 becomes a structure which has a conductive layer (conductive circuit layer 13) one layer each on the front and back of the insulated substrate 12, rather than what has multiple layers each. Formation of the metal part 18 is facilitated, and resistance welding is also facilitated.

[Second Embodiment]
The present embodiment is different from the first embodiment in the connection between the two through-hole conductors 15 and the conductive circuit layers 13 on the front and back sides. That is, in the first substrate 11 of the present embodiment, as shown in FIG. 15, a common pad 17A (in the present invention) in which two through-hole conductors 15 are commonly connected to the conductive circuit layer 13 on the B surface 12B side. The two independent pads 17B and 17B are connected to the conductive circuit layer 13 on the F-plane 12F side, and the two through-hole conductors 15 are independently connected to each other. (Corresponding to the “second connecting portion” of the present invention).

  The two independent pads 17B and 17B of the first substrate 11 are directly resistance-welded to the bonding pads 34B of the second substrate 20, whereby the first substrate 11 and the second substrate 20 are bonded.

[Third Embodiment]
In the first and second embodiments, the first substrate 11 has one conductive layer (conductive circuit layer 13) laminated on the front and back of the insulating substrate 12. However, in the present embodiment, FIG. As shown in FIG. 2, the two layers are formed (conductive circuit layer 13 and conductive layer 11X).

  Specifically, the insulating resin layer 11Z and the conductive layer 11X are laminated on the front and back surfaces of the insulating substrate 12 from above the conductive circuit layer 13. Two through-hole conductors 15 penetrating the insulating substrate 12 are connected via the front and back conductive circuit layers 13 and 13, and the conductive circuit layer 13 and the conductive layer 11 </ b> X are connected to the through-hole conductors 15. A via conductor 11D is formed. The via pads 11D and 11D on the two through-hole conductors 15 are independently connected to the conductive layer 11X on the F surface 12F side and the conductive layer 11X on the B surface 12B side, respectively. , 17B are provided.

  In the present embodiment, the metal portion 18 is formed from the through-hole conductor 15 and the via conductors 11D and 11D and the upper portions of the independent pads 17B and 17B. In the present embodiment, the conductive layer connecting the two metal portions 18 is the inner one, but it may be the outermost one. Alternatively, a configuration in which three or more conductive layers are stacked on the front and back of the insulating substrate 12 may be employed.

[Other Embodiments]
The present invention is not limited to the above-described embodiment. For example, the embodiments described below are also included in the technical scope of the present invention, and various modifications are possible within the scope of the invention other than the following. It can be changed and implemented.

(1) In the above embodiment, a plurality of electronic components are mounted, but one electronic component may be provided. Even in this case, if electronic components are arranged on the first substrate 11, the thickness balance of the entire electronic device 100 can be improved.

(2) In the above embodiment, the solder resist layer 16 is laminated on a portion other than the receiving portion 19 on the F surface 12F side of the first substrate 11, but the solder resist layer is disposed on the F surface 12F side of the first substrate 11. The structure which is not laminated | stacked may be sufficient.

(3) The first substrate 11 may be joined to a heat radiating member (for example, a heat sink, a heat diffusion sheet, etc.) by resistance welding instead of the second substrate 20.

10 Device substrate (composite wiring board)
11 First board (wiring board)
12 Insulating substrate (insulating layer, first central insulating layer)
13 Conductive circuit layer (conductive layer)
13B Plating layer 15 Through-hole conductor 17A Common pad (first connection part)
17B Independent pad (2nd connection part)
18 Metal part 20 Second substrate 21 Core substrate (insulating layer, second central insulating layer)
23 Conductive circuit layer (conductive layer)
31 Insulating resin layer (insulating layer)
32 Conductive layer 34B Bonding pad (third connection part)
38 1st mounting part 39 2nd mounting part 95,96 Electrode (welding tool)
90, 91 Electronic parts (first part, second part)
100 electronic devices

Claims (14)

A wiring board in which conductive layers having plating layers and insulating layers are alternately laminated,
At least a portion is formed integrally with the plating layer of the conductive layer, connects the outermost conductive layers on the front and back sides, and is exposed on both sides of the front and back sides, and through at least one conductive layer Having two metal parts conducting to each other,
The two metal parts are made of a welding base material. The wiring board according to claim 1,
The two metal parts are made of a resistance welding base material. The wiring board according to claim 1 or 2,
The outermost conductive layer on one side of the front and back is provided with a first connection part in which two metal parts are connected in common and includes one surface of the two metal parts,
The second outermost conductive layer on the front and back sides is provided with two second connection portions to which the two metal portions are separately connected and each includes the other surface of the metal portion. A first substrate as a wiring board according to any one of claims 1 to 3,
A conductive layer and an insulating layer are alternately laminated, and the third connection portion in which the two metal portions of the first substrate are commonly bonded to the outermost conductive layer on one of the front and back sides. And a second wiring board. A first substrate as a wiring board according to claim 3;
A third connection portion, in which conductive layers and insulating layers are alternately stacked, and the two second connection portions of the first substrate are commonly bonded to the outermost conductive layer on the front and back sides. A composite wiring board comprising: a second substrate having: The composite wiring board according to claim 4 or 5,
The first substrate has one conductive layer on each side of the first central insulating layer as the insulating layer, while the second substrate has the conductive layer on the front and back of the second central insulating layer as the insulating layer. A plurality of layers are provided. A composite wiring board according to any one of claims 4 to 6,
A first mounting portion for mounting a first component is provided on the outermost conductive layer on the second substrate side of the first substrate,
A second component for mounting a second component smaller in the plate thickness direction of the first substrate than the first component on the outermost conductive layer on the opposite side to the first substrate side of the second substrate. A mounting part is provided. A method for manufacturing a wiring board in which conductive layers having plating layers and insulating layers are alternately laminated,
Forming two metal portions that connect the outermost conductive layers on the front and back sides and that are exposed on both sides of the front and back sides and that are electrically connected to each other through at least one conductive layer;
Forming the metal part integrally with the plating layer of the conductive layer;
The two metal parts are made of a welding base material. It is a manufacturing method of the wiring board according to claim 8,
Two said metal parts are comprised from the base material of resistance welding. A method for manufacturing a wiring board according to any one of claims 8 to 9,
The first outermost conductive layer on one side of the front and back is provided with a first connection part in which the two metal parts are connected in common and includes one surface of the two metal parts,
Two second connection portions are provided on the outermost conductive layer on the other side of the front and back sides, and the two metal portions are separately connected to each other and each include the other surface of the metal portion. The 1st board | substrate as a wiring board manufactured by the manufacturing method of the wiring board of any one of Claims 8 thru | or 10, The 2nd board | substrate by which an electroconductive layer and an insulating layer are laminated | stacked alternately, , A method of manufacturing a composite wiring board formed by bonding,
Forming a third connection portion in which the two metal portions of the first substrate can be contacted in common with the outermost conductive layer on one of the front and back sides of the second substrate;
Stacking the first substrate on the second substrate such that the third connection portion and the two metal portions are in contact with each other;
A welding tool is brought into contact with the surface of the two metal portions opposite to the third connection portion, and the first substrate and the second substrate are joined by resistance welding. A composite wiring board formed by bonding a first substrate as a wiring board manufactured by the method for manufacturing a wiring board according to claim 10 and a second substrate in which conductive layers and insulating layers are alternately stacked. A manufacturing method of
Forming, on the outermost conductive layer on one of the front and back surfaces of the second substrate, a third connection portion on which the two second connection portions of the first substrate can come into contact in common;
Stacking the first substrate on the second substrate so that the third connection portion and the two second connection portions are in contact with each other;
A welding tool is brought into contact with two metal portions of the first connection portion of the first substrate, and the first substrate and the second substrate are joined by resistance welding. A method for manufacturing a composite wiring board according to claim 11 or 12,
On the first substrate, the conductive layers are formed one by one on the front and back of the first central insulating layer as the insulating layer, while on the front and back of the second central insulating layer as the insulating layer on the second substrate. A plurality of the conductive layers are formed. A method of manufacturing a composite wiring board according to any one of claims 11 to 13,
A first mounting portion for mounting a first component is provided on the outermost conductive layer on the second substrate side of the first substrate,
A second component for mounting a second component smaller in the plate thickness direction of the first substrate than the first component on the outermost conductive layer on the opposite side to the first substrate side of the second substrate. A mounting part is provided.

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