JP2017168598A - Semiconductor memory device and manufacturing method thereof - Google Patents

Abstract

A semiconductor memory device and a method for manufacturing the same are provided. According to an embodiment, a semiconductor memory device includes a first wiring, a first cross wiring, a first resistance change unit, and a first insulating unit. The first wiring includes a first extending portion extending in the first direction and a first protruding portion protruding in the second direction intersecting the first direction. The first cross wiring extends in a third direction that intersects the first direction and the second direction. At least a portion of the first resistance change portion is provided between at least a portion of the first cross wiring and the first protruding portion. At least a portion of the first insulating portion is provided between a portion of the first extension portion and at least a portion of the first cross wiring in the second direction. [Selection] Figure 1

Description

  Embodiments described herein relate generally to a semiconductor memory device and a method for manufacturing the same.

  There is a memory device using a resistance change type memory cell such as an ion memory. In such a memory device, memory cells are arranged three-dimensionally. In a memory device, the reliability of the memory operation may be lowered due to the influence between adjacent memory cells.

JP 2011-129737 A

  Embodiments of the present invention provide a semiconductor memory device that can improve the reliability of a memory operation and a method of manufacturing the same.

  According to the embodiment of the present invention, the semiconductor memory device includes a first wiring, a first cross wiring, a first resistance change unit, and a first insulating unit. The first wiring includes a first extending portion that extends in a first direction and a first protruding portion that protrudes in a second direction that intersects the first direction. The first cross wiring extends in a third direction that intersects the first direction and the second direction. At least a portion of the first resistance change portion is provided between at least a portion of the first cross wiring and the first protruding portion. At least a part of the first insulating portion is provided between a part of the first extension part and the at least part of the first cross wiring in the second direction.

FIG. 1A and FIG. 1B are schematic perspective views illustrating the semiconductor memory device according to the first embodiment. 1 is a schematic perspective view illustrating a semiconductor memory device according to a first embodiment. 1 is a schematic perspective view illustrating a semiconductor memory device according to a first embodiment. 1 is a flowchart illustrating a method for manufacturing a semiconductor memory device according to a first embodiment. FIG. 3 is a schematic perspective view in order of the processes, illustrating the method for manufacturing the semiconductor memory device according to the first embodiment. FIG. 3 is a schematic perspective view in order of the processes, illustrating the method for manufacturing the semiconductor memory device according to the first embodiment. FIG. 3 is a schematic perspective view in order of the processes, illustrating the method for manufacturing the semiconductor memory device according to the first embodiment. FIG. 3 is a schematic perspective view in order of the processes, illustrating the method for manufacturing the semiconductor memory device according to the first embodiment. FIG. 3 is a schematic perspective view in order of the processes, illustrating the method for manufacturing the semiconductor memory device according to the first embodiment. FIG. 3 is a schematic perspective view in order of the processes, illustrating the method for manufacturing the semiconductor memory device according to the first embodiment. FIG. 6 is a schematic perspective view illustrating another semiconductor memory device according to the first embodiment. FIG. 12A and FIG. 12B are schematic perspective views illustrating the semiconductor memory device according to the second embodiment.

Embodiments of the present invention will be described below with reference to the drawings.
The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between the parts, and the like are not necessarily the same as actual ones. Even in the case of representing the same part, the dimensions and ratios may be represented differently depending on the drawings.
In the present specification and drawings, the same elements as those described above with reference to the previous drawings are denoted by the same reference numerals, and detailed description thereof is omitted as appropriate.

(First embodiment)
FIG. 1A and FIG. 1B are schematic perspective views illustrating the semiconductor memory device according to the first embodiment.
As shown in FIG. 1A, the semiconductor memory device 110 according to the present embodiment includes a first wiring 11, a first cross wiring 21, a first resistance change unit 31, and a first insulating unit 41. Including.
In FIG. 1B, the first wiring 11 is extracted and drawn.

  The first wiring 11 includes a first extending portion 11e and a first protruding portion 11p. The first extending portion 11e extends in the first direction D1. The first projecting portion 11p projects in the second direction D2. The second direction D2 intersects the first direction D1.

  The first direction D1 is the Z direction. One direction perpendicular to the Z direction is defined as the X direction. A direction perpendicular to the Z direction and the X direction is taken as a Y direction.

  In this example, the second direction D2 is along the X direction. The second direction D2 is, for example, the −X direction.

  The first cross wiring 21 extends in the third direction D3. The third direction D3 intersects the first direction D1 and the second direction D2. In this example, the third direction D3 is the Y direction.

  At least a part of the first resistance change portion 31 is provided between at least a part of the first cross wiring 21 and the first protruding portion 11p. The first resistance change unit 31 overlaps at least a part of the first cross wiring 21 and the first protruding portion 11p in the first direction D1 (Z direction).

  At least part of the first insulating portion 41 is at least one part of the first extending portion 11e (part 11ea) and the above-mentioned at least one of the first cross wirings 21 in the second direction D2 (in this example, −X direction). Between the two.

  For example, one memory unit (first memory unit MP1) is formed at an intersection between the first intersecting wiring 21 and the first protruding portion 11p.

  As described above, in the semiconductor memory device 110, for example, the first protruding portion 11p protruding in the −X direction is provided in a part of the first extending portion 11e extending in the Z direction. A first cross wiring 21 is provided apart from the first protruding portion 11p in the Z direction. In the first memory unit MP1 formed between the first protruding portion 11p and the first cross wiring 21, the current flows along the Z direction. The first insulating part 41 insulates between the first memory part MP1 and the first extending part 11e.

  In the semiconductor memory device 110, the second cross wiring 22, the second resistance change unit 32, and the second insulating unit 42 are further provided.

  The second cross wiring 22 extends in the third direction D3 (Y direction). The second cross wiring 22 is aligned with the first cross wiring 21 in the first direction D1 (Z direction). At least a part of the second resistance change portion 32 is provided between at least a part of the second cross wiring 22 and the first protruding portion 11p. At least a part of the second insulating part 42 is in the second direction D2 (−X direction), another part of the first extending part 11e (part 11eb), and at least a part of the second cross wiring 22 described above. And between.

  For example, another memory part (second memory part MP2) is formed at the intersection of the second intersecting wiring 22 and the first protruding part 11p.

  For example, the first projecting portion 11p is provided between the first cross wiring 21 and the second cross wiring 22 in the Z direction. A memory portion is provided between each of the two cross wirings and the protruding portion. The two memory portions and the first wiring 11 (first extending portion 11e) are insulated by the first insulating portion 41 and the second insulating portion 42. Leakage on the side surface (for example, the surface along the Z direction) of the memory unit (memory cell) is suppressed by these insulating units. The information stored in the memory unit is held well. In the embodiment, for example, a semiconductor memory device that can improve the reliability of the memory operation can be provided.

  In this example, the first wiring 11 further includes a second extending portion 11f. The second extending portion 11f extends in the first direction D1 (Z direction). The second extending portion 11f is aligned with the first extending portion 11e in the second direction D2 (−X direction). In this example, the second extending portion 11f is connected to the first protruding portion 11p.

  Between the first extending portion 11e and the second extending portion 11f, the first cross wiring 21 and the first resistance change portion 31 are disposed.

  The first insulating portion 41 extends in a region between the second extending portion 11 f and the first cross wiring 21. The first insulating portion 41 insulates between the second extending portion 11 f and the first cross wiring 21.

  In this example, a third cross wiring 23 and a fourth cross wiring 24 are further provided. These cross wirings extend in the third direction D3 (Y direction). The first wiring 11 further includes a second protruding portion 11q. The protruding portion 11q is provided between the third cross wiring 23 and the fourth cross wiring 24 in the Z direction.

  A third resistance change portion 33 is provided between the third cross wiring 23 and the protruding portion 11q. A fourth resistance change portion 34 is provided between the fourth cross wiring 24 and the protruding portion 11q. A third memory portion MP3 is formed at the intersection of the third intersection wiring 23 and the protruding portion 11q. A fourth memory unit MP4 is formed at the intersection of the fourth intersecting wiring 24 and the protruding portion 11q. The first to fourth memory units MP1 to MP4 are arranged in the ZX plane, for example.

  As shown in FIG. 1A, the second wiring 12 and the third wiring 13 are provided. The first to third wirings 11 to 13 are arranged in the Y direction. The second wiring 12 and the third wiring 13 have the same configuration as the first wiring 11. A memory unit is formed at each of the intersections between the first to third wirings 11 to 13 and the first to fourth intersection wirings 21 to 24. In the semiconductor memory device 110, the memory unit is arranged three-dimensionally in the X, Y, and Z directions.

  In the embodiment, the first to third wirings 11 to 13 and the first to fourth cross wirings 21 to 24 include, for example, a metal (for example, tungsten). These wirings and cross wirings may include, for example, a semiconductor containing impurities.

  In this example, the first resistance change unit 31 includes a first metal-containing layer 31M and a first insulating layer 31i. The first metal-containing layer 31M includes, for example, at least one of silver, copper, aluminum, and tellurium. The first insulating layer 31i is aligned with the first metal-containing layer 31M in the first direction D1 (Z direction). In the example shown in FIG. 1A, the first insulating layer 31i is provided between the first metal-containing layer 31M and the first protruding portion 11p. That is, the first metal-containing layer 31M is provided between the first insulating layer 31i and the first cross wiring 21.

  The first insulating layer 31i includes, for example, silicon oxide.

  When a voltage is applied between the first intersecting wiring 21 and the first projecting portion 11p (first wiring 11), for example, ions of metal contained in the first metal-containing layer 11M are generated from the first metal-containing layer 11M. 1 It penetrates into the insulating layer 31i. For example, a filament is formed. The resistance in this state is low. For example, when a reverse polarity voltage is applied, metal ions return to the first metal-containing layer 31M. For example, the filament disappears. The resistance in this state is high.

  For example, in a configuration in which at least a part of the first metal-containing layer 31M is disposed between the first cross wiring 21 and the first insulating layer 31i (see FIG. 1A), two states are formed. The In the first state, the potential of the first cross wiring 21 is higher than the potential of the first wiring 11 (that is, the potential of the first protruding portion 11p). On the other hand, in the second state, the potential of the first cross wiring 21 is lower than the potential of the first wiring 11. The resistance of the first resistance change unit 31 in the first state is lower than the resistance of the first resistance change unit 31 in the second state. In the first state, for example, a filament is formed. In the second state, for example, the filament disappears. The first state is a write state, for example, and the second state is an erase state, for example. In the embodiment, when the potential of the first conductor is higher than the potential of the second conductor, a current flows from the first conductor toward the second conductor. The first metal-containing layer 31M becomes, for example, an ion supply layer. The first insulating layer 31i is, for example, a resistance change layer.

  Similarly, the second resistance change unit 32 includes a second metal-containing layer 32M and a second insulating layer 32i. The second metal-containing layer 32M includes at least one of silver, copper, aluminum, and tellurium. The second insulating layer 32i is aligned with the second metal-containing layer 32M in the Z direction. The second insulating layer 32i includes, for example, silicon oxide. Also in the second resistance change unit 32, the same resistance change as described with respect to the first resistance change unit 31 occurs. The second metal-containing layer 32M becomes, for example, an ion supply layer. The second insulating layer 32i is, for example, a resistance change layer.

  In the embodiment, the configuration of the resistance change unit is arbitrary. For example, the resistance change portion may include a resistance change material such as nickel oxide. The resistance change unit may include a phase change material.

  As shown in FIG. 1A, in this example, the stacking order of the stacked films included in the second resistance change unit 32 is opposite to the stacking order of the stacked films included in the first resistance change unit 31. . In this example, the first projecting portion 11p is disposed between the first cross wiring 21 and the second cross wiring 22. A first insulating layer 31i is disposed between the first cross wiring 21 and the first protruding portion 11p. A first metal-containing layer 31M is disposed between the first cross wiring 21 and the first insulating layer 31i. A second insulating layer 32i is disposed between the second cross wiring 22 and the first protruding portion 11p. A second metal-containing layer 32M is disposed between the second cross wiring 22 and the second insulating layer 32i.

  In this example, the first insulating layer 31i includes a plurality of regions (a first region 31a and a second region 31b). The first region 31 a is provided between the second region 31 b and the first cross wiring 21. The second insulating layer 32i includes a plurality of regions (a third region 32a and a fourth region 32b). The third region 32 a is provided between the fourth region 32 b and the second cross wiring 22. As will be described later, these regions are formed in different steps in the manufacturing process. Once formed, the boundaries between these regions may be unclear.

  As shown in FIG. 1A, in this example, the first insulating portion 41 is continuous with at least a part of the first resistance change portion 31. For example, the second region 31b included in the first insulating layer 31i extends between the first cross wiring 21 and the portion 11ea of the first extending portion 11e. This extended portion is at least a part of the first insulating portion 41.

  Similarly, the second insulating part 42 is continuous with at least a part of the second resistance change part 32. For example, the fourth region 32b included in the second insulating layer 32i extends between the second cross wiring 22 and another portion 11eb of the first extending portion 11e. This extended portion is at least a part of the second insulating portion 42.

  As shown in FIG. 1A, in the semiconductor memory device 110, a first intermediate layer 51a is further provided. The first intermediate layer 51a is provided between the first cross wiring 21 and the first metal-containing layer 31M. The first intermediate layer 51a includes, for example, a nitride of at least one of Ti, Ta, and W. The first intermediate layer 51a functions as a barrier metal, for example.

  Further, in the semiconductor memory device 110, a first side surface intermediate layer 51s is provided. The first side surface intermediate layer 51 s is provided between the first extending portion 11 e (portion 11 ea) and the first insulating portion 41. The first side surface intermediate layer 51s includes, for example, a nitride of at least one of Ti, Ta, and W. The first side surface intermediate layer 51s functions as a barrier metal, for example.

  Similarly, a second intermediate layer 52a may be further provided. The second intermediate layer 52a is provided between the second cross wiring 22 and the second metal-containing layer 32M. The second intermediate layer 52a includes, for example, the same material as that of the first intermediate layer 51a.

  Similarly, the second side surface intermediate layer 52s may be provided. The second side surface intermediate layer 52s is provided between the first extending portion 11e (portion 11eb) and the second insulating portion 42. The second side surface intermediate layer 52s includes, for example, the same material as that of the first side surface intermediate layer 51s.

FIG. 2 is a schematic perspective view illustrating the semiconductor memory device according to the first embodiment.
FIG. 2 is a schematic view illustrating a cross section taken along line A1-A2 of FIG.

  As shown in FIG. 2, an interlayer insulating layer ILL is provided between the first cross wiring 21 and the second cross wiring 22 and between the third cross wiring 23 and the fourth cross wiring 24. In this example, an interlayer insulating layer ILL is disposed between the first resistance change unit 31 and the second resistance change unit 32 and between the third resistance change unit 33 and the fourth resistance change unit 34. The interlayer insulating layer ILL includes, for example, silicon nitride.

  On the other hand, the insulating section 40 is provided between the first cross wiring 21 and the third cross wiring 23 and between the second cross wiring 22 and the fourth cross wiring 24. The insulating unit 40 is also provided between the first resistance change unit 31 and the third resistance change unit 33 and between the second resistance change unit 32 and the fourth resistance change unit 34. For example, the insulating part 40 may be continuous with the first insulating part 41 and the second insulating part 42. The insulating part 40 may include materials used for the first insulating part 41 and the second insulating part 42.

FIG. 3 is a schematic perspective view illustrating the semiconductor memory device according to the first embodiment.
As shown in FIG. 3, the semiconductor memory device 110 may further include a semiconductor substrate 10. The semiconductor substrate 10 has a surface 10a (for example, a main surface). On the surface 10 a of the semiconductor substrate 10, wiring (first to third wirings 11 to 13 etc.), cross wiring (first to fourth crossing wirings 21 to 24 etc.), resistance change portion (first to fourth resistances) Change portions 31 to 34, etc.) and insulating portions (first to fourth insulating portions 41 to 44) are provided. The first direction D1 (Z direction) intersects the surface 10a. The first direction D1 is, for example, perpendicular to the surface 10a. The second direction D2 (−X direction) and the third direction D3 (Y direction) are along the surface 10a. The second direction D2 and the third direction D3 are, for example, substantially parallel to the surface 10a. The semiconductor substrate 10 may include a semiconductor circuit (such as a transistor) electrically connected to the memory unit (not shown).

  As shown in FIG. 3, a layer 10i such as an insulating layer may be provided on the surface 10a. Further, for example, a contact electrode 10c may be provided. The contact electrode 10c extends, for example, in the layer 10i along the Z direction. The contact electrode 10 c electrically connects each of the wirings (first to third wirings 11 to 13 and the like) and the semiconductor circuit of the semiconductor substrate 10. Furthermore, a contact electrode 10d may be provided. The contact electrode 10d extends, for example, in the layer 10i along the Z direction. 10 d of contact electrodes electrically connect each of cross wiring (1st-4th wiring 21-24 etc.) and the semiconductor substrate 10 semiconductor circuit.

  In the semiconductor memory device 110, wirings extending in the Z direction (first to third wirings 11 to 13 and the like) are electrically connected to the semiconductor substrate 10 through the contact electrodes 10c. The connection between the wiring (first to third wirings 11 to 13 and the like) and the semiconductor substrate 10 is simple.

  On the other hand, in the reference example, a plurality of X-direction wirings extending in the X direction, a plurality of Y-direction wirings extending in the Y direction, and a resistance change element portion provided therebetween are provided. A plurality of sets of a plurality of X direction wirings and a plurality of Y direction wirings are stacked in the Z direction. In such a reference example, a contact electrode is provided on each of the X direction wirings having different positions in the Z direction and the Y direction wirings having different positions in the Z direction. For this reason, the connection is complicated. The number of contact electrodes is large, and the area of the contact region where the contact electrodes are formed increases. Conversely, the area ratio of the memory region in which the memory unit is provided is reduced.

  In the semiconductor memory device 110 according to the embodiment, since one wiring group (first to third wirings 11 to 13 and the like) extends in the Z direction, the number of contact electrodes 10c is small. For this reason, the area of the contact region can be reduced, and the area ratio of the memory region can be increased. For example, it is easy to obtain a large-capacity storage device.

  As shown in FIG. 3, in the semiconductor memory device 110, the number of cross wirings arranged in the Z direction is arbitrary. FIG. 1 corresponds to a partial PA shown in FIG.

Hereinafter, an example of a method for manufacturing the semiconductor memory device 110 will be described.
FIG. 4 is a flowchart illustrating the method for manufacturing the semiconductor memory device according to the first embodiment.
5 to 10 are schematic perspective views in the order of steps illustrating the method for manufacturing the semiconductor memory device according to the first embodiment.
As shown in FIG. 4, the stacked body ML is formed (step S110).
For example, as illustrated in FIG. 5, the stacked body ML including the stacked portion MB is formed on the surface 10 a of the semiconductor substrate 10. In this example, a layer 10i is formed on the surface 10a, and a contact electrode 10c is formed at a predetermined position. A stacked body ML is formed thereon. The stacked body ML includes, for example, a plurality of stacked portions MB stacked in the Z direction. Hereinafter, one stacked unit MB will be described.

  The stacked unit MB includes a first conductive film 21f, a second conductive film 22f, an interlayer insulating film ILf, a first resistance change film 31f, and a second resistance change film 32f. The second conductive film 22f is separated from the first conductive film 21f in the first direction (for example, the −Z direction) intersecting the surface 10a of the semiconductor substrate 10. The interlayer insulating film ILf is provided between the first conductive film 21f and the second conductive film 22f. The first resistance change film 31f is provided between the first conductive film 21f and the interlayer insulating film ILf. The second resistance change film 32f is provided between the second conductive film 22f and the interlayer insulating film ILf. The interlayer insulating film ILf becomes at least a part of the interlayer insulating layer ILL.

  The first conductive film 21f is, for example, one of the cross wirings (for example, the first cross wiring 21). The second conductive film 22f is, for example, another cross wiring (for example, the second cross wiring 22). The interlayer insulating film ILf is a sacrificial film, for example. As will be described later, at least a part of the interlayer insulating film ILf is removed, and wirings (first to third wirings 11 to 13 and the like) are formed at the place where the interlayer insulating film ILf was formed. For example, the first resistance change film 31 f becomes at least a part of the first resistance change unit 31. The second resistance change film 32 f becomes at least a part of the second resistance change portion 32.

  In this example, the first resistance change film 31f includes a first metal-containing film 31Mf and a first insulating film 31iaf. In this example, the first metal-containing film 31Mf is disposed between the first conductive film 21f and the first insulating film 31iaf. The second resistance change film 32f includes, for example, a second metal-containing film 32Mf and a second insulating film 32iaf. For example, the second metal-containing film 32Mf is disposed between the second conductive film 22f and the second insulating film 32iaf.

  In this example, the stacked unit MB further includes a first intermediate film 51af and a second intermediate film 52af. The first intermediate film 51af is provided between the first conductive film 21f and the first resistance change film 31f. The second intermediate film 52af is provided between the second conductive film 22f and the second resistance change film 32f. As will be described later, the first intermediate film 51af becomes the first intermediate layer 51a, and the second intermediate film 52af becomes the second intermediate layer 52a.

For example, an SiO ₂ film is formed on the surface 10a of the semiconductor substrate 10 (on the layer 10i). A W (tungsten) film (for example, the second conductive film 22f) is formed thereon. Further, a TiN film (for example, the second intermediate film 52af) is formed thereon. An Ag film (for example, the second metal-containing film 32Mf) is formed thereon. Further, an SiO ₂ film (for example, the second insulating film 32iaf) is formed. A SiN film (for example, the interlayer insulating film ILf) is formed thereon. A SiO ₂ film (for example, the first insulating film 31iaf) is formed thereon. An Ag film (for example, the first metal-containing film 31Mf) is formed thereon. A TiN film (for example, the first intermediate film 51af) is formed thereon. Further, a W film (for example, the first conductive film 21f) is formed thereon. Thereby, one laminated part MB is formed. Such film formation is repeated. Thereby, the stacked body ML is formed. The SiO ₂ film is formed using, for example, TEOS.

As shown in FIG. 4, the stacked body ML is divided (step S120).
For example, as shown in FIG. 5, a mask MLM is formed on the stacked body ML. The mask has a groove MLMT extending along the Y direction. Using this mask MLM, a groove is formed in the stacked body ML.

  Hereinafter, one stacked unit MB illustrated in FIG. 5 is illustrated.

  As shown in FIG. 6, a groove MLT is formed in the stacked body ML by processing using the mask MLM. The groove MLT extends in the third direction D3. The third direction D3 is one direction that intersects the first direction D1 (Z direction), and in this example, is the Y direction. In this way, the stacked body ML is divided in the second direction D2. The second direction D2 is a direction that intersects the first direction D1 and the third direction D3, and in this example, is the X direction.

As shown in FIG. 4, the trench MLT is filled with the first insulating material film (step S130).
That is, as shown in FIG. 7, the trench MLT of the multilayer body ML is filled with the first insulating material film IMf1. The first insulating material film IMf1 extends in the Y direction. For example, a SiO ₂ film is formed as the first insulating material film IMf1. At least a part of the first insulating material film IMf1 becomes, for example, the insulating portion 40.

As shown in FIG. 4, the first insulating material film IMf1 is divided in the third direction D3 (step S140).
That is, as shown in FIG. 8, the hole IMfh is formed in the first insulating material film IMf1. The hole IMfh extends in the Z direction. The hole IMfh may be a groove. The first insulating material film IMf1 is divided in the third direction D3 (Y direction) by the hole IMfh. The plurality of divided first insulating material films IMf1 are arranged in the third direction D3 (Y direction).

As shown in FIG. 4, a space is formed between at least part of the first resistance change film 31f and at least part of the second resistance change film 32f (step S150).
That is, as shown in FIG. 9, at least a part of the interlayer insulating film ILf is removed through the hole IMfh. Space ILs is formed in the region from which interlayer insulating film ILf has been removed. The space ILs is located between at least a part of the first resistance change film 31f and at least a part of the second resistance change film 32f.

  When SiN is used as the interlayer insulating film ILf, for example, a wet process using hot phosphoric acid is performed in removing at least a part of the interlayer insulating film ILf. In the removal, for example, a CDE (Chemical Dry Etching) process using at least one of fluorine gas and chlorine gas may be performed. By this method, isotropic etching of SiN is performed at a high selectivity with respect to other films.

As shown in FIG. 4, the second insulating material film IMf2 is formed (step S160).
For example, as shown in FIG. 10, in at least one of the space ILs and the hole IMfh, the surface of the first conductive film 21f, the second conductive film 22f, the first resistance change film 31f, and the second resistance change film 32f is formed. Then, a second insulating material film IMf2 is formed. For example, the first conductive film 21f, the second conductive film 22f, the first resistance change film 31f, and the second resistance change film 32f are exposed in at least one of the space ILs and the hole IMfh. A second insulating material film IMf2 is formed on the exposed surfaces of these films. For example, a SiO ₂ film is formed as the second insulating material film IMf2. For example, a part of the second insulating material film IMf2 and the first insulating film 31iaf become the first insulating layer 31i. Another part of the second insulating material film IMf2 becomes the first insulating portion 41. The first metal-containing film 31Mf becomes the first metal-containing layer 31M.

  In this example, a TiN film (a first side surface intermediate film 51sf and a second side surface intermediate film 52sf) is further formed on the second insulating material film IMf2.

As shown in FIG. 4, a conductive material is embedded in the remaining region (step S170).
That is, as shown in FIG. 10, after the step of forming the second insulating material film IMf2 (step S160) (in this example, after the formation of the TiN film), the conductive material CMf (for example, tungsten) is embedded. . The conductive material CMf is embedded in the remaining region of the space ILs and the remaining region of the hole IMfh. A wiring (first to third wirings 11 to 13, etc., see FIG. 1) is formed by the embedded conductive material CMf.

  Thereby, the semiconductor memory device 110 illustrated in FIGS. 1 and 3 is formed.

  As described above, in this example, a step of forming a TiN film is further provided between the step of forming the second insulating material film IMf2 (step S160) and the step of embedding the conductive material CMf (step S170). It is done. That is, a process of forming a film (for example, a TiN film) containing a nitride of at least one of Ti, Ta, and W on at least a part of the second insulating material film IMf2 between Step S160 and Step S170. May be further implemented. This film (for example, a TiN film) becomes, for example, the first side surface intermediate layer 51s and the second side surface intermediate layer 52s.

  In the process described with reference to FIG. 9 (the process of forming the space ILs, step S150), in one cross section along the plane (ZX plane) including the first direction D1 and the second direction D2, the space ILs is The first resistance change film 31f is formed between the second resistance change film 32f and the second resistance change film 32f. Thereby, in one cross section along the Z-X plane, the first projecting portion 11p is provided between all of the first resistance change film 31f and all of the second resistance change film 32f. As will be described later, the space ILs may be formed between a part of the first resistance change film 31f and a part of the second resistance change film 32f in one cross section along the Z-X plane. .

  FIG. 11 is a schematic perspective view illustrating another semiconductor memory device according to the first embodiment. As shown in FIG. 11, another semiconductor memory device 111 according to the present embodiment also includes a first wiring 11, a first cross wiring 21, a first resistance change unit 31, and a first insulating unit 41. . In the semiconductor memory device 111, the stacking order of the layers provided in the first resistance change unit 31 is different from that of the semiconductor memory device 110. Other than this, the semiconductor memory device 110 is the same as the semiconductor memory device 110, and the description thereof is omitted.

  In the semiconductor memory device 111, the first resistance change unit 31 includes a first metal-containing layer 31M and a first insulating layer 31i. Also in this case, the first metal-containing layer 31M includes at least one of silver, copper, aluminum, and tellurium. The first insulating layer 31i is aligned with the first metal-containing layer 31M in the Z direction. In the semiconductor memory device 111, at least a part of the first metal-containing layer 31M is disposed between the first protruding portion 11p and the first insulating layer 31i.

  Also in the semiconductor memory device 111, the first state and the second state are formed. In the first state, the potential of the first cross wiring 21 is lower than the potential of the first wiring 11 (the potential of the first protruding portion 11p). In the second state, the potential of the first cross wiring 21 is higher than the potential of the first wiring 11. For example, the resistance of the first resistance change unit 31 in the first state is lower than the resistance of the first resistance change unit 31 in the second state. Such resistance difference is made to correspond to stored information.

  Again. A first intermediate layer 51a may be provided. The first intermediate layer 51a is provided between the first protruding portion 11p and the first insulating layer 31i. The first intermediate layer 51a includes, for example, a nitride of at least one of Ti, Ta, and W.

(Second Embodiment)
FIG. 12A and FIG. 12B are schematic perspective views illustrating the semiconductor memory device according to the second embodiment.
As shown in FIG. 12A, the semiconductor memory device 120 according to the present embodiment includes the first wiring 11, the first cross wiring 21, the first resistance change unit 31, and the first insulating unit 41. Including.
In FIG. 12B, the first wiring 11 is extracted and drawn.

  Also in the semiconductor memory device 120. The first wiring 11 includes a first extending portion 11e extending in the first direction D1 (Z direction), a first protruding portion 11p protruding in a second direction D2 (−X direction) intersecting the first direction D1, including. The first cross wiring 21 extends in a third direction D3 (Y direction) that intersects the first direction D1 and the second direction D2. At least a part of the first resistance change portion 31 is provided between at least a part of the first cross wiring 21 and the first protruding portion 11p. At least a portion of the first insulating portion 41 is provided between a portion of the first extending portion 11e and at least a portion of the first cross wiring 21 in the second direction D2.

  Also in this case, the first resistance change unit 31 includes the first metal-containing layer 31M including at least one of silver, copper, aluminum, and tellurium, and the first insulating layer aligned with the first metal-containing layer 31M in the first direction D1. 31i. In the first resistance change unit 31, a change in resistance occurs.

  In the semiconductor memory device 120, the second wiring 12, the second resistance change unit 32, and the second insulating unit 42 are further provided. In the semiconductor memory device 120, the second wiring 12 is aligned with the first wiring 11 in the second direction D2 (−X direction). That is, the arrangement of the second wiring 12 in the semiconductor memory device 120 is different from that in the semiconductor memory device 110. Hereinafter, the second wiring 12 will be described.

  The second wiring 12 includes a second extending portion 12e and a second protruding portion 12p. The second extending portion 12e extends in the first direction D1 (Z direction). The second extending portion 12e is aligned with the first extending portion 11e in the second direction D2. The second protruding portion 12p protrudes toward the first protruding portion 11p along the second direction D2. A divided insulating portion ILA is provided between the second extending portion 12e and the first extending portion 11e. The second wiring 12 can be controlled independently of the first wiring 11. Between the first extension portion 11e and the second extension portion 12e, the first cross wiring 21 and the first resistance change portion 31 are disposed.

  The second resistance change portion 32 is provided between a part of the first cross wiring 21 and the second protruding portion 12p. In this example, the second resistance change unit 32 is continuous with the first resistance change unit 31.

  The second insulating portion 42 is provided between a part of the second extending portion 12e and the first cross wiring 21 in the second direction D2 (−X direction). In this example, the second insulating portion 42 is continuous with at least a part of the second resistance change portion 32. In this example, the second resistance change portion 32 includes a second metal-containing layer 32M including at least one of silver, copper, aluminum, and tellurium, and a second insulating layer aligned with the second metal-containing layer 32M in the first direction D1. 32i. The second insulating part 42 is continuous with at least a part of the second insulating layer 32 i of the second resistance change part 32. The second resistance change unit 32 is continuous with the first resistance change unit 31.

  In the semiconductor memory device 120, the first memory unit MP1 is formed between the first cross wiring 21 and the first protruding portion 11p. A second memory unit MP2 is formed between the first cross wiring 21 and the second protruding portion 12p. For example, one continuous resistance change unit between one cross wiring (for example, a bit line) and two wirings (for example, the first wiring 11 and the second wiring 12, for example, a word line). (Ion supply layer and resistance change layer) are provided. Two independent memory cells (memory portions) are formed between the two word lines. In the ion memory, a filament serving as a current path is locally formed in the variable resistance layer. A memory function is exhibited by locally formed filaments. Therefore, a desired operation is performed even when the bit line, the ion supply layer, and the resistance change layer are shared. For example, the number of bits per unit volume can be doubled.

  In the semiconductor memory device 120, a second cross wiring 22 is provided. A third memory unit MP3 is formed between the second cross wiring 22 and the first protruding portion 11p. A fourth memory unit MP4 is formed between the second cross wiring 22 and the second protruding portion 12p.

  Also in the semiconductor memory device 120, the reliability of the memory operation can be improved.

  Also in the semiconductor memory device 120, the first wiring 11, the first cross wiring 21, the first resistance change unit 31, the first insulating unit 41, and the like may be provided on the surface 10 a of the semiconductor substrate 10. The first direction D1 intersects the surface 10a. The second direction D2 and the third direction D3 are along the surface 10a.

  In the semiconductor memory device 120, for example, in the process described with reference to FIG. 9 (process for forming the space ILs, step S150), the space ILs is separated from the first resistance change film 31f in one cross section along the ZX plane. And a portion of the second resistance change film 32f. That is, a part of the interlayer insulating film ILf is removed through the hole IMfh, and another part of the interlayer insulating film ILf is left. Thus, in the step of forming the space ILs (step S150), a part of the interlayer insulating film ILf is formed in the cross section along the plane (ZX plane) including the first direction D1 and the second direction D2. It may also be included in a part between the first resistance change film 31f and the second resistance change film 32f. With this exception, the semiconductor memory device 120 can be manufactured in the same manner as the steps described with reference to FIGS.

  The method according to the present embodiment can provide a method for manufacturing a semiconductor memory device that can improve the reliability of the memory operation.

  According to the embodiment, it is possible to provide a semiconductor memory device that can improve the reliability of the memory operation and a manufacturing method thereof.

  In the present specification, “vertical” and “parallel” include not only strictly vertical and strictly parallel, but also include, for example, variations in the manufacturing process, and may be substantially vertical and substantially parallel. is good.

  The embodiments of the present invention have been described above with reference to specific examples. However, embodiments of the present invention are not limited to these specific examples. For example, the specific configuration of each element such as a wiring, a cross wiring, a resistance changing portion, and an insulating portion included in the semiconductor memory device can be similarly implemented by appropriately selecting from a well-known range by those skilled in the art. As long as the same effect can be obtained, it is included in the scope of the present invention.

  Moreover, what combined any two or more elements of each specific example in the technically possible range is also included in the scope of the present invention as long as the gist of the present invention is included.

  In addition, all semiconductor memory devices and methods for manufacturing the same that can be implemented by those skilled in the art based on the semiconductor memory devices and methods for manufacturing the semiconductor devices described above as embodiments of the present invention are also included in the gist of the present invention. As long as it is included, it belongs to the scope of the present invention.

  In addition, in the category of the idea of the present invention, those skilled in the art can conceive of various changes and modifications, and it is understood that these changes and modifications also belong to the scope of the present invention. .

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate, 10a ... Surface, 10c, 10d ... Contact electrode, 10i ... Layer, 11 ... 1st wiring, 11M ... 1st metal containing layer, 11e ... 1st extension part, 11ea, 11eb ... part, 11f ... 2nd extending part, 11p ... 1st protruding part, 11q ... protruding part, 12 ... 2nd wiring, 12e ... 2nd extending part, 12p ... 2nd protruding part, 13 ... 3rd wiring, 21 ... 1st crossing Wiring, 21f ... 1st conductive film, 22 ... 2nd cross wiring, 22f ... 2nd conductive film, 23 ... 3rd cross wiring, 24 ... 4th cross wiring, 31 ... 1st resistance change part, 31M ... 1st metal Containing layer, 31Mf ... first metal containing film, 31a ... first region, 31b ... second region, 31f ... first resistance change film, 31i ... first insulating layer, 31iaf ... first insulating film, 32 ... second resistance Changing part, 32M ... Two metal-containing layers, 32Mf ... second metal-containing film, 32a ... third region, 32b ... fourth region, 32f ... second resistance change film, 32i ... second insulating layer, 32iaf ... second insulating film, 33 ... first 3 resistance changing section, 34... 4th resistance changing section, 40... Insulating section, 41 and 42... First and second insulating sections, 51 a... First intermediate layer, 51 af ... first intermediate film, 51 s. 51sf ... first side surface intermediate film, 52a ... second intermediate layer, 52af ... second intermediate film, 52s ... second side surface intermediate layer, 52sf ... second side surface intermediate film, 110, 111, 120 ... semiconductor memory device, CMf: Conductive material, D1 to D3: First to third directions, ILA: Divided insulating part, ILL ... Interlayer insulating layer, ILf ... Interlayer insulating film, ILs ... Space, IMf1 ... First insulating material film, IMf2 ... Second Insulating material film, IMfh ... hole, MB ... laminated part, ML ... laminated body, MLM ... mask, MLMT ... groove, MLT ... groove, MP1 to MP4 ... first to fourth memory parts, PA ... partial

Claims (20)

A first wiring including a first extending portion extending in a first direction and a first protruding portion protruding in a second direction intersecting the first direction;
A first cross wiring extending in a third direction intersecting the first direction and the second direction;
A first resistance change unit;
A first insulating part;
With
At least a part of the first resistance change part is provided between at least a part of the first cross wiring and the first protruding part,
The semiconductor memory device, wherein at least a part of the first insulating part is provided between a part of the first extension part and the at least part of the first cross wiring in the second direction. A semiconductor substrate;
On the surface of the semiconductor substrate, the first wiring, the first cross wiring, the first resistance change unit, and the first insulating unit are provided,
The first direction intersects the surface;
The semiconductor memory device according to claim 1, wherein the second direction and the third direction are along the surface. A second cross wiring extending in the third direction and aligned with the first cross wiring in the first direction;
A second resistance change unit;
A second insulating portion;
Further comprising
At least a part of the second resistance change part is provided between at least a part of the second cross wiring and the first protruding part,
The at least part of the second insulating part is provided between another part of the first extension part and the at least part of the second cross wiring in the second direction. 2. The semiconductor memory device according to 2. The first resistance change unit includes:
A first metal-containing layer containing at least one of silver, copper, aluminum, and tellurium;
A first insulating layer aligned with the first metal-containing layer in the first direction;
The semiconductor memory device according to claim 1, comprising: The first wiring further includes a second extending portion extending in the first direction and connected to the first projecting portion along with the first extending portion in the second direction,
5. The semiconductor memory device according to claim 1, wherein the first cross wiring and the first resistance change portion are disposed between the first extension portion and the second extension portion. 6. . A second extending portion extending in the first direction and aligned with the first extending portion in the second direction; and a second protruding portion protruding toward the first protruding portion along the second direction. The second wiring, wherein the first intersecting wiring and the first resistance change portion are disposed between the first extending portion and the second extending portion;
A second resistance change portion provided between a part of the first cross wiring and the second protruding portion;
A second insulating portion provided between a part of the second extending portion and the first cross wiring in the second direction;
The semiconductor memory device according to claim 1, further comprising: The second insulating part is continuous with at least a part of the second resistance change part,
The semiconductor memory device according to claim 6, wherein the second resistance change unit is continuous with the first resistance change unit.   The semiconductor memory device according to claim 1, wherein the first insulating unit is continuous with at least a part of the first resistance change unit. At least a part of the first metal-containing layer is disposed between the first cross wiring and the first insulating layer,
The resistance of the first resistance change portion in the first state in which the potential of the first cross wiring is higher than the potential of the first wiring is such that the potential of the first cross wiring is lower than the potential of the first wiring. The semiconductor memory device according to claim 4, wherein the resistance is lower than the resistance of the first resistance change unit in the second state.   10. The semiconductor memory device according to claim 9, further comprising a first intermediate layer provided between the first cross wiring and the first insulating layer and including a nitride of at least one of Ti, Ta, and W. 11. At least a part of the first metal-containing layer is disposed between the first protruding portion and the first insulating layer,
The resistance of the first resistance change portion in the first state in which the potential of the first cross wiring is lower than the potential of the first wiring is such that the potential of the first cross wiring is higher than the potential of the first wiring. The semiconductor memory device according to claim 4, wherein the resistance is lower than the resistance of the first resistance change unit in the second state.   12. The semiconductor memory device according to claim 11, further comprising a first intermediate layer that is provided between the first protruding portion and the first metal-containing layer and includes a nitride of at least one of Ti, Ta, and W.   The semiconductor memory device according to claim 4, wherein the first insulating layer includes silicon oxide.   The first side surface intermediate layer according to claim 1, further comprising a first side surface intermediate layer that is provided between the first extending portion and the first insulating portion and includes a nitride of at least one of Ti, Ta, and W. The semiconductor memory device according to one. Forming a stacked body including a stacked portion on a surface of a semiconductor substrate, wherein the stacked portion includes a first conductive film and the first conductive film in a first direction intersecting the surface; The separated second conductive film, the interlayer insulating film provided between the first conductive film and the second conductive film, and the first provided between the first conductive film and the interlayer insulating film The step of forming the stacked body including a resistance change film, and a second resistance change film provided between the second conductive film and the interlayer insulating film;
Forming a groove extending in a third direction intersecting the first direction in the laminate and dividing the laminate in the first direction and the second direction intersecting the third direction;
Filling the groove with a first insulating material film;
Forming a hole in the first insulating material film to divide the first insulating material film in the third direction;
Removing at least part of the interlayer insulating film through the hole to form a space between at least part of the first resistance change film and at least part of the second resistance change film;
Forming a second insulating material film on the first conductive film, the second conductive film, the first resistance change film, and the second resistance change film in at least one of the space and the hole;
After the step of forming the second insulating material film, a step of embedding a conductive material in the remaining region of the space and the remaining region of the hole;
A method for manufacturing a semiconductor memory device comprising: The first resistance change film includes:
A first metal-containing film of at least one of silver, copper, aluminum, and tellurium;
A first insulating material film aligned with the first metal-containing film in the first direction;
The method of manufacturing a semiconductor memory device according to claim 15, comprising:   In the step of forming the space, in the cross-section along the plane including the first direction and the second direction, the space is formed with all of the first resistance change film and all of the second resistance change film. The method of manufacturing a semiconductor memory device according to claim 15, further comprising forming between them.   In the step of forming the space, in a cross section along a plane including the first direction and the second direction, a part of the interlayer insulating film is formed on the first resistance change film and the second resistance change film. The method of manufacturing a semiconductor memory device according to claim 15, further comprising: leaving a part between the two.   The method of manufacturing a semiconductor memory device according to claim 15, wherein the stacked body includes a plurality of the stacked portions stacked in the first direction.   Between the step of forming the second insulating material film and the step of embedding the conductive material, at least part of the second insulating material film includes at least one of Ti, Ta and W nitrides. The method for manufacturing a semiconductor memory device according to claim 15, further comprising a step of forming a film including the semiconductor.

Images