JP2017098338A - Electronic device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electronic device capable of preventing a crack from entering a surface layer resin part.SOLUTION: An electronic device 100 is constructed by being mounted in an engine room of a vehicle. The electronic device 100 comprises first layer wiring L1 to tenth layer wiring L10 which are laminated through a first build up layer 11 to a sixth build up layer 16 and a first core layer 17a to a third core layer 17c. The electronic device 100 comprises field vias 31 and 32 to the first build up layer 11 between the first layer wiring L1 and the second layer wiring L2. A linear expansion coefficient of the first build up layer 11 in a Z direction is similar to that of the field vias 31 and 32.SELECTED DRAWING: Figure 2

Description

  The present invention relates to an electronic device in which a plurality of wirings stacked via an electrically insulating resin substrate are formed.

  Conventionally, there is an electronic device disclosed in Patent Document 1 as an example of an electronic device in which a plurality of wirings laminated via an electrically insulating resin base material is formed.

  This electronic device includes a build-up layer (hereinafter referred to as a surface layer resin) in which at least one of a rod-like, flattened, and flake-like additive is mixed in a resin in addition to a spherical filler that controls a thermal expansion coefficient. Part).

JP 2014-220310 A

  By the way, in the electronic device, filled vias are formed in the surface resin portion. The surface resin portion and the filled via have different linear expansion coefficients in the wiring lamination direction. For this reason, in the electronic device, when the temperature of the usage environment changes, stress may be applied to the surface layer resin portion and cracks may occur. When a crack occurs, the electronic device has a problem that the filled via and the inner layer wiring are disconnected from the crack, or a water droplet or the like enters the crack and the land and the inner layer wiring are short-circuited.

  This invention is made | formed in view of the said problem, and it aims at providing the electronic device which can suppress that a crack enters into a surface layer resin part.

In order to achieve the above object, the present invention provides:
A plurality of wirings (L1 to L10) stacked via electrically insulating resin base materials (11 to 16, 17a to 17c);
Mounted parts (L1a, L10a) that are part of the surface layer wirings (L1, L10) provided on the surface layer of the resin substrate among the plurality of wirings and on which the circuit elements (70, 200) can be mounted;
Fills the hole provided in the surface layer resin portion (11, 12) between the surface layer wiring in the resin substrate and the second layer wiring (L2, L9) provided in the next layer of the surface layer wiring, Filled vias (31 to 34) that electrically and mechanically connect the portion and the second layer wiring,
The linear expansion coefficient of the surface resin portion in the wiring lamination direction is the same as the linear expansion coefficient of filled vias.

  Thus, in the present invention, the mounted portion and the second layer wiring are electrically and mechanically connected by the filled via. The filled via fills a hole provided in the surface resin portion between the surface layer wiring and the second layer wiring. The surface layer resin portion and the filled via expand or contract in accordance with a change in environmental temperature.

  In the present invention, the linear expansion coefficient of the surface layer resin portion is the same as the linear expansion coefficient of the filled via. For this reason, the present invention suppresses the application of stress to the surface layer resin portion because the surface layer resin portion and the filled via will expand and contract in the same manner even if the environmental temperature at which the device is disposed changes. Can do. Therefore, this invention can suppress that a crack enters into a surface layer resin part.

  The reference numerals in parentheses described in the claims and in this section indicate the correspondence with the specific means described in the embodiments described later as one aspect, and the technical scope of the invention is as follows. It is not limited.

It is a top view which shows schematic structure of the electronic device in 1st Embodiment. It is sectional drawing which follows the II-II line of FIG. It is an image figure which shows the mounting environment of the electronic device in 1st Embodiment. It is a graph which shows the relationship between a crack generation rate and a linear expansion coefficient. It is sectional drawing which shows schematic structure of the electronic device in 2nd Embodiment. It is sectional drawing which shows schematic structure of the electronic device in 3rd Embodiment. It is sectional drawing which shows schematic structure of the electronic device in 4th Embodiment. It is sectional drawing which shows schematic structure of the electronic device in 5th Embodiment.

  Hereinafter, a plurality of embodiments for carrying out the invention will be described with reference to the drawings. In each embodiment, portions corresponding to the matters described in the preceding embodiment may be denoted by the same reference numerals and redundant description may be omitted. In each embodiment, when only a part of the configuration is described, the other configurations described above can be applied to other portions of the configuration.

  In the following, the stacking direction of the first layer wiring L1 to the seventh layer wiring L7 is referred to as the Z direction. In addition, the Z direction can be rephrased as the thickness direction. Furthermore, the X direction and the Y direction in the drawing are directions orthogonal to each other and orthogonal to the Z direction.

(First embodiment)
The electronic device 100 according to the first embodiment will be described with reference to FIGS. The electronic device 100 has a function as a control device for a vehicle, for example. As shown in FIG. 3, the electronic device 100 is mounted, for example, in an engine room 200 of a vehicle. In the engine room 200, for example, an engine and an automatic transmission (hereinafter referred to as a transmission) 210 are mounted. In the present embodiment, an example in which the electronic device 100 is disposed in the transmission 210 is employed as an example. Specifically, the electronic device 100 is disposed in the housing of the transmission 210. The transmission 210 is filled with oil 220 in the housing. Therefore, the electronic device 100 is disposed in the transmission 210 while being exposed to the oil 220. Note that the temperature in the transmission 210 changes in a range of about −40 ° C. to 150 ° C. That is, the electronic device 100 changes its own ambient temperature in a range of about −40 ° C. to 150 ° C.

  However, the present invention is not limited to this. The electronic device 100 may be disposed around the engine and the transmission 210 in the engine room 200. That is, the electronic device 100 may be disposed in the same space as the engine and the transmission 210. For example, the electronic device 100 is directly mounted on a metal case of the engine or a housing of the transmission 210 by a fixing tool such as a bolt. Note that the temperature of the engine room 200 also changes in a range of about −40 ° C. to 150 ° C. The engine room 200 may also have a relatively high humidity. Furthermore, the electronic device 100 may be mounted on a device different from a vehicle in which the ambient temperature changes at about −40 ° C. to 150 ° C.

  As shown in FIGS. 1 and 2, the electronic device 100 includes a first buildup layer 11 to a sixth buildup layer 16, a first core layer 17 a to a third core layer 17 c, and first layers stacked via these layers. The first-layer wiring L1 to the tenth-layer wiring L10 are provided. The first buildup layer 11 to the sixth buildup layer 16 and the first core layer 17a to the third core layer 17c correspond to the resin base material in the claims. The first layer wiring L1 to the tenth layer wiring L10 correspond to the wiring in the claims. In the following description, the first buildup layer 11 to the sixth buildup layer 16 are omitted, the buildup layers 11 to 16 are described, the first core layer 17a to the third core layer 17c are omitted, and the core layer It may be described as 17a to 17c.

  Furthermore, the electronic device 100 includes filled vias 31 to 34 and conformal vias 21 to 24 that electrically and mechanically connect wirings of different layers. The structure composed of the build-up layers 11 to 16 and the core layers 17a to 17c, the first layer wiring L1 to the tenth layer wiring L10, the filled vias 31 to 34, and the conformal vias 21 to 24 is a multilayer. It can be called a substrate. The multilayer substrate includes one surface S1 and an opposite surface S2 that is a surface opposite to the one surface S1. The multilayer substrate has, for example, a flat plate shape. The multilayer substrate includes a through via 40. However, the electronic device 100 may not include the through via 40.

  Furthermore, the electronic device 100 includes a circuit element 70 mounted on one surface S1, and a sealing resin 50 that integrally covers the one surface S1, the first layer wiring L1, and the circuit element 70. In addition, the sealing resin 50 integrally covers the solder 80 connecting the circuit element 70 and the multilayer substrate. As described above, since the sealing resin 50 is provided on the one surface S1 of the electronic device 100, it is not necessary to provide a solder resist for protecting the first layer wiring L1 and for electrical insulation. The sealing resin 50 includes a known epoxy resin or the like, and is formed by a transfer molding method, a compression molding method, or the like. The sealing resin 50 is formed only on the one surface S1 side and is not formed on the opposite surface S2 side. Therefore, it can be said that the electronic device 100 has a half mold structure.

  The circuit element 70 is a component constituting a circuit together with the first layer wiring L1 and the like, and an IC, MOSFET, IGBT, diode, resistor, capacitor, or the like can be adopted. Further, since the circuit element 70 is covered with the sealing resin 50, it can be adopted as a bare chip. The circuit element 70 includes an electrode 71. In the circuit element 70, the land L1a, which is a part of the first layer wiring L1 formed on the one surface S1, and the electrode 71 are electrically and mechanically connected by the solder 80. The member that connects the electrode 71 and the land L1a is not limited to the solder 80, and any conductive connecting member can be used. Therefore, it can be said that the electronic device 100 includes a conductive connection member.

  In the electronic device 100, the sealing resin 50 is not provided on the opposite surface S2. Therefore, the electronic device 100 includes a solder resist 60 that covers the tenth layer wiring L10 formed on the opposite surface S2. More specifically, the solder resist 60 has an opening 61 for exposing a part of the tenth layer wiring L10. In the tenth layer wiring L10, a portion exposed from the opening 61 is a land L10a. The electronic device 100 is attached to the transmission 210 with heat radiation grease or the like provided in the opening 61 and the solder resist 60 and the transmission 210 facing each other. In addition, the electronic device 100 may have a heat sink attached to the opening 61 or the like in a state where heat dissipation grease or the like is provided and the solder resist 60 and the heat sink face each other. As a result, the electronic device 100 forms a heat dissipation path through the land L10a.

  Moreover, the electrode of the mounting component mounted in the opposite surface S2 side may be electrically and mechanically connected to the land L10a via the electroconductive connection member. This mounted component is a component that constitutes a part of the circuit like the circuit element 70, but is difficult to cover with the sealing resin 50 because it cannot withstand the molding pressure when the sealing resin 50 is molded. It is.

  Here, the multilayer substrate will be described in detail. First, the core layers 17a to 17c will be described. The core layers 17a to 17c are mainly composed of an electrically insulating resin, and are, for example, an epoxy resin containing an electrically insulating inorganic filler such as alumina or silica. Moreover, the core layers 17a-17c may be comprised including the epoxy resin and glass cloth containing an inorganic filler. However, the core layers 17a to 17c are not limited to this, and may not include an inorganic filler or a glass cloth. Further, the core layers 17a to 17c may be made of only a resin not containing an inorganic filler and glass cloth.

  The core layers 17a to 17c have a configuration in which the second core layer 17b is sandwiched between the first core layer 17a and the third core layer 17c. In the second core layer 17b, a patterned fifth layer wiring L5 is formed on the one surface S1 side, and a patterned sixth layer wiring L6 is formed on the opposite surface S2 side. In the second core layer 17b, a first core layer 17a is formed so as to cover the fifth layer wiring L5, and a third core layer 17c is formed so as to cover the sixth layer wiring L6. Further, the first core layer 17a is formed with a fourth layer wiring L4 patterned on the one surface S1 side. The third core layer 17c has a seventh layer wiring L7 patterned on the opposite surface S2 side. The through via 40 is provided through the core layers 17a to 17c in the Z direction between the fourth layer wiring L4 and the seventh layer wiring L7. For the through via 40, refer to Patent Document 1 and the like.

  In the multilayer substrate, the fifth buildup layer 15, the third buildup layer 13, and the first buildup layer 11 are laminated in this order on the one surface S1 side of the first core layer 17a. In the multilayer substrate, the sixth buildup layer 16, the fourth buildup layer 14, and the second buildup layer 12 are laminated in this order on the opposite surface S2 side of the third core layer 17c. The first buildup layer 11 and the second buildup layer 12 correspond to the surface resin portion in the claims. On the other hand, each of the third buildup layer 13 to the sixth buildup layer 16 corresponds to the inner resin layer in the claims.

  Each of the first buildup layer 11, the third buildup layer 13, and the fifth buildup layer 15 is, like the first core layer 17a, the first layer wiring L1 and the second layer wiring patterned on the one surface S1 side. L2 and the third layer wiring L3 are formed. Similarly to the third core layer 17c, each of the second buildup layer 12, the fourth buildup layer 14, and the sixth buildup layer 16 includes the tenth layer wiring L10 patterned on the opposite surface S2 side, the first buildup layer 16, and the sixth buildup layer 16. Ninth-layer wiring L9 and eighth-layer wiring L8 are formed. In the multilayer substrate, the surface of the first buildup layer 11 corresponds to one surface S1, and the surface of the second buildup layer 12 corresponds to the opposite surface S2. Therefore, the first layer wiring L1 is formed on one surface S1. The tenth layer wiring L10 is formed on the opposite surface S2.

Next, the first layer wiring L1 to the tenth layer wiring L10 will be described. Each of the layer wirings L1 to L10 is a conductor pattern that is formed on the XY plane and includes a metal such as copper or aluminum. In other words, each of the layer wirings L1 to L10 is composed mainly of a metal such as copper or aluminum. In the present embodiment, an example in which copper is the main component is employed. Therefore, each layer wiring L1 to L10 has a linear expansion coefficient in the Z direction of 17 × 10 ⁻⁶ / ° C. In the following, the linear expansion coefficient in the Z direction is also simply referred to as a linear expansion coefficient.

  In this embodiment, as an example, as shown in FIG. 2, the thicknesses of the first layer wiring L1 to the fourth layer wiring L4 and the seventh layer wiring L7 to the tenth layer wiring L10 are set to the fifth layer wiring L5 and the fifth layer wiring L5. The electronic device 100 that is thicker than the thickness of the six-layer wiring L6 is employed. Furthermore, the thicknesses of the first layer wiring L1 to the fourth layer wiring L4 and the seventh layer wiring L7 to the tenth layer wiring L10 are sufficiently thicker than the wiring thickness of the multilayer substrate used for a personal computer or a portable terminal. In addition, the thickness here is the film thickness of the conductor pattern which comprises the 1st layer wiring L1, the 5th layer wiring L5, etc. For this reason, the multilayer substrate of the electronic device 100 can pass a larger current than the multilayer substrate used for a personal computer, a portable terminal, etc., and has good heat dissipation. Therefore, a MOSFET or IGBT as the circuit element 70 can employ a so-called power element that generates a relatively large amount of heat during operation. In the electronic device 100, the fifth layer wiring L5 and the sixth layer wiring L6 may have the same thickness as the first layer wiring L1.

  Next, the first buildup layer 11 to the sixth buildup layer 16 will be described. Filled vias 31 to 34 are formed in each of the first buildup layer 11 and the second buildup layer 12. More specifically, the first buildup layer 11 has filled vias 31 and 32 formed therein. On the other hand, filled vias 33 and 34 are formed in the second buildup layer 12. The filled vias 31 and 32 fill holes provided in the first buildup layer 11 and electrically and mechanically connect the land L1a and the second layer wiring L2. The hole provided in the first buildup layer 11 penetrates the first buildup layer 11 in the Z direction. The land L1a corresponds to the mounted portion in the scope of the claims. The land L1a is a part of the first layer wiring L1 and is a part where the circuit element 70 can be mounted. An electrode 71 is electrically and mechanically connected to the land L1a via a solder 80. The filled vias 31 and 32 are provided directly below the land L1a (in other words, directly below).

Each filled via 31 to 34 is composed mainly of a metal such as copper or silver paste. In the present embodiment, an example in which copper is the main component is employed. Accordingly, each filled via 31 to 34 has a linear expansion coefficient of 17 × 10 ⁻⁶ / ° C.

  The filled vias 33 and 34 are provided immediately above the land L10a (in other words, directly above), and electrically and mechanically connect the land L10a and the ninth layer wiring L9. The filled vias 33 and 34 are different from the filled vias 31 and 32 in the connected wiring layer, but are otherwise the same as the filled vias 31 and 32, and thus detailed description thereof is omitted.

  On the other hand, conformal vias 21 to 24 are formed in each of the third buildup layer 13 to the sixth buildup layer 16. More specifically, the third buildup layer 13 has a conformal via 21 formed thereon. The fourth buildup layer 14 is formed with a conformal via 24. In the fifth buildup layer 15, conformal vias 22 are formed. In the sixth buildup layer 16, a conformal via 23 is formed.

  The conformal via 21 is formed on the wall surface of the hole without filling the hole provided in the third buildup layer 13, and is electrically connected between the two wirings (L 2, L 3) sandwiching the third buildup layer 13. And mechanically connected. The hole provided in the third buildup layer 13 penetrates the third buildup layer 13 in the Z direction. The conformal via 21 is formed only on the surface of this hole.

  In addition, although the conformal vias 22 to 24 are different from the conformal via 21 in the wiring connected thereto, the other details are the same as the conformal via 21 and will not be described in detail. The conformal via 22 connects the third layer wiring L3 and the fourth layer wiring L4. The conformal via 23 connects the seventh layer wiring L7 and the eighth layer wiring L8. The conformal via 24 connects the eighth layer wiring L8 and the ninth layer wiring L9.

  As described above, the electronic device 100 is formed with both filled vias 31 and 32 and conformal vias 21 to 24. Filled vias have advantages such as the ability to mount circuit elements 70 and the like, high heat dissipation, large current, and miniaturization of multilayer substrates, as compared to conformal vias. On the other hand, conformal vias have advantages such as higher reliability and lower cost than filled vias. In the electronic device 100, filled vias 31 and 32 are provided only in the surface resin portion, and conformal vias 21 to 24 are provided in the inner resin portion. For this reason, it can be said that the electronic device 100 has both the advantages of filled vias and the advantages of conformal vias. That is, the electronic device 100 can ensure reliability while enabling the circuit element 70 to be mounted on the one surface S1.

  Each of the first buildup layer 11 and the second buildup layer 12 is made of, for example, an epoxy resin containing an electrically insulating inorganic filler such as alumina or silica, or an electrically insulating inorganic filler such as alumina or silica. The contained BT resin can be employed. BT resin is a registered trademark and is an abbreviation for bismaleimide triazine resin.

In particular, the first buildup layer 11 and the second buildup layer 12 have the same linear expansion coefficient as that of the filled vias 31 to 34. That is, the first buildup layer 11 and the second buildup layer 12 have a linear expansion coefficient of 17 × 10 ⁻⁶ / ° C. The linear expansion coefficient can be decreased as the amount of the inorganic filler contained in the epoxy resin or the like is increased. Therefore, in the electronic device 100, the amount of the inorganic filler is adjusted so that the linear expansion coefficients of the first buildup layer 11 and the second buildup layer 12 are 17 × 10 ⁻⁶ / ° C. On the other hand, the third buildup layer 13 to the sixth buildup layer 16 and the first core layer 17a to the third core layer 17c have a linear expansion coefficient of 40 × 10 ⁻⁶ / ° C.

  Thus, in the electronic device 100, the land L1a and the second layer wiring L2 are electrically and mechanically connected by the filled vias 31 and 32. The filled vias 31 and 32 fill a hole provided in the first buildup layer 11 between the first layer wiring L1 and the second layer wiring L2. The first buildup layer 11 and the filled vias 31 and 32 expand or contract according to changes in the environmental temperature.

  The electronic device 100 is mounted in the transmission 210. Therefore, it is conceivable that the environmental temperature of the environment in which the electronic device 100 is mounted changes in a range of about −40 ° C. to 150 ° C. Since the electronic device 100 is mounted in such an environment, it is considered that expansion and contraction of the first buildup layer 11 and the filled vias 31 and 32 appear remarkably due to a change in environmental temperature.

  Therefore, in the electronic device 100, the linear expansion coefficient of the first buildup layer 11 is the same as the linear expansion coefficient of the filled vias 31 and 32. For this reason, the electronic device 100 causes the first buildup layer 11 and the filled vias 31 and 32 to expand and contract in the same manner even when the environmental temperature changes as described above. Application of stress can be suppressed. Therefore, the electronic device 100 can suppress cracks in the first buildup layer 11.

  For example, when the first buildup layer 11 has a large difference in linear expansion coefficient from the filled vias 31 and 32, there is a possibility that the crack C may occur as shown by the dotted line in FIG. . The crack C is generated from the corner of the land L1a and reaches the interface between the filled via 31 and the second layer wiring L2. However, the electronic device 100 can suppress the generation of the crack C as described above.

Note that the linear expansion coefficients of the first buildup layer 11 and the second buildup layer 12 may not completely match the linear expansion coefficients of the filled vias 31 to 34. The linear expansion coefficients of the first buildup layer 11 and the second buildup layer 12 may be 17 ± 5 × 10 ⁻⁶ / ° C., that is, 12 to 22 × 10 ⁻⁶ / ° C. It has been confirmed by experiments that the electronic device 100 can suppress the crack C when used at the environmental temperature as long as the linear expansion coefficient is 12 to 22 × 10 ⁻⁶ / ° C. FIG. 4 is a graph showing the results of this experiment.

  In this experiment, the electronic device 100 is placed in a thermostat, and the temperature in the thermostat is changed in a temperature range of −40 ° C. to 150 ° C. and −40 ° C. to 150 ° C. Is observed. More specifically, in this experiment, the electronic device 100 is left in a constant temperature bath at −40 ° C. for 30 minutes, and then the temperature in the constant temperature bath is set to 150 ° C. for 10 minutes with the electronic device 100 being placed in the constant temperature bath. The electronic device 100 is left in a constant temperature bath at 150 ° C. for 30 minutes. In this experiment, this was repeated 500 times to observe whether or not the crack C was generated. Note that the temperature in the thermostatic chamber can be rephrased as the ambient temperature of the electronic device 100.

As is clear from the results shown in FIG. 4, the crack occurrence rate is 0 in the range of the linear expansion coefficient from 10.5 × 10 ⁻⁶ / ° C. to 22 × 10 ⁻⁶ / ° C., but the linear expansion coefficient is It is higher when it is smaller than 10.5 × 10 ⁻⁶ / ° C. and larger than 22 × 10 ⁻⁶ / ° C. Therefore, if the linear expansion coefficient of the first buildup layer 11 and the second buildup layer 12 is 17 ± 5 × 10 ⁻⁶ / ° C., the electronic device 100 has crack C when used at the above environmental temperature. Can be suppressed.

In the electronic device 100, the linear expansion coefficient of all the resin base materials including the first buildup layer 11 and the second buildup layer 12 may be 17 × 10 ⁻⁶ / ° C. That is, the electronic device 100 includes not only the first buildup layer 11 and the second buildup layer 12 but also the third buildup layer 13 to the sixth buildup layer 16 and the first core layer 17a to the third core layer 17c. Also, the linear expansion coefficient may be 17 × 10 ⁻⁶ / ° C. As a result, the electronic device 100 also has a difference in linear expansion coefficient between each layer wiring and each conformal via with respect to the third buildup layer 13 to the sixth buildup layer 16 and the first core layer 17a to the third core layer 17c. Can be eliminated or reduced. Therefore, the electronic device 100 can suppress the occurrence of cracks in the third buildup layer 13, for example.

  In the electronic device 100, when the environmental temperature at which the electronic device 100 is disposed changes, the first buildup layer 11 and the filled vias 31 and 32 expand and contract in the same manner. For this reason, even if the electronic device 100 is not disposed in the transmission 210, the same effect as described above can be obtained.

  The preferred embodiments of the present invention have been described above. However, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the spirit of the present invention. Below, 2nd Embodiment-5th Embodiment are demonstrated as another form of this invention. The above embodiment and the second to fifth embodiments can be carried out independently, but can also be carried out in combination as appropriate. The present invention is not limited to the combinations shown in the embodiments, and can be implemented by various combinations.

(Second Embodiment)
As shown in FIG. 5, the electronic device 110 is different from the electronic device 100 in that filled vias 35 to 28 are formed instead of the conformal vias 21 to 24. That is, in the electronic device 110, the conformal vias 21 to 24 are not provided, and only the filled vias 31 to 28 are formed as interlayer connection members. The electronic device 110 includes not only the first buildup layer 11 and the second buildup layer 12 but also the third buildup layer 13 to the sixth buildup layer 16 and the first core layer 17a to the third core layer 17c. Also, the linear expansion coefficient is 17 × 10 ⁻⁶ / ° C.

  The electronic device 110 can achieve the same effect as the electronic device 100. Furthermore, the electronic device 110 can be made smaller than the electronic device 100 because only the filled vias 31 to 28 are formed as interlayer connection members.

(Third embodiment)
As shown in FIG. 6, the electronic device 120 is different from the electronic device 100 in that the sealing resin 50, the circuit element 70, and the solder 80 are not provided. That is, the electronic device 120 corresponds to the multilayer substrate described in the first embodiment. The electronic device 120 can achieve the same effect as the electronic device 100.

(Fourth embodiment)
As shown in FIG. 7, the electronic device 130 is different from the electronic device 100 in that the multilayer substrate is mounted on one side. The electronic device 130 is also different from the electronic device 100 in that the sixth buildup layer 16 and the tenth layer wiring L10 are not formed. The electronic device 130 can achieve the same effect as the electronic device 100.

(Fifth embodiment)
As shown in FIG. 8, the electronic device 140 is different from the electronic device 100 in that the first core layer 17 a to the third core layer 17 c are not formed. That is, in the electronic device 140, only the first buildup layer 11 to the sixth buildup layer 16 are formed as the resin base material. The electronic device 140 can achieve the same effect as the electronic device 100. In the electronic device 140, the first layer wiring L1 and the seventh layer wiring L7 correspond to the surface layer wiring. Therefore, in the electronic device 140, the code L7a is a land.

  11-16 First buildup layer to sixth buildup layer, 17a to 17c First core layer to third core layer, 21-24 Conformal via, 31 to 34 Filled via, L1 to L10 First layer wiring to tenth Layer wiring, L1a, L7a, L10a land, 40 through via, 50 sealing resin, 60 solder resist, 61 opening, 70 circuit element, 71 electrode, 80 solder, 100-140 electronic device, 200 engine room, 210 automatic transmission , 220 Torque converter, S1 side, S2 opposite side

Claims (5)

A plurality of wirings (L1 to L10) stacked via electrically insulating resin base materials (11 to 16, 17a to 17c);
A part of the surface layer wiring (L1, L10) provided on the surface layer of the resin base material among the plurality of wirings, and a mounted portion (L1a, L10a) on which the circuit element (70) can be mounted;
Fills the hole provided in the surface layer resin portion (11, 12) between the surface layer wiring in the resin base material and the second layer wiring (L2, L9) provided in the next layer of the surface layer wiring. And filled vias (31 to 34) electrically and mechanically connecting the mounted portion and the second layer wiring,
The electronic device in which the linear expansion coefficient of the surface layer resin portion in the wiring lamination direction is the same as the linear expansion coefficient of the filled via.   2. The electronic device according to claim 1, wherein the resin base material has the same linear expansion coefficient as that of the filled via in the entire linear expansion coefficient including the surface resin portion.   It is formed in the wall surface of the hole without filling the hole provided in the inner layer resin part (13 to 16) different from the surface layer resin part in the resin base material, and between the two wirings sandwiching the inner layer resin part The electronic device according to claim 1, further comprising: conformal vias (21 to 24) that electrically and mechanically connect each other. The circuit element (70) mounted on the mounted portion;
The electronic device according to claim 1, further comprising: a sealing resin portion (50) that integrally seals the surface layer, the surface layer wiring, and the circuit element.   5. The electronic device according to claim 1, wherein the resin base material includes a core layer (17 a to 17 c) and a build-up layer including the surface layer resin portion.

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