JP2016038920A - Semiconductor device and semiconductor system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily and optimally set the number of banks and a page size for each application.SOLUTION: A semiconductor system comprises a semiconductor device, and a control device connected to the semiconductor device via a system bus. The control device comprise an application control unit to control applications, and a setting unit to set, for the semiconductor device in accordance with the applications, one of a plurality of different page sizes and one of a plurality of different numbers of banks.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device and a semiconductor system.

  In a computer system, the optimal page size often varies depending on the application. For example, in an application that handles data with high spatial locality (the possibility of referencing nearby data is high), the page hit rate can be improved and the access efficiency can be improved by storing the data in a large-sized page. Can be improved.

  On the other hand, in applications that handle data with low spatial locality (the possibility of referring to nearby data is low), the randomness of the access pattern is often high. Similarly, when a plurality of applications and threads are distributed and executed on a plurality of cores using a multi-core CPU (Central Processing Unit), the randomness of the access pattern is often high. In that case, increasing the page size does not contribute to the improvement of the page hit rate. Therefore, the access efficiency of bank interleaving can be improved by increasing the number of banks. Bank interleaving refers to sequentially accessing different memory banks.

  By the way, in recent years, an STT-RAM (Spin Transfer Torque-Random Access Memory) which is a kind of MRAM (Magnetoresistive Random Access Memory) is expected to be applied as a main memory. In addition, a technique for improving the access efficiency of the STT-RAM has been proposed (Patent Document 1).

  Patent Document 1 discloses a technique for shortening the writing time of the STT-RAM. In the technique disclosed in Patent Literature 1, in order to shorten the writing time, writing in a current direction that requires a long time for writing is performed on the target memory cell before the write data is determined.

JP 2008-310876 A

  The disclosure of the above prior art document is incorporated herein by reference. The following analysis was made by the present inventors.

  In the STT-RAM, the page size and the number of banks are not standardized. Further, Patent Document 1 does not disclose improvement of the page hit rate and improvement of bank interleave access efficiency.

  According to a first aspect of the present invention, there is provided a semiconductor system including a semiconductor device and a control device connected to the semiconductor device via a system bus, wherein the control device controls application. And a setting unit that sets, in the semiconductor device, one page size among a plurality of different page sizes and one number of banks out of a plurality of different bank sizes in accordance with the application A semiconductor system is provided.

  According to a second aspect of the present invention, a memory cell array having a plurality of pages and a plurality of banks, and an information storage area, the information storage area of the memory cell array has a plurality of page sizes and a plurality of pages. A semiconductor device is provided that stores the information in the information storage area in association with each other.

  According to each aspect of the present invention, there are provided a semiconductor device, a semiconductor system, and a semiconductor device writing method that contribute to easily and optimally setting the number of banks and the page size for each application.

It is a block diagram which shows the structure of the semiconductor device which concerns on one Embodiment. It is a block diagram which shows the structure of a semiconductor system. It is a block diagram which shows the structure of a semiconductor device control block. It is a block diagram which shows the whole structure of a semiconductor device. It is a figure which shows an example of combinations, such as page size set to a mode register, the number of banks. It is a figure which shows an example of arrangement | positioning of the block in a chip | tip. It is a figure which shows an example of a structure of one area | region in a block. It is a figure which shows the memory cell array and the peripheral module of a memory cell array. It is a figure which shows an example of a block control circuit. It is a figure which shows an example of the production | generation of a column selection signal. It is a figure which shows an example of the production | generation of a row activation signal. It is a figure which shows an example of the production | generation of a column activation signal.

  First, an outline of an embodiment will be described with reference to FIG. Note that the reference numerals of the drawings attached to the outline are attached to the respective elements for convenience as an example for facilitating understanding, and the description of the outline is not intended to be any limitation.

  FIG. 1 is a block diagram showing an example of the internal configuration of the semiconductor system 500. The semiconductor system 500 includes a semiconductor device 502 and a control device 501 connected to the semiconductor device 502 via a system bus.

  The control device 501 includes an application control unit 511 and a setting unit 512. The application control unit 511 controls an application. The setting unit 512 sets, in the semiconductor device 502, one page size among a plurality of different page sizes and one bank number among a plurality of different bank sizes, depending on the application. Therefore, the semiconductor system 500 contributes to easily and optimally setting the number of banks and the page size for each application.

[First Embodiment]
Next, the first embodiment will be described in detail. In the following description, the above-described application control unit is referred to as a multi-core processor.

(Configuration of the first embodiment)
FIG. 2 is a block diagram showing a configuration of the semiconductor system 200.

  The semiconductor system 200 includes a semiconductor device 100 and a multi-core processor 230.

  The multi-core processor 230 includes a core_1 to a core_n (231a to 231n), an I / O 232, a semiconductor device control block 233, and an on-chip memory 234. The core_1 to core_n (231a to 231n), the semiconductor device control block 233, and the on-chip memory 234 are connected via a processor internal bus 235. The semiconductor device control block 233 controls the semiconductor device 100 by exchanging command signals, address signals, clock signals, and data signals with the semiconductor device 100.

  The semiconductor device 100 includes a memory cell array 101 and an information storage area 102. The memory cell array 101 has a plurality of pages and a plurality of banks. The information storage area 102 stores information on a plurality of page sizes and a plurality of banks.

  Specifically, the information storage area 102 includes a page size included in the plurality of page sizes, a number of banks included in the plurality of banks, based on a condition that a product of the page size and the number of banks is constant. Are stored in association with each other.

  FIG. 3 is a block diagram showing a configuration of the semiconductor device control block 233.

  The semiconductor device control block 233 includes a control logic unit 410, a command generation unit 421, an address generation unit 422, a data output unit 423, and a data input unit 242. The control logic unit 410 controls the command generation unit 421, the address generation unit 422, the data output unit 423, and the data input unit 424.

  The command generation unit 421 supplies a command signal to the semiconductor device 100. The address generation unit 422 supplies an address signal to the semiconductor device 100. The data output unit 423 writes a data signal to the semiconductor device 100 and supplies it as a data signal. The data input unit 424 reads a data signal from the semiconductor device 100 and acquires it as a data signal.

  The control logic unit 410 includes a state machine 411, an access queue 412, a scheduler 413, and a setting unit 414.

  The state machine 411 controls the entire semiconductor device control block 233. The access queue 412 accumulates access requests. The scheduler 413 controls the access order.

  The setting unit 414 sets the bank address, the number of column addresses, the page size, and the number of banks. Then, the semiconductor device control block 233 controls the semiconductor device 100 based on the set bank address, the number of column addresses, the page size, and the number of banks.

  Hereinafter, the setting unit 414 will be described in detail.

  The setting unit 414 sets, in the semiconductor device 100, one page size among a plurality of different page sizes and one bank number among a plurality of different bank numbers, depending on the application. . Specifically, the setting unit 414 has a plurality of combinations of the page size and the number of banks, and sets one combination from the plurality of combinations in the semiconductor device 100.

  More specifically, the setting unit 414 determines the page size included in the plurality of page sizes, the number of banks included in the plurality of banks based on the condition that the product of the page size and the number of banks is constant. Are associated with each other. Then, the setting unit 414 selects one page size among the plurality of page sizes and one bank number among the plurality of banks based on the association.

  Here, the plurality of page sizes may include a first page size and a second page size smaller than the first page size. The plurality of bank numbers may include a first bank number and a second bank number smaller than the first bank number. In this case, the setting unit 414 sets the second number of banks in the semiconductor device 100 when setting the first page size in the semiconductor device 100 according to the application. The setting unit 414 sets the first bank number in the semiconductor device 100 when setting the second page size in the semiconductor device 100.

  For example, the page size and the number of banks that are optimal for the application may be set as attribute information for the application. Further, the application creator may set (input) a page size and a bank number that are optimal for the application.

  Next, the semiconductor device 100 will be described in detail. In the following description, the information storage area 102 is referred to as a mode register 20.

  FIG. 4 is a block diagram showing the overall configuration of the semiconductor device 100 according to the present embodiment. In the following description, it is composed of seven bank addresses (BA6 to BA0), 14 row addresses (X13 to X0), 11 column addresses (Y10 to Y0), and an 8-bit data input / output terminal DQ. The semiconductor device 100 will be described. However, this is not intended to limit the bank address, the number of bits of the column address, and the capacity in the semiconductor device 100 according to the present embodiment.

  The semiconductor device 100 includes external clock terminals CK and / CK, a clock enable terminal CKE, command terminals / CS, / RAS, / CAS, / WE, and a data input / output terminal DQ as external terminals. In the present specification, a signal having “/” at the beginning of a signal name means an inverted signal of the corresponding signal or a low active signal. Therefore, CK and / CK are complementary signals.

  The clock generation circuit 23 receives external clock signals CK and / CK and a clock enable signal CKE, and the clock generation circuit 23 generates an internal clock signal required inside the semiconductor device 100 and supplies it to each unit.

  The command terminals / CS, / RAS, / CAS, / WE are supplied with a chip select signal / CS, a row address strobe signal / RAS, a column address strobe signal / CAS, and a write enable signal / WE, respectively. These command signals are supplied to the command decoder 22. The command decoder 22 decodes the input command signal and supplies it to the chip control circuit 21.

  The mode register 20 sets the operation mode of the semiconductor device 100. Details of the mode register 20 will be described later.

  The chip control circuit 21 inputs the output of the command decoder 22 and the operation mode set in the mode register 20, generates various control signals based on them, and generates block control circuits 12a to 12h, RW (read / write) amplifiers. 14, the parallel / serial conversion circuit 15, the column address buffer 17, the row address buffer 18, and the bank address buffer 19.

  The address signal includes bank addresses BA6 to BA0 that specify banks, row addresses X13 to X0 that specify word lines, and column addresses Y10 to Y0 that specify bit lines. Of the address signals, the bank addresses BA6 to BA0 are supplied to the bank address buffer 19, the row addresses X13 to X0 are supplied to the row address buffer 18, and the column addresses Y10 to Y0 are supplied to the column address buffer 17. Although not particularly limited, the row addresses X13 to X0 and the column addresses Y10 to Y0 are input in an address multiplex format using common address signals A13 to A0.

  The semiconductor device 100 includes a memory cell array / sense amplifier (2a to h). The memory cell array / sense amplifiers (2a to 2h) are connected to the row / column decoder 13, the main amplifier 11, and the block control circuits (12a to 12h), respectively. In other words, the block control circuit 12, the row / column decoder 13, the memory cell array / sense amplifier 2, and the main amplifier 11 are divided into eight blocks (blocks 0 to 7). In the following description, each memory cell array / sense amplifier (2a-h) is referred to as a memory cell array / sense amplifier 2 when it is not necessary to distinguish between them. In the following description, each block control circuit (12a to 12h) is referred to as a block control circuit 12 when it is not necessary to distinguish between them.

  In the semiconductor device 100 according to the present embodiment, one sense amplifier corresponds to N (N is an integer of 1 or more) bit lines. Then, N bit lines are selectively connected to the sense amplifier with Log2 (N) row addresses.

  The bank address buffer 19 outputs the bank address to the corresponding block control circuits 12a to 12h according to the bank address.

  The row address buffer 18 outputs a row address. The row address output from the row address buffer 18 is decoded by the row / column decoder 13, and one of the word lines is selected in accordance with the decoding.

  The column address output from the column address buffer 17 is decoded by the row / column decoder 13, and a bit line corresponding to the column address is selected from the plurality of bit lines in accordance with the decoding.

  64 I / O lines (I / O line pair (64 bits) 89 shown in FIG. 4) connect the main amplifier 11 and the RW (read / write) amplifier 14.

  The RW amplifier 14 is a read amplifier circuit and a write amplifier circuit connected to a data input / output terminal DQ which is an external terminal via a parallel / serial conversion circuit 15 and a data input / output buffer 16.

  The RW amplifier 14 inputs / outputs 8-bit data as burst data from the data input / output terminal DQ via the parallel / serial conversion circuit 15 in accordance with the column addresses Y2 to Y0. The parallel / serial conversion circuit 15 and the data input / output buffer 16 are supplied with an internal clock signal from the clock generation circuit 23 to control the timing of data input / output between the memory cell array and the data input / output terminal DQ. .

  Next, the mode register 20 will be described in detail.

  In the semiconductor device 100 according to the present embodiment, the mode register 20 sets the combination of the bank address and the column address so that the sum of the bank address number and the column address number is constant. As a result, the mode register 20 can change the combination of the number of banks and the page size under the condition “number of banks × page size = constant”.

  FIG. 5 is a diagram showing an example of a combination of page size, bank number, bank address, row address, and column address set in the mode register 20.

  In the mode register 20 shown in FIG. 5, the number of banks, the page size, the number of bank addresses, and the number of column addresses are determined by a combination of values of the Az, Ay, and Ax fields. For example, in FIG. 5, it is assumed that 0, 0, and 0 are set in Az, Ay, and Ax. FIG. 5 shows that in this case, the chip configuration is set such that the number of banks is 4, the page size is 2048 bytes, the bank addresses are 2 (BA1 to BA0), and the column addresses are 11 (Y10 to Y0). Show. FIG. 5 shows that the setting signals CF4 to CF0 are set to 0, 0, 0, 0, 0 in order to realize this configuration.

  For example, assume that 1, 0, 1 are set in the Az, Ay, Ax fields. FIG. 5 shows that in that case, the chip configuration is set such that the number of banks is 128, the page size is 64 bytes, the bank address is 7 (BA6 to BA0), and the column address is 6 (Y5 to Y0). Show. FIG. 5 shows that the setting signals CF4 to CF0 are set to 1, 1, 1, 1, 1 in order to realize this configuration. Details of the chip configuration change using CF4 to CF0 will be described later.

  FIG. 6 is a diagram illustrating an example of the arrangement of blocks in a chip. As shown in FIG. 6, the chip of the semiconductor device 100 has a configuration of 8 blocks (blocks 0 to 7, 30a to 30h), and two rows of row decoders 31 with a column decoder 32 sandwiched in one direction in the center of each block. Be placed. A main amplifier 33 is arranged in the center of each block and in a direction intersecting with the column decoder 32 and the row decoder 31.

  Each block (30a to 30h) includes four areas divided by the column decoder 32, the row decoder 31, and the main amplifier 33. In each area, four minimum bank areas 41 are arranged. The In each minimum bank area 41, a sense amplifier 34 and a memory cell array are arranged. On the other hand, an area corresponding to two blocks is the maximum bank area 40.

  For example, when “0, 0, 0” is set in the Ax, Ay, and Az fields shown in FIG. 5 and the number of banks is 4 and the page size is 2048 bytes, the bank area is maximum, One bank has a 256 Mbit configuration. On the other hand, when “1, 0, 1” is set in the Ax, Ay, Az fields shown in FIG. 5 and the number of banks is 128 and the page size is configured to 64 bytes, the bank area is minimum, One bank has an 8M bit configuration.

  FIG. 7 is a diagram illustrating an example of the configuration of one area among the areas divided by the column decoder 32, the row decoder 31, and the main amplifier 33 in each of the blocks (30a to 30h) illustrated in FIG. . 7 is a diagram obtained by rotating the area divided by the column decoder 32 and the row decoder 31 and the main amplifier 33 shown in FIG. 6 by 90 degrees.

  The area shown in FIG. 7 includes four minimum bank areas 41. In each minimum bank area 41, a row decoder 31 is arranged at the bottom with a column decoder 32 interposed therebetween. In addition, a sense amplifier 34 is arranged in a direction crossing the row decoder 31 at the center of each minimum bank area 41. In the minimum bank area 41 shown in FIG. 7, the memory cell array is divided into eight in the direction facing the row decoder 31. In addition, the sub word driver 50 is arranged at both ends of each minimum bank area 41 and in a direction intersecting with the sense amplifier 34. That is, the sub word driver 50 is arranged in the direction intersecting with the sense amplifier 34 with the memory cell array interposed therebetween. Thus, by arranging the memory cell array and the sub word driver 50, it is possible to prevent the rise and fall of the voltage change of the word line from being reduced when the word line is selected.

  Each area shown in FIG. 7 is arranged with the main amplifier 33 interposed therebetween, and the main amplifier 33 is shared by the four minimum bank areas 41 arranged on both sides of the main amplifier 33.

  The row decoder 31 holds the selected state of the selected word line when the corresponding bank is in the active period. The sense amplifier 34 maintains an active state when the corresponding bank is in the active period. As a result, paying attention to the minimum bank area 41, the minimum bank area 41 includes functions necessary for operating independently as a bank. Specifically, the minimum bank area 41 can operate as an independent bank having a page size of 64 bytes. For example, when the page size is set to 128 bytes and the number of banks is set to 64, the two minimum bank areas 41 may be controlled as one bank. The page size and the number of banks can be changed by changing the combination of the bank address and the column address.

  FIG. 8 shows memory cell arrays 61-1-0 to 61-1-511, 61-2-0 to 61-2511 as a part of the memory cell array shown in FIG. Memory cell arrays 61-1-0 and 61-2-0 correspond to the lowermost sense amplifier 34 in the memory cell array shown in FIG. The memory cell arrays 61-1-511 and 61-2-511 correspond to the uppermost sense amplifier 34 in the memory cell array shown in FIG. In the following description, a memory cell array composed of 1024 word lines, 8 normal bit lines, and one reference bit line will be described as an example. Hereinafter, each memory cell array (61-1-0 to 61-1-511, 61-2-0 to 61-2511) is referred to as a memory cell array 61 when it is not necessary to distinguish between them.

  Each memory cell array 61 includes a normal cell and a reference cell. Specifically, each memory cell array 61 includes 1024 × 8 normal cells and 1024 reference cells.

  For accessing the memory cells included in each memory cell array 61, 1024 word lines and 9 bit lines are used.

  Of the 9 bit lines, 8 bit lines are used as bit lines for accessing normal cells. Of the nine bit lines, one bit line is used as a reference bit line for accessing a reference cell.

  512 sense amplifiers SA (34-0 to 34-) are provided between the memory cell array (61-1-0 to 61-1-511) and the memory cell array (61-2-0 to 61-2511). 511) and 512 column selection circuits CSW (73-0 to 73-511) are arranged. Hereinafter, the sense amplifiers SA (34-0 to 34-511) are referred to as sense amplifiers 34 when it is not necessary to distinguish them. Hereinafter, each column selection circuit CSW (73-0 to 73-511) is referred to as a column selection circuit 73 when it is not necessary to distinguish between them.

  The selectors SEL (71-1-0 to 71-1-511, 71-2-0 to 71-2511) are arranged for each memory cell array 61. The selector 71 selects one of the normal bit connected to the sense amplifier 34 and the reference bit line. Eight normal bit lines and one reference bit line are connected to the sense amplifier 34.

  The selectors SEL (71-1-0 to 71-1-511) are connected to the memory cell arrays (61-1-0 to 61-1-511) and are connected to the memory cell arrays (61-1-0 to 61-61), respectively. One of the normal bit line and the reference bit line of (-1-511) is selected.

  The selectors SEL (71-2-0 to 71-2511) are connected to the memory cell arrays (61-2-0 to 61-2511), and are connected to the memory cell arrays (61-2-0 to 61-61), respectively. 2-511) One of the normal bit line and the reference bit line is selected. Hereinafter, the selectors SEL (71-1-0 to 71-1-511, 71-2-0 to 71-2511) are referred to as selectors 71 when it is not necessary to distinguish them.

  The row decoder 31-1 includes a row decoder 31-1-1 that receives row addresses X9 to X0 and a row decoder 31-1-2 that receives row addresses X13 to X10. On the other hand, the row decoder 31-2 includes a row decoder 31-2-1 that receives row addresses X9 to X0 and a row decoder 31-2-2 that receives row addresses X13 to X10. .

  When the row address X13 is 0 (ie, low level), the row decoder 31-1-2 selects one of the normal bit lines, and the row decoder 31-2-2 selects the reference bit line. On the other hand, when the row address X13 is 1 (ie, high level), the row decoder 31-1-2 selects the reference bit line, and the row decoder 31-2-2 selects one of the normal bit lines. To do. As a result, the normal bit line is connected to one input of the sense amplifier 34, and the reference bit line is connected to the other input.

  Among the row decoders 31-1, the row decoder 31-1-1 starts from 1024 word lines extending the memory cell arrays (61-1-0 to 61-1-511) based on the row addresses X9 to X0. One word line is selected.

  Similarly, among the row decoders 31-2, the row decoder 31-2-1 extends 1024 memory cell arrays (61-2-0 to 61-2511) based on the row addresses X9 to X0. One word line is selected from the word lines. Here, the word line selected by the row decoder 31-1-1 and the word line selected by the row decoder 31-2-1 are symmetrical with respect to the sense amplifier 34.

  The column decoder 32 decodes the column addresses Y5 to Y3, drives one of the column selection lines, and controls the column selection circuit 73. Further, the column decoder 32 converts 64 sense amplifiers out of 512 sense amplifiers 34 into 64 local IO lines (LIO lines), that is, I / O line pairs (64 bits) 89 shown in FIG. Connect to.

  The block control circuits 12a to 12h generate 128 row activation signals RA0 to RA127 and 128 column activation signals CA0 to CA127. In the minimum bank area, the row activation signals RA0 to RA127, 128 are generated. The column activation signals CA0 to CA127 are supplied.

  When row activation signals RA0-RA127 are at a high level, row decoder 31 in the corresponding minimum bank area is activated. Further, when the row decoder 31 is activated, the sense amplifier 34 is controlled to be activated.

  When the column activation signals CA0 to CA127 are at a high level, the column decoder 32 in the corresponding minimum bank area is activated. Further, when the column decoder 32 is activated, the column selection circuit 73 controls to connect the sense amplifier 34 and the local IO line.

  Next, the block control circuit 12 will be described in detail with reference to FIGS.

  First, the bank selection circuits 91a to 91e will be described with reference to FIG. The bank selection circuit 91a includes an inverter circuit INV01, PMOS transistors P11 to P14, and NMOS transistors N11 to N14.

  The source of the PMOS transistor P11 and the source of the NMOS transistor N11 are connected in common and connected to the power supply VDD. Further, the source of the PMOS transistor P12 and the source of the NMOS transistor N12 are commonly connected, and the bank address BA2 is connected.

  The gate of the PMOS transistor P11 and the gate of the NMOS transistor N12 are commonly connected, and the setting signal CF0 is connected. The gate of the NMOS transistor N11 and the gate of the PMOS transistor P12 are connected in common, and the inverted signal / CF0 of CF0 is connected. Further, the drains of the PMOS transistors P11 and P12 and the drains of the NMOS transistors N11 and N12 are connected in common, and the bank selection signal BS2 is connected.

  The source of the PMOS transistor P13 and the source of the NMOS transistor N13 are connected in common, and the power supply VDD is connected. The source of the PMOS transistor P14 and the source of the NMOS transistor N14 are connected in common, and the inverted signal / BA2 of the bank address BA2 is connected.

  The gate of the PMOS transistor P13 and the gate of the NMOS transistor N14 are commonly connected, and the setting signal CF0 is connected. Further, the gate of the NMOS transistor N13 and the gate of the PMOS transistor P14 are connected in common, and the inverted signal / CF0 of CF0 is connected. Further, the drains of the PMOS transistors P13 and P14 and the drains of the NMOS transistors N13 and N14 are connected in common, and the inverted signal / BS2 of the bank selection signal BS2 is connected.

  Therefore, when the setting signal CF0 is at a high level, the bank address BA2 is output as the bank selection signal BS2, and the inverted signal / BA2 of BA2 is output as the inverted signal / BS2 of the bank selection signal BS2. On the other hand, when the setting signal CF0 is at the low level, the power supply VDD is output to the bank selection signal BS2 and the inverted signal / BS2.

  The bank selection circuits 91b to 91e have the same configuration as the bank selection circuit 91a. Therefore, the bank addresses BA3 to BA6 or the power supply VDD is output to the bank selection signals BS3 to BS6 according to the setting signals CF1 to CF4. Since the details of the bank selection circuits 91b to 91e are the same as those of the bank selection circuit 91a, detailed description thereof is omitted.

  Next, the column selection signal control circuits 92a to 92e will be described with reference to FIG. The column selection signal control circuit 92a includes an inverter circuit INV02, PMOS transistors P21 to P24, and NMOS transistors N21 to N24.

  The difference between the block control circuit 91a shown in FIG. 9 and the column selection signal control circuit 92a shown in FIG. 10 is that the column address is connected to the sources of the PMOS transistor P21 and the NMOS transistor N21, to which the setting signal CF0 is connected at the gate. A point where Y10 is connected and a point where the inverted signal / Y10 of the column address Y10 is connected to the sources of the PMOS transistor P23 and the NMOS transistor N23 to which the setting signal CF0 is connected at the gate. In the column selection signal control circuit 92a, the drains of the PMOS transistors P21 and P22 and the drains of the NMOS transistors N21 and N22 are connected to the column selection signal CS2. The drains of the PMOS transistors P23 and P24 and the drains of the NMOS transistors N23 and N24 are connected to the inverted signal / CS2 of the column selection signal CS2.

  In the column selection signal control circuit 92a, when the setting signal CF0 is at a high level, the bank address BA2 is output as the column selection signal CS2, and the inverted signal / BA2 of BA2 is output as the inverted signal / CS2 of the column selection signal CS2. . On the other hand, in the column selection signal control circuit 92a, when the setting signal CF0 is at the low level, the column address Y10 is output to the column selection signal CS2, and the inverted signal / Y10 of the column address Y10 is the inverted signal / CS2 of the column selection signal CS2. Is output.

  The column selection signal control circuits 92b to 92e have the same configuration as the column selection signal control circuit 92a. Therefore, the bank addresses BA3 to BA6 or the column addresses Y9 to Y6 are output to the column selection signals CS2 to CS6 according to the setting signals CF1 to CF4.

  Next, the row activation signals RA0 to RA127 will be described with reference to FIG.

  The AND circuit AND01-1 shown in FIG. 11 receives the bank address inversion signals / BA0 and / BA1 and the bank selection signal inversion signals / BS2 to / BS6, and outputs a row activation signal RA0. Similarly, a logical product circuit (AND01−) that receives seven signals among the bank addresses BA0 and BA1, and the inverted signals / BA0 and / BA1, the bank selection signals BS2 to BS6, and the inverted signals / BS2 to / BS6. 0-AND01-127) output row activation signals RA0-RA127.

  Next, column activation signals CA0 to CA127 will be described with reference to FIG.

  The AND circuit AND02-1 shown in FIG. 12 receives the bank address inversion signals / BA0 and / BA1 and the column selection signal inversion signals / CS2 to / CS6, and outputs the column activation signal CA0. Similarly, an AND circuit (AND02-0) that inputs seven signals out of the bank addresses BA0 and BA1, and the inverted signals / BA0 and / BA1, the column selection signals CS2 to CS6, and the inverted signals / CS2 to / CS6. To AND02-127) output column activation signals CA0 to CA127.

  Hereinafter, the determination of the bank configuration will be described in detail with reference to the setting of the mode register shown in FIG.

  For example, referring to FIG. 5, when the number of banks is 4, the setting signal (CF0, CF1, CF2, CF3, CF4) = (0, 0, 0, 0, 0). That is, all the setting signals CF0 to CF4 are at the low level. When (CF0, CF1, CF2, CF3, CF4) = (0, 0, 0, 0, 0) is input to the bank selection circuits 91a to 91e shown in FIG. The power supply voltage VDD is output to the signals / BS2 to / BS6. Then, the word line and the sense amplifier 34 are activated in all the minimum bank areas in the maximum bank area composed of 32 minimum bank areas. As a result, the page size is 2048 bytes, and a 4-bank configuration selected by the bank addresses BA1 to BA0 can be realized.

  When (CF0, CF1, CF2, CF3, CF4) = (0, 0, 0, 0, 0) is input to the column selection signal control circuits 92a to 92e shown in FIG. 10, the column selection signals CS2 to CS6, The column addresses Y10 to Y6 and the inverted signals / Y10 to / Y6 are output to the inverted signals / CS2 to / CS6. In the bank selected by the bank addresses BA1 to BA0, 64 sense amplifiers 34 selected by the column addresses Y10 to Y3 are connected to the local IO lines. As a result, page mode access is possible for the bank selected by the bank addresses BA1 to BA0.

  Further, for example, referring to FIG. 5, when the number of banks is 128, the setting signal (CF0, CF1, CF2, CF3, CF4) = (1, 1, 1, 1, 1). That is, all of the setting signals CF0 to CF4 are at a high level. When (CF0, CF1, CF2, CF3, CF4) = (1, 1, 1, 1, 1) is input to the bank selection circuits 91a to 91e shown in FIG. Bank addresses BA2 to BA6 and inverted signals / BA2 to / BS6 are output as signals / BS2 to / BS6. Then, the word line and the sense amplifier 34 are activated in the minimum bank area including one minimum bank area. As a result, the page size is 64 bytes, and a 128 bank configuration selected by the bank addresses BA6 to BA0 can be realized.

  When (CF0, CF1, CF2, CF3, CF4) = (1, 1, 1, 1, 1) is input to the column selection signal control circuits 92a to 92e shown in FIG. 10, the column selection signals CS2 to CS6, The bank addresses BA2 to BA6 and the inverted signals / BA2 to / BA6 are output to the inverted signals / CS2 to / CS6. In the bank selected by the bank addresses BA6 to BA0, 64 sense amplifiers 34 selected by the column addresses Y5 to Y3 are connected to the local IO line. As a result, page mode access is possible to the bank selected by the bank addresses BA6 to BA0.

  As described above, according to the semiconductor system 200 according to the present embodiment, the combination of the bank address number and the column address number is set in the semiconductor device 100.

  According to the semiconductor system 200 according to the present embodiment, the combination of the number of bank addresses and the number of column addresses is set in the semiconductor device 100 so that the sum of the number of bank addresses and the number of column addresses is constant.

  According to the semiconductor system 200 according to the present embodiment, the combination of the number of banks and the page size can be changed under the condition “number of banks × page size = constant”. Therefore, the semiconductor system 200 according to the present embodiment contributes to easily and optimally setting the number of banks and the page size for each application. Therefore, the semiconductor system 200 according to the present embodiment contributes to improving memory access.

  The semiconductor system 200 according to the present embodiment is described above using an STT-RAM (Spin Transfer Torque-Random Access Memory). However, the present invention is not limited to this, and the DRAM, PCRAM, ReRAM, Flash Memory, and NAND Memory are not limited thereto. The present invention may be applied to various memories.

  The disclosure of the above patent document is incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiment can be changed and adjusted based on the basic technical concept. Further, various combinations or selections of various disclosed elements (including each element of each claim, each element of each embodiment, each element of each drawing, etc.) are possible within the framework of the entire disclosure of the present invention. is there. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea. In particular, with respect to the numerical ranges described in this document, any numerical value or small range included in the range should be construed as being specifically described even if there is no specific description.

2a to 2h Memory cell array / sense amplifier 11, 33 Main amplifiers 12a to 12h Block control circuit 13 Row / column decoder 14 RW amplifier 15 Parallel / serial conversion circuit 16 Data input / output buffer 17 Column address buffer 18 Row address buffer 19 Bank address buffer 20 Mode register 21 Chip control circuit 22 Command decoder 23 Clock generation circuit 30a-30h Block 0-7
31, 31-1-1, 31-1-2, 31-2-1, 31-2-2 Row decoder 32 Column decoder 34, 34-0 to 34-511 Sense amplifier 40 Maximum bank area 41 Minimum bank area 50 Sub-word drivers 61-1-0 to 61-1-511, 61-2-0 to 61-2511, 101 memory cell arrays 71-1-0 to 71-1-511, 71-2-0 to 71-2 -511 Selector 73-0 to 73-511 Column selection circuit 89 I / O line pair (64 bits)
91a to 91e Bank selection circuits 92a to 92e Column selection signal control circuits 100 and 502 Semiconductor device 102 Information storage area 200 and 500 Semiconductor system 230 Multi-core processors 231a to 231n Cores 1 to n
232 I / O line pairs (64 bits)
233 Semiconductor device control block 234 On-chip memory 235 Processor internal bus 410 Control logic unit 411 State machine 412 Access queue 413 Scheduler 414, 512 Setting unit 421 Command generation unit 422 Address generation unit 423 Data output unit 424 Data input unit 501 Control device 511 Application control unit 512 Setting units AND01-0 to AND01-127, AND02-0 to AND02-127 AND circuits INV01, INV02 Inverter circuits N11 to N14, N21 to N24 NMOS transistors P11 to P14, P21 to P24 PMOS transistors A0 to A13 Address signals BA0 to BA6, / BA2 to / BA6 Bank addresses BS2 to BS6, / BS2 to / BS6 Bank selection signals CA0 to CA 127 Column activation signal CF0 to CF4 Setting signal CK, / CK External clock terminal CKE Clock enable terminal / CS, / CAS, / RAS, / WE Command terminals CS2 to CS6, / CS2 to / CS6 Column selection signal DQ Data input / output Terminal LIO Local IO lines RA0 to RA127 Row activation signals X0 to X13 Row addresses Y0 to Y13, / Y6 to / Y10 Column address VDD Power supply

Claims (13)

A semiconductor system including a semiconductor device and a control device connected to the semiconductor device via a system bus,
The controller is
An application control unit for controlling the application;
In accordance with the application, a setting unit that sets one page size among a plurality of different page sizes and one bank number among a plurality of different bank numbers in the semiconductor device,
A semiconductor system comprising:   The semiconductor system according to claim 1, wherein the setting unit has a plurality of combinations of page size and number of banks according to the application, and sets one combination from the plurality of combinations in the semiconductor device.   The setting unit associates a page size included in the plurality of page sizes and a bank number included in the plurality of banks based on a condition that a product of a page size and the number of banks is constant. The semiconductor system according to claim 1, wherein one page size of the plurality of page sizes and one bank number of the plurality of banks are selected based on the association. The plurality of page sizes includes a first page size and a second page size that is smaller than the first page size;
The plurality of banks includes a first bank number and a second bank number smaller than the first bank number;
The setting unit sets the second number of banks in the semiconductor device and sets the second page size in the semiconductor device when the first page size is set in the semiconductor device according to the application. 4. The semiconductor system according to claim 1, wherein the first bank number is set in the semiconductor device. The semiconductor device includes:
A memory cell array having a plurality of pages and a plurality of banks;
An information storage area,
5. The semiconductor system according to claim 1, wherein the information storage area stores information on the plurality of page sizes and the plurality of banks.   6. The semiconductor according to claim 5, wherein the information storage area stores, in association with each other, a page size included in the plurality of page sizes and a number of banks included in the plurality of banks based on the condition. system. A memory cell array having a plurality of pages and a plurality of banks;
An information storage area,
The information storage area is a semiconductor device that stores the plurality of page sizes and the plurality of banks included in the memory cell array in association with each other.   The information storage area includes a page size included in the plurality of page sizes and a bank number included in the plurality of banks based on a condition that a product of a page size and the number of banks is constant. The semiconductor device according to claim 7, which is stored in association with each other. The memory array is
A plurality of word lines and a plurality of bit lines;
A plurality of memory cells, each of which is arranged at an intersection of each word line and each bit line and used as either a normal cell or a reference cell,
One bit line of the plurality of bit lines is used as a reference bit line for accessing the reference cell;
9. The semiconductor device according to claim 7, wherein another bit line of the plurality of bit lines is used as a normal bit line for accessing the normal cell.   10. The semiconductor device according to claim 9, further comprising a selector connected to the memory cell array, wherein one of the normal bit line and the reference bit line is selected and another bit is not selected. .   The semiconductor device according to claim 7, further comprising a block control circuit that supplies a plurality of row activation signals and a plurality of column activation signals to the memory array.   The block control circuit generates the plurality of row activation signals in response to receiving a setting signal generated based on information stored in the information storage area, a bank address, and a power supply signal. The semiconductor device according to claim 11.   The semiconductor device according to claim 12, wherein the block control circuit generates the plurality of column activation signals in response to receiving the setting signal, the bank address, and the power supply signal.

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