JP2016015374A - Semiconductor laminate structure and semiconductor element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor laminate structure having a nitride semiconductor layer which is high in quality on a gallium oxide substrate and excellent in uniformity within a plane, and a semiconductor element having the semiconductor laminate structure.SOLUTION: A semiconductor laminate structure 1 has a GaOsubstrate 2, a dielectric layer 3 which is formed partially in contact with the upper surface of the GaOsubstrate 2 and so that the difference in refractive index between the dielectric layer and the GaOsubstrate 2 is not more than 0.15, a buffer layer 4 which is formed of GaN crystal so as to be in contact with the remaining upper surface which is not covered by the dielectric layer 4 of the GaOsubstrate 2, and a nitride semiconductor layer 5 which is formed of AlGaInN (0≤x≤1, 0≤y≤1, 0≤z≤1, x+y+z=1) crystal through the buffer layer 4 on the GaOsubstrate 2.

Description

  The present invention relates to a semiconductor multilayer structure and a semiconductor element.

  As a conventional light emitting device, one formed by growing a crystal film on a surface of a translucent substrate on which a concavo-convex pattern is formed is known (for example, see Patent Document 1). In Patent Document 1, a GaN-based semiconductor layer is grown on the surface of the sapphire substrate on which the concavo-convex pattern is formed.

  The concavo-convex pattern of the sapphire substrate of Patent Document 1 is emitted from the light emitting layer in the GaN-based semiconductor layer due to the difference in refractive index between the sapphire substrate and the GaN-based semiconductor layer at the interface between the sapphire substrate and the GaN-based semiconductor layer. It has a function of suppressing reflection of emitted light. By suppressing such reflection, absorption of reflected light by the light emitting layer and attenuation due to multiple reflection of reflected light can be reduced, and the light extraction efficiency of the light emitting element can be improved.

However, in a β-Ga ₂ O ₃ single crystal substrate having a β-gallia structure belonging to a monoclinic system, depending on the direction of substrate processing, a GaN-based semiconductor layer grows also from a processed part side wall or the like. There is a possibility that a crystal having a c-axis in the vertical direction of the substrate and a crystal having a c-axis other than the vertical direction are mixed, and the GaN-based semiconductor layer becomes polycrystalline. In that case, it has been clarified by the present inventors that the quality of the nitride semiconductor layer is remarkably deteriorated (see, for example, Patent Document 2).

Japanese Patent No. 3595277 JP 2014-22446 A

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a semiconductor laminated structure having a nitride semiconductor layer having high quality on the gallium oxide substrate and high uniformity in the plane. And a semiconductor element including the semiconductor multilayer structure.

  In order to achieve the above object, one embodiment of the present invention provides a semiconductor stacked structure according to [1] to [5].

[1] and _Ga 2 _{O 3} substrate, the _Ga 2 _{O 3} is formed so as to contact with the upper surface part on the substrate, the dielectric difference in refractive index between the _Ga 2 _{O 3} substrate is 0.15 or less A buffer layer made of a GaN crystal so as to be in contact with the remaining upper surface of the Ga ₂ O ₃ substrate that is not covered with the dielectric layer, and the buffer layer on the Ga ₂ O ₃ substrate. And a nitride semiconductor layer made of Al _x Ga _y In _z N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z = 1) crystal formed via .

[2] The semiconductor multilayer structure according to [1], wherein the nitride semiconductor layer has a (002) plane diffraction half-value width of 270 seconds or less in X-ray rocking curve measurement.

[3] The semiconductor multilayer structure according to [1] or [2], wherein the nitride semiconductor layer has a (101) plane diffraction half-value width of 270 seconds or less in X-ray rocking curve measurement.

[4] The semiconductor multilayer structure according to any one of [1] to [3], wherein the dielectric layer is formed of a SiN layer containing SiN as a main component.

[5] The semiconductor multilayer structure according to any one of [1] to [4], wherein the nitride semiconductor layer is made of a GaN crystal.

  Another aspect of the present invention provides the semiconductor device according to [6] in order to achieve the above object.

[6] A semiconductor element comprising the semiconductor multilayer structure according to any one of [1] to [5].

  According to the present invention, a nitride semiconductor layer having high quality and high in-plane uniformity that can comprehensively improve device characteristics determined by reliability, leakage current, temperature characteristics, light emission efficiency, and the like. It is possible to provide a semiconductor stacked structure having the semiconductor stack and a semiconductor element including the semiconductor stacked structure.

FIG. 1 is a vertical sectional view of a semiconductor multilayer structure (first embodiment). Figure 2 is a conceptual diagram showing the orientation relationship between the _β-Ga 2 _{O 3} and the unit cell of the crystal, _β-Ga 2 _{O 3} principal surface of the substrate (the first embodiment). FIGS. 3A to 3C are schematic views showing the relationship between the offset angle θs of the main surface of the Ga ₂ O ₃ substrate and the inclination angle θ of the main surface of the nitride semiconductor layer (first embodiment). Form). FIGS. 4A to 4E are vertical sectional views showing a manufacturing process of a semiconductor multilayer structure (first embodiment). FIGS. 5A and 5B are graphs showing variations in crystal quality of the nitride semiconductor layer for each semiconductor stacked structure (first embodiment). FIG. 6 is a graph showing variations in dislocation density for each semiconductor stacked structure (first embodiment). FIG. 7 is a vertical sectional view of a semiconductor laminated structure in which electrodes for measuring current-voltage characteristics are connected (first embodiment). FIG. 8 is a graph showing the current density-voltage characteristics in the vertical direction of the semiconductor multilayer structure (first embodiment). FIG. 9 is a graph showing an example of the relationship between the material of the dielectric layer and the light extraction efficiency of the light emitting element obtained by optical simulation (first embodiment). 10A and 10B are graphs showing variations in crystal quality of the nitride semiconductor layer for each semiconductor stacked structure (first embodiment). FIG. 11 is a graph showing variation in Δθ for each semiconductor stacked structure (first embodiment). 12A to 12D show the nitride semiconductor layer when the inclination angle θ of the main surface of the nitride semiconductor layer is 0.14 °, 0.25 °, 0.45 °, and 0.63 °. FIG. 3 is a photograph showing the state of the main surface of the first embodiment. FIG. 13A is a photograph showing the state of the main surface of the nitride semiconductor layer when the GaN buffer layer is used, and FIG. 13B is a nitride semiconductor layer when the AlN buffer layer is used. FIG. 3 is a photograph showing the state of the main surface of the first embodiment. FIG. 14 is a vertical sectional view of a vertical LED (second embodiment). FIG. 15 is a vertical sectional view of a vertical FET (third embodiment). FIG. 16 is a vertical sectional view of a vertical FET (fourth embodiment). FIG. 17 is a vertical sectional view of a vertical FET (fifth embodiment). FIG. 18 is a vertical sectional view of a vertical FET (sixth embodiment). FIG. 19 is a vertical sectional view of an HBT (seventh embodiment). FIG. 20 is a vertical sectional view of an SBD (eighth embodiment).

  Preferred embodiments of the present invention will be specifically described below with reference to the accompanying drawings.

[First Embodiment]
(Structure of semiconductor laminated structure)
In Figure 1, the semiconductor multilayer structure 1, _Ga 2 _{O 3} substrate 2, _Ga 2 _{O 3} and the dielectric layer 3 formed so as to partially contact with the upper surface of the substrate 2, _Ga 2 _{O 3} substrate 2 A GaN buffer layer 4 formed so as to be in contact with the remaining upper surface not covered with the dielectric layer 3, and a nitride semiconductor layer 5 formed on the Ga ₂ O ₃ substrate 2 via the GaN buffer layer 4. And have.

The Ga ₂ O ₃ substrate 2 is made of a β-Ga ₂ O ₃ single crystal. The upper surface of the Ga ₂ O ₃ substrate 2 is a flat surface without unevenness, and can serve as a foundation for the growth of high-quality nitride semiconductor crystals (101), (−201), (310), (3 -10), a plane having a plane orientation such as (100). The refractive index of the Ga ₂ O ₃ substrate 2 is approximately 1.9.

Figure 2 is a conceptual diagram illustrating a unit cell of the _β-Ga 2 _{O 3} crystal, the orientation relationship between the main surface 2a of the _β-Ga 2 _{O 3} substrate 2. 2 represents an offset angle in the [102] direction from the (−201) plane. In FIG. 2, it is assumed that the offset angle in the [010] direction from the (−201) plane is 0 °.

A unit cell 2b in FIG. 2 is a unit cell of a β-Ga ₂ O ₃ crystal. The β-Ga ₂ O ₃ crystal has a β-gallia structure belonging to a monoclinic system, and a typical lattice constant of the β-Ga ₂ O ₃ crystal not containing impurities is a ₀ = 12.23Å, b ₀ = 3.04 cm, c ₀ = 5.80 cm, α = γ = 90 °, β = 103.7 °. Here, a ₀ , b ₀ , and c ₀ represent axis lengths in the [100] direction, [010] direction, and [001] direction, respectively.

The main surface 2a of the Ga ₂ O ₃ substrate 2 is a surface that is inclined at an offset angle θs in the [102] direction with respect to the (−201) plane, that is, a normal vector having the (−201) plane as a reference. The surface is inclined at an offset angle θs in the [102] direction.

  The offset angle θs is preferably −0.4 ° or more and 0.2 ° or less, and more preferably −0.2 ° or more and 0.0 ° or less.

The dielectric layer 3 is made of, for example, a SiN layer containing SiN as a main component, and has a refractive index difference of 0.15 or less with respect to the Ga ₂ O ₃ substrate 2. When the refractive index of the Ga ₂ O ₃ substrate 2 is 1.9, for example, the refractive index of the dielectric layer 3 is 1.75 or more and 2.05 or less. The pattern shape of the dielectric layer 3 is, for example, a mesa pattern, a recess pattern, a line and space pattern, or the like.

Refractive index of the dielectric layer 3 is closer to the refractive index of the Ga ₂ O ₃ substrate 2, to suppress the total reflection at the interface of Ga ₂ O ₃ substrate 2 and the dielectric layer 3, the efficiency of the light from the light-emitting layer Can be taken out. When the dielectric layer 3 is a SiN layer, elements other than Si and N such as O may be included for adjusting the refractive index.

The refractive index of the dielectric layer 3 is adjusted by controlling the formation conditions such as the film formation temperature of the dielectric layer 3, and the difference between the refractive index of the dielectric layer 3 and the refractive index of the Ga ₂ O ₃ substrate 2 is adjusted. Can be made smaller.

  The GaN buffer layer 4 is made of a GaN crystal and may contain a conductive impurity such as Si.

The nitride semiconductor layer 5 is made of a nitride semiconductor crystal, that is, an Al _x Ga _y In _z N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z = 1) crystal. In particular, when the nitride semiconductor layer 5 is a GaN layer made of a GaN crystal (y = 1, x = z = 0), in the configuration of the semiconductor multilayer structure 1 of the present embodiment, the nitride semiconductor layer 5 Crystal quality can be increased.

The nitride semiconductor layer 5 may have a multilayer structure in which a plurality of layers made of different nitride semiconductor crystals are stacked. In the case of forming a light emitting element using the semiconductor multilayer structure 1, the light emitting layer and the clad layer sandwiching the light emitting layer can be constituted by the nitride semiconductor layer 5. Note that the Ga ₂ O ₃ substrate 2 and the nitride semiconductor layer 5 may include a conductive impurity such as Si or Sn.

FIGS. 3A to 3C are schematic diagrams showing the relationship between the offset angle θs of the main surface 2 a of the Ga ₂ O ₃ substrate 2 and the inclination angle θ of the main surface 5 a of the nitride semiconductor layer 5. 3A to 3C is a plane parallel to the [102] direction orthogonal to the (−201) plane of the Ga ₂ O ₃ substrate 2.

As shown in FIG. 3A, when the main surface 2a of the Ga ₂ O ₃ substrate 2 does not have the offset angle θs (θs = 0 °), the main surface 5a of the nitride semiconductor layer 5 has a predetermined value. Inclined from the (001) plane at an inclination angle θ.

As shown in FIG. 3B, when the main surface 2a of the Ga ₂ O ₃ substrate 2 has an offset angle θs and the inclination angle θ of the main surface 5a of the nitride semiconductor layer 5 becomes small, the nitride semiconductor layer 5 is suppressed, and the surface roughness of the main surface 5a can be reduced.

As shown in FIG. 3C, the inclination angle θ of the main surface 5a of the nitride semiconductor layer 5 is set to 0 ° by providing the main surface 2a of the Ga ₂ O ₃ substrate 2 with an appropriate offset angle θs. Can be approached. Thereby, the surface roughness of main surface 5a of nitride semiconductor layer 5 can be effectively reduced.

Specifically, when the offset angle θs of the main surface 2a of the Ga ₂ O ₃ substrate 2 is −0.4 ° or more and 0.2 ° or less, the inclination angle θ of the main surface 5a of the nitride semiconductor layer 5 is set to 0. The offset angle θs of the main surface 2a of the Ga ₂ O ₃ substrate 2 is −0.2 ° or more and 0.0 ° or less. In some cases, the inclination angle θ of the main surface 5a of the nitride semiconductor layer 5 can be within a numerical range of −0.2 ° to 0.2 ° which is closer to 0 °.

(Method for manufacturing semiconductor laminated structure)
Hereinafter, as an example of the manufacturing process of the semiconductor multilayer structure according to the first embodiment, an example of the manufacturing process when the dielectric layer 3 is a SiN layer will be described.

  4A to 4E are vertical cross-sectional views showing manufacturing processes of the semiconductor multilayer structure according to the first embodiment.

First, organic cleaning and SPM (Sulfuric acid / hydrogen peroxide mixture) cleaning are performed on the Ga ₂ O ₃ substrate 2 subjected to CMP (Chemical Mechanical Polishing).

Next, the Ga ₂ O ₃ substrate 2 is transferred into the chamber of the plasma CVD apparatus.

Next, as shown in FIG. 4A, a film-like dielectric layer 3 is formed on the Ga ₂ O ₃ substrate 2. The film-like dielectric layer 3 is made of SiH ₄ as a raw material of Si, NH ₃ gas as a raw material of N, and N ₂ gas as an atmospheric gas while maintaining the temperature in the chamber at 300 to 350 ° C. Is supplied into the chamber, and SiN is deposited on the Ga ₂ O ₃ substrate 2. At this stage, the dielectric layer 3 is a substantially uniform film having a thickness of about 1 μm. The raw materials for each element are not limited to the above.

  Next, as shown in FIG. 4B, a resist pattern 6 is formed on the dielectric layer 3. The pattern shape of the resist pattern 6 is, for example, a triangular lattice pattern with a dot diameter of 2 μm and a pitch of 4 μm. The resist pattern 6 is formed by, for example, photolithography.

  Next, as shown in FIG. 4C, the dielectric layer 3 is etched with BHF (buffered hydrofluoric acid) using the resist pattern 6 as a mask, and the pattern of the resist pattern 6 is transferred to the dielectric layer 3.

Next, as shown in FIG. 4D, the remaining resist pattern 6 is removed. Next, the surface of the structure composed of the Ga ₂ O ₃ substrate 2 and the dielectric layer 3 is cleaned by organic cleaning and SPM cleaning, and transported to the MOCVD apparatus.

Next, as shown in FIG. 4E, NH _{3 is used} as a source material for N, trimethyl gallium (TMG) is used as a source material for Ga, and the temperature of the substrate surface is kept at around 500 ° C. to form the GaN buffer layer 4. .

Thereafter, NH ₃ gas as a raw material for N, trimethylgallium (TMG) gas as a raw material for Ga, trimethylaluminum (TMA) gas as a raw material for Al, and trimethylindium (TMI) gas as a raw material for In are contained in the chamber. The Al _x Ga _y In _z N crystal, which is a nitride semiconductor crystal, is selectively grown on the Ga ₂ O ₃ substrate 2 to form the nitride semiconductor layer 5. Thereby, the semiconductor multilayer structure 1 is obtained.

The nitride semiconductor crystal constituting the nitride semiconductor layer 5 grows from a region not covered by the dielectric layer 3 on the upper surface of the Ga ₂ O ₃ substrate 2 and does not grow from the dielectric layer 3. Thus, the nitride semiconductor crystal grows selectively, and then grows in the lateral direction to cover the dielectric layer 3. At this time, the dislocation density in the nitride semiconductor layer 5 is reduced, and the crystal quality is improved. Such a crystal growth method using selective growth is called ELO (Epitaxial Lateral Overgrowth).

(Evaluation of semiconductor laminated structure)
Below, the evaluation result of the semiconductor laminated structure 1 is shown. In this evaluation, the nitride semiconductor layer 5 made of GaN crystal was used.

(Crystal quality)
FIGS. 5A and 5B are graphs showing variations in crystal quality of the nitride semiconductor layer 5 for each semiconductor stacked structure 1. 5A shows the cumulative relative power distribution of the half width of the X-ray rocking curve in the (002) plane diffraction of the nitride semiconductor layer 5, and FIG. 5B shows the (101) plane diffraction of the nitride semiconductor layer 5. Represents the cumulative relative frequency distribution of the full width at half maximum of the X-ray rocking curve.

  The marks ◯ plotted in FIGS. 5A and 5B represent the cumulative relative frequency distribution of the half width of the X-ray rocking curve in the semiconductor multilayer structure 1 using the GaN buffer layer 4, and the mark □ is AlN The cumulative relative frequency distribution of the half value width of the X-ray rocking curve in the semiconductor laminated structure using a buffer layer is represented.

  5A and 5B show that when the GaN buffer layer 4 is used, the crystal quality of the nitride semiconductor layer 5 varies less for each semiconductor stacked structure 1 than when the AlN buffer layer is used. Although it does not change, it shows that the crystal quality of the nitride semiconductor layer 5 is improved. The half width when the GaN buffer layer 4 was used was 223 to 269 arcsec in the (002) plane diffraction and 225 to 264 arcsec in the (101) plane diffraction.

FIG. 6 is a graph showing variation in dislocation density for each semiconductor stacked structure.
The mark ◯ plotted in FIG. 6 represents the cumulative relative frequency distribution of the dislocation density of the X-ray rocking curve in the semiconductor multilayer structure 1 using the GaN buffer layer 4, and the mark □ represents the semiconductor multilayer using the AlN buffer layer. It represents the cumulative relative frequency distribution of the dislocation density of the structure. The dislocation density was evaluated by using cathodoluminescence and counting the density of dark spots. The dislocation density evaluation results can also be obtained by counting the density of etch pits obtained by TEM observation or chemical etching using KOH, NaOH, or the like.

FIG. 6 shows that in both the measurement results for the GaN buffer layer 4 and the AlN buffer layer, the crystal quality of the nitride semiconductor layer 5 varies from one semiconductor stack structure 1 to another and the dislocation density is almost the same. This value is comparable to that on the sapphire substrate, indicating that the crystal quality of the nitride semiconductor layer 5 is high. The dislocation density when the GaN buffer layer 4 was used was 1.52 × 10 ^{8 to} 2.14 × 10 ⁸ / cm ² .

(Electrical conductivity)
FIG. 7 shows a state in which electrodes are connected to the Ga ₂ O ₃ substrate 2 and the nitride semiconductor layer 5 of the semiconductor multilayer structure 1. An electrode 6a (Ti / Al) and an electrode 6b (Ti / Au), which are ohmic electrodes, were connected to the nitride semiconductor layer 5 and the Ga ₂ O ₃ substrate 2, respectively.

FIGS. 8A and 8B are graphs showing current density-voltage characteristics in the vertical direction of the semiconductor multilayer structure 1. 8A and 8B, the horizontal axis represents voltage (V) and the vertical axis represents current density (A / cm ² ). FIG. 8A shows the current density-voltage characteristic when the GaN buffer layer 4 is used, and FIG. 8B shows the current density-voltage characteristic when the AlN buffer layer is used.

  8A and 8B, the plotted mark ◯ represents the current density-voltage characteristic in the vertical direction of the semiconductor multilayer structure 1 that does not have the dielectric layer 3, and the mark Δ represents the dielectric layer. The current density-voltage characteristic of the vertical direction of the semiconductor laminated structure which has is represented.

  When the dielectric layer 3 is a SiN layer, it has been confirmed that the current density-voltage characteristics in the vertical direction (vertical direction) of the semiconductor multilayer structure 1 can be obtained as being particularly excellent.

  As shown in FIGS. 8A and 8B, the semiconductor multilayer structure having the dielectric layer 3 that is the SiN layer is more specific than the semiconductor multilayer structure having no dielectric layer that is the SiN layer. The voltage required to pass current is small. This result indicates that the drive voltage can be reduced by providing the dielectric layer 3 which is a SiN layer.

8A and 8B show a potential barrier at the interface between the Ga ₂ O ₃ substrate and the nitride semiconductor layer in the semiconductor stacked structure according to the comparative example that does not have the dielectric layer that is the SiN layer. In the semiconductor multilayer structure 1 according to the first embodiment that exists and has the dielectric layer 3 that is a SiN layer, there is no potential barrier at the interface between the Ga ₂ O ₃ substrate 2 and the nitride semiconductor layer 5. In other words, the Ga ₂ O ₃ substrate 2 and the nitride semiconductor layer 5 are in ohmic contact. This result shows that the electrical resistance in the vertical direction of the semiconductor multilayer structure 1 is reduced by providing the dielectric layer 3 which is a SiN layer.

(Light extraction efficiency)
FIG. 9 is a graph showing an example of the relationship between the material of the dielectric layer 3 and the light extraction efficiency of the light emitting element obtained by optical simulation.

In this optical simulation, the Ga ₂ O ₃ substrate 2 has a refractive index of 1.9, the dielectric layer 3 is composed of a mesa pattern having a diameter of 3 μm, a pitch of 6 μm, and a height of 1 μm, and light emitted from the light emitting layer. Was taken out from the Ga ₂ O ₃ substrate 2 side. Here, as the dielectric layer 3, a SiO ₂ layer (n = 1.46), a SiN layer (n = 1.9), and a ZnO layer (n = 2.2) were used. Of these, only the SiN layer satisfies the refractive index condition of the dielectric layer 3 of the present embodiment.

The light extraction efficiency in FIG. 9 is standardized on the basis of the light extraction efficiency in the case where unevenness of the same shape is formed on the surface of the Ga ₂ O ₃ substrate 2 instead of the dielectric layer in the light emitting element. However, this standard light extraction efficiency is that an n-type cladding layer, a light-emitting layer, a p-type cladding layer, and a contact layer with good crystal quality are formed on the Ga ₂ O ₃ substrate 2 having irregularities formed on the surface. This is the theoretical value when assumed. Actually, since it is difficult to form the nitride semiconductor layer 5 having a good crystal quality on the Ga ₂ O ₃ substrate 2 having a surface with irregularities, an n-type cladding layer, a light emitting layer, It becomes difficult to obtain a p-type cladding layer and a contact layer.

  FIG. 9 shows that the light extraction efficiency is highest when a SiN layer that satisfies the refractive index condition of the dielectric layer is used as the dielectric layer 3.

Further, according to the optical simulation, when the refractive index of the dielectric layer 3 is 1.75 or more and 2.05 or less, that is, when the refractive index difference from the Ga ₂ O ₃ substrate 2 is 0.15 or less, It is found that the light extraction efficiency is about 98.5% or more of the reference value.

(In-plane offset variation)
10A and 10B show the in-plane of the semiconductor multilayer structure 1 in which the difference Δθ between the offset angle θs of the main surface of the Ga ₂ O ₃ substrate 2 and the inclination angle θ of the main surface of the nitride semiconductor layer 5 is obtained. It is a graph showing distribution of. FIG. 10A shows the distribution of Δθ when the GaN buffer layer 4 is used, and FIG. 10B shows the distribution of Δθ when the AlN buffer layer is used.

Here, if the angle formed by the (−201) plane of the Ga ₂ O ₃ substrate 2 and the (001) plane of the nitride semiconductor layer 5 is Δθ, the relationship between Δθ, θ, and θs is Δθ = θ−θs. expressed.

10A and 10B represents the position in the X direction or Y direction in the plane of the semiconductor multilayer structure 1. Here, the mark ◯ plotted in FIGS. 10A and 10B passes through the center of the surface of the semiconductor multilayer structure 1 and is measured on a line parallel to the [010] direction of the Ga ₂ O ₃ substrate 2. Represents a value. The mark □ represents a measured value on a line parallel to the [102] direction of the Ga ₂ O ₃ substrate 2 through the center in the plane of the semiconductor multilayer structure 1. These measured values have the in-plane center of the semiconductor multilayer structure 1 as the origin of the measurement position.

  In FIGS. 10A and 10B, when the GaN buffer layer 4 is used, the variation in Δθ in the plane of the semiconductor multilayer structure 1 is larger in the [010] direction than when the AlN buffer layer is used. 102] indicates that the nitride semiconductor layer 5 having a small offset angle and a uniform offset angle in the plane is formed. When the GaN buffer layer 4 was used, the difference between the maximum value and the minimum value of Δθ in the plane was 0.15 ° in the [010] direction and 0.07 ° in the [102] direction.

(Offset variation between wafers)
FIG. 11 is a graph showing variation in Δθ in the [102] direction of the Ga ₂ O ₃ substrate 2 for each semiconductor multilayer structure 1. The vertical axis represents the cumulative relative frequency distribution of Δθ. 11 represents the cumulative relative power distribution of Δθ in the semiconductor multilayer structure 1 using the GaN buffer layer 4, and the mark □ represents the cumulative Δθ in the semiconductor multilayer structure using the AlN buffer layer. Represents a relative frequency distribution. Note that these values of Δθ are measured at the center position in the plane.

  FIG. 11 shows that when the GaN buffer layer 4 is used, variation in Δθ for each semiconductor multilayer structure 1 is smaller than when the AlN buffer layer is used. The difference between the maximum value and the minimum value of Δθ between the semiconductor stacked structures when the GaN buffer layer 4 was used was 0.12 °.

12A to 12D show that the inclination angle θ of the main surface of the nitride semiconductor layer 5 in the [102] direction of the Ga ₂ O ₃ substrate 2 is 0.14 °, 0.25 °, 0.45 °. , A photograph showing the state of the main surface of nitride semiconductor layer 5 at 0.63 °.

  12A to 12D show that the step bunching appearing on the main surface of the nitride semiconductor layer 5 increases as the tilt angle θ increases. Step bunching can hardly be confirmed on the main surface of the nitride semiconductor layer 5 shown in FIGS. 12A and 12B, but the main surface of the nitride semiconductor layer 5 shown in FIGS. Step bunching can be clearly seen on the surface.

  From FIGS. 12A to 12D, it is estimated that the step bunching can be clearly confirmed when the inclination angle θ is larger than about 0.4 ° (smaller than −0.4 °). Further, when the inclination angle θ is about −0.2 ° or more and 0.2 ° or less, it is presumed that the step bunching becomes smaller and the smooth surface is obtained as the observation with the optical microscope becomes difficult.

(Surface condition of nitride semiconductor layer)
FIG. 13A is a photograph showing the state of the main surface of the nitride semiconductor layer 5 when the GaN buffer layer 4 is used, and FIG. 13B is a nitride when the AlN buffer layer is used. It is the photograph which copied the state of the main surface of a semiconductor layer.

  13A and 13B show that when the GaN buffer layer 4 is used, the hillock-like protrusions observed on the main surface of the nitride semiconductor layer 5 are larger than when the AlN buffer layer is used. It shows that it is greatly reduced.

Specifically, the hillock density of the main surface of the nitride semiconductor layer 5 is less than 1 per 1 cm ² when the GaN buffer layer 4 is used, and 10 ² to 10 ³ per 1 cm ² when the AlN buffer layer is used. It was a piece.

  The generation of hillocks is hardly affected by the inclination angle θ of the main surface of the nitride semiconductor layer 5, but the surface flatness is improved more effectively by reducing the hillock density using the GaN buffer layer 4. can do.

(Evaluation results)
From the above, the evaluation results of the semiconductor multilayer structure having the dielectric layer and the AlN buffer layer and the semiconductor multilayer structure 1 having the dielectric layer 3 and the GaN buffer layer 4 are summarized in Table 1 below.

  As apparent from Table 1 above, by using the structure having the dielectric layer 3 and the GaN buffer layer 4, it is possible to grow a nitride semiconductor crystal excellent in crystal quality, electrical conductivity, light extraction efficiency, and the like. I understand that there is. This is very important for comprehensively improving the device characteristics determined by the reliability, leakage current, temperature characteristics, light emission efficiency, etc. of the semiconductor elements formed on the nitride semiconductor layer. Further, it is possible to reduce in-plane offset variation and surface roughness, and it can be said that it is very effective for producing semiconductor devices with a high yield.

[Second Embodiment]
The semiconductor multilayer structure 1 according to the first embodiment can be used for manufacturing various semiconductor elements. Below, vertical LED is demonstrated as an example of the semiconductor element.

FIG. 14 is a vertical sectional view of the vertical LED 10 according to the second embodiment. The vertical LED 10 includes a Ga ₂ O ₃ substrate 2, a dielectric layer 3 and a GaN buffer layer 4 on the Ga ₂ O ₃ substrate 2, an n-type cladding layer 14 on the GaN buffer layer 4, and an n-type cladding layer 14. The upper light emitting layer 15, the p-type cladding layer 16 on the light-emitting layer 15, the contact layer 17 on the p-type cladding layer 16, the p-type electrode 18 on the contact layer 17, and the GaN of the Ga ₂ O ₃ substrate 2 It has an n-type electrode 19 on the surface opposite to the buffer layer 4.

  In addition, the side surface of the laminate composed of the dielectric layer 3, the GaN buffer layer 4, the n-type cladding layer 14, the light emitting layer 15, the p-type cladding layer 16, and the contact layer 17 is covered with the insulating film 20.

Here, the n-type cladding layer 14 corresponds to the nitride semiconductor layer 5 constituting the semiconductor multilayer structure 1 of the first embodiment. The thicknesses of the Ga ₂ O ₃ substrate 2, the dielectric layer 3, the GaN buffer layer 4, and the n-type cladding layer 14 are, for example, 400 μm, 1 μm, 48 nm, and 5 μm.

  The light emitting layer 15 is composed of, for example, a three-layer multiple quantum well structure and a GaN crystal film having a thickness of 10 nm thereon. Each multiple quantum well structure is composed of a GaN crystal film having a thickness of 6 nm and an InGaN crystal film having a thickness of 2 nm. The light emitting layer 15 is formed by epitaxially growing each crystal film on the n-type cladding layer 14 at a growth temperature of 700 to 800 ° C., for example.

The p-type cladding layer 16 is, for example, a GaN crystal film having a thickness of 100 nm and containing Mg having a concentration of 5.0 × 10 ¹⁹ / cm ³ . The p-type cladding layer 16 is formed, for example, by epitaxially growing a GaN crystal containing Mg on the light emitting layer 15 at a growth temperature of 900 to 1050 ° C.

The contact layer 17 is, for example, a GaN crystal film having a thickness of 10 nm and containing Mg having a concentration of 1.5 × 10 ²⁰ / cm ³ . The contact layer 17 is formed, for example, by epitaxially growing a GaN crystal containing Mg on the p-type cladding layer 16 at a growth temperature of 900 to 1050 ° C.

In the formation of the GaN buffer layer 4, the n-type cladding layer 14, the light emitting layer 15, the p-type cladding layer 16, and the contact layer 17, TMG (trimethylgallium) gas as the Ga material, TMI (trimethylindium) gas as the In material, MtSiH ₃ (monomethylsilane) gas can be used as the Si material, Cp ₂ Mg (biscyclopentadienylmagnesium) gas can be used as the Mg material, and NH ₃ (ammonia) gas can be used as the N material.

The insulating film 20 is made of an insulating material made of SiO ₂ or the like, and is formed, for example, by sputtering.

The p-type electrode 18 and the n-type electrode 19 are electrodes that are in ohmic contact with the contact layer 17 and the Ga ₂ O ₃ substrate 2, respectively, and are formed by, for example, a vapor deposition apparatus.

The vertical LED 10 includes a dielectric layer 3, a GaN buffer layer 4, an n-type cladding layer 14, a light-emitting layer 15, a p-type cladding layer 16, a contact layer 17, and a p-type electrode on a Ga ₂ O ₃ substrate 2 in a wafer state. After the 18 and n-type electrodes 19 are formed, they are obtained by dicing them into, for example, a 300 μm square chip size.

The vertical LED 10 is, for example, an LED chip that extracts light from the Ga ₂ O ₃ substrate 2 side, and is mounted on a can-type stem using Ag paste.

Since the n-type cladding layer 14 of the vertical LED 10 is formed on the Ga ₂ O ₃ substrate 2 whose main surface is a surface inclined at a special offset angle, the surface roughness is small and the crystal quality is excellent. . The light emitting layer 15, the p-type cladding layer 16, and the contact layer 17 formed by epitaxial crystal growth on the n-type cladding layer 14 having excellent crystal quality also have excellent crystal quality. For this reason, the LED element 10 is excellent in leak characteristics and reliability.

(Effect of the second embodiment)
According to the second embodiment, a buffer layer made of a GaN crystal is provided with a dielectric layer structure made of SiN or the like on a β-Ga ₂ O ₃ substrate whose main surface is a plane inclined from the (−201) plane. A high-quality nitride semiconductor layer can be obtained by epitaxial growth of Al _x Ga _y In _z N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z = 1). it can. Specifically, hillocks with a narrow half-value width measured by X-ray rocking curve, low dislocation density, excellent electrical conductivity, excellent light extraction efficiency, small off-angle variation in the surface, and poor surface morphology The density of can be reduced. In addition, the off-angle variation between wafers is small, and a nitride semiconductor layer with stable quality can be obtained.

  Further, by using such a nitride semiconductor layer, it is possible to produce a semiconductor element having excellent overall element characteristics determined by leakage current, reliability, temperature characteristics, light emission efficiency, and the like with a high yield.

[Third Embodiment]
As a third embodiment, a vertical FET (Field effect transistor) including the semiconductor multilayer structure 1 of the first embodiment will be described.

FIG. 15 is a vertical sectional view of a vertical FET which is a semiconductor element according to the third embodiment. The vertical FET 30 includes a semiconductor laminated structure 1 including a Ga ₂ O ₃ substrate 2, a dielectric layer 3, a GaN buffer layer 4, and a nitride semiconductor layer (n ⁺ -GaN layer) 5, and a nitride semiconductor layer 5. A GaN-based vertical FET 31 formed on the surface (the upper surface in FIG. 15), a gate electrode 32 and a source electrode 33 formed on the GaN-based vertical FET 31, and the surface of the Ga ₂ O ₃ substrate 2 (FIG. 15 and the drain electrode 34 formed on the lower surface in FIG.

  Note that the vertical FET 30 is an example of a vertical FET that can be formed using the semiconductor multilayer structure 1.

[Fourth Embodiment]
As a fourth embodiment, a vertical FET having a MIS (Metal Insulator Semiconductor) gate structure including the semiconductor multilayer structure 1 of the first embodiment will be described.

FIG. 16 is a vertical sectional view of a vertical FET which is a semiconductor element according to the fourth embodiment. The vertical FET 40 includes a semiconductor laminated structure 1 including a Ga ₂ O ₃ substrate 2, a dielectric layer 3, a GaN buffer layer 4, and a nitride semiconductor layer (n ⁺ -GaN layer) 5, and a nitride semiconductor layer 5. P ⁺ -GaN layer 41 formed by introducing a p-type impurity into the surface, and an Al _0.2 Ga _0.8 N layer formed on the surface of nitride semiconductor layer 5 (the upper surface in FIG. 16) _42, a Si ion implanted region 43 formed by introducing n-type impurities such as Si into the Al 0.2 _{Ga 0.8} n layer _42, on the Al 0.2 _{Ga 0.8} n layer 42 The gate electrode 45 formed through the gate insulating film 44, the source electrode 46 connected to the Si ion implantation region 43 and the p ⁺ -GaN layer 41, and the surface of the Ga ₂ O ₃ substrate 2 (the lower side in FIG. 16) The drain electrode 4 formed on the surface Including the door.

Here, the thickness of the nitride semiconductor layer 5 is, for example, 5 μm, and the Si concentration is 1 × 10 ¹⁸ / cm ³ . The thickness of the p ⁺ -GaN layer 41 is, for example, 1 μm, and the concentration of the p-type impurity is 1 × 10 ¹⁸ / cm ³ . The Al _0.2 Ga _0.8 N layer 42 does not contain impurities and has a thickness of, for example, 30 nm. The source electrode 46 is made of a laminate of, for example, a Ti film and an Al film. The drain electrode 47 is made of a laminate of, for example, a Ti film and an Au film. The gate electrode 45 is made of, for example, Al, and the gate insulating film 44 is made of, for example, SiO ₂ .

  The vertical FET 40 is an example of a vertical FET having a MIS gate structure that can be formed using the semiconductor multilayer structure 1.

[Fifth Embodiment]
As a fifth embodiment, a vertical FET having a Schottky gate structure including the semiconductor multilayer structure 1 of the first embodiment will be described.

FIG. 17 is a vertical sectional view of a vertical FET which is a semiconductor element according to the fifth embodiment. The vertical FET 50 includes a semiconductor multilayer structure 1 including a Ga ₂ O ₃ substrate 2, a dielectric layer 3, a GaN buffer layer 4, and a nitride semiconductor layer (n ⁻ -GaN layer) 5, and a nitride semiconductor layer 5. A p ⁺ -GaN layer 51, an n ⁺ -GaN layer 52, a GaN layer 53, an Al _0.2 Ga _0.8 N layer 54, and an Al _0.2 layer laminated on the surface (the upper surface in FIG. 17). a gate electrode 55 formed on the Ga _0.8 n layer ^54, is connected to the p + -GaN layer ^51, n + -GaN layer 52, GaN layer 53, and _Al 0.2 _{Ga 0.8} n layer 54 Source electrode 56 and drain electrode 57 formed on the surface of Ga ₂ O ₃ substrate 2 (the lower surface in FIG. 17).

Here, the thickness of the nitride semiconductor layer 5 is, for example, 5 μm, and the Si concentration is 1 × 10 ¹⁶ / cm ³ . Further, the thickness of the p ⁺ -GaN layer 51 is, for example, 1 μm, and the concentration of the p-type impurity is 1 × 10 ¹⁸ / cm ³ . Further, the thickness of the n ⁺ -GaN layer 52 is, for example, 200 nm, and the concentration of the n-type impurity is 1 × 10 ¹⁸ / cm ³ . The GaN layer 53 does not contain impurities and has a thickness of, for example, 100 nm. The Al _0.2 Ga _0.8 N layer 54 does not contain impurities and has a thickness of, for example, 30 nm. The source electrode 56 is made of a laminate of, for example, a Ti film and an Al film. The drain electrode 57 is made of a laminate of, for example, a Ti film and an Au film. The gate electrode 55 is made of, for example, a stacked body of a Ni film and an Au film.

  The vertical FET 50 is an example of a vertical FET having a Schottky gate structure that can be formed using the semiconductor multilayer structure 1.

[Sixth Embodiment]
As a sixth embodiment, another Schottky gate structure vertical FET including the semiconductor multilayer structure 1 of the first embodiment will be described.

FIG. 18 is a vertical sectional view of a vertical FET which is a semiconductor element according to the sixth embodiment. The vertical FET 60 includes a semiconductor multilayer structure 1 including a Ga ₂ O ₃ substrate 2, a dielectric layer 3, a GaN buffer layer 4, and a nitride semiconductor layer (n ⁺ -GaN layer) 5, and a nitride semiconductor layer 5. surface ⁿ formed (upper surface in FIG. 18) on - and -GaN layer ^61, n - a gate electrode 62 formed on the flat portion of the -GaN layer ^61, n - projections of -GaN layer 61 It includes a source electrode 64 formed thereon via an n ⁺ -InAlGaN contact layer 63 and a drain electrode 65 formed on the surface of Ga ₂ O ₃ substrate 2 (the lower surface in FIG. 18).

Here, the thickness of the nitride semiconductor layer 5 is, for example, 5 μm, and the Si concentration is 1 × 10 ¹⁸ / cm ³ . The thickness of the flat portion of the n ⁻ -GaN layer 61 is, for example, 3 μm, and the concentration of the n-type impurity is 1 × 10 ¹⁶ / cm ³ . The source electrode 64 is made of, for example, WSi. The drain electrode 65 is made of a laminate of, for example, a Ti film and an Al film. The gate electrode 62 is made of, for example, PdSi.

  The vertical FET 60 is an example of a vertical FET having a Schottky gate structure that can be formed using the semiconductor multilayer structure 1.

[Seventh Embodiment]
As a seventh embodiment, a heterojunction bipolar transistor (HBT) including the semiconductor multilayer structure 1 of the first embodiment will be described.

FIG. 19 is a vertical sectional view of an HBT that is a semiconductor element according to the seventh embodiment. The HBT 70 includes a semiconductor laminated structure 1 including a Ga ₂ O ₃ substrate 2, a dielectric layer 3, a GaN buffer layer 4, and a nitride semiconductor layer (n ⁺ -GaN layer) 5, and the surface of the nitride semiconductor layer 5 ( The n ⁻ -GaN layer 71 and the p ⁺ -GaN layer 72 stacked on the upper surface in FIG. 19 and the n ⁺ -Al _0.1 Ga _0.9 N stacked on the p ⁺ -GaN layer 72. Layers 73, n ⁺ -GaN layer 74, base electrode 75 formed on p ⁺ -GaN layer 72, emitter electrode 75 formed on n ⁺ -GaN layer 74, and Ga ₂ O ₃ substrate 2. And a collector electrode 76 formed on the surface (the lower surface in FIG. 19).

Here, the thickness of the nitride semiconductor layer 5 is, for example, 4 μm, and the Si concentration is 1 × 10 ¹⁸ / cm ³ . The thickness of the n ⁻ -GaN layer 71 is 2 μm, for example, and the concentration of the n-type impurity is 1 × 10 ¹⁶ / cm ³ . The thickness of the p ⁺ -GaN layer 72 is, for example, 100 nm, and the concentration of the p-type impurity is 1 × 10 ¹⁸ / cm ³ . The thickness of the n ⁺ -Al _0.1 Ga _0.9 N layer 73 is, for example, 500 nm, and the concentration of the n-type impurity is 1 × 10 ¹⁸ / cm ³ . Further, the thickness of the n ⁺ -GaN layer 74 is, for example, 1 μm, and the concentration of the n-type impurity is 1 × 10 ¹⁸ / cm ³ . The emitter electrode 75 is made of, for example, a laminate of a Ti film and an Al film. The collector electrode 76 is made of a laminated body of, for example, a Ti film and an Au film. The base electrode 75 is made of, for example, a laminate of Ni film and Au film.

  The HBT 70 is an example of a heterojunction bipolar transistor that can be formed using the semiconductor multilayer structure 1.

[Eighth Embodiment]
As an eighth embodiment, a Schottky barrier diode (SBD) including the semiconductor multilayer structure 1 of the first embodiment will be described.

FIG. 20 is a cross-sectional view of an SBD that is a semiconductor element according to the eighth embodiment. The SBD 80 includes a semiconductor laminated structure 1 including a Ga ₂ O ₃ substrate 2, a dielectric layer 3, a GaN buffer layer 4, and a nitride semiconductor layer (n ⁺ -GaN layer) 5, and the surface of the nitride semiconductor layer 5 ( The n ⁻ -GaN layer 81 formed on the upper surface in FIG. 20, the anode electrode 82 formed on the n ⁻ -GaN layer 81, and the surface of the Ga ₂ O ₃ substrate 2 (lower side in FIG. 20). A cathode electrode 83 formed on the surface.

Here, the thickness of the nitride semiconductor layer 5 is, for example, 5 μm, and the Si concentration is 1 × 10 ¹⁸ / cm ³ . The thickness of the n ⁻ -GaN layer 81 is, for example, 7 μm, and the concentration of the n-type impurity is 1 × 10 ¹⁶ / cm ³ . The anode electrode 82 is made of, for example, Au. The cathode electrode 83 is made of, for example, a laminate of a Ti film and an Au film.

  The SBD 80 is an example of a Schottky barrier diode that can be formed using the semiconductor multilayer structure 1.

(Effects of the third to eighth embodiments)
A dielectric layer structure made of SiN or the like is provided on a β-Ga ₂ O ₃ substrate having a plane inclined from the (−201) plane as a main surface, and a buffer layer made of GaN crystal is used to obtain Al _x Ga _y In _z N ( 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z = 1) By epitaxially growing a crystal, a high-quality nitride semiconductor layer can be obtained. Specifically, the half width by X-ray rocking curve measurement is narrow, the dislocation density is low, the electric conduction characteristics are excellent, the off-angle variation in the surface is small, and the density of hillocks, which are surface morphology defects, can be reduced. In addition, the off-angle variation between wafers is small, and a nitride semiconductor layer with stable quality can be obtained. Further, by using such a semiconductor multilayer structure, device characteristics such as reliability, leakage current, and temperature characteristics can be improved comprehensively.

  As is clear from the above description, each of the representative embodiments and the illustrated examples according to the present invention have been illustrated, but the above-described embodiments and illustrated examples do not limit the invention according to the claims. Absent. Therefore, it should be noted that not all the combinations of features described in the above embodiments and illustrated examples are necessarily essential to the means for solving the problems of the invention.

1 ... semiconductor stack, 2 ... _Ga 2 _{O 3} substrate, 3 ... dielectric layer, 4 ... GaN buffer layer, 5 ... nitride semiconductor layer, 6 ... resist pattern, 10 ... vertical LED, 14 ... n-type clad Layer 15 luminescent layer 16 p-type cladding layer 17 contact layer 18 p-type electrode 19 n-type electrode 20 insulating film 30, 40, 50, 60 vertical FET 31 GaN-based vertical FET, 32 ... gate electrode, 33 ... source electrode, 34 ... drain electrode, 41, 51 ... p ⁺ -GaN layer, 42 ... Al _0.2 Ga _0.8 N layer, 43 ... Si ion implantation region 44, gate insulating film, 45, 55, 62 ... gate electrode, 46, 56, 64 ... source electrode, 47, 57, 65 ... drain electrode, 52, 74 ... n ⁺ -GaN layer, 53 ... GaN layer, 54 ... _Al 0.2 _{Ga 0.8} N layer, 6 , 71, 81 ^... n - -GaN ^layer, 63 ... n + -InAlGaN contact ^{layer, 70 ... HBT, 72 ... p} + -GaN ^{_{layer, 73 ... n + -Al 0.1 Ga}} 0.9 N layer, 75 ... Base electrode, 75 ... emitter electrode, 76 ... collector electrode, 80 ... Schottky barrier diode, 82 ... anode electrode, 83 ... cathode electrode

Claims (6)

A Ga ₂ O ₃ substrate;
The Ga ₂ O ₃ is formed such that the upper surface portion in contact with the substrate, and the dielectric layer a difference in refractive index between the Ga ₂ O ₃ substrate is 0.15 or less,
A buffer layer made of a GaN crystal formed in contact with the remaining upper surface of the Ga ₂ O ₃ substrate that is not covered with the dielectric layer;
An Al _x Ga _y In _z N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z = 1) crystal formed on the Ga ₂ O ₃ substrate via the buffer layer. A nitride semiconductor layer;
A semiconductor laminated structure having:   2. The semiconductor multilayer structure according to claim 1, wherein the nitride semiconductor layer has a (002) plane diffraction half-value width of 270 seconds or less in X-ray rocking curve measurement.   3. The semiconductor multilayer structure according to claim 1, wherein the nitride semiconductor layer has a (101) plane diffraction half-value width of 270 seconds or less in X-ray rocking curve measurement.   4. The semiconductor multilayer structure according to claim 1, wherein the dielectric layer is made of a SiN layer containing SiN as a main component.   The semiconductor multilayer structure according to claim 1, wherein the nitride semiconductor layer is made of GaN crystal.   The semiconductor element containing the semiconductor laminated structure of any one of the said Claims 1-5.