JP2016012737A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent deterioration in high frequency property and improve humidity resistance.SOLUTION: A semiconductor device comprises: first and second electrodes which are arranged at a distance from each other and provided in an element region on a principal surface of a semiconductor substrate; a gap formation metal film which is provided on the principal surface as to form a gap that includes the first electrode and has an opening with a part of the principal surface, and joined to the second electrode; a cured resin which blocks the opening; a liquid repellent film which is provided on an inner surface of the gap and has physical properties to make a contact angle of the resin in a liquid state be larger than that of each of the semiconductor substrate and the gap formation metal film; a first metal film which is joined with the gap formation metal film, and covers the gap formation metal film and the resin, and is joined with the semiconductor substrate in an outer peripheral region on an outer periphery of the element region; and a second metal film which is provided on a rear face of the semiconductor substrate and connected to the first electrode via a via hole which pierces the semiconductor substrate.

Description

  The present invention relates to a semiconductor device employing a non-hermetic package such as a mold package, and more particularly to a semiconductor device capable of preventing deterioration of high frequency characteristics and improving moisture resistance.

  High-frequency semiconductor devices such as field effect transistors using compound semiconductors such as GaAs and GaN are rapidly becoming widely used, and cost reduction is strongly demanded. In order to meet this demand, low-priced mold packages have been adopted in place of conventional completely airtight metal packages. However, when a non-hermetic package such as a mold package is employed, it is necessary to improve the moisture resistance of the semiconductor device in order to prevent various degradations caused by moisture.

  Conventionally, an electrode provided on the main surface of a semiconductor substrate is covered with a thick insulating film such as a SiN film formed by plasma CVD or the like. This prevented moisture from entering and secured moisture resistance.

  However, since a thick dielectric film having a high dielectric constant exists between the semiconductor substrate and the electrode, there is a problem that the capacitance component increases and the high frequency characteristics deteriorate. In addition, an insulating film formed by plasma CVD or the like tends to absorb moisture depending on the film forming conditions. When the film thickness is increased, the insulating film is peeled off due to a stress change when the insulating film absorbs moisture slightly, and coverage and film quality deteriorate at a step portion of the transistor, so that moisture is easily transmitted or absorbed. Therefore, it has been difficult to sufficiently prevent moisture from entering the transistor.

  In order to prevent deterioration of the high-frequency characteristics, there is a semiconductor device in which a gap is formed between the main surface of the semiconductor substrate and a gap forming film, a gate electrode or a drain electrode is included in the gap, and the opening of the gap is closed with a resin. It has been proposed (see, for example, Patent Document 1).

JP 2009-184067 A, particularly FIGS. 30 and 31

  Patent Document 1 does not describe in detail a method for connecting an electrode in a gap to an electrode pad outside the gap. When both are connected by metal wiring, one end of the metal wiring is connected to the electrode, and the other end of the metal wiring comes out of the resin and is connected to the electrode pad. However, when the resin is thermoset in the manufacturing process, a gap is likely to be generated at the interface between the metal wiring and the resin. Therefore, there was a problem that the moisture resistance deteriorated.

  The present invention has been made to solve the above-described problems, and an object thereof is to obtain a semiconductor device capable of preventing deterioration of high-frequency characteristics and improving moisture resistance.

  A semiconductor device according to the present invention includes a semiconductor substrate having a main surface and a back surface facing each other, first and second electrodes provided in an element region on the main surface and spaced apart from each other, and the first electrode A void-forming metal film provided on the main surface so as to be formed between the main surface and a void having an opening and including the opening, and the opening A cured resin that closes the liquid, a liquid repellent film that is provided on the inner surface of the void and has a physical property that makes the contact angle of the resin in a liquid state larger than that of the semiconductor substrate and the void-forming metal film, and the void formation A first metal film that is bonded to a metal film, covers the gap-forming metal film and the resin, and is bonded to the semiconductor substrate in an outer peripheral area at an outer periphery of the element area; and is provided on the back surface of the semiconductor substrate. Through the semiconductor substrate Characterized in that it comprises a second metal layer connected to the first electrode through the via hole to be.

  According to the present invention, deterioration of high frequency characteristics can be prevented and moisture resistance can be improved.

It is a top view which shows the semiconductor device which concerns on Embodiment 1 of this invention. It is sectional drawing along II of FIG. It is sectional drawing along II-II of FIG. It is a top view in the height of II-II of FIG. It is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on Embodiment 1 of this invention. It is sectional drawing which shows the semiconductor device which concerns on a comparative example. It is sectional drawing which shows the modification 1 of the semiconductor device which concerns on Embodiment 1 of this invention. It is sectional drawing which shows the modification 2 of the semiconductor device which concerns on Embodiment 1 of this invention. It is sectional drawing which shows the semiconductor device which concerns on Embodiment 2 of this invention. It is sectional drawing which shows the semiconductor device which concerns on Embodiment 3 of this invention. It is a top view which shows the semiconductor device which concerns on Embodiment 4 of this invention. It is a bottom view which shows the semiconductor device which concerns on Embodiment 4 of this invention. It is sectional drawing in alignment with II of FIG. It is a top view in the height of II-II of FIG. It is sectional drawing which shows the semiconductor device which concerns on Embodiment 5 of this invention. It is a top view which shows the semiconductor device which concerns on Embodiment 6 of this invention. FIG. 25 is a cross-sectional view taken along the line II of FIG. 24. It is a top view in the height of II-II of FIG. It is a top view which shows the semiconductor device which concerns on Embodiment 7 of this invention. It is a bottom view which shows the semiconductor device which concerns on Embodiment 7 of this invention. It is sectional drawing in alignment with II of FIG. It is a top view in the height of II-II of FIG. It is a top view which shows the inside of the semiconductor device which concerns on Embodiment 8 of this invention. It is a bottom view which shows the semiconductor device which concerns on Embodiment 8 of this invention.

  A semiconductor device and a manufacturing method thereof according to an embodiment of the present invention will be described with reference to the drawings. The same or corresponding components are denoted by the same reference numerals, and repeated description may be omitted.

Embodiment 1 FIG.
FIG. 1 is a top view showing a semiconductor device according to Embodiment 1 of the present invention. FIG. 2 is a cross-sectional view taken along the line II of FIG. FIG. 3 is a cross-sectional view taken along the line II-II in FIG. FIG. 4 is a top view at a height of II-II in FIG.

  In the element region on the main surface of the semiconductor substrate 1, a drain electrode 2 and a source electrode 3 are provided apart from each other, and a gate electrode 4 is provided therebetween. The drain electrode 2 and the source electrode 3 are ohmic metal layers, and the gate electrode 4 is a Schottky electrode. A drain wiring 5 having one end connected to the drain electrode 2 is provided on the main surface. A source wiring 6 is also provided on the source electrode 3. These constitute a transistor. These surfaces are protected by the SiN film 7. A contact hole is formed in the SiN film 7 at a place where the SiN film 7 is unnecessary, for example, on the source wiring 6 on the source electrode 3.

  A plated power feeding layer 8 and an Au plated layer 9 are provided on the main surface, and are joined to the source electrode 3 via the source wiring 6. A gap 10 is formed between the plating power supply layer 8 and the Au plating layer 9 and a part of the main surface. The air gap 10 includes one end of the drain wiring 5, the gate electrode 4 and the drain electrode 2, and has an opening 11. A drain electrode pad 12 and a gate electrode pad 13 are provided outside the element region on the main surface. The drain electrode pad 12 is separated from the drain wiring 5.

  The cured polyimide film 14 closes the opening 11 and covers the other end of the drain wiring 5 without covering the drain electrode pad 12 and the gate electrode pad 13. The other end of the drain wiring 5 does not protrude from the polyimide film 14. A liquid repellent film 15 is provided on the inner surface of the gap 10. The liquid repellent film 15 has physical properties that make the contact angle of the polyimide film 14 in a liquid state larger than that of the semiconductor substrate 1, the plated power feeding layer 8, and the Au plated layer 9.

  The other end of the drain wiring 5 and the drain electrode pad 12 are connected to each other by the plating power feeding layer 17 and the Au plating layer 18 through the opening 16 provided in the cured (imidized) polyimide film 14. Although not shown, the gate wiring connected to the gate electrode 4 and the gate electrode pad 13 are also connected in the same manner.

  Next, a method for manufacturing a semiconductor device according to the present embodiment will be described. 5 to 14 are cross-sectional views showing the manufacturing steps of the semiconductor device according to the first embodiment of the present invention.

  First, as shown in FIG. 5, the gate electrode 4, the drain electrode 2, and the source electrode 3 are formed in the element region on the main surface of the semiconductor substrate 1. Drain wiring 5 having one end connected to drain electrode 2 is formed on the main surface. On these surfaces, an SiN film 7 is formed as an insulating protective film by plasma CVD, and contact holes are formed in the SiN film 7.

  Next, as shown in FIG. 6, a photoresist film 19 is applied to the entire surface, and the photoresist film 19 is opened on the source wiring 6 on the source electrode 3 by a transfer process.

  Next, as shown in FIG. 7, a plated power feeding layer 8 made of Ti / Au is formed on the entire surface by, eg, sputtering.

  Next, as shown in FIG. 8, a photoresist film 20 is applied over the entire surface and opened by a transfer process. Thereafter, an Au plating layer 9 is formed on the plating power feeding layer 8 in the opening of the photoresist film 20 by electroplating. At this time, the drain electrode pad 12 and the gate electrode pad 13 are formed outside the element region on the main surface.

  Next, as shown in FIGS. 9 and 10, the photoresist film 20 is removed, and the plated power feeding layer 8 in the region where the photoresist film 20 is removed is removed by, for example, ion milling. Thereafter, the photoresist film 19 is removed. As a result, a gap 10 is formed between the plating power supply layer 8 and the Au plating layer 9 and a part of the main surface.

  Next, as shown in FIGS. 11 and 12, a liquid repellent film 15 is formed on the entire surface by an isotropic film forming method. Here, the isotropic film formation method is a film formation method in which a film formation object is deposited with approximately the same thickness regardless of the orientation and position of a film formation surface. Thereby, the liquid repellent film 15 having a sufficient thickness can be formed also on the inner surface of the gap 10. Thereafter, the unnecessary liquid repellent film 15 formed outside the inner surface of the gap 10 is removed by, for example, anisotropic etching using an RIE apparatus.

  Next, as shown in FIG. 13, a photosensitive polyimide film 14 in a liquid state is applied to the entire surface using, for example, a spray coater or a spin coater. As a result, the opening 11 of the gap 10 is closed and the other end of the drain wiring 5 is covered. Thereafter, the polyimide film 14 is cured. At this time, the gap 10 is maintained without being filled with the polyimide film 14 due to the effect of the liquid repellent film 15. Next, an opening 16 is formed in the cured polyimide film 14 on the other end of the drain wiring 5 by a transfer process.

  Next, as shown in FIGS. 1 and 2, a plating power feeding layer 17 and an Au plating layer 18 are formed and patterned by the same method as the plating power feeding layer 8 and the Au plating layer 9. As a result, the plating power feeding layer 17 and the Au plating layer 18 that connect the other end of the drain wiring 5 and the drain electrode pad 12 through the opening 16 are formed.

  Then, the effect of this Embodiment is demonstrated. In the present embodiment, a gap 10 is formed between the plated power feeding layer 8 and the Au plating layer 9 and a part of the main surface. This void 10 encloses one end of the drain wiring 5 in the element region, the drain electrode 2 and the gate electrode 4. Accordingly, since there is no insulating film having a high dielectric constant between the semiconductor substrate 1 and the gate electrode 4 and the drain electrode 2, it is possible to prevent deterioration of the high frequency characteristics.

  Another effect of the present embodiment will be described in comparison with a comparative example. FIG. 14 is a cross-sectional view showing a semiconductor device according to a comparative example. In the comparative example, the other end of the drain wiring 5 protrudes from the polyimide film 14 in order to connect the other end of the drain wiring 5 and the drain electrode pad 12. For this reason, when the polyimide film 14 is thermally cured in the manufacturing process, a gap is generated at the interface between the drain wiring 5 and the polyimide film 14. Since this gap becomes a moisture intrusion path into the gap 10, the moisture resistance is deteriorated.

  On the other hand, in the present embodiment, the other end of the drain wiring 5 and the drain electrode pad 12 are connected by the plated power feeding layer 17 and the Au plating layer 18 through the opening 16 provided in the cured polyimide film 14. Therefore, the other end of the drain wiring 5 can be prevented from coming out of the polyimide film 14. Thereby, since generation | occurrence | production of the gap | interval which can become the water | moisture-content intrusion path | route to the space | gap 10 can be suppressed, moisture resistance can be improved.

  FIG. 15 is a cross-sectional view showing Modification 1 of the semiconductor device according to Embodiment 1 of the present invention. The plating power supply layer 17 and the Au plating layer 18 completely cover the portion directly above the opening 11. Thereby, moisture resistance can be improved further.

  FIG. 16 is a sectional view showing a second modification of the semiconductor device according to the first embodiment of the present invention. In the above embodiment, the plated power supply layer 17 and the Au plated layer 18 are air bridge metal wirings. However, as shown in FIG. 16, the plated power supply layer 17 and the Au plated layer 18 may not be air bridge metal wirings. If there is no problem of disconnection depending on the shape of the polyimide film 14, the plated power supply layer 17 and the Au plating layer 18 may be substituted by vapor deposition metal wiring.

  An insulating protective film such as a SiN film may be formed on the polyimide film 14. Thereby, the plating power feeding layer 17 and the Au plating layer 18 are formed on the polyimide film 14 via the insulating protective film, and the adhesion is increased, so that the moisture resistance can be further improved.

Embodiment 2. FIG.
FIG. 17 is a sectional view showing a semiconductor device according to the second embodiment of the present invention. In the present embodiment, the drain wiring 5 and the drain electrode pad 12 are connected by the epi resistance layer 21 provided inside the semiconductor substrate 1. Note that the semiconductor layer is not limited to the epi-resistance layer 21 and may be any semiconductor layer to which impurities are added, such as an implantation resistance layer.

  The outer periphery of the polyimide film 14 intersects immediately above the epiresistance layer 21. In order to obtain an ohmic contact between the epi resistance layer 21 and the drain wiring 5, an ohmic metal 22 is provided. Although not shown, the gate wiring connected to the gate electrode 4 and the gate electrode pad 13 are also connected in the same manner.

  In the present embodiment, the other end of the drain wiring 5 does not protrude from the polyimide film 14, and the drain wiring 5 and the drain electrode pad 12 are connected by the epi resistance layer 21. Thereby, since generation | occurrence | production of the gap | interval which can become a water | moisture-content intrusion path | route to the space | gap 10 can be suppressed, moisture resistance can be improved. Further, since the gap 10 is formed as in the first embodiment, it is possible to prevent deterioration of the high frequency characteristics.

Embodiment 3 FIG.
FIG. 18 is a sectional view showing a semiconductor device according to the third embodiment of the present invention. In the present embodiment, the drain wiring 5 and the drain electrode pad 12 are connected by the metal layer 23 embedded in the semiconductor substrate 1. Although not shown, the gate wiring connected to the gate electrode 4 and the gate electrode pad 13 are also connected in the same manner. Other configurations are the same as those of the second embodiment, and the same effects as those of the second embodiment can be obtained.

Embodiment 4 FIG.
FIG. 19 is a top view showing a semiconductor device according to the fourth embodiment of the present invention. FIG. 20 is a bottom view showing a semiconductor device according to the fourth embodiment of the present invention. FIG. 21 is a cross-sectional view taken along the line II of FIG. FIG. 22 is a top view at the height of II-II in FIG. Only parts different from the first embodiment will be described.

  The other end of the drain wiring 5 exits from the polyimide film 14 and is connected to the drain electrode pad 12. Although not shown, the gate wiring connected to the gate electrode 4 and the gate electrode pad 13 are also connected in the same manner. These structures are covered with a photosensitive polyimide film 24.

  In the polyimide films 14 and 24, openings are formed on the plating power supply layer 8 and the Au plating layer 9. The plated power feeding layer 25 and the Au plated layer 26 are joined to the Au plated layer 9 through this opening. The plated feed layer 25 and the Au plated layer 26 completely cover the plated feed layer 8, the Au plated layer 9, and the polyimide film 14 in the element region, and are bonded to the semiconductor substrate 1 in the outer peripheral region at the outer periphery of the element region. .

  Au plating layers 27 and 28 are provided on the back surface of the semiconductor substrate 1. The Au plating layer 27 is connected to the drain electrode 2 via a via hole 29 penetrating the semiconductor substrate 1 and the drain wiring 5. Similarly, the Au plating 28 is connected to the gate electrode 4 through the via hole 30 or the like.

  Here, a method of forming the via holes 29 and 30 and the Au plating layers 27 and 28 will be described. First, after the plating power supply layer 25 and the Au plating layer 26 are formed, the semiconductor substrate 1 is thinned from the back side. Next, the via holes 29 and 30 are formed by dry-etching the back surface of the semiconductor substrate 1 using the photoresist as a mask to expose the plated power feeding layer 25. Next, an Au plating layer is formed on the entire surface, and an unnecessary area of the Au plating layer is removed after the transfer process using, for example, an Au etching solution (a mixed aqueous solution of iodine and potassium iodide). , 28 are formed.

  Then, the effect of this Embodiment is demonstrated. In the present embodiment, a gap 10 is formed between the plated power feeding layer 8 and the Au plating layer 9 and a part of the main surface. This void 10 encloses one end of the drain wiring 5 in the element region, the gate electrode 4 and the drain electrode 2. Accordingly, since there is no insulating film having a high dielectric constant between the semiconductor substrate 1 and the gate electrode 4 and the drain electrode 2, it is possible to prevent deterioration of the high frequency characteristics.

  In the present embodiment, the element region is completely covered by the plated power feeding layer 25 and the Au plated layer 26. For this reason, as long as the interface between the plating power supply layer 25 and the semiconductor substrate 1 does not peel in the outer peripheral region, there is no moisture intrusion path into the element region. Furthermore, the plating power supply layer 25 and the Au plating layer 26 are metal materials that are extremely resistant to moisture corrosion. Therefore, moisture resistance can be improved. Further, in the manufacturing process after the plated power supply layer 25 and the Au plated layer 26 are formed, it is possible to prevent damage to the element region and the electrode pad completely covered with the plated power supply layer 25 and the Au plated layer 26.

  When the semiconductor device according to the present embodiment is mounted on a package, the main surface side on which the Au plating layer 26 is provided becomes a die bond surface, and wire bonding is performed on the Au plating layers 27 and 28 on the back surface of the substrate.

  In this embodiment, not only active elements such as transistors but also passive elements such as MIM capacitors and microstrip lines are integrated on the main surface of the semiconductor substrate 1 so-called MMIC (Monolithic Microwave Integrated Circuit). (Wave integrated circuit). In this case, the plating power supply layer 25 and the Au plating layer 26 completely cover not only the transistor but also the passive element. Thereby, even when the material of the passive element is easily corroded, it is possible to prevent the passive element from being deteriorated (corroded). A passive element may also be formed on the back side of the semiconductor substrate 1.

Embodiment 5 FIG.
FIG. 23 is a sectional view showing a semiconductor device according to the fifth embodiment of the present invention. An ohmic metal layer 31 that is in ohmic contact with the semiconductor substrate 1 is provided in the outer peripheral region of the main surface. The plating power supply layer 25 and the Au plating layer 26 are bonded to the semiconductor substrate 1 via the ohmic metal layer 31. Other configurations are the same as those in the fourth embodiment.

  During the formation of the ohmic metal layer 31, the semiconductor substrate 1 and the eutectic part are formed by heat treatment. Therefore, the adhesion strength at the interface between the ohmic metal layer 31 and the semiconductor substrate 1 is stronger than the adhesion strength at the interface between the plated power feeding layer 8 and the semiconductor substrate 1. Thereby, since peeling between the plating power supply layer 25 and the semiconductor substrate 1 which can be a moisture intrusion path into the gap 10 can be suppressed, moisture resistance can be improved.

Embodiment 6 FIG.
FIG. 24 is a top view showing a semiconductor device according to the sixth embodiment of the present invention. 25 is a cross-sectional view taken along the line II of FIG. FIG. 26 is a top view at the height of II-II in FIG.

  Also in the region between the element region and the outer peripheral region, the plating power feeding layer 25 and the Au plating layer 26 are bonded to the semiconductor substrate 1. As a result, even when the adhesion between the plated power supply layer 25 and the semiconductor substrate 1 is weak, it is possible to prevent the peeling at the interface between the two due to the external force applied in the manufacturing process or the like. Note that the configuration of the present embodiment can also be applied to the fifth embodiment.

Embodiment 7 FIG.
FIG. 27 is a top view showing a semiconductor device according to the seventh embodiment of the present invention. FIG. 28 is a bottom view showing a semiconductor device according to Embodiment 7 of the present invention. 29 is a cross-sectional view taken along the line II of FIG. FIG. 30 is a top view at a height of II-II in FIG.

  Au plating layers 32 and 33 are provided outside the Au plating layer 26 on the main surface. The Au plating layer 32 is connected to the Au plating layer 27 through a via hole 34 penetrating the semiconductor substrate 1. Although not shown, the Au plating layer 28 and the Au plating layer 33 are connected in the same manner. Other configurations are the same as those in the fourth embodiment.

  As described above, since the gate, source, and drain external terminals are provided on the main surface of the semiconductor substrate 1, so-called flip-chip mounting can be supported. Therefore, the package can be downsized and thinned. The configuration of the present embodiment can also be applied to the fifth and sixth embodiments.

Embodiment 8 FIG.
FIG. 31 is a top view showing the inside of the semiconductor device according to the eighth embodiment of the present invention. FIG. 32 is a bottom view showing a semiconductor device according to the eighth embodiment of the present invention.

  An Au plating layer 35 is provided on the back surface of the semiconductor substrate 1. The Au plating layer 35 is connected to the plating power supply layer 8 and the Au plating layer 9 through a via hole 36 penetrating the semiconductor substrate 1. Other configurations are the same as those in the fourth embodiment.

  As described above, since the gate, source, and drain external terminals are provided on the back surface of the semiconductor substrate 1, so-called surface mounting can be supported. In addition, since the outer dimensions of the semiconductor device can be reduced as compared with the seventh embodiment, the package can be further reduced in size and thinned as compared with the seventh embodiment. The configuration of the present embodiment can also be applied to the fifth and sixth embodiments.

  In the above embodiment, the case where the field effect transistor is provided in the element region on the main surface of the semiconductor substrate 1 has been described. However, a bipolar transistor having a base electrode, an emitter electrode, and a collector electrode in the element region. May be provided.

1 Semiconductor substrate 2 Drain electrode (electrode, first electrode)
3 Source electrode (second electrode)
4 Gate electrode (electrode, first electrode)
5 Drain wiring (metal wiring)
8 Plating power supply layer (void formation film, gap formation metal film)
9 Au plating layer (void formation film, gap formation metal film)
10 gap 11 opening 12 drain electrode pad (electrode pad)
14 Polyimide film 15 Liquid repellent film 17 Plating power supply layer (metal film)
18 Au plating layer (metal film)
21 Epi resistance layer (conductive layer)
23 Metal layer (conductive layer)
25 Plating feeding layer (first metal film)
26 Au plating layer (first metal film)
27, 28 Au plating layer (second metal film)
29, 30, 36 Via hole 31 Ohmic metal layer 32, 33, 35 Au plating layer (third metal film)

Claims (5)

A semiconductor substrate having a main surface and a back surface facing each other;
First and second electrodes provided in an element region on the main surface and spaced apart from each other;
A void-forming metal film which is provided on the main surface so as to be formed between the first electrode and the first electrode so that a void having an opening is formed between the first electrode and the second electrode. When,
A cured resin that closes the opening;
A liquid repellent film provided on the inner surface of the void and having a physical property that makes the contact angle of the resin in a liquid state larger than that of the semiconductor substrate and the void-forming metal film;
A first metal film that is bonded to the gap-forming metal film, covers the gap-forming metal film and the resin, and is bonded to the semiconductor substrate in an outer peripheral region at an outer periphery of the element region;
A semiconductor device comprising: a second metal film provided on the back surface of the semiconductor substrate and connected to the first electrode through a via hole penetrating the semiconductor substrate. An ohmic metal layer provided in the outer peripheral region of the main surface and in ohmic contact with the semiconductor substrate;
The semiconductor device according to claim 1, wherein the first metal film is bonded to the semiconductor substrate via the ohmic metal layer.   3. The semiconductor device according to claim 1, wherein the first metal film is bonded to the semiconductor substrate also in a region between the element region and the outer peripheral region.   A third metal film is further provided on the main surface outside the first metal film and connected to the second metal film through a via hole penetrating the semiconductor substrate. The semiconductor device according to claim 1.   4. The semiconductor device according to claim 1, further comprising a third metal film provided on the back surface and connected to the gap-forming metal film through a via hole penetrating the semiconductor substrate. The semiconductor device described.

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