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JP2015158964A - RAM cell using thyristor - Google Patents

RAM cell using thyristor Download PDF

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JP2015158964A
JP2015158964A JP2014048132A JP2014048132A JP2015158964A JP 2015158964 A JP2015158964 A JP 2015158964A JP 2014048132 A JP2014048132 A JP 2014048132A JP 2014048132 A JP2014048132 A JP 2014048132A JP 2015158964 A JP2015158964 A JP 2015158964A
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ram
memory
thyristor
cell
access
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JP6007396B2 (en
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正仁 櫨田
Masahito Utsugida
正仁 櫨田
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Abstract

PROBLEM TO BE SOLVED: To solve a problem that the conventional memory element cannot allow a CPU to access a memory rapidly due to refresh operation of a D-RAM and a large occupied cell area by an S-RAM.SOLUTION: There is provided a RAM cell that obtains a current mode memory function using a thyristor, performs current-voltage conversion by causing current to flow through a replacement FET for resistor, has a smaller occupied area than an S-RAM and no cross wiring, has no peripheral circuit preventing high-speed access. This configuration allows the RAM cell to perform input and output of data with high speed.

Description

この発明はコンピューターのメモリーに関する。  The present invention relates to a memory of a computer.

この発明は、コンピューターのメモリーにおいて、コンデンサー等の従来のメモリー素子を用いず、ゲート電圧で電流を制御できるサイリスタを使用することで電流モードのメモリー機能を持たせ、抵抗によって電流−電圧変換を行い、電圧出力を得られるようにしたものである。  This invention uses a thyristor that can control the current with a gate voltage without using a conventional memory element such as a capacitor in a memory of a computer, so that it has a memory function in a current mode and performs current-voltage conversion with a resistor. The voltage output can be obtained.

コンピューターのデータ処理のスピードはＣＰＵの処理速度によっており、その処理時間の大部分をメモリーとのデータの入出力に取られている。そのメモリーを構成するメモリーセルは、Ｄ−ＲＡＭでのメモリー素子はコンデンサであり、自然放電に対するリフレシュ動作とそのアクセス方法による周辺回路のセンスアンプの安定化までのプリチャージタイムがメモリーアクセス高速化への問題であった。また、Ｓ−ＲＡＭでは、メモリー機能がフリップフロップによる結線構造にあり、出力はラインを読むだけで済むのでアクセスは速いのだが、ＲＡＭセルの構成素子数が多いのと配線が多少複雑なので専有面積が大きく、また、１ビット当たりのコストもＤ−ＲＡＭよりも大きいので、コスト面からコンピューターへの大量使用は敬遠されていた。
そこで、ＲＡＭセルのメモリー素子をサイリスタ素子に変えることでリフレシュ動作とプリチャージタイムにかかる時間を省き、また、Ｓ−ＲＡＭよりもクロス配線等のＲＡＭセルの配線を簡素化することができる。The data processing speed of the computer depends on the processing speed of the CPU, and most of the processing time is taken for data input / output with the memory. The memory cell constituting the memory is a memory element in the D-RAM that is a capacitor, and the refresh operation against natural discharge and the precharge time until the sense amplifier of the peripheral circuit is stabilized by the access method increase the memory access speed. It was a problem. In S-RAM, the memory function is a flip-flop connection structure, and the output is only read by reading the line, so the access is fast. However, because the number of components of the RAM cell is large and the wiring is somewhat complicated, the occupied area is large. In addition, since the cost per bit is larger than that of D-RAM, large-scale use for computers has been avoided from the viewpoint of cost.
Therefore, by changing the memory element of the RAM cell to a thyristor element, the time required for the refresh operation and the precharge time can be omitted, and the wiring of the RAM cell such as the cross wiring can be simplified as compared with the S-RAM.

近年、コンピューターのシステム・クロックは次第に速くなり、ＣＰＵがメモリーをアクセスする時にＷａｉｔを掛けるのは避けられない状況となっている。それは、Ｄ−ＲＡＭがメモリーセルからデータを呼び出すのに ６０ｎｓ〜８０ｎｓ程時間がかかり、この時間がシステム・クロックの一周期の時間より遅いためにこうなるのである。
この発明は、ＣＰＵのメモリーへのアクセス時にＷａｉｔを掛ける為に遅くなる問題点と、リフレッシュ動作、プリチャージタイムを無くし、サイリスタの降下電圧を小さくする事でメモリーセルの出力電圧を高くそのまま出力して、メモリーアクセス時間の遅れとなる、メモリーの周辺回路を無くし、書き込みデータと読み出しデータを分けたことで、Ｄ−ＲＡＭよりも速くアクセス出来るようにするものである。In recent years, computer system clocks have become increasingly faster, and it is inevitable that the CPU will multiply the wait when accessing the memory. This is because it takes about 60 ns to 80 ns for the D-RAM to recall data from the memory cell, and this time is slower than the period of one cycle of the system clock.
In the present invention, the problem that the CPU is delayed when accessing the memory is delayed, the refresh operation and the precharge time are eliminated, and the output voltage of the memory cell is output as it is by reducing the voltage drop of the thyristor. Thus, the peripheral circuit of the memory that causes a delay in the memory access time is eliminated, and the write data and the read data are separated so that the access can be made faster than the D-RAM.

この為、この発明においては、ＣＰＵのメモリーへのアクセスにおいてＷａｉｔを入れないように、メモリーの書き込み、読み出し信号を分け、動作速度を速くしている。  For this reason, in the present invention, the write and read signals of the memory are divided so as to increase the operation speed so as not to put a wait in accessing the memory of the CPU.

この発明によりＣＰＵのメモリーへのアクセスがＷａｉｔ無しで出来るようになり、また、Ｄ−ＲＡＭのようにリフレシュ動作も必要なく、結果としてＣＰＵは数十倍の速さでメモリーをアクセス出来るようになる。  According to the present invention, it becomes possible to access the memory of the CPU without waiting, and no refresh operation is required unlike the D-RAM, and as a result, the CPU can access the memory several tens of times faster. .

が本発明のＲＡＭセルである。回路図は電流メモリー機能を持つサイリスタと電流−電圧変換する抵抗代用のＦＥＴ、このＦＥＴの電圧を読みだすＦＥＴ、それにサイリスタへデ−タの書き込みをするＦＥＴの４素子から構成されている。データ書き込み用のＦＥＴに電源電圧（Ｈｉｇｈ ｌｅｖｅｌ）を掛けるとサイリスタがＯＮとなり、電流−電圧変換する抵抗代用のＦＥＴに電圧が発生し、ＲＡＭセルのロジックとしては１になる。この１を出力用のＦＥＴで読みだす。また、この書き込み用のＦＥＴにアース電圧（Ｌｏｗ ｌｅｖｅｌ）を掛けると、サイリスタがＯＦＦとなり、出力電圧は電流−電圧変換する抵抗代用のＦＥＴでアース電圧にプル・ダウンされ、ＲＡＭセルのロジックとしては０になり、読みだすときには、この０電圧を出力用のＦＥＴで読みだす。このＲＡＭセルに必要な配線は、サイリスタに電流を供給するＩ線とＲＡＭセルをセレクトし、読み書きするＲ／Ｗ線、書き込みデータと出力データを分けた為の書き込み用のＷ線と読み出し用のＤ線の４本が必要となる。Is the RAM cell of the present invention. The circuit diagram is composed of four elements: a thyristor having a current memory function, a resistance substitute FET for current-voltage conversion, an FET for reading the voltage of the FET, and an FET for writing data to the thyristor. When a power supply voltage (High level) is applied to the data write FET, the thyristor is turned on, and a voltage is generated in the resistor substitute FET for current-voltage conversion, which becomes 1 as the logic of the RAM cell. This 1 is read out by the output FET. When a ground voltage (Low level) is applied to the write FET, the thyristor is turned off, and the output voltage is pulled down to the ground voltage by a resistor-substitute FET that performs current-voltage conversion. When it becomes 0 and is read, this 0 voltage is read by the FET for output. The wiring necessary for this RAM cell is selected from the I line for supplying current to the thyristor and the RAM cell, the R / W line for reading and writing, the writing W line for separating write data and output data, and the reading line. Four D lines are required.

Claims (1)

コンデンサー等の従来のメモリー素子を使用せず、メモリー素子にサイリスタ素子を使うことで電流モードのメモリー機能を持たせ、抵抗代用のＦＥＴで電流−電圧変換を行う事によりスタティック−ＲＡＭ（以下、Ｓ−ＲＡＭ）より配線を簡素化し、また、センスアンプ等の周辺回路を使用しない事でダイナミック−ＲＡＭ（以下、Ｄ−ＲＡＭ）より高速にアクセス出来るようにしたＲＡＭセル。  Without using a conventional memory element such as a capacitor, the memory element has a memory function in a current mode by using a thyristor element, and a static-RAM (hereinafter, S A RAM cell in which wiring is simplified from that of (RAM) and access is made faster than dynamic RAM (hereinafter referred to as D-RAM) by not using a peripheral circuit such as a sense amplifier.
JP2014048132A 2014-02-24 2014-02-24 RAM cell using thyristor Expired - Fee Related JP6007396B2 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019102115A (en) * 2017-12-06 2019-06-24 正仁 櫨田 Method for doubling operation speed in cpu of computer
KR20200027823A (en) * 2018-09-05 2020-03-13 고려대학교 산학협력단 Feedback field-effect array device capable of changing operation between volatile operation and nonvolatile operation and array circuit using the same

Citations (7)

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JPS57111883A (en) * 1980-12-29 1982-07-12 Fujitsu Ltd Integrated storage circuit
EP1420413A1 (en) * 2002-11-12 2004-05-19 Hitachi, Ltd. Improved memory device
JP2005222668A (en) * 2004-02-04 2005-08-18 Masahito Utsugida Ram cell using thyristor
US6944051B1 (en) * 2003-10-29 2005-09-13 T-Ram, Inc. Data restore in thryistor based memory devices
JP2009087459A (en) * 2007-09-28 2009-04-23 Sony Corp Semiconductor device
JP2011522413A (en) * 2008-05-29 2011-07-28 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド Gated lateral thyristor-based random access memory (GLTRAM) cell having separate read and write access transistors and memory device and integrated circuit incorporating the same
JP2011523785A (en) * 2008-05-29 2011-08-18 グローバルファウンドリーズ・インコーポレイテッド Method for manufacturing a gated lateral thyristor based random access memory (GLTRAM) cell

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57111883A (en) * 1980-12-29 1982-07-12 Fujitsu Ltd Integrated storage circuit
EP1420413A1 (en) * 2002-11-12 2004-05-19 Hitachi, Ltd. Improved memory device
US6944051B1 (en) * 2003-10-29 2005-09-13 T-Ram, Inc. Data restore in thryistor based memory devices
JP2005222668A (en) * 2004-02-04 2005-08-18 Masahito Utsugida Ram cell using thyristor
JP2009087459A (en) * 2007-09-28 2009-04-23 Sony Corp Semiconductor device
JP2011522413A (en) * 2008-05-29 2011-07-28 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド Gated lateral thyristor-based random access memory (GLTRAM) cell having separate read and write access transistors and memory device and integrated circuit incorporating the same
JP2011523785A (en) * 2008-05-29 2011-08-18 グローバルファウンドリーズ・インコーポレイテッド Method for manufacturing a gated lateral thyristor based random access memory (GLTRAM) cell

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019102115A (en) * 2017-12-06 2019-06-24 正仁 櫨田 Method for doubling operation speed in cpu of computer
KR20200027823A (en) * 2018-09-05 2020-03-13 고려대학교 산학협력단 Feedback field-effect array device capable of changing operation between volatile operation and nonvolatile operation and array circuit using the same
US10643699B2 (en) 2018-09-05 2020-05-05 Korea University Research And Business Foundation Feedback field-effect array device capable of converting between volatile and non-volatile operations and array circuit using the same
KR102118440B1 (en) * 2018-09-05 2020-06-03 고려대학교 산학협력단 Feedback field-effect array device capable of changing operation between volatile operation and nonvolatile operation and array circuit using the same

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