JP2015029158A - Multilayer ceramic capacitor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a reliable multilayer ceramic capacitor which is high in resistance against an impact from the outside, and superior in moisture resistance, and capable of reducing the occurrence of cracks or chips, and without suffering from moisture infiltration from portions where the cracks or chips occur.SOLUTION: A multilayer ceramic capacitor comprises: a ceramic elemental body 10 including dielectric layers and internal electrodes 2 arranged between the dielectric layers; and external electrodes provided to electrically connect with the corresponding internal electrodes 2. The ceramic elemental body has margin areas M. The content of Si in dielectric ceramic in each margin area M is made higher than those in other areas; the content of Si in dielectric ceramic in each margin area is 10-24%. Also, the content of Si in the dielectric ceramic in the outermost dielectric layer 1a is made higher than those in other areas other than the margin areas. The outermost dielectric layer is made thinner than the margin areas in thickness.

Description

  The present invention relates to a multilayer ceramic capacitor, and more particularly, to a multilayer ceramic capacitor having a structure in which an external electrode is provided in a ceramic body having an internal electrode so as to be electrically connected to the internal electrode.

  One typical ceramic electronic component is, for example, a multilayer ceramic capacitor as disclosed in Patent Document 1.

As shown in FIG. 5, this multilayer ceramic capacitor has a pair of ceramic laminates (ceramic bodies) 110 in which a plurality of internal electrodes 102 (102a, 102b) are laminated via a ceramic layer 101 which is a dielectric layer. The end surface 103 (103a, 103b) has a structure in which a pair of external electrodes 104 (104a, 104b) are disposed so as to be electrically connected to the internal electrode 102 (102a, 102b).
Such multilayer ceramic capacitors are widely used in various fields.

However, when the multilayer ceramic capacitor as described above and the ceramic body produced in the manufacturing process are moved between facilities used for manufacturing the multilayer ceramic capacitor or handled in a packaged state. In such a case, there is a problem that cracks and chips are likely to occur due to an impact caused by a collision between multilayer ceramic capacitors or ceramic bodies.
In addition, there is a problem that moisture enters from a portion where a crack or chip occurs, leading to deterioration of characteristics such as insulation resistance, and there is a problem that reliability as a multilayer ceramic capacitor is lowered.

JP2013-12418A

  The present invention solves the above problems, has high resistance to external impact, can suppress the occurrence of cracks and chips, and prevents moisture from entering from the cracked or chipped parts. An object of the present invention is to provide a highly reliable monolithic ceramic capacitor that has no fear of incurring and has excellent moisture resistance.

In order to solve the above problems, the multilayer ceramic capacitor of the present invention is
A ceramic body comprising: a dielectric layer made of a dielectric ceramic; and a plurality of internal electrodes stacked via the dielectric layer and positioned at a plurality of interfaces between the dielectric layers, A main surface and a second main surface opposite to the first main surface; a first end surface orthogonal to the first main surface; a second end surface opposite to the first end surface; and the first A rectangular parallelepiped shape including a first side surface orthogonal to the end surface of the first side surface and a second side surface facing the first side surface, and a direction from the first main surface toward the second main surface is the dielectric. A ceramic body in which the body layers and the internal electrodes are stacked, and the plurality of internal electrodes are alternately drawn to the first end face and the second end face;
A multilayer ceramic capacitor comprising a pair of external electrodes disposed on the ceramic body so as to be electrically connected to the internal electrodes drawn out to the first end surface and the second end surface;
A laminate formed by the plurality of internal electrodes and the dielectric layer interposed between the internal electrodes when the ceramic body is viewed from the first or second end face side, and the ceramic body And the Si content in the dielectric ceramic in the margin region located between the first and second side surfaces is higher than the Si content in the dielectric ceramic in the other regions, and
The Si content in the dielectric ceramic in the margin region is in the range of 10 to 24%.

  In the multilayer ceramic capacitor of the present invention, among the plurality of internal electrodes, the outermost dielectric layer positioned outside the outermost internal electrode in the stacking direction also has an Si content in the dielectric ceramic. It is preferable that the Si content in the dielectric ceramic in the other region excluding the margin region is higher.

By increasing the Si content in the dielectric ceramic in the outermost dielectric layer, it is possible to improve the shock absorbing ability when an external impact is applied to the outermost dielectric layer.
As a result, the margin region and the outermost dielectric layer can reliably absorb the impact applied from the total four sides of the ceramic body, and a highly reliable multilayer ceramic capacitor can be obtained. Is possible.

  Further, the thickness of the outermost dielectric layer is a distance from the end in the width direction of the internal electrode to the first or second side surface of the ceramic body facing the end in the width direction. It is preferable to make it thinner than the thickness of the margin region.

By increasing the Si content in the dielectric ceramic in the outermost dielectric layer, the necessary shock absorbing performance can be ensured without increasing the thickness of the outermost dielectric layer.
Therefore, even when the thickness of the outermost dielectric layer is made thinner than the thickness of the margin region, the necessary shock absorbing performance can be ensured.
Further, by reducing the thickness of the outermost dielectric layer, the dimension in the height direction of the multilayer ceramic capacitor can be reduced.
Further, when the height dimension of the multilayer ceramic capacitor is the same, the number of stacked internal electrodes can be increased.
As a result, it is possible to increase the capacity of the multilayer ceramic capacitor while ensuring reliability such as impact resistance.

As described above, in the multilayer ceramic capacitor of the present invention, the Si content in the dielectric ceramic in the margin region is made higher than the Si content in the dielectric ceramic in the other regions, and the dielectric in the margin region Since the Si content in the ceramic is in the range of 10 to 24%, the elastic modulus of the margin region can be reduced and the amount of bending of the ceramic body with respect to external force can be reduced.
As a result, it is possible to prevent cracks and chips from occurring when an external impact is applied, and a highly reliable multilayer ceramic capacitor can be obtained.

  The Si content of 10 to 24% was analyzed by WDX for the exposed surface exposed by polishing the ceramic body from the first or second end surface side to the center in the length direction. In this case, the ratio of the area of the region where Si is detected to the area of the exposed surface is 10 to 24%.

If the Si content is less than 10%, a decrease in the elastic modulus of the margin region cannot be expected, and the ceramic body is likely to be cracked or chipped.
On the other hand, when the Si content exceeds 24%, the characteristics as glass are remarkably exhibited, and cracks / chips tend to occur.

It is a front sectional view showing the composition of the multilayer ceramic capacitor concerning one embodiment of the present invention. 1 is a perspective view showing an external configuration of a multilayer ceramic capacitor according to an embodiment of the present invention. It is side surface sectional drawing which shows the structure of the multilayer ceramic capacitor concerning one Embodiment of this invention. It is a figure which shows the modification of the multilayer ceramic capacitor concerning one Embodiment of this invention. It is front sectional drawing which shows the structure of the conventional multilayer ceramic capacitor.

  Embodiments of the present invention will be described below to describe the features of the present invention in more detail.

  FIG. 1 is a front sectional view showing a configuration of a multilayer ceramic capacitor 50 according to one embodiment (Embodiment 1) of the present invention, and FIG. 2 is a perspective view showing an external configuration of the multilayer ceramic capacitor 50.

  As shown in FIGS. 1 and 2, the multilayer ceramic capacitor 50 includes a dielectric layer 1 made of a dielectric ceramic and a plurality of internal electrodes 2 (2a, 2b) disposed at a plurality of interfaces between the dielectric layers 1. And a pair of external electrodes 5 (5a, 5b) disposed on the outer surface of the ceramic body 10 so as to be electrically connected to the internal electrodes 2 (2a, 2b). Yes.

An auxiliary electrode 6 (6a, 6b) is disposed between the internal electrode 2 (2a, 2b) and a first main surface 11a and a second main surface 11b of the ceramic body 10, which will be described later. ing. The auxiliary electrode 6 (6a, 6b) is electrically connected to an external electrode having the same potential as the adjacent internal electrode 2 (2a, 2b). However, it may not be electrically connected to the external electrode.
Further, it is possible to adopt a configuration in which the auxiliary electrode 6 (6a, 6b) is not provided.

The dielectric layer 1 constituting the ceramic body 10 is made of a BaTiO ₃ -based or CaZrO ₃ -based ceramic dielectric.
The internal electrode 2 is a metal layer mainly composed of a base metal such as Ni or Cu.

  The ceramic body 10 has a rectangular parallelepiped shape, and includes a first main surface 11a, a second main surface 11b facing the first main surface 11a, and a first main surface 11a orthogonal to the first main surface 11a. An end surface 21a, a second end surface 21b facing the first end surface 21a, a first side surface 31a orthogonal to the first end surface 21a, and a second side surface 31b facing the first side surface 31a are provided. .

  When the direction connecting the first main surface 11a and the second main surface 11b is the height direction, the height direction is the stacking direction of the dielectric layer 1 and the internal electrodes 2 (2a, 2b). .

  A plurality of internal electrodes 2 (2a, 2b) are alternately drawn out on the first end face 21a and the second end face 21b, the internal electrode 2a is drawn out on the first end face 21a, and the second end face The internal electrode 2b is drawn out to 21b.

  In the multilayer ceramic capacitor 50 according to this embodiment, the external electrode 5 (5a, 5b) has a structure including the sintered metal layer 12 (12a, 12b) and the plating layer 32 (32a, 32b). ing.

  The sintered metal layer 12 (12a, 12b) is a baked electrode (thick film electrode) formed by applying and baking a conductive paste containing Cu powder or Ni powder as a conductive component on the ceramic body 10. The constituent material of the sintered metal layer 12 (12a, 12b) is not limited to the above-described Cu or Ni, and other metal materials can also be used.

The sintered metal layer 12 (12a, 12b) is formed from the first end surface 21a and the second end surface 21b of the ceramic body 10 and the first and second main surfaces 11a, 11b of the ceramic body 10 and It is formed so as to go around the first and second side surfaces 31a and 31b.
The thickness of the sintered metal layer 12 is usually desirably in the range of 0.5 μm to 10 μm.
However, the thickness of the sintered metal layer 12 is not limited to the above range, and may be other thicknesses.

  The plating layer 32 (32a, 32b) is formed so as to cover the entire sintered metal layer 12 (12a, 12b).

  In this embodiment, the plating layer 32 (32a, 32b) includes the Ni plating layer 33 (33a, 33b) formed on the sintered metal layer 12 (12a, 12b) and the Ni plating layer 33 (33a, 33b). 33b) a plating layer having a two-layer structure including the Sn plating layer 34 (34a, 34b) formed thereon.

  In the multilayer ceramic capacitor 50, the boundary between the auxiliary electrode 6 (6a, 6b) and the outer ceramic layer (that is, the ceramic layer on the first main surface 11a and the second main surface 11b side). Is provided with 69% or more of a boundary layer containing Mg and Mn. The auxiliary electrode 6 (6a, 6b) has a continuity of 60% or more. Furthermore, segregated materials containing Si are present in 39% or more of the defect portions, which are regions where continuity is interrupted. The molar ratio Mn / Mg of the Mn content to the Mg content in the boundary layer is not particularly limited, but is particularly preferably in the range of Mn / Mg = 0.005 to 0.7.

  The presence of the boundary layer of the auxiliary electrode 6 (6a, 6b) was confirmed as follows. First, the multilayer ceramic capacitor was polished by a polishing machine in such a manner that the surface defined by the length direction and the thickness direction was exposed. At this time, after polishing to a depth of about ½ in the width direction of the multilayer ceramic capacitor, sagging of the internal electrode due to the polishing was removed.

  Then, on the polished end face polished as described above, a straight line substantially perpendicular to the internal electrode 2 is drawn (assumed) at the central position in the length direction of the multilayer ceramic capacitor. And the area | region (boundary layer) where the boundary part of the auxiliary electrode 6 (6a, 6b) and the said straight line orthogonally crossed was observed by magnification 10,000 times using the electron microscope. And in this embodiment, the presence of the boundary layer of the auxiliary electrode 6 (6a, 6b) was confirmed by setting the width of the observation visual field to 10 μm and performing observation with FE-WDX.

The thickness of the internal electrode 2 (2a, 2b) was determined as follows.
First, the polishing end face was divided into three equal parts in the thickness direction, and was divided into three regions: an upper region, an intermediate region, and a lower region. And in each area | region, except the outermost internal electrode 2, the thickness of the internal electrode 2 of the position orthogonal to said straight line was measured at random 5 layers each, and the average value was calculated | required. The thickness of the internal electrode was measured using a scanning electron microscope. However, parts that could not be measured due to a lack of internal electrodes were excluded from the measurement target.

  In addition, the thickness of the dielectric layer 1 is measured by randomly measuring five layers of the dielectric layer 1 at positions orthogonal to the straight line in each of the three regions, the upper region, the middle region, and the lower region. The average value was obtained. The thickness of the dielectric layer was measured using a scanning electron microscope.

  In the multilayer ceramic capacitor 50 of this embodiment, as shown in FIG. 3, the plurality of internal electrodes 2 when the ceramic body 10 is viewed from the first or second end face side 21a, 21b (FIG. 2). And a laminated portion 40 formed by the dielectric layer 1 interposed between the internal electrodes 2, and a margin region located between the laminated portion 40 and the first and second side surfaces 31a and 31b of the ceramic body 10 The Si content in the dielectric ceramic at M is set higher than the Si content in the dielectric ceramic in other regions, and the Si content in the margin region is in the range of 10 to 24%.

  Here, the Si content was analyzed by WDX after removing the polishing sagging on the exposed surface exposed by polishing the ceramic body from the first or second end surface side to the center in the length direction. In this case, the ratio of the area of the detected Si area to the area of the exposed surface.

  As described above, by making the Si content in the dielectric ceramic in the margin region M higher than in other regions and setting the Si content in the margin region to 10 to 24%, an external impact is applied. In this case, it is possible to prevent cracks and chips from occurring, and a highly reliable multilayer ceramic capacitor can be obtained.

As a method for increasing the Si content in the dielectric ceramic in the margin region M as compared with other regions, for example, by adding a Si component to the ceramic green sheet on which the internal electrode pattern is formed, firing is performed. Examples include a method in which Si is segregated in the process, and the Si content in the dielectric ceramic in the margin region M after firing is higher than the Si content in the dielectric ceramic in other regions.
It is also possible to configure so as separately adding SiO ₂ containing material to a predetermined ceramic green sheets.

Further, in this multilayer ceramic capacitor 50, as shown in FIG. 4, the Si content in the margin region M is increased, and the outer side of the inner electrode 2 located on the outermost side in the stacking direction among the plurality of inner electrodes 2. It is also possible to make the Si content in the dielectric ceramic in the outermost dielectric layer 1a located at a position higher than the Si content in the dielectric ceramic in other regions except the margin region M. is there.
Note that the Si content in the dielectric ceramic in the outermost dielectric layer 1a may be different from the Si content in the margin region M.

  It should be noted that by increasing the Si content in the dielectric ceramic in the outermost dielectric layer 1a, it is possible to improve the impact absorbing ability when an external impact is applied to the outermost dielectric layer 1a. As a result, the first and second side surfaces 31a and 31b of the ceramic body 10 and the first and second main surfaces 11a and 11b are added by the margin region M and the outermost dielectric layer 1a. It becomes possible to absorb the impact more reliably.

  Further, it is desirable that the thickness t1 of the outermost dielectric layer 1a be configured to be thinner than the thickness tM of the margin region M.

  As shown in FIGS. 3 and 4, the margin region M has a thickness tM from the width direction end 2xa or 2xb of the internal electrode 2 to the first or second of the ceramic body 10 facing the width direction ends 2xa and 2xb. It is the distance to the side surfaces 31a and 31b.

  When the thickness t1 of the outermost dielectric layer 1a is made smaller than the thickness tM of the margin region M, if the dimensions in the height direction of the multilayer ceramic capacitor are made the same, the number of stacked internal electrodes can be increased, and the resistance The capacity of the multilayer ceramic capacitor can be increased while ensuring reliability such as impact properties.

In this embodiment, as the multilayer ceramic capacitor 50,
(A) Multi-layer ceramic capacitor having dimensions including an external electrode: length (L): 1.0 mm, width (W): 0.5 mm, height (T): 0.5 mm;
(B) Multi-layer ceramic capacitors having dimensions including the external electrode, the length (L): 0.6 mm, the width (W): 0.3 mm, and the height (T): 0.3 mm;
(C) A monolithic ceramic capacitor having dimensions including the external electrode of length (L): 0.4 mm, width (W): 0.2 mm, and height (T): 0.2 mm was produced.

  However, the present invention is not limited to the monolithic ceramic capacitor having the dimensions as described above, and can be applied to monolithic ceramic capacitors having different dimensions.

Next, a method for manufacturing the multilayer ceramic capacitor 50 will be described.
First, a ceramic raw material slurry in which a binder and a solvent are mixed and dispersed in a dielectric ceramic powder mainly composed of BaTiO ₃ or CaZrO ₃ is thinly stretched on a resin film such as a PET film and formed into a sheet shape. A ceramic green sheet is prepared.

  Then, a conductive paste is printed on the ceramic green sheet using a method such as screen printing or gravure printing to form an internal electrode pattern.

  Then, a predetermined number of ceramic green sheets on which internal electrode patterns are formed and ceramic green sheets on which no internal electrode patterns are formed (ceramic green sheets for outer layers) are stacked in a predetermined order.

  And the obtained laminated block is pressed and each ceramic green sheet is crimped | bonded. In pressing the laminated block, for example, the pressure-bonding block is sandwiched between resin films and pressed by a method such as isostatic pressing.

  Thereafter, the pressed laminated pressure-bonded body is divided into rectangular parallelepiped-shaped chips (pieces) using a method such as pressing and cutting, and barrel polishing is performed.

  The barrel-polished chip (the piece that becomes the ceramic body 10 (FIG. 1) after firing) is heated to a predetermined temperature to remove the binder, and then fired at, for example, 900 to 1000 ° C. to obtain a rectangular parallelepiped. A shaped ceramic body is obtained.

  In the case of the multilayer ceramic capacitor of the present invention, for example, the ceramic green sheet can be fired (cofired) simultaneously with the internal electrode pattern, and a ceramic green sheet containing Si is used to perform the cofire process. Thus, by segregating Si into the margin region M, the Si content in the dielectric ceramic in the margin region M can be configured to be higher than in other regions.

  In addition, as another method for increasing the Si content in the dielectric ceramic in the margin region M as compared with other regions, a method of applying a Si-containing ceramic slurry to a portion that becomes a margin region of the ceramic green sheet, etc. It is also possible to use it.

  Further, as a method of increasing the Si content in the dielectric ceramic in the outermost dielectric layer, as in the case of increasing the Si content in the dielectric ceramic in the margin region M, a method of segregating Si, Si A method of adding components separately can be used.

  Then, the other end face side of the ceramic body is held, and one end face of the ceramic body is immersed in a conductive paste layer formed by applying a conductive paste containing Cu powder or Ni powder on the surface plate. Thus, the conductive paste is applied to one end surface of the ceramic body and dried.

  Next, a conductive paste is applied and dried on the other end face of the ceramic body in the same manner.

  Then, a sintered metal layer is formed by baking the conductive paste at one end and the other end of the ceramic body applied as described above.

Thereafter, Ni plating and Sn plating are performed in this order on the sintered metal layer to form a Ni plating layer and a Sn plating layer.
Thereby, the multilayer ceramic capacitor 50 according to the embodiment of the present invention having the structure as shown in FIGS. 1 and 2 is obtained.

<Test>
In order to confirm the effect of the present invention, Sample No. 1 in which the Si content in the dielectric ceramic in the margin region was made higher than the other regions, and as shown in Table 1, the Si content in the margin region was varied. -5 multilayer ceramic capacitors (samples) were produced.

  In addition, as a multilayer ceramic capacitor, the dimension including an external electrode was produced with length (L): 0.6 mm, width (W): 0.3 mm, and height (T): 0.3 mm.

  Then, these multilayer ceramic capacitors were fixed to the stage, a 5.0 g weight was dropped from a position 20 mm away in the height direction, and the number of samples in which cracks and chips occurred was examined. The number of samples was 10. The results are shown in Table 1.

  As shown in Table 1, in the case of Sample Nos. 2 to 4 where the Si content in the dielectric ceramic in the margin region is 10 to 24%, the occurrence of cracks and chips in any of the 10 samples. I was not able to admit.

  On the other hand, in the case of the sample No. 1 in which the Si content in the dielectric ceramic in the margin region is 8%, and in the case of the sample No. 5 in which the Si content in the dielectric ceramic is 30%, 10 Of the two samples, cracks and chipping were observed in two samples.

  In addition, about the sample of sample numbers 2-4, it analyzed by WDX about the exposed surface which grind | polished and exposed the multilayer ceramic capacitor from the 1st or 2nd end surface side to the center part of a length direction, and contains silicon It was confirmed that the rate was as designed.

  From the above results, the Si content in the dielectric ceramic in the margin region is made higher than the Si content in the dielectric ceramic in the other regions, and the Si content in the dielectric ceramic in the margin region is 10 to 10. By setting the range to 24%, resistance to external impact is high, generation of cracks and chips can be suppressed, moisture does not enter from the cracked or chipped part, and moisture resistance is achieved. It was confirmed that an excellent and reliable multilayer ceramic capacitor was obtained.

  In addition, this invention is not limited to the said embodiment, A various application and deformation | transformation are possible within the scope of the invention.

DESCRIPTION OF SYMBOLS 1 Dielectric layer 1a Outermost layer dielectric 2 (2a, 2b) Internal electrode 2xa, 2xb End part of width of internal electrode 5 (5a, 5b) External electrode 6 (6a, 6b) Auxiliary electrode 10 Ceramic element body 11a Ceramic element First main surface of body 11b Second main surface of ceramic body 12 (12a, 12b) Sintered metal layer 20 Internal electrode thickness increasing portion 21a First end surface of ceramic body 21b Second of ceramic body End surface 31a First side surface 31b of ceramic body 32b Second side surface of ceramic body 32 (32a, 32b) Plating layer 33 (33a, 33b) Ni plating layer 34 (34a, 34b) Sn plating layer 50 Multilayer ceramic capacitor L Length of multilayer ceramic capacitor T Height of multilayer ceramic capacitor W Width of multilayer ceramic capacitor M Margin area t1 Outermost dielectric layer tM Margin area thickness

Claims (3)

A ceramic body comprising: a dielectric layer made of a dielectric ceramic; and a plurality of internal electrodes stacked via the dielectric layer and positioned at a plurality of interfaces between the dielectric layers, A main surface and a second main surface opposite to the first main surface; a first end surface orthogonal to the first main surface; a second end surface opposite to the first end surface; and the first A rectangular parallelepiped shape including a first side surface orthogonal to the end surface of the first side surface and a second side surface facing the first side surface, and a direction from the first main surface toward the second main surface is the dielectric. A ceramic body in which the body layers and the internal electrodes are stacked, and the plurality of internal electrodes are alternately drawn to the first end face and the second end face;
A multilayer ceramic capacitor comprising a pair of external electrodes disposed on the ceramic body so as to be electrically connected to the internal electrodes drawn out to the first end surface and the second end surface;
A laminate formed by the plurality of internal electrodes and the dielectric layer interposed between the internal electrodes when the ceramic body is viewed from the first or second end face side, and the ceramic body And the Si content in the dielectric ceramic in the margin region located between the first and second side surfaces is higher than the Si content in the dielectric ceramic in the other regions, and
A multilayer ceramic capacitor, wherein a Si content in the dielectric ceramic in the margin region is in a range of 10 to 24%.   Among the plurality of internal electrodes, even in the outermost dielectric layer located outside the internal electrode located on the outermost side in the stacking direction, the Si content in the dielectric ceramic other than the margin region 2. The multilayer ceramic capacitor according to claim 1, wherein the content is higher than the Si content in the dielectric ceramic in the region.   The margin region, wherein the thickness of the outermost dielectric layer is a distance from the widthwise end of the internal electrode to the first or second side surface of the ceramic body facing the widthwise end. 3. The multilayer ceramic capacitor according to claim 1, wherein the thickness is less than the thickness of the multilayer ceramic capacitor.

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