JP2019004021A - Multilayer ceramic capacitor - Google Patents

Abstract

To provide a multilayer ceramic capacitor which enables enhancement of an electrostatic capacitance with stability while suppressing occurrence of an internal defect and a reduction in coverage factor of internal electrodes even if ceramic powder is not added to the internal electrodes.SOLUTION: A multilayer ceramic capacitor of the present invention comprises: a plurality of dielectric layers which are laminated; a plurality of internal electrode layers laminated so as to alternate with the dielectric layers and exposed at end faces; and external electrodes connected to the internal electrode layers and disposed on the end faces. In the multilayer ceramic capacitor, sulfur is present at an interface of the internal electrode layer and the dielectric layer and in a region ranging from the interface and to a 5-nm depth in a thickness direction of the internal electrode layer at an internal electrode layer side; and no sulfur is present in a center portion of the internal electrode layer in the thickness direction. In the multilayer ceramic capacitor, the internal electrode layers include Ni. It is preferred that a sulfur concentration to Ni falls within a range of 0.9 mol or more and 11.1 mol% or less in the region where the sulfur is present.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a multilayer ceramic capacitor, and more particularly to a multilayer ceramic capacitor including a multilayer body in which dielectric layers and internal electrodes are alternately stacked.

  Multilayer ceramic capacitors are widely used as small and large-capacity electronic components. However, the multilayer ceramic capacitor is required to be further reduced in size, capacity, and reliability. In general, in a multilayer ceramic capacitor, the shrinkage start temperature during firing of the ceramic dielectric layer portion and the internal electrode portion differs between the ceramic dielectric layer portion and the internal electrode portion. As a result, internal defects such as delamination that cause peeling between the ceramic dielectric layer portion and the internal electrode portion, and a decrease in the coverage (coverage) of the internal electrode layer with respect to the ceramic dielectric layer occur. The problem of a decrease in capacitance value is likely to occur.

  In order to solve the above problem, for example, in the internal electrode paste, the shrinkage start temperature of the conductive powder, the organic vehicle and the ceramic powder is + 50 ° C. or higher and + 100 ° C. or lower compared to the shrinkage start temperature of the material of the dielectric ceramic layer. A technique for containing at least one ceramic powder in the range is disclosed (see Patent Document 1).

JP 2002-57060 A

  However, in the structure of Patent Document 1, it is necessary to prepare an internal electrode paste for each type of dielectric layer, which not only complicates the management, but also may mix ceramic components having different compositions into the dielectric layer. There is a possibility of affecting the quality. Further, in the structure of Patent Document 1, when the thickness of the dielectric layer is reduced by reducing the thickness, the common material (ceramic powder) contained in the internal electrode diffuses into the dielectric layer, so that the dielectric It is conceivable that the composition of the body layer tends to shift and the characteristic change becomes large.

  Therefore, in the present invention, without adding ceramic powder to the internal electrode paste, it is possible to stably improve the capacitance while suppressing internal defects such as delamination and a decrease in coverage (coverage) of the internal electrode. Provided is a multilayer ceramic capacitor.

A plurality of dielectric layers stacked, the first main surface and the second main surface facing the stacking direction, the first side surface and the second side surface facing the width direction orthogonal to the stacking direction; A laminated body including a first end face and a second end face opposed to each other in a length direction perpendicular to the laminating direction and the width direction, and a plurality of internal electrode layers laminated alternately with dielectric layers and exposed to the end face; A multilayer ceramic capacitor having an external electrode connected to the internal electrode layer and disposed on the end surface, wherein the internal electrode layer is formed along the interface between the internal electrode layer and the dielectric layer and from the interface along the thickness direction of the internal electrode layer. This is a multilayer ceramic capacitor in which sulfur S is present in the region 5 nm on the side, and sulfur S is not present in the central portion in the thickness direction of the internal electrode layer.
In the multilayer ceramic capacitor described above, in the region where the internal electrode layer contains Ni and sulfur S is present, the sulfur concentration relative to Ni is more preferably in the range of 0.9 mol% or more and 11.1 mol% or less. .

According to the multilayer ceramic capacitor in accordance with the present invention, the region (hereinafter referred to as “interface”) having a thickness of 5 nm from the interface and interface between the internal electrode layer and the dielectric layer to the internal electrode side of the internal electrode layer along the thickness direction of the internal electrode layer In the vicinity region "), sulfur S is present, and no sulfur S is present in the central portion of the internal electrode layer in the thickness direction (hereinafter referred to as" internal electrode central region "). For example, when the internal electrode layer contains Ni, Ni sulfide has a lower melting point than Ni metal or Ni oxide. Therefore, the melting point inside the electrode is high, but only the surface has a low melting point. Only the surface of the internal electrode layer has a low melting point, so that only the surface of the internal electrode layer has atomic remelting due to elution / reprecipitation of the internal electrode. Arrangement is likely to occur, and the effect of filling the gap between the electrodes will work. Therefore, without adding ceramic powder to the internal electrode paste, it is possible to stably improve the capacitance while suppressing internal defects such as delamination and a decrease in coverage (coverage) of the internal electrode. .
Further, in the region where the internal electrode layer contains Ni and sulfur S exists, when the sulfur concentration with respect to Ni is in the range of 0.9 mol% or more and 11.1 mol% or less, the capacitance is more stable. Improvements can be made.

  Therefore, the main object of the present invention is to stabilize the capacitance while suppressing internal defects such as delamination and lowering the coverage (coverage) of the internal electrode without adding ceramic powder to the internal electrode paste. It is an object of the present invention to provide a multilayer ceramic capacitor capable of improving the above.

  The above-described object, other objects, features, and advantages of the present invention will become more apparent from the following description of embodiments for carrying out the invention with reference to the drawings.

1 is an external perspective view showing an example of a multilayer ceramic capacitor according to the present invention. It is sectional drawing in the II-II line of FIG. 1 which shows the multilayer ceramic capacitor concerning this invention. It is sectional drawing in the III-III line of FIG. 1 which shows the multilayer ceramic capacitor concerning this invention. FIG. 4 is an enlarged view of part a shown in FIG. 3, and is a detailed view of a situation of an interface between the internal electrode layer and the dielectric layer of the multilayer ceramic capacitor according to the present invention. In an experiment example, it is an illustration figure which shows the measurement point which measures the sulfur S in an internal electrode layer of an multilayer ceramic capacitor, and EDX.

1. Multilayer Ceramic Capacitor A multilayer ceramic capacitor according to the present invention will be described. FIG. 1 is an external perspective view showing an example of a multilayer ceramic capacitor according to the present invention. 2 is a cross-sectional view taken along the line II-II of FIG. 1 showing the multilayer ceramic capacitor according to the present invention. FIG.
It is sectional drawing in the III-III line of FIG. 1 which shows the multilayer ceramic capacitor concerning this invention.

  As shown in FIGS. 1 to 3, the multilayer ceramic capacitor 10 includes a rectangular parallelepiped multilayer body 12.

(Laminated body 12)
The stacked body 12 includes a plurality of dielectric layers 14 and a plurality of internal electrode layers 16 stacked. The stacked body 12 includes a first main surface 12a and a second main surface 12b facing the stacking direction x, and a first side surface 12c and a second side surface facing the width direction y orthogonal to the stacking direction x. 12d, and a first end surface 12e and a second end surface 12f that are opposed to a length direction z orthogonal to the stacking direction x and the width direction y. Moreover, it is preferable that the laminated body 12 is rounded in the corner | angular part or the ridgeline part. In addition, a corner | angular part is a part where three adjacent surfaces of a laminated body cross, and a ridgeline part is a part where two adjacent surfaces of a laminated body intersect. Furthermore, the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d, and the first end surface 12e and the second end surface 12f are principal surfaces, side surfaces, and part of the end surfaces. Or the unevenness | corrugation etc. may be formed in the whole.

(Dielectric layer 14)
The dielectric layer 14 of the stacked body 12 includes an outer layer portion 14a and an inner layer portion 14b. The outer layer portion 14a is located on the first main surface 12a side and the second main surface 12b side of the laminate 12, and is formed between the first main surface 12a and the internal electrode layer 16 closest to the first main surface 12a. And a dielectric layer 14 positioned between the second main surface 12b and the internal electrode layer closest to the second main surface 12b. A region sandwiched between both outer layer portions is the inner layer portion 14b.

As the ceramic material of the dielectric layer 14 of the multilayer body 12, for example, a dielectric ceramic composed of main components such as BaTiO ₃ , CaTiO ₃ , SrTiO ₃ , and CaZrO ₃ can be used. Moreover, you may use what added subcomponents, such as a Mn compound, Fe compound, Cr compound, Co compound, Ni compound, to these main components.

  The thickness of the dielectric layer 14 after firing is preferably 0.5 μm or more and 10 μm or less.

(Internal electrode layer 16)
The plurality of internal electrode layers 16 of the multilayer body 12 have a plurality of first internal electrode layers 16a and second internal electrode layers 16b that are substantially rectangular. The plurality of first internal electrode layers 16 a and second internal electrode layers 16 b are stacked so as to be alternately arranged at equal intervals along the stacking direction x of the stacked body 12 with the dielectric layers 14 interposed therebetween.

The first internal electrode layer 16a is positioned at one end of the first counter electrode portion 18a facing the second internal electrode layer 16b and the first internal electrode layer 16a, and is laminated from the first counter electrode portion 18a. It has the 1st extraction electrode part 20a to the 1st end surface 12e of the body 12. FIG. The end portion of the first extraction electrode portion 20a is drawn out to the first end surface 12e and exposed.
The second internal electrode layer 16b is positioned at one end of the second counter electrode portion 18b facing the first internal electrode layer 16a and the second internal electrode layer 16b, and is laminated from the second counter electrode portion 18b. It has the 2nd extraction electrode part 20b to the 2nd end surface 12f of the body 12. FIG. The end portion of the second extraction electrode portion 20b is drawn out to the second end face 12f and exposed.

The stacked body 12 includes a first counter electrode portion 18a and a second counter electrode portion between one end in the width direction y of the first counter electrode portion 18a and the second counter electrode portion 18b and the first side surface 12c, and the first counter electrode portion 18a and the second counter electrode portion. The side part (henceforth "W gap") 22a of the laminated body 12 formed between the other end of the width direction y of 18b, and the 2nd side surface 12d is included.
Furthermore, the multilayer body 12 includes a second extraction electrode between the end of the first internal electrode layer 16a opposite to the first extraction electrode portion 20a and the second end surface 12f and the second extraction electrode of the second internal electrode layer 16b. It includes an end portion (hereinafter referred to as an “L gap”) 22b of the stacked body 12 formed between an end opposite to the portion 20b and the first end face 12e.

  The first internal electrode layer 16a and the second internal electrode layer 16b contain, for example, a metal such as Ni, Cu, Ag, Pd, an Ag—Pd alloy, or Au. Of these, Ni is preferable.

FIG. 4 is an enlarged view of a part shown in FIG. 3 and is a detailed view of the interface state between the internal electrode layer and the dielectric layer of the multilayer ceramic capacitor according to the present invention.
As shown in FIG. 4, the interface 16c between the first internal electrode layer 16a or the second internal electrode layer 16b and the dielectric layer 14 and the inside of the internal electrode layer along the thickness direction of the internal electrode layer from the interface 16c. Sulfur S is present in the region 16d that is 5 nm on the electrode side (region near the interface), and sulfur S is not present in the central portion in the thickness direction of the internal electrode layer (internal electrode central region). In the interface 16c between the first internal electrode layer 16a or the second internal electrode layer 16b and the dielectric layer 14, and in the vicinity of the interface 16d, sulfur S is detected by TEM-EDX (transmission electron microscope-energy dispersion type). X-ray spectroscopy). Moreover, the measurement of the change of the electrostatic capacitance by sulfur concentration (S concentration) can be confirmed using an automatic bridge type measuring device.

  When the internal electrode layer 16 contains Ni, in the region where sulfur S is present, the sulfur concentration (S concentration) (mol%) with respect to Ni is preferably in the range of 0.9 mol% or more and 11.1 mol% or less. .

  The thicknesses of the first internal electrode layer 16a and the second internal electrode layer 16b are preferably 0.2 μm or more and 2.0 μm or less. Further, the number of the first internal electrode layers 16a and the second internal electrode layers 16b is not particularly limited.

(External electrode 24)
External electrodes 24 are disposed on the first end surface 12 e side and the second end surface 12 f side of the multilayer body 12. The external electrode 24 includes a first external electrode 24a and a second external electrode 24b.
The first external electrode 24a is disposed on the surface of the first end surface 12e of the multilayer body 12, extends from the first end surface 12e, and has a first main surface 12a, a second main surface 12b, and a first It is formed so as to cover a part of each of the side surface 12c and the second side surface 12d. In this case, the first external electrode is electrically connected to the first extraction electrode portion 20a of the first internal electrode layer 16a.
The second external electrode 24b is disposed on the surface of the second end surface 12f of the multilayer body 12, and extends from the second end surface 12f to provide the first main surface 12a, the second main surface 12b, and the first main surface 12b. It is formed so as to cover a part of each of the side surface 12c and the second side surface 12d. In this case, the second external electrode is electrically connected to the second extraction electrode portion 20b of the second internal electrode layer 16b.

  In the stacked body 12, the first counter electrode portion 18 a of the first internal electrode layer 16 a and the second counter electrode portion 18 b of the second internal electrode layer 16 are opposed to each other with the dielectric layer 14 interposed therebetween. Thus, a capacitance is formed. Therefore, a capacitance can be obtained between the first external electrode 24a to which the first internal electrode layer 16a is connected and the second external electrode 24b to which the second internal electrode layer 16b is connected. The characteristics of the capacitor are manifested.

  As shown in FIGS. 2 and 3, the first external electrode 24a is a first plating disposed on the surface of the first base electrode layer 26a and the first base electrode layer 26a in this order from the laminate 12 side. Layer 28a. Similarly, the second external electrode 24b includes a second base electrode layer 26b and a second plating layer 28b disposed on the surface of the second base electrode layer 26b in this order from the stacked body 12 side.

The first base electrode layer 26a is disposed on the surface of the first end surface 12e of the multilayer body 12, and extends from the first end surface 12e to form the first main surface 12a, the second main surface 12b, and the first main surface 12e. It is formed to cover each of the side surface 12c and the second side surface 12d. However, the first base electrode layer 26 a may be disposed only on the surface of the first end face 12 e of the multilayer body 12.
The second base electrode layer 26b is disposed on the surface of the second end surface 12f of the multilayer body 12, and extends from the second end surface 12f to the first main surface 12a, the second main surface 12b, and the first main surface 12b. It is formed to cover each of the side surface 12c and the second side surface 12d. However, the second base electrode layer 26 b may be disposed only on the surface of the second end face 12 f of the multilayer body 12.

The first base electrode layer 26a and the second base electrode layer 26b include at least one selected from a baking layer, a resin layer, a thin film layer, and the like.
Here, the first base electrode layer 26a and the second base electrode layer 26b formed by the baking layer will be described.

  The baking layer includes glass and metal. Examples of the glass for the baking layer include at least one selected from B, Si, Ba, Mg, Al, Li, and the like. Moreover, as a metal of a baking layer, at least 1 chosen from Cu, Ni, Ag, Pd, an Ag-Pd alloy, Au etc. is included, for example. The baking layer may be formed of a plurality of layers. The baking layer is obtained by applying a conductive paste containing glass and metal to the laminated body 12 and baking it, and may be fired simultaneously with the dielectric layer 14 and the internal electrode layer 16. The internal electrode layer 16 may be baked after being baked. The thickest part of the thickness of the baking layer is preferably 10 μm or more and 50 μm or less.

  The resin layer includes, for example, conductive particles and a thermosetting resin. The resin layer may be formed on the surface of the baking layer, or may be directly formed on the surface of the first end surface 12e or the second end surface 12f of the laminate 12 without forming the baking layer. The resin layer may be formed of a plurality of layers. The thickest part of the thickness of the resin layer is preferably 10 μm or more and 150 μm or less.

  The thin film layer is a layer of 1 μm or less formed by a thin film forming method such as a sputtering method or a vapor deposition method and deposited with metal particles.

The first plating layer 28a is disposed so as to cover the first base electrode layer 26a. Specifically, the first plating layer 28a is disposed on the first end surface 12e on the surface of the first base electrode layer 26a, and the first main surface 12a and the first main surface 12a on the surface of the first base electrode layer 26a. It is preferable that the second main surface 12b, the first side surface 12c, and the second side surface 12d are provided. In the case where the first base electrode layer 26a is disposed only on the surface of the first end face 12e of the multilayer body 12, the first plating layer 28a is only the surface of the first base electrode layer 26a. As long as it is provided so as to cover.
Similarly, the second plating layer 28b is disposed so as to cover the second base electrode layer 26b. Specifically, the second plating layer 28b is disposed on the second end surface 12f on the surface of the second base electrode layer 26b, and the first main surface 12a and the second main surface 12a on the surface of the second base electrode layer 26b. It is preferable that the second main surface 12b, the first side surface 12c, and the second side surface 12d are provided. When the second base electrode layer 26b is disposed only on the surface of the second end face 12f of the stacked body 12, the second plating layer 28b is only the surface of the second base electrode layer 26b. As long as it is provided so as to cover.

As the first plating layer 28a and the second plating layer 28b (hereinafter also simply referred to as “plating layer”), for example, at least one selected from Cu, Ni, Ag, Pd, Ag—Pd alloy, Au, and the like. Preferably it contains a seed metal or alloy.
Moreover, the plating layer may be formed of a plurality of layers. In this case, a two-layer structure of a Ni plating layer and a Sn plating layer is preferable. The Ni plating layer is provided so as to cover the surface of the base electrode layer, thereby preventing the base electrode layer from being eroded by the solder when the multilayer ceramic capacitor 10 is mounted. By providing the Sn plating layer on the surface of the Ni plating layer, the wettability of the solder when the multilayer ceramic capacitor 10 is mounted can be improved and can be easily mounted.

  The thickness per plating layer is preferably 1 μm or more and 15 μm or less. It is preferable that a plating layer does not contain glass. It is preferable that the metal ratio per unit volume of a plating layer is 99 volume% or more.

Next, the case where the 1st foundation electrode layer 26a and the 2nd foundation electrode layer 26b consist of a plating electrode is demonstrated.
The first base electrode layer 26a is composed of a plating layer directly connected to the first internal electrode layer 16a, is disposed on the surface of the first end surface 12e of the multilayer body 12, and extends from the first end surface 12e. The first main surface 12a, the second main surface 12b, the first side surface 12c, and the second side surface 12d are formed so as to cover each of them.
The second base electrode layer 26b is composed of a plating layer directly connected to the second internal electrode layer 16b, is disposed on the surface of the second end surface 12f of the multilayer body 12, and extends from the second end surface 12f. The first main surface 12a, the second main surface 12b, the first side surface 12c, and the second side surface 12d are formed so as to cover each of them.
In such a case, the plating layer may be formed after disposing the catalyst on the surface of the laminate as a pretreatment.

The plating layer preferably includes a lower plating electrode formed on the surface of the laminate and an upper plating electrode formed on the surface of the lower plating electrode. Each of the lower plating electrode and the upper plating electrode preferably includes at least one metal selected from, for example, Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, and Zn, or an alloy containing the metal. .
For example, the lower plating electrode is preferably formed using Ni having solder barrier performance, and the upper plating electrode is preferably formed using Sn or Au having good solder wettability. Moreover, when the 1st internal electrode 16a and the 2nd internal electrode 16b are formed using Ni, it is preferable that a lower layer plating electrode is formed using Cu with good bondability with Ni.
Note that the upper plating electrode may be formed as necessary, and each of the first external electrode 24a and the second external electrode 24b may be composed of only the lower plating electrode. The upper plating electrode may be the outermost layer, or another plating electrode may be formed on the surface of the upper plating electrode.

  The thickness of each plating layer is preferably 1 μm or more and 15 μm or less. Moreover, it is preferable that a plating layer does not contain glass. Furthermore, it is preferable that the metal ratio per unit volume of a plating layer is 99 volume% or more.

2. Next, a method for manufacturing a multilayer ceramic capacitor according to the present invention will be described.

(A) Production of Dielectric Material Powder In order to produce the multilayer ceramic capacitor 10, a material for the dielectric layer 14 is prepared. First, a predetermined amount of BaCO ₃ powder and TiO ₂ powder are weighed and mixed by a ball mill for a certain period of time, followed by heat treatment to obtain a main component BaTiO ₃ powder.

On the other hand, powders of Dy ₂ O ₃ , MgO, MnO, and SiO ₂ that are subcomponents are prepared. Then, Dy ₂ O ₃ is 0.75 molar parts per 100 parts by mol of the main ingredient, MgO is 1 part by mol, MnO 0.2 molar parts, SiO ₂ is weighing so that one mole portion. These powders are blended with the main component BaTiO ₃ powder, mixed for a certain time by a ball mill, and then dried and dry pulverized to obtain a dielectric ceramic raw material.

(B) Production of Multilayer Ceramic Capacitor Next, a polyvinyl butyral binder and an organic solvent such as ethanol are added to the dielectric ceramic raw material and wet mixed by a ball mill to prepare a ceramic slurry. A short ceramic green sheet A is obtained by sheet-forming this ceramic slurry by the doctor blade method. The thickness of the ceramic green sheet A is, for example, 2.2 μm.

  On the other hand, a polyvinyl butyral binder, an organic solvent such as ethanol, and balsam sulfide are added to the dielectric ceramic raw material and wet mixed by a ball mill to prepare a ceramic slurry. For example, when the internal electrode layer contains Ni, the balsam sulfide may be added so that the sulfur concentration (S concentration) (mol%) with respect to Ni is 0.9 mol% or more and 11.1 mol% or less. preferable. A short ceramic green sheet B is obtained by sheet-forming this ceramic slurry by the doctor blade method. The thickness of the ceramic green sheet B is, for example, 0.3 μm.

  Next, a conductive powder is prepared, an organic solvent such as a polyvinyl butyral binder and ethanol is added, and wet mixed by a ball mill to obtain a conductive paste for internal electrodes.

  Next, the conductive paste for internal electrodes is printed on the ceramic green sheet B, and the conductive paste layer for comprising an internal electrode is formed. This sheet is referred to as a ceramic green sheet C.

  Next, the ceramic green sheet A is stacked on the ceramic green sheet B, and the ceramic green sheet C is further stacked thereon. A laminate block is obtained by stacking a plurality of these three-layer ceramic green sheets so that the conductive paste layers serving as lead portions for the internal electrodes are alternately drawn.

  Thereafter, the laminated body block is cut into a predetermined shape and an unfired laminated body is cut out.

The green laminate was heated at 350 ° C. in an N ₂ atmosphere to burn the binder, and then H ₂ —N ₂ —H ₂ having an oxygen partial pressure of 10 ⁻¹² MPa to 10 ⁻¹⁰ MPa. The temperature is raised at 20 ° C./min in a reducing atmosphere made of O gas, and calcination is performed at 1200 ° C. for 20 minutes.

A conductive paste for external electrodes containing B ₂ O ₃ —SiO ₂ —BaO glass frit is applied to both end faces of the fired laminate, and baked at a temperature of 600 ° C. in an N ₂ atmosphere. An electrically connected external electrode is formed.

  As described above, the multilayer ceramic capacitor 10 according to the present embodiment is manufactured.

  The detection method of sulfur S can be confirmed using TEM-EDX. Specifically, it is as follows.

The cross-section of line III-III shown in FIG. 1 of the multilayer ceramic capacitor (laminated body) after firing.
In the L direction about 1/2, the area where the internal electrode layer of the sample is laminated is divided into three equal parts in the T direction, and the central part in each W direction is divided into three areas: an upper area, a central area, a lower area (FIG. 5), and in each of the three regions, a thinned analysis sample is prepared using a microsampling processing method using a focused ion beam (FIB). The flake sample thickness is processed to be 60 nm or less. The damaged layer on the sample surface formed during the FIB processing is removed by Ar ion milling. For processing the analysis sample, FIB uses SMI3050SE (manufactured by Seiko Instruments Inc.), and Ar ion milling uses PIPS (manufactured by Gatan).

  The sample was observed with a STEM, and five interfaces were searched from each region in the sample, which were substantially perpendicular to the cross-section of the sliced sample. A region in which the internal electrode layer in contact with the substantially vertical interface enters 5 nm from the interface into the internal electrode in a direction perpendicular to the stacking direction with respect to the substantially vertical interface (region near the interface 16d) Are divided into a central region (internal electrode central region) in the thickness direction of the same internal electrode.

  The interface that was substantially perpendicular to the sample cross section was searched for as follows. Observe the line appearing on both sides of the interface with STEM, that is, the Fresnel fringe, look for the interface where the contrast of the Fresnel fringe changes almost symmetrically on both sides when the focus is changed, and make this almost perpendicular to the sample cross section Interface.

Moreover, in STEM analysis, JEM-2200FS (made by JEOL) was used for STEM. The acceleration voltage is 200 kV. The detector EDX uses JED-2300T and a 60 mm ² aperture SDD detector, and the EDX system uses Noran system 7 (manufactured by Thermo Fisher Scientific).

  Quantitative analysis of sulfur S is performed using EDX at a total of 20 locations of 5 locations × 4 locations for each of the interface vicinity region and the internal electrode central region. The diameter of the electron beam measurement probe is about 1 nm, and the measurement time is 30 seconds. The quantitative correction from the obtained EDX spectrum uses cliff-lolimer correction.

  Moreover, the measuring method of an electrostatic capacitance (Cap) measures an electrostatic capacitance by AC voltage 1Vrms and 1kHz using an automatic bridge type measuring device.

As shown in FIG. 4, the multilayer ceramic capacitor thus obtained contained 5 nm from the interface 16c between the internal electrode layer and the dielectric layer to the internal electrode layer side along the thickness direction of the internal electrode layer. In the region (interface vicinity region 16d), sulfur S exists, but sulfur S does not exist in the central portion (internal electrode central region) in the thickness direction of the internal electrode layer. For example, when the internal electrode layer contains Ni, Ni sulfide has a lower melting point than Ni metal or Ni oxide. Therefore, the inside of the electrode has a high melting point, but only the surface has a low melting point. Since the melting point of only the surface of the internal electrode layer is low, atomic rearrangement due to elution and reprecipitation of Ni is likely to occur only on the surface of the internal electrode layer, and the effect of filling the gap between the electrodes works. Therefore, without adding ceramic powder to the internal electrode paste, it is possible to stably improve the capacitance while suppressing internal defects such as delamination and a decrease in coverage (coverage) of the internal electrode. .
Further, in the region where the internal electrode layer contains Ni and sulfur S exists, when the sulfur concentration (S concentration) (mol%) with respect to Ni is in the range of 0.9 mol% or more and 11.1 mol% or less, The capacitance can be improved more stably.

3. Experimental Example Next, in order to confirm the effect of the multilayer ceramic capacitor 10 according to the present invention described above, the sulfur concentration and the capacitance in the internal electrode of the multilayer ceramic capacitor were measured.

(1) Preparation of Sample for Evaluation Hereinafter, the multilayer capacitor of each sample (sample number 1 to sample number 8) of the experimental example was manufactured based on the following conditions using the manufacturing method described above.

(A) Production of Dielectric Material Powder First, a predetermined amount of BaCO ₃ powder and TiO ₂ powder were weighed and mixed for a certain period of time by a ball mill, followed by heat treatment to obtain a main component BaTiO ₃ powder.

On the other hand, powders of Dy ₂ O ₃ , MgO, MnO, and SiO ₂ that are subcomponents were prepared. Then, Dy ₂ O ₃ is 0.75 molar parts per 100 parts by mol of the main ingredient, MgO is 1 part by mol, MnO 0.2 molar parts, SiO ₂ was weighed so that one mole portion. These powders were blended with the main component BaTiO ₃ powder, mixed for a certain time by a ball mill, and then dried and dry pulverized to obtain a dielectric ceramic raw material.

(B) Production of Multilayer Ceramic Capacitor Next, an organic solvent such as a polyvinyl butyral binder and ethanol was added to the dielectric ceramic raw material, and wet mixed by a ball mill to prepare a ceramic slurry. This ceramic slurry was formed into a sheet by a doctor blade method to obtain a ceramic green sheet 1-A having a thickness of 2.2 μm and a ceramic green sheet 1-B having a thickness of 2.8 μm.

  On the other hand, a polyvinyl butyral binder and an organic solvent such as ethanol and an added amount of balsam sulfide shown in Table 1 were added to this dielectric ceramic raw material, and wet mixed by a ball mill to prepare a ceramic slurry. This ceramic slurry was formed into a sheet by a doctor blade method to obtain a ceramic green sheet 2 having a thickness of 0.3 μm.

  Next, Ni powder was prepared as a conductive powder, an organic solvent such as a polyvinyl butyral binder and ethanol was added, and wet mixed by a ball mill to prepare a conductive paste for internal electrodes.

  Next, the conductive paste for internal electrodes was printed on the ceramic green sheet 2, and the conductive paste layer for comprising an internal electrode was formed. This sheet is referred to as a ceramic green sheet 3.

  On the other hand, the conductive paste for internal electrodes was printed on the ceramic green sheet 1-B, and the conductive paste layer for comprising an internal electrode was formed. This sheet is referred to as a ceramic green sheet 4.

  Next, the ceramic green sheet 1-A was stacked on the ceramic green sheet 2, and the ceramic green sheet 3 was further stacked thereon. A laminate A was obtained by laminating a plurality of these three-layer ceramic green sheets so that the side from which the conductive paste layer serving as the lead-out portion of the internal electrode was drawn was alternated.

  On the other hand, a plurality of ceramic green sheets 4 were laminated so that the side from which the conductive paste layer serving as the lead-out portion of the internal electrode was drawn was alternated to obtain a laminate B.

After heating these laminated bodies at a temperature of 350 ° C. in an N ₂ atmosphere and burning the binder, an H ₂ —N ₂ —H ₂ O gas having an oxygen partial pressure of 10 ⁻¹² MPa to 10 ⁻¹⁰ MPa. The temperature was raised at 20 ° C./min in a reducing atmosphere consisting of baked at 1200 ° C. for 20 minutes.

A conductive paste for external electrodes containing B ₂ O ₃ —SiO ₂ —BaO glass frit is applied to both end faces of the fired laminate, and baked at a temperature of 600 ° C. in an N ₂ atmosphere. Electrically connected external electrodes were formed.

The outer dimensions (including external electrodes) of the multilayer capacitor thus obtained are 1.6 mm in length, 0.8 mm in width, and 1.0 mm in thickness, and the thickness of the dielectric layer interposed between the internal electrodes. Was 2.3 μm. The total number of effective dielectric ceramic layers was 250, and the area of the counter electrode portion per layer was 0.9 × 10 ⁻⁶ m ² . The number of samples for each sample number is 10 (80 in total) for each condition of the addition amount of balsam sulfide in the ceramic green sheets 2 of sample numbers 1 to 8 in Table 1, and the sulfur concentration (S concentration). And the capacitance was measured.

  About these obtained samples, the sulfur concentration (S concentration) and the capacitance were measured by the following procedure.

  Regarding the sulfur concentration (S concentration), in the laminated ceramic capacitor after firing, sulfur S is present in the interface between the dielectric layer and the internal electrode layer or in the region where the internal electrode side is 5 nm (region near the interface), The absence of sulfur S in the internal electrodes was confirmed as follows. Moreover, the detection of sulfur S was confirmed using TEM-EDX.

First, as shown in FIG. 5, III-III in FIG.
In the L direction of about 1/2 in the cross section of the line, the region in which the internal electrode layer of the sample is laminated is divided into three equal parts in the T direction, and the central part in each W direction is an upper region, a central region, and a lower region. And divided into three regions, and in each of the three regions, a thinned analysis sample was prepared using a microsampling processing method by FIB.

  The thin sample thickness was processed so as to be 60 nm or less. The damaged layer on the sample surface formed during the FIB processing was removed by Ar ion milling. For processing the analysis sample, SMI3050SE (manufactured by Seiko Instruments Inc.) was used for FIB, and PIPS (manufactured by Gatan) was used for Ar ion milling.

  The sample was observed with a STEM, and five interfaces were searched from each region in the sample, which were substantially perpendicular to the cross-section of the sliced sample. The internal electrode layer that is in contact with the substantially vertical interface is a region (near the interface) that is 5 nm from the interface into the internal electrode in a direction perpendicular to the stacking direction with respect to the substantially vertical interface. The same internal electrode layer was divided into a central region in the thickness direction (internal electrode central region).

  The interface that was substantially perpendicular to the sample cross section was searched for as follows. Observe the line appearing on both sides of the interface with STEM, that is, the Fresnel fringe, look for the interface where the contrast of the Fresnel fringe changes almost symmetrically on both sides when the focus is changed, and make this almost perpendicular to the sample cross section Interface.

Moreover, in STEM analysis, JEM-2200FS (made by JEOL) was used for STEM. The acceleration voltage is 200 kV. The detector EDX was a JED-2300T 60 mm ² caliber SDD detector, and the EDX system was Noran system 7 (manufactured by Thermo Fisher Scientific).

  Quantitative analysis of sulfur S was performed using EDX at a total of 20 locations of 5 locations × 4 locations for each of the interface vicinity region and the internal electrode central region. The electron beam measurement probe diameter was about 1 nm and the measurement time was 30 seconds. The quantitative correction from the obtained EDX spectrum was Cliff-Lolimer correction.

  The values in Table 1 show the average value of the sulfur concentration (S concentration) obtained from 10 samples prepared for each condition of the balsam sulfide addition amount.

  Moreover, the measuring method of the electrostatic capacitance (Cap) measured the electrostatic capacitance at an AC voltage of 1 Vrms and 1 kHz using an automatic bridge type measuring device. The values in Table 1 show the average value of the capacitance obtained from 10 samples prepared for each condition of the balsam sulfide addition amount.

  Table 1 shows the results of the change in the sulfur concentration (S concentration) and the change in the capacitance with the change in the amount of balsam sulfide added to the ceramic green sheet 2 of the multilayer ceramic capacitor for each sample number. Note that sample numbers marked with * in the table are outside the scope of the present invention. Further, in the present invention, “there is no sulfur S in the central portion in the thickness direction of the internal electrode layer” indicates that the sulfur is below the detection lower limit in the measurement method.

  As shown in Table 1, in the case of sample number 1, which is outside the scope of the present invention, it was confirmed that sulfur S was not present in the central region of the internal electrode and the region near the interface. Sample No. 8 was confirmed to contain sulfur S not only in the vicinity of the interface but also in the central region of the internal electrode. Sample No. 1 and Sample No. 8 both had a capacitance of less than 2.4 μF.

  On the other hand, in the region of the internal electrode layer and the dielectric layer, which is a requirement of the present invention, and in the region 5 nm from the interface to the internal electrode layer along the thickness direction of the internal electrode layer (region near the interface), sulfur S is contained. Sample No. 2 to No. 7 satisfying the absence of sulfur S at the center in the thickness direction of the internal electrode layer have a capacitance of 2.4 μF or more, and the capacitance Has been confirmed to improve.

  In the region where the internal electrode layer contains Ni and sulfur S exists, which is a requirement of the present invention, the sulfur concentration (S concentration) (mol%) with respect to Ni is 0.9 mol% or more and 11.1 mol% or less. Sample No. 3 to Sample No. 6 that satisfy the above condition have a capacitance of 2.8 μF or more, and it was confirmed that the capacitance was further improved.

  In addition, this invention is not limited to the said embodiment, In the range of the summary, it changes variously.

DESCRIPTION OF SYMBOLS 10 Multilayer ceramic capacitor 12 Laminated body 12a 1st main surface 12b 2nd main surface 12c 1st side surface 12d 2nd side surface 12e 1st end surface 12f 2nd end surface 14 Dielectric layer 14a Outer layer part 14b Inner layer part 16 Internal electrode layer 16a 1st internal electrode layer 16b 2nd internal electrode layer 16c interface 16d interface vicinity area 18a 1st counter electrode part 18b 2nd counter electrode part 20a 1st extraction electrode part 20b 2nd extraction electrode Part 22a Side (W gap)
22b End (L gap)
24 external electrode 24a first external electrode 24b second external electrode 26a first base electrode layer 26b second base electrode layer 28a first plating layer 28b second plating layer x stacking direction y width direction z length direction

Claims (2)

A plurality of dielectric layers stacked, the first main surface and the second main surface facing the stacking direction, the first side surface and the second side surface facing the width direction orthogonal to the stacking direction; A laminated body including a first end face and a second end face opposed to each other in a length direction orthogonal to the lamination direction and the width direction;
A plurality of internal electrode layers alternately stacked with the dielectric layers and exposed at the end face;
In the multilayer ceramic capacitor having an external electrode connected to the internal electrode layer and disposed on the end face,
Sulfur S is present in the interface between the internal electrode layer and the dielectric layer and in a region 5 nm from the interface to the internal electrode layer side along the thickness direction of the internal electrode layer. A multilayer ceramic capacitor in which sulfur S does not exist in the center in the thickness direction.   2. The multilayer ceramic capacitor according to claim 1, wherein in the region where the internal electrode layer contains Ni and the sulfur S is present, the sulfur concentration relative to Ni is in a range of 0.9 mol% or more and 11.1 mol% or less.

Images