JP2015023581A - Analog-to-digital converter circuit, method of driving fully differential circuit, and interface circuit for driving fully differential circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an interface circuit for driving a fully differential circuit.SOLUTION: The interface circuit for driving a fully differential circuit has a first circuit configured to decrease a voltage at an output thereof in response to an increase in an average value of a first input voltage and a second input voltage. A first network receives the first input voltage and the output voltage of the first circuit to provide a first output voltage for driving the fully differential circuit. A second network receives the second input voltage and the output voltage of the first circuit to provide a second output voltage for driving the fully differential circuit. An impedance ratio of the first network is substantially matched to an impedance ratio of the second network.

Description

  No. 61 / 847,697 entitled “Interface Circuit for Driving Fully Differential Circuits” filed July 18, 2013, which is incorporated herein by reference. Claim priority of issue.

TECHNICAL FIELD This disclosure relates to analog circuits and methods. In particular, this disclosure relates to interfacing fully differential circuits including analog-to-digital converter circuits.

  Analog-to-digital converters (ADCs) are used in a wide range of applications including, but not limited to, sensor interfaces, industrial applications, consumer applications, and communications. Various circuits and technologies are available for various applications and analog-to-digital (A / D) conversions aimed at their different requirements in terms of speed, resolution, noise, power consumption, and other performance-related parameters. Has been developed. A precision low noise ADC can be constructed to receive and convert a fully differential input signal with very little common mode variation. The interface circuit may be required, for example, to transform a single-ended analog input signal into a fully differential analog signal suitable for interfacing with a fully differential circuit.

  FIG. 1 shows an exemplary ADC circuit 100 that includes an interface circuit 101 and a fully differential ADC 102. The ADC circuit 100 may be configured to receive a single-ended input signal VIP within a full scale range from (−2 * VREF) to (+ 2 * VREF). Note that VREF can be provided by the reference voltage source 103. For example, VREF can be 5V and the full scale range of the ADC circuit 100 can be (-10V) to (+ 10V). VIN can be biased at a reference potential (ground) VIN = GND when the ADC circuit 100 is configured to convert a single-ended input signal VIP = V (VIP, GND). The ADC circuit 100 is configured so that VIP = (− 2 * VREF) corresponds to the numerical value d (k) = (− 1) and VIP = (+ 2 * VREF) corresponds to d (k) = (+ 1). Can be configured. The behavior that is considered ideal may thus be described as d (k) = VIP / (2 * VREF) for any input voltage VIP within the full scale input range.

  Fully differential ADC 102 may be configured to sample two single-ended voltages VP and VN at first ADC input terminal 104 and second ADC input terminal 105, respectively. The fully differential ADC 102 may provide a numerical value d (k) nominally representing the difference V (VP, VN) = VP−VN between the sampled voltages VP and VN, normalized to the reference voltage VREF. , D (k) = V (VP, VN) / VREF. For single-ended signals, VP = V (VP, GND) and VN = V (VN, GND). For example, for VREF = 5V, VP = 4V, and VN = 1V, the nominal response can be d (k = V (VP, VN) / VREF = (4V-1V) /5V=0.6. The dynamic ADC 102 may require that the common-mode voltage VCM = (VP + VN) / 2 be close to a nominal value such as VREF / 2, for example, (VP + VN) is greater than or equal to VREF−0.2V and less than or equal to VREF + 0.2V. When the common mode requirement is met, the fully differential ADC 102 is substantially independent of the sampled voltage difference V (VP, VN) where the numerical value d (k) is substantially independent of the common mode voltage VCM. As shown, good in-phase rejection may be provided.

  The interface circuit 101 of FIG. 1 can be implemented using a differential amplifier 106 configured as shown in FIG. Resistors RN1 and RP2 provide a weighted average of the applied input voltage VIN and the first output voltage VP provided by the differential amplifier 106 at the first non-inverting output terminal 104 at the inverting amplifier input terminal 107. Configured as follows. Similarly, resistors RP1 and RN2 provide a weighted average of the applied voltage VIP and the second output voltage VN provided by the differential amplifier 106 at the second inverting output terminal 105, and a non-inverting amplifier input terminal 108. Configured to give in. Accordingly, resistors RN1, RP2, RP1, and RN2 are configured to provide negative feedback for differential amplifier 106. The differential amplifier 106 may be configured to provide a very large differential gain ADIFF for the voltage difference from the amplifier input terminals 107, 108 to the output terminals 104, 105, thereby providing stability and non-overload operation. Considering, amplifier input terminals 107, 108 may have very little voltage across them. The differential amplifier 106 may be said to provide a “virtual short” between the amplifier input terminals 107 and 108 when the differential gain ADIFF approaches infinity. Virtual shorts can exist (in approximation) for any common voltage to amplifier input terminals 107,108. The differential amplifier 106 may be configured such that the output common mode voltage VCM = (VP + VN) / 2 is nominally the same as the applied control voltage VC. For example, the control voltage VC = VREF / 2 may be applied to meet the common mode requirement when driving a fully differential ADC (the terminal for applying the control voltage VC is not explicitly shown in FIG. 1). . Therefore, the interface circuit 101 of FIG. 2 includes an output common-mode voltage VCM = (VP + VN) / 2 that is substantially the same as the applied control voltage VC, an input voltage difference V (VIP, VIN), and resistors RN1, RP2. , RP1, and RN2 can be provided with an output voltage difference V (VP, VN) substantially set by a selected value. In one exemplary embodiment, RN1 = RP1 = R1 and RP2 = RN2 = R2 may be selected and the nominal behavior is V (VP, VN) = (R2 / R1) * V (VIP, VIN ) And VCM = (VP + VN) / 2 = VC = VREF / 2.

  The differential amplifier 106 is subject to real imperfections such as finite gain, nonlinear gain, finite bandwidth, nonlinear bandwidth, non-zero offset, non-zero thermal noise, and flicker-type noise. Therefore, the virtual short circuit between the amplifier input terminals 107 and 108 is not perfect, and the output voltage difference V (VP, VN) may be distorted with respect to the ideal value (R2 / R1) * V (VIP, VIN). The ADC 102 (FIG. 1) can evaluate V (VP, VN) and provide its numerical representation d (k) with an accuracy that can be on the order of 1 million parts per million (1 ppm). The differential amplifier 106 used to implement the prior art interface circuit 101 (FIG. 2) is required to provide over a million differential gains ADIFF to ensure overall equally high accuracy. Can be done. Similarly, the offset of the differential amplifier 106 may have to be less than VREF / 1,000,000. The noise from the differential amplifier 106 is combined with the noise from the resistors RN1, RP2, RP1, RN2, and as a result, the noise level of the output voltage difference V (VP, VN) exceeding the level of noise from the resistor alone. It becomes. Thus, it may be very difficult to provide a differential amplifier 106 for the prior art interface circuit 101 (FIG. 2) that can meet the performance and accuracy provided by any current technology ADC 102 (FIG. 1). .

  Accordingly, the first differential ADC is driven with the selected common-mode voltage VCM = (VP + VN) / 2 so that the accuracy of the entire ADC circuit such as the circuit 100 is balanced with the accuracy of the fully differential ADC such as the circuit 102. There is a need for an interface circuit that will be able to transform the second and second input voltages VIP, VIN to the first and second output voltages VP, VN.

  In addition, single-ended voltage VIP = V (VIP, GND) = V (VIP, VIN) and common type voltage where common mode voltage (VIP + VIN) / 2 may not be strictly specified or controlled There is a need for an interface circuit that will be able to transform the difference V (VIP, VIN).

SUMMARY OF THE DISCLOSURE In accordance with one aspect of the present disclosure, an interface circuit is provided for driving a fully differential circuit. The interface circuit is configured to receive the first input voltage and the second input voltage and is further configured to provide the first output voltage and the second output voltage. The interface circuit
-A first circuit configured to receive the first and second input voltages and to provide a voltage at the output of the first circuit, the first circuit comprising the first input voltage; And a voltage at the output of the first circuit in response to an increase in the average value of the first input voltage and the second input voltage; And a first network configured to receive a first output voltage, wherein the first network is characterized by a first impedance ratio, and A second network configured to receive a second input voltage and a voltage at the output of the first circuit, and further configured to provide a second output voltage; A second impedance ratio that is substantially matched to the first impedance ratio; And features.

  For example, the first impedance ratio may be substantially the same as the second impedance ratio.

  In an exemplary embodiment of the present disclosure, the first circuit may be a regulator circuit configured to receive the first and second input voltages and generate a regulator voltage at its output, the regulator The voltage decreases in response to an increase in the average value of the first input voltage and the second input voltage.

  The first impedance ratio may be substantially the ratio of impedance values of two resistors included in the first network, and the second impedance ratio is substantially included in the second network. It may be a ratio of impedance values of two resistors.

  The first output voltage may be substantially a weighted average of the first input voltage and the regulator voltage.

The first impedance ratio may be substantially equal to 1.
The first and second circuitry may be interchangeable.

The first and second circuitry may be incorporated within the differential circuitry.
According to an exemplary implementation, the first network is coupled to a first input node whose first terminal is biased with a first input voltage, and the second terminal provides a first output voltage. A first resistor coupled to the first output node connected may be included. The first network also includes a second resistor having a first terminal coupled to the second terminal of the first resistor and a second terminal coupled to a node to which the regulator voltage is applied. But you can. The second network has a first terminal coupled to a second input node that is biased with a second input voltage, and a second terminal coupled to a second output node that is provided with a second output voltage. A third resistor may be included. The second network also includes a fourth resistor having a first terminal coupled to the second terminal of the third resistor and a second terminal coupled to a node to which the regulator voltage is applied. But you can.

  The regulator circuit may be separate from the first and second networks, and the first and second input nodes and the first at only three circuit nodes, which are nodes to which the regulator voltage is applied. And may be coupled to the second network.

  The regulator circuit may comprise an operational amplifier and a third network characterized by a third impedance ratio, wherein the third impedance ratio is substantially matched to the first and second impedance ratios. Also good. The third network may be a resistive network.

  In the exemplary embodiment, the third network includes fifth and sixth resistors coupled between the first input node and the second input node, and the fifth resistor and the sixth resistor. And a seventh resistor coupled between the node connecting the first resistor and the node to which the regulator voltage is applied. The seventh resistor may be provided between the inverting input and the output of the operational amplifier.

  The impedance value of the fifth resistor may be substantially equal to the impedance value of the sixth resistor, and the impedance value of the sixth resistor is effective in a parallel configuration representing the fifth and sixth resistors. It may be substantially equal to twice the impedance value. The third impedance ratio may be a ratio between the effective impedance value of the parallel configuration and the impedance value of the seventh resistor.

  For example, the interface circuit of the present disclosure may be configured to drive a fully differential analog to digital converter.

  The fully differential analog-to-digital converter may be realized on a semiconductor substrate shared with at least part of the interface circuit.

  The interface circuit and fully differential analog-to-digital converter may be encapsulated in a shared package.

  The difference between the first output voltage and the second output voltage may be substantially independent of the average value of the first input voltage and the second input voltage.

  Also, the difference between the first output voltage and the second output voltage may be substantially independent of the regulator voltage provided by the regulator circuit.

  The regulator circuit may be further configured to receive a control voltage. The regulator voltage provided by the regulator circuit may be a substantially linear combination of the first and second input voltages and the control voltage.

  For example, the average value of the first output voltage and the second output voltage may be substantially equal to the control voltage.

In an exemplary embodiment, the regulator circuit may comprise a switched capacitor.
The input impedance of the interface circuit may be substantially resistive.

According to another aspect of the present disclosure, an analog-to-digital converter (ADC) circuit includes a fully differential ADC and an interface circuit for driving the fully differential ADC, the interface circuit comprising a first input voltage and It is configured to receive a second input voltage and is further configured to provide a first output voltage and a second output voltage. The interface circuit
A first circuit configured to receive the first and second input voltages and to provide a voltage at the output of the first circuit, the first circuit including the first input voltage and the second input voltage; Configured to reduce the voltage at the output of the first circuit in response to an increase in average value with the input voltage of the input circuit, and further to receive the first input voltage and the voltage at the output of the first circuit. And further configured to provide a first output voltage, wherein the first network is characterized by a first impedance ratio, and
-A second network configured to receive a second input voltage and a voltage at the output of the first circuit and further configured to provide a second output voltage; Is characterized by a second impedance ratio substantially matched to the first impedance ratio.

In accordance with the method of the present disclosure, the fully differential circuit is driven using an interface circuit having a first circuit and first and second networks coupled to the first circuit. To drive a fully differential circuit,
Providing the first and second input voltages to the first circuit;
Reducing the output voltage of the first circuit in response to an increase in the average value of the first input voltage and the second input voltage;
Providing a first input voltage and an output voltage of the first circuit to a first network to generate a first output voltage for driving the first input of the fully differential circuit;
Providing a second input voltage and an output voltage of the first circuit to a second network to generate a second output voltage for driving the second input of the fully differential circuit; Do
The impedance ratio of the first network is substantially matched to the impedance ratio of the second network.

  Additional advantages and aspects of the disclosure will be readily apparent to those skilled in the art from the following detailed description. Embodiments of the present disclosure are shown and described for purposes of illustration only of the best mode contemplated for practicing the present disclosure. As will be described, the disclosure is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the spirit of the disclosure. Accordingly, the drawings and descriptions are to be regarded as illustrative in nature and not as restrictive.

  The following detailed description of embodiments of the present disclosure can be best understood when read in conjunction with the following drawings. In the drawings, features are not necessarily drawn to scale, but rather are drawn to best illustrate the relevant features.

1 is a diagram illustrating an ADC circuit 100 including a fully differential ADC 102 and an interface circuit 101. FIG. FIG. 2 shows an interface circuit 101 with a differential amplifier 106 in a negative feedback configuration with resistors RN1, RP2, RP1, and RN2. FIG. 2 is a diagram illustrating a first exemplary embodiment of the present disclosure that includes an interface circuit 201 that may be used in place of the interface circuit 101 in the ADC circuit 100 of FIG. FIG. 4 is a diagram illustrating expressions of first and second output voltages VP and VN for the interface circuit 201 of FIG. 3. Using the notation (R1 / R2) = (RP1 / RP2) = (RN1 / RN2), the first impedance ratio (RP1 / RP2) is matched to the second impedance ratio (RN1 / RN2). It is a figure which shows the type | formula about the output voltage difference V (VP, VN) about the applied input voltage difference V (VIP, VIN). When the first impedance ratio is matched to the second impedance ratio (R1 / R2) = (RP1 / RP2) = (RN1 / RN2), for VP and VN derived from the equations given in FIG. It is a figure which shows the formula of the common mode voltage VCM. 3 shows an equation for the nominal regulator voltage VREG provided by the regulator circuit 202 of FIG. 3, where VCM can be substituted with an applied control voltage VC to adjust VCM = (VP + VN) / 2, (R1 / It is a figure where R2) = (RP1 / RP2) = (RN1 / RN2). FIG. 3 shows an interface circuit 201 (FIG. 3) including an exemplary implementation of a regulator circuit 202 comprising an operational amplifier 206 and resistors RXP = RXN = 2 * RX1 and RX2, where (RX1 / RX2) = (RP1 / RP2) = FIG. 6 is a diagram in which a third impedance ratio (RX1 / RX2) can be selected to match the first and second impedance ratios to be (RN1 / RN2).

Detailed Disclosure of Embodiments FIG. 3 illustrates an exemplary embodiment of the present disclosure. In particular, FIG. 3 shows an interface circuit 201 that may be used in place of the interface circuit 101 of FIG. 1 to drive a fully differential ADC 102. The interface circuit 201 is configured to receive the first and second input voltages VIP = V (VIP, GND) and VIN = V (VIN, GND), and the first and second output voltages VP = V ( VP, GND) and VN = V (VN, GND) are further configured. The interface circuit 201 includes a regulator circuit 202 configured to receive the first and second input voltages VIP and VIN and the control voltage VC = V (VC, GND). Regulator circuit 202 is further configured to provide regulator voltage VREG = V (VREG, GND) to set output common mode voltage VCM = (VP + VN) / 2. In exemplary embodiments of the present disclosure, the regulator circuit 202 may be an open loop circuit. However, as those skilled in the art will appreciate, closed loop control may also be used to provide the regulator voltage VREG for setting the common mode voltage VCM.

  The interface circuit 201 is configured to receive a first input voltage VIP and a regulator voltage VREG and is further configured to provide a first output voltage VP and includes a first network including resistors RP1 and RP2. 203. The first network 203 may be a passive network and may feature a first impedance ratio (RP1 / RP2). Note that RP1 and RP2 can be the resistances of the respective resistors. The interface circuit 201 further comprises a second network 204 including resistors RN1 and RN2, which is further configured to receive the second input voltage VIN and the regulator voltage VREG and to provide the second output voltage VN. . The second network 204 may be a passive network and may be characterized by a second impedance ratio (RN1 / RN2). Note that RN1 and RN2 can be the resistances of the respective resistors. The first and second impedance ratios may be nominally matched (RP1 / RP2) = (RN1 / RN2). The regulator circuit 202 is separate from the first and second networks 203 and 204. Regulator circuit 202 is coupled to first and second circuitry 203, 204 only at three nodes, each representing first input voltage VIP, second input voltage VIN, and regulator voltage VREG. Optional connections through the power supply terminals including GND need not be counted.

  The first network 203 is a resistance divider circuit that provides a first output voltage VP as a first weighted average of the first input voltage VIP and the regulator voltage VREG in accordance with a first impedance ratio (RP1 / RP2). There may be. Similarly, the second network 204 is a resistor that provides the second output voltage VN as a second weighted average of the second input voltage VIN and the regulator voltage VREG in accordance with the second impedance ratio (RN1 / RN2). A divided circuit may be used. The equations for VP and VN expressed as first and second weighted averages are given in FIG. The first and second circuitry 203, 204 may be interchangeable and / or may be included in the differential circuitry.

  For example, the resistor RP1 of the first network 203 may be coupled between an input node for receiving the first input voltage VIP and an output node for providing the first output voltage VP. Resistor RN1 of second network 204 may be coupled between an input node for receiving second input voltage VIN and an output node for providing second output voltage VN. Resistors RP2 and RN2 may be coupled between output nodes for providing output voltages VP and VN, and regulator voltage VREG is provided to a common node between resistors RP2 and RN2.

  The first and second impedance ratios may be matched (RP1 / RP2) = (RN1 / RN2), and they may be expressed as nominal matching impedance ratios (R1 / R2) = (RP1 / RP2) ) = (RN1 / RN2). (R2 / R1) may represent the reciprocal of the nominal matching impedance ratio (R1 / R2).

  FIG. 5 provides an equation for the output voltage difference V (VP, VN) derived from the equation of FIG. 4 for the matched impedance ratio (RP1 / RP2) = (RN1 / RN2). Therefore, the difference V (VP, VN) between the first output voltage and the second output voltage is substantially independent of the average value (VIP + VIN) / 2 of the first input voltage and the second input voltage. Or may be substantially independent of the regulator voltage VREG provided by the regulator circuit 202.

  FIG. 6 provides an equation for the output common mode voltage VCM = (VP + VN) / 2 derived from the equation of FIG. 4 for a matched impedance ratio (R1 / R2) = (RP1 / RP2) = (RN1 / RN2). . Thus, the output common mode voltage VCM = (VP + VN) / 2 may be a third weighted average of the input common mode voltage (VIP + VIN) / 2 and the regulator voltage VREG according to the matched impedance ratio (R1 / R2). Thus, the regulator voltage VREG may be derived from an impedance ratio (R1 / R2) matched to the input common mode voltage (VIP + VIN) / 2 so as to achieve the desired output common mode voltage VCM that may be indicated by the control voltage VC. Good.

  The equation of FIG. 6 can be reconstructed as given in FIG. By substituting the output common mode voltage VCM with the control voltage VC, the equation of FIG. 7 describes the nominal operation of the regulator circuit 202 for a matched impedance ratio (RP1 / RP2) = (RN1 / RN2). Thus, the nominal operation of the regulator circuit 202 represented in FIG. 7 for VCM = VC may be to adjust the output common mode voltage VCM to be nominally equal to the control voltage VC for any input voltage VIP, VIN. The regulator circuit 202 may thus be configured to decrease the regulator voltage VREG in response to an increase in the average (VIP + VIN) / 2 of the first input voltage and the second input voltage. Equally, the regulator circuit 202 may be configured to increase the regulator voltage VREG in response to a decrease in the average (VIP + VIN) / 2 of the first input voltage and the second input voltage.

  FIG. 8 illustrates an exemplary implementation of the interface circuit 201 of FIG. 3 including an exemplary implementation of the regulator circuit 202. The regulator circuit 202 may include a third network 205 including a plurality of resistors RXP, RXN, RX2. The resistance values RXP and RXN of each resistor may be nominally matched and may be characterized by RXP = RXN = 2 * RX1 and an effective parallel configuration impedance RX1. The third impedance ratio (RX1 / RX2) that characterizes the third network 205 may be matched to the first and second impedance ratios that characterize the first and second networks 203, 204, thereby Nominally, (RX1 / RX2) = (RP1 / RP2) = (RN1 / RN2) = (R1 / R2). The regulator circuit 202 further includes a single-ended operational amplifier 206. The third network 205 may be resistive and may be configured to provide negative feedback for the operational amplifier 206 as shown in FIG.

  For example, the resistors RXP and RXN of the third network 205 may be coupled between the input nodes VIP and VIN. A common node between resistors RXP and RXN may be coupled to the inverting input of operational amplifier 206. Resistor RX2 may be coupled between the output of operational amplifier 206 and the inverting input. The non-inverting input of the operational amplifier 206 may be supplied with the control voltage VC, and the regulator voltage VREG may be provided at the output of the operational amplifier 206.

  A person skilled in the art, using the well-known superposition principle, has a first contribution from VIP to VREG at a first gain of (-RX2 / RXP), a second gain of (-RX2 / RXN). A second contribution from VIN to VREG and a third contribution from VC to VREG at a third gain of (RX2 / (RXP // RXN) +1) = (RX2 / RX1 + 1) may be calculated. . Therefore, for a matched impedance ratio (RP1 / RP2) = (RN1 / RN2) = (RX1 / RX2) = (R1 / R2), the regulator circuit 202 of FIG. 8 has the equation given in FIG. 7 for VCM = VC. May be described. Therefore, the regulator circuit 202 may nominally adjust the output common mode voltage VCM = (VP + VN) / 2 to track the control voltage VC. The construction of operational amplifiers is well known to those skilled in the art and need not be described herein.

  Impedance mismatch in the first, second, and / or third circuitry 203, 204, 205 and / or imperfection of the operational amplifier 206 may result in an output common mode voltage VCM = (VP + VN) / 2 relative to the control voltage VC. May cause small disturbances. This is typically not a problem. This is because the perturbation may be less than what may be required by a fully differential circuit that receives V (VP, VN).

  The interface circuit 201 may provide some amount of noise and other artifacts that can be observed as modulation of the output common mode voltage VCM = (VP + VN) / 2. Such common mode modulation can be suppressed by a typically large common mode rejection ratio that characterizes a fully differential ADC configured to receive and evaluate V (VP, VN), as shown in FIG. For example, the interface circuit 201 (instead of the interface circuit 101 of FIG. 1) may be configured to keep the modulation of VCM = (VP + VN) / 2 at a level that is at least 60 dB below full scale, and the fully differential ADC 102 Gives 80 dB common-mode rejection, which can result in an overall disturbance that can be as small as 1 million parts.

  Some amount of noise and other artifacts may also be observed with regulator voltage VREG. Due to mismatch of the first impedance ratio (RP1 / RP2) to the second impedance ratio (RN1 / RN2), noise / artifact on VREG appears as noise / artifact on output voltage difference V (VP, VN) There is. Performance with current technology can be achieved firstly by minimizing noise and artifacts on the regulator voltage VREG and secondly by providing a good match of the first and second impedance ratios. is there. For example, the regulator circuit 202 can be configured to keep noise and artifacts on the regulator voltage VREG at a level that is at least 60 dB below full scale. The first and second networks 203, 204 may be, for example, less than about 0.01% even if there is a mismatch in the first and second impedance ratios (RP1 / RP2) and (RN1 / RN2). In addition, it can be realized using well-matched precision resistors. Therefore, any noise / artifact on the regulator voltage VREG is suppressed by about 80 dB when observed at V (VP, VN), so that the resulting turbulence is an extremely high part of 1 million. It is certain that there will be only a small percentage.

  Those skilled in the art will appreciate further advantages of the present disclosure over the conventional interface circuit 101. The output voltage difference V (VP, VN) can be evaluated by a fully differential ADC that samples V (VP, VN) on the differential capacitor C. The thermal noise process is associated with sampling the voltage on capacitor C and those skilled in the art will appreciate that the total noise power is k * T / C, where k is the Boltzmann constant and T is the absolute temperature. It can be recognized that this is possible. The k * T / C result is typically derived by assuming a sampling switch impedance and observing that an inverse relationship between noise power spectral density and noise bandwidth may exist. As a result, the total noise power k * T / C can be independent of the sampling switch impedance. On the other hand, for the prior art interface circuit 101 (FIG. 2), the resistors RN1, RP2, RP1, RN2 give thermal noise to V (VP, VN), and between the noise power spectral density and the noise power. It can be observed that there is no inverse proportional relationship. Thus, even if the differential amplifier 106 is noiseless, the total noise power can exceed k * T / C when sampling the output voltage difference V (VP, VN) on capacitor C. On the other hand, for the present disclosure, illustrated here by interface circuit 201 in FIG. 8, resistors RP1, RP2, RN1, RN2 also add noise to V (VP, VN) when the sampling switch is closed. However, the output impedance of the first and second networks 203, 204 and the sampling capacitance C can establish an inverse relationship between the noise bandwidth observed at V (VP, VN) and the noise power spectral density. . As a result, the total noise power can only be k * T / C after the sampling switch is opened. Thus, the interface circuit 201 may give very little, if any, additional noise when driving a fully differential ADC.

  To those skilled in the art, the present disclosure provides improved linearity while imposing only relatively loose requirements on, for example, operational amplifier 206 (eg, as compared to differential amplifier 106 of conventional interface circuit 101 of FIG. 2). It is understood that noise performance can be provided. For example, an open loop gain of 1,000 (ie 60 dB), and an offset of at most 10 mV can be easily achieved and may be sufficient to achieve an overall accuracy of 1 ppm. The relatively loose requirement represents a major advantage and purpose of the present disclosure.

  The overall linearity of the interface circuit 201 (FIG. 8) is better than the linearity of the individual resistors RP1, RP2, RN1, RN2 (first and second networks 203, 204 of FIG. 8). obtain. Resistor nonlinearity can be (partially) expressed in terms of voltage and temperature coefficient. The equation given in FIG. 5 shows that the overall linearity depends on the linearity of the impedance ratio (R1 / R2) that the nonlinear term can be made to cancel. Thus, in exemplary embodiments of the present disclosure, the first and second networks 203, 204 may be understood as a combination of unit elements that are thermally tightly coupled. For example, resistors RP1, RN1, RP2, RN2 are each implemented as a parallel-series combination of 16 unit resistors R (eg, RP1 = RP2 = RN1 = RN2 = 4R // 4R // 4R // 4R) 4 * 16 = 64 unit resistors may be configured in a compact 8 × 8 layout arrangement. The resistor may be configured in a shared package, or preferably as an integrated circuit on a shared semiconductor substrate.

  In an exemplary embodiment, the full scale range of the input voltage difference V (VIP, VIN) may be (-10V) to (+ 10V), and the differential ADC 102 that evaluates the output voltage difference V (VP, VN). The full scale range of (FIG. 1) may be from -5V to + 5V. The desired magnification may be achieved by selecting the first and second impedance ratios to be 1, and the first and second networks each have two well-matched resistors RP1 = RP2 and RN1 = RN2 may be provided. Other magnifications may be selected by selecting other values for resistors RP1, RP2, RN1, and RN2. An impedance ratio (R1 / R2) = 1 that is 1 may facilitate better matching and overall linear performance than an impedance ratio that is not 1.

  The requirements for operational amplifier 206 (FIG. 8) may be relatively relaxed and can be easily met. The operational amplifier 206 may thus be implemented using integrated circuit technology (eg, CMOS technology) that is well suited to ADC implementations, and is not well suited for implementations of high performance operational amplifier circuits. May be. Accordingly, the present disclosure provides an improved interface circuit 201 that can be implemented on a semiconductor substrate shared with an ADC to facilitate full integration of the ADC system 100 (FIG. 1).

  Some fully differential ADCs may impose very loose requirements for VCM = (VP + VN) / 2. In that case, the third impedance ratio (RX1 / RX2) characterizing the third network 205 may be chosen relatively freely, possibly the first and second characterizing the first and second networks 203,204. The impedance ratio (RP1 / RP2) and (RN1 / RN2) of 2 may be substantially different. The third impedance ratio may be selected, for example, to relax the requirements in terms of the power supply required for the operational amplifier 206. Although not explicitly shown in FIG. 7, those skilled in the art will recognize that power is provided to operational amplifier 206. The third impedance ratio may be selected, for example, to maximize signal swing and dynamic range for a given set of power supply requirements.

  Impedances RP1, RP2, RN1, RN2, RXP, RXN, RX2 need not be primarily resistive, but can be any type of impedance including resistive, capacitive, inductive, or any combination thereof Also good. The frequency response of the first, second, and / or third impedance ratio need not be substantially constant with frequency and may include non-cancelling poles and / or zeros.

  The interface circuit 201 in FIG. 8 includes a first capacitor between VP and GND, and a second capacitor CN between VN and GND (not shown in FIG. 8), thereby forming a low-pass filter. Characteristics may be obtained. Alternatively, in another exemplary embodiment, a lower differential capacitor CDIFF = CP / 2 = CN / 2 (not shown in FIG. 8) is placed between VP and VN to equalize low A pass filter characteristic may be obtained. Many variations of the present disclosure may be provided. For example, the first and second networks may not be separate, but rather they are first and second input nodes for receiving VIP, VIN and first and second for providing VP, VN. It may be configured in a differential network having a second output node, a common node for receiving the regulator voltage VREG, and an optional connection to GND and other fixed potentials. The exemplary embodiments described in this paragraph are examples for providing a differential network comprising CP, CN, and / or CDIFF.

  The frequency response of the third network may be selected depending on the frequency response of the first and second networks to achieve the desired frequency response from the input VIP, VIN to the output VP, VN. . For example, in one embodiment, the interface circuit may be as shown in FIG. 8 where an additional capacitor (not shown) is connected between VP and VN. In another embodiment, the interface circuit replaces resistors RP1 and RN1 with capacitors CP1 and CN1 to match an impedance ratio that can be expressed as a time constant CP1 * RP2 = CN1 * RN2 = CX1 * RX2. And RXN may be replaced by capacitors CXP = CX1 / 2, CXN = CX1 / 2, as shown in FIG.

  Interface circuit 201 of FIG. 8 incorporates resistors RXP, RXN, and RX2 in combination with operational amplifier 206 to provide the nominal response of regulator circuit 202. Other embodiments of the present disclosure may provide a switched capacitor circuit or some other circuit technology to provide a regulator circuit with a similar response. Thus, the third network 205 need not be the same type as the first and second circuits 203, 204 (FIG. 8). For example, one type of circuitry may be a switched capacitor and the other type of circuitry may be resistive.

  The interface circuit 201 (FIG. 8) may be provided in a package shared with a fully differential ADC. The input impedance of the interface circuit 201 may be substantially resistive. The shared package external resistor may be configured to provide a resistive voltage division to the substantially resistive input impedance of the interface circuit 201, thereby providing an external extended full scale range (eg, -100V). To + 100V) maps to the nominal full scale range (eg, -10V to + 10V) for V (VIP, VIN).

  Many variations of the present disclosure are envisioned. Appropriate selection of circuit configuration depends on the specific application and available types of semiconductors, capacitors, resistors, reliability voltage limits, silicon area, cost, and additions typically involved in integrated circuit design Depending on other factors such as general factors and considerations. Various embodiments may incorporate switches implemented as CMOS transmission gate switches, bootstrap switches, single device switches, and / or any other suitable switching device. For example, the operation of the switch may involve a type of circuit known as a “switched operational amplifier”, which is an implicit situation where the switch controls the output impedance of the amplifier.

  Interface circuits implemented in accordance with the present disclosure incorporate various types of semiconductor devices (including all types of MOS, BJT, IGBT, IGFET, JFET, FINFET, organic transistors, nanocarbon tube devices, electromechanical switches, etc.) May be. Some may be selected to withstand high voltage signals and some may be selected for fast settling of low voltage circuit nodes.

  The interface circuit may be implemented using a process technology that provides an asymmetric device (such as a BCD) in addition to a symmetric MOS device, the process technology being an oxide, as well as other having various dimensions and electrical properties A physical structure may be incorporated. The resistor-type impedance element is made using any suitable material available in a given technology, such as, for example, a polycrystalline silicon material, a crystalline silicon material, a metallic material, a carbon material, a composite material (eg silicon-chromium). It may be realized. The resistor-type material may be provided as a thin film and / or a thick film in the form of a lump, with a uniform / non-uniform structure or the like. Capacitor-type impedance elements may also include common structures such as poly-insulator-poly (PIP) capacitors, poly-insulator-metal (PIM) capacitors, metal-insulator-metal (MIM and MOM) capacitors, etc. May be implemented using any suitable material. The capacitor insulator layer may be air, vacuum, or various high / low dielectric materials. The impedance element may be insulated from other devices by an insulator such as silicon oxide, printed wiring board material, air, vacuum, PN junction, plastic, ceramic or the like.

  Any known method of overcoming or suppressing imperfections in a circuit (or sub-circuit, such as a reference voltage circuit) may be used in combination with the present disclosure. The disclosed arrangement may be incorporated as a subsystem in a larger ADC system (eg, it may be combined with any type of ADC including pipeline ADC, SAR ADC, delta-sigma ADC, etc. ). The present disclosure is implemented in higher functional complexity electrical and / or electromechanical systems such as industrial control systems, medical applications (eg, X-ray and MRI equipment), consumer applications (eg, games and television), etc. May be.

  An ADC system according to the present disclosure may provide multiple channels that interface several separate analog signals, eg, through an array of multiplexed front end circuits and / or sample and hold circuits. The ADC is described herein as an example of a fully differential circuit that can be configured to receive V (VP, VN) from an interface circuit according to the present disclosure.

  An ADC circuit including an interface circuit implemented in accordance with the present disclosure may be assembled on a single semiconductor substrate, or as multiple semiconductors in a package, or on a printed circuit board (or otherwise). May be realized.

  One skilled in the art will recognize that the present disclosure may be advantageous for interfacing a wide range of fully differential circuits including, for example, filters and sensors.

  The foregoing description illustrates and describes aspects of the present invention. Additionally, while the disclosure shows and describes only preferred embodiments, as mentioned above, the invention can be used in various other combinations, modifications, and environments, and the above teachings and / or related It should be understood that changes or modifications within the scope of the inventive concept as represented herein may be made commensurate with the skill or knowledge of the technology.

  The embodiments described above illustrate the best mode known for the practice of the invention, and in such or other embodiments, those skilled in the art will be able to use various modifications as required by the particular application or use of the invention. Is further intended to allow the invention to be utilized. Accordingly, the description is not intended to limit the invention to the form disclosed herein.

  201 interface circuit, 202 regulator circuit, 203 first circuit network, 204 second circuit network, 205 third circuit network, 206 operational amplifier.

Claims (31)

An analog-to-digital converter (ADC) circuit comprising a fully differential ADC and an interface circuit for driving the fully differential ADC, wherein the interface circuit receives a first input voltage and a second input voltage. And is further configured to provide a first output voltage and a second output voltage, the interface circuit comprising:
A first circuit configured to receive the first and second input voltages and to provide a voltage at an output of the first circuit, the first circuit comprising: Configured to decrease the voltage at the output of the first circuit in response to an increase in an average value with the second input voltage, and further comprising the first input voltage and the first circuit A first network configured to receive the voltage at the output and further configured to provide the first output voltage, the first network characterized by a first impedance ratio; And a second network configured to receive the second input voltage and the voltage at the output of the first circuit, and further configured to provide the second output voltage The second circuit network includes the first impedance. Wherein the second impedance ratios that are substantially aligned with the dance ratio, analog - digital converter (ADC) circuit. A method of driving a fully differential circuit using an interface circuit having a first circuit and a first and second network coupled to the first circuit, the method comprising:
Providing first and second input voltages to the first circuit;
Reducing the output voltage of the first circuit in response to an increase in an average value of the first input voltage and the second input voltage;
Supplying the first input voltage and the output voltage of the first circuit to the first network to generate a first output voltage for driving a first input of the fully differential circuit Step to
Supplying the second input voltage and the output voltage of the first circuit to the second network to generate a second output voltage for driving a second input of the fully differential circuit And having a step
The impedance ratio of the first network is substantially matched to the impedance ratio of the second network. An interface circuit for driving a fully differential circuit, wherein the interface circuit is configured to receive a first input voltage and a second input voltage, and the first output voltage and the second output voltage. The interface circuit is further configured to provide
A regulator circuit configured to receive the first and second input voltages and to provide a regulator voltage at an output of the regulator circuit, the regulator circuit including the first input voltage and the second input; Configured to reduce the regulator voltage at the output of the regulator circuit in response to an increase in average value with voltage, further configured to receive the first input voltage and the regulator voltage, and A first network further configured to provide a first output voltage, wherein the first network is characterized by a first impedance ratio and further receives the second input voltage and the regulator voltage; And further comprising a second network configured to provide the second output voltage, the second network comprising: Wherein the second impedance ratios that are substantially aligned in serial first impedance ratio, the interface circuit.   4. The circuit of claim 3, wherein the first impedance ratio is substantially the ratio of impedance values of two resistors included in the first network.   The circuit of claim 4, wherein the second impedance ratio is substantially a ratio of impedance values of two resistors included in the second network.   The circuit of claim 3, wherein the first output voltage is substantially equal to a weighted average of the first input voltage and the regulator voltage.   The circuit of claim 3, wherein the first impedance ratio is substantially equal to one.   4. The circuit of claim 3, wherein the first and second circuitry are interchangeable.   4. The circuit of claim 3, wherein the first and second circuitry are incorporated within a differential circuitry.   The first network has a first output coupled to a first input node having a first terminal supplied by the first input voltage and a second terminal provided with the first output voltage. The circuit of claim 3 including a first resistor coupled to the node.   The first network includes a second resistor having a first terminal coupled to the second terminal of the first resistor and a second terminal coupled to a node to which the regulator voltage is applied. The circuit of claim 10, further comprising:   The second network has a first terminal coupled to a second input node to which the second input voltage is supplied, and a second terminal to which the second output voltage is applied. The circuit of claim 11, comprising a third resistor coupled to the node.   The second network includes a fourth resistor having a first terminal coupled to the second terminal of the third resistor and a second terminal coupled to the node to which the regulator voltage is applied. The circuit of claim 12, comprising a vessel.   The first impedance ratio is a ratio of impedance values of the first and second resistors, and the second impedance ratio is a ratio of impedance values of the third and fourth resistors. The circuit according to claim 13.   4. The circuit of claim 3, wherein the regulator circuit is separate from the first and second circuitry.   The regulator circuit includes first and second input nodes for receiving the first and second input voltages, and an output node to which the regulator voltage is applied, and the regulator circuit includes the first and second input nodes. 4. The circuit of claim 3, coupled to the first and second circuitry only through two input nodes and the output node.   4. The circuit of claim 3, wherein the regulator circuit comprises an operational amplifier and a third network characterized by a third impedance ratio substantially matched to the first and second impedance ratios. .   The circuit of claim 17, wherein the third network is a substantially resistive network.   The regulator circuit includes first and second input nodes for receiving the first and second input voltages, and an output node to which the regulator voltage is applied, and the third circuit network includes the first and second input nodes. First and second resistors coupled between one input node and the second input node, and coupled between a node connecting the first and second resistors and the output node The circuit of claim 18, comprising: a third resistor configured.   The circuit of claim 19, wherein the third resistor is coupled between an inverting input and an output of the operational amplifier.   The impedance value of the first resistor is substantially equal to the impedance value of the second resistor, and the impedance value of the second resistor is in a parallel configuration representing the first and second resistors. 21. The circuit of claim 20, wherein the circuit is substantially equal to twice the effective impedance value.   The circuit of claim 21, wherein the third impedance ratio is a ratio of the effective impedance value to the impedance value of the third resistor.   The circuit of claim 3, wherein the interface circuit is configured to drive a fully differential analog-to-digital converter.   24. The circuit of claim 23, wherein the fully differential analog to digital converter is implemented on a semiconductor substrate shared with at least a portion of the interface circuit.   24. The circuit of claim 23, wherein the interface circuit and the fully differential analog-to-digital converter are disposed in a shared package.   The difference between the first output voltage and the second output voltage is substantially independent of an average value of the first input voltage and the second input voltage. The circuit described.   4. The circuit of claim 3, wherein the difference between the first output voltage and the second output voltage is substantially independent of the regulator voltage provided by the regulator circuit.   The regulator circuit is configured to receive a control voltage, and the regulator voltage provided by the regulator circuit is a substantially linear combination of the first and second input voltages and the control voltage. Circuit described in.   30. The circuit of claim 28, wherein an average value of the first output voltage and the second output voltage is substantially equal to the control voltage.   The circuit of claim 3, wherein the regulator circuit comprises a switched capacitor.   The circuit of claim 3, wherein an input impedance of the interface circuit is substantially resistive.