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JP2015023209A - Multilayer ceramic capacitor with interposer, and interposer for multilayer ceramic capacitor - Google Patents

Multilayer ceramic capacitor with interposer, and interposer for multilayer ceramic capacitor Download PDF

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JP2015023209A
JP2015023209A JP2013151645A JP2013151645A JP2015023209A JP 2015023209 A JP2015023209 A JP 2015023209A JP 2013151645 A JP2013151645 A JP 2013151645A JP 2013151645 A JP2013151645 A JP 2013151645A JP 2015023209 A JP2015023209 A JP 2015023209A
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interposer
multilayer ceramic
ceramic capacitor
electrodes
insulating substrate
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JP6144139B2 (en
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和也 石川
Kazuya Ishikawa
和也 石川
佐々木 信弘
Nobuhiro Sasaki
信弘 佐々木
秀男 石原
Hideo Ishihara
秀男 石原
勝之助 芳賀
Katsunosuke Haga
勝之助 芳賀
麦谷 英児
Hideji Mugitani
英児 麦谷
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Taiyo Yuden Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/30Stacked capacitors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/002Details
    • H01G4/228Terminals
    • H01G4/232Terminals electrically connecting two or more layers of a stacked or rolled capacitor

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Ceramic Capacitors (AREA)

Abstract

【課題】回路基板等に実装した状態においてコンデンサ本体の電歪現象を原因として発生し得る音鳴きを確実に抑制できるインターポーザ付き積層セラミックコンデンサを提供する。【解決手段】インターポーザ20は、絶縁基板21の上面に設けられた2つの接続電極22と、絶縁基板21の下面に設けられた2つの実装電極23と、一方の接続電極22と一方の実装電極23を接続するように絶縁基板21に設けられた筒状の第1貫通ビア24と、他方の接続電極22と一方の実装電極23を接続するように絶縁基板21に設けられた筒状の第2貫通ビア24と、第1及び第2貫通ビア24の内孔24aそれぞれの上端開口を塞ぐように設けられたハンダ非付着膜25を備え、各接続電極22の表面には積層セラミックコンデンサ10の各外部電極12の回り込み部12bの一面がハンダSOLを介して接合されている。【選択図】図2An object of the present invention is to provide a multilayer ceramic capacitor with an interposer that can surely suppress noise that may occur due to electrostriction of a capacitor body when mounted on a circuit board or the like. An interposer 20 includes two connection electrodes 22 provided on an upper surface of an insulating substrate 21, two mounting electrodes 23 provided on a lower surface of the insulating substrate 21, one connection electrode 22 and one mounting electrode. A cylindrical first through-via 24 provided in the insulating substrate 21 so as to connect the second connecting electrode 22 and the one mounting electrode 23 so as to connect the first mounting electrode 23 to the cylindrical first through-hole 24 provided in the insulating substrate 21 so as to connect to the second cylindrical electrode. 2 through vias 24 and solder non-adhering films 25 provided so as to close the upper end openings of the inner holes 24a of the first and second through vias 24. The surface of each connection electrode 22 has a multilayer ceramic capacitor 10 One surface of the wraparound portion 12b of each external electrode 12 is joined via solder SOL. [Selection] Figure 2

Description

本発明は、積層セラミックコンデンサにインターポーザが取り付けられたインターポーザ付き積層セラミックコンデンサと、積層セラミックコンデンサを回路基板等に実装する際に用いられる積層セラミックコンデンサ用インターポーザに関する。   The present invention relates to a multilayer ceramic capacitor with an interposer in which an interposer is attached to a multilayer ceramic capacitor, and an interposer for a multilayer ceramic capacitor used when the multilayer ceramic capacitor is mounted on a circuit board or the like.

後記特許文献1の段落0024〜0036と図1(A)及び図2(A)〜図2(D)には、前記インターポーザ付き積層セラミックコンデンサに対応するチップ部品構造体10が記載されている。   In paragraphs 0024 to 0036 and FIG. 1 (A) and FIGS. 2 (A) to 2 (D) of Patent Document 1 described later, a chip component structure 10 corresponding to the multilayer ceramic capacitor with an interposer is described.

このチップ部品構造体10は積層セラミックコンデンサ20とインターポーザ30を備えており、インターポーザ30の絶縁性基板31の長手方向の両端には厚さ方向に貫通する円弧状凹部310がそれぞれ形成されている。また、絶縁性基板31の第1主面には第1実装用電極321及び第2実装用電極331が形成され、第2主面には第1外部接続用電極322及び第2外部接続用電極332が形成されている。さらに、絶縁性基板31の各凹部310の円弧状側壁面には接続導体343が形成され、これら接続導体343によって、第1実装用電極321と第1外部接続用電極322が導通し、第2実装用電極331と第2外部接続用電極332が導通している。一方、積層セラミックコンデンサ20の第1外部電極221はインターポーザ30の第1実装用電極321に接合され、第2外部電極222はインターポーザ30の第2実装用電極331に接合されている。   The chip component structure 10 includes a multilayer ceramic capacitor 20 and an interposer 30, and arc-shaped recesses 310 penetrating in the thickness direction are formed at both ends in the longitudinal direction of the insulating substrate 31 of the interposer 30. In addition, the first mounting electrode 321 and the second mounting electrode 331 are formed on the first main surface of the insulating substrate 31, and the first external connection electrode 322 and the second external connection electrode are formed on the second main surface. 332 is formed. Further, connection conductors 343 are formed on the arc-shaped side wall surfaces of the respective recesses 310 of the insulating substrate 31, and the first mounting electrodes 321 and the first external connection electrodes 322 are electrically connected by the connection conductors 343, so that the second The mounting electrode 331 and the second external connection electrode 332 are electrically connected. On the other hand, the first external electrode 221 of the multilayer ceramic capacitor 20 is bonded to the first mounting electrode 321 of the interposer 30, and the second external electrode 222 is bonded to the second mounting electrode 331 of the interposer 30.

また、このチップ部品構造体10は、後記特許文献1の段落0037及び0038と図1(B)、図3(A)及び図3(B)に記載されているように、第1外部接続用電極322及び第2外部接続用電極332を接合剤400(例えばハンダ)を用いて各実装用ランド901に接合することによって外部回路基板90に実装される。   Further, the chip component structure 10 is used for the first external connection as described in paragraphs 0037 and 0038 of Patent Document 1 described later and FIGS. 1B, 3A, and 3B. The electrode 322 and the second external connection electrode 332 are mounted on the external circuit board 90 by bonding to each mounting land 901 using a bonding agent 400 (for example, solder).

ところで、後記特許文献1の段落0039及び0040には、前記実装によってインターポーザ30の各接続導体343に接合剤400のフィレットが形成されること、並びに、各接続導体343に接合剤400のフィレットが形成されても該接合剤400が積層セラミックコンデンサ20の第1外部電極221及び第2外部電極222の主面(積層セラミックコンデンサ20の長さ方向の端面)に到達し難いことが記載されている。   By the way, in paragraphs 0039 and 0040 of Patent Document 1 described later, a fillet of the bonding agent 400 is formed on each connection conductor 343 of the interposer 30 by the mounting, and a fillet of the bonding agent 400 is formed on each connection conductor 343. However, it is described that the bonding agent 400 hardly reaches the main surfaces (end surfaces in the length direction of the multilayer ceramic capacitor 20) of the first external electrode 221 and the second external electrode 222 of the multilayer ceramic capacitor 20.

しかしながら、後記特許文献1の図1(B)、図3(A)及び図3(B)からも明らかなように、インターポーザ30の各接続導体343が積層セラミックコンデンサ20の第1外部電極221及び第2外部電極222の端面下に在るため、接合剤400が該第1外部電極221及び第2外部電極222の端面に濡れ上がることを抑制することは難しい。   However, as is apparent from FIGS. 1B, 3A, and 3B of Patent Document 1 described later, each connection conductor 343 of the interposer 30 is connected to the first external electrode 221 of the multilayer ceramic capacitor 20 and Since it is below the end surface of the second external electrode 222, it is difficult to suppress the bonding agent 400 from getting wet to the end surfaces of the first external electrode 221 and the second external electrode 222.

要するに、前記チップ部品構造体10では、前記実装によって接合剤400のフィレットが外部回路基板90の各実装用ランド901から積層セラミックコンデンサ20の第1外部電極221及び第2外部電極222の端面それぞれに及んで形成されることを回避できない。そのため、前記実装状態で積層セラミックコンデンサ20に電圧、特に交流電圧が印加されてセラミック積層体21に電歪現象を生じると、該電歪現象に伴う反り及びその復元が外部回路基板90に生じて所謂音鳴きを発生し易い。   In short, in the chip component structure 10, the fillet of the bonding agent 400 is applied from the mounting lands 901 of the external circuit board 90 to the end surfaces of the first external electrode 221 and the second external electrode 222 of the multilayer ceramic capacitor 20 by the mounting. It cannot be avoided that it is formed. Therefore, when a voltage, particularly an AC voltage, is applied to the multilayer ceramic capacitor 20 in the mounted state to cause an electrostriction phenomenon in the ceramic multilayer body 21, warpage associated with the electrostriction phenomenon and its restoration occur in the external circuit board 90. It is easy to generate a so-called sound.

特開2012−204572号公報JP 2012-204572 A

本発明の目的は、回路基板等に実装した状態においてコンデンサ本体の電歪現象を原因として発生し得る音鳴きを確実に抑制できるインターポーザ付き積層セラミックコンデンサ、及び積層セラミックコンデンサ用インターポーザを提供することにある。   An object of the present invention is to provide a multilayer ceramic capacitor with an interposer and an interposer for a multilayer ceramic capacitor that can surely suppress the noise that may occur due to the electrostriction phenomenon of the capacitor body when mounted on a circuit board or the like. is there.

前記目的を達成するため、本発明のインターポーザ付き積層セラミックコンデンサは、積層セラミックコンデンサにインターポーザが取り付けられたインターポーザ付き積層セラミックコンデンサであって、(1)前記積層セラミックコンデンサは長さ>幅及び高さの関係を満足する略直方体状を成していて、複数の内部電極層が誘電体層を介して積層された構造の容量形成部を有する略直方体状のコンデンサ本体と、前記コンデンサ本体の長さ方向の端面それぞれを覆う略矩形状の端面部及び該各端面部と連続して前記コンデンサ本体の4側面の一部を覆う略4角筒状の回り込み部を有し、且つ、前記複数の内部電極層の一部が一方に接続され残部が他方に接続された2つの外部電極を備えており、(2)前記インターポーザは長さ>幅及び高さの関係を満足する略直方体状を成していて、略直方体状の絶縁基板と、前記絶縁基板の厚さ方向の一面に前記2つの外部電極の回り込み部の一面それぞれと向き合うように設けられた略矩形状の2つの接続電極と、前記絶縁基板の厚さ方向の他面に前記2つの接続電極それぞれと向き合うように設けられた略矩形状の2つの実装電極と、前記絶縁基板の長さ方向の端面よりも内側において前記2つの接続電極の一方と前記2つの実装電極の一方を接続するように、且つ、内孔の一端が前記2つの接続電極の一方の表面で開口し他端が前記2つの実装電極の一方の表面で開口するように設けられた筒状の第1貫通ビアと、前記絶縁基板の長さ方向の端面よりも内側において前記2つの接続電極の他方と前記2つの実装電極の他方を接続するように、且つ、内孔の一端が前記2つの接続電極の他方の表面で開口し他端が前記2つの実装電極の他方の表面で開口するように設けられた筒状の第2貫通ビアと、前記第1貫通ビアの内孔の一端開口と前記第2貫通ビアの内孔の一端開口を塞ぐように設けられたハンダ非付着膜を備えており、(3)前記インターポーザの前記2つの接続電極の表面それぞれには、前記積層セラミックコンデンサの前記2つの外部電極の回り込み部の一面それぞれがハンダを介して接合されており、(4)前記インターポーザの前記第1貫通ビアの内孔の他端開口から前記ハンダ非付着膜に至る領域と前記第2貫通ビアの内孔の他端開口から前記ハンダ非付着膜に至る領域は何れも空の状態となっている。   In order to achieve the above object, the multilayer ceramic capacitor with an interposer of the present invention is a multilayer ceramic capacitor with an interposer in which the interposer is attached to the multilayer ceramic capacitor, and (1) the multilayer ceramic capacitor has a length> width and height. A substantially rectangular parallelepiped capacitor body having a capacity forming portion having a structure in which a plurality of internal electrode layers are stacked via a dielectric layer, and a length of the capacitor body. A substantially rectangular end surface portion covering each of the end surfaces in the direction, and a substantially rectangular tubular wraparound portion covering a part of the four side surfaces of the capacitor body continuously with each end surface portion, and the plurality of internal portions Two external electrodes, one part of which is connected to one side and the other part is connected to the other, (2) the interposer has a length> width and It has a substantially rectangular parallelepiped shape that satisfies the height relationship, and is provided so as to face one surface of the wraparound portion of the two external electrodes on one surface in the thickness direction of the insulating substrate. Two substantially rectangular connection electrodes, two substantially rectangular mounting electrodes provided on the other surface in the thickness direction of the insulating substrate so as to face the two connection electrodes, and the insulating substrate. One of the two connection electrodes and one of the two mounting electrodes are connected to the inner side of the end face in the length direction, and one end of the inner hole is opened on one surface of the two connection electrodes. A cylindrical first through via provided with an end opened on one surface of the two mounting electrodes, the other of the two connection electrodes on the inner side of the end surface in the length direction of the insulating substrate, and the Connect the other of the two mounting electrodes And a cylindrical second through via provided so that one end of the inner hole is opened on the other surface of the two connection electrodes and the other end is opened on the other surface of the two mounting electrodes. A solder non-adhering film provided to close one end opening of the inner hole of the first through via and one end opening of the inner hole of the second through via, and (3) the two connections of the interposer One surface of each of the wraparound portions of the two external electrodes of the multilayer ceramic capacitor is bonded to each of the electrode surfaces via solder. (4) The other end of the inner hole of the first through via of the interposer The region from the opening to the solder non-adhering film and the region from the other end opening of the inner hole of the second through via to the solder non-adhering film are both empty.

一方、本発明の積層セラミックコンデンサ用インターポーザは、積層セラミックコンデンサを回路基板等に実装する際に用いられる積層セラミックコンデンサ用インターポーザであって、(1)前記積層セラミックコンデンサは長さ>幅及び高さの関係を満足する略直方体状を成していて、複数の内部電極層が誘電体層を介して積層された構造の容量形成部を有する略直方体状のコンデンサ本体と、前記コンデンサ本体の長さ方向の端面それぞれを覆う略矩形状の端面部及び該各端面部と連続して前記コンデンサ本体の4側面の一部を覆う略4角筒状の回り込み部を有し、且つ、前記複数の内部電極層の一部が一方に接続され残部が他方に接続された2つの外部電極を備えており、(2)前記インターポーザは長さ>幅及び高さの関係を満足する略直方体状を成していて、略直方体状の絶縁基板と、前記絶縁基板の厚さ方向の一面に前記2つの外部電極の回り込み部の一面それぞれと向き合うように設けられた略矩形状の2つの接続電極と、前記絶縁基板の厚さ方向の他面に前記2つの接続電極それぞれと向き合うように設けられた略矩形状の2つの実装電極と、前記絶縁基板の長さ方向の端面よりも内側において前記2つの接続電極の一方と前記2つの実装電極の一方を接続するように、且つ、内孔の一端が前記2つの接続電極の一方の表面で開口し他端が前記2つの実装電極の一方の表面で開口するように設けられた筒状の第1貫通ビアと、前記絶縁基板の長さ方向の端面よりも内側において前記2つの接続電極の他方と前記2つの実装電極の他方を接続するように、且つ、内孔の一端が前記2つの接続電極の他方の表面で開口し他端が前記2つの実装電極の他方の表面で開口するように設けられた筒状の第2貫通ビアと、前記第1貫通ビアの内孔の一端開口と前記第2貫通ビアの内孔の一端開口を塞ぐように設けられたハンダ非付着膜を備えており、(3)前記インターポーザの前記2つの接続電極の表面それぞれは、前記積層セラミックコンデンサの前記2つの外部電極の回り込み部の一面それぞれをハンダを介して接合するためのものであり、(4)前記インターポーザの前記第1貫通ビアの内孔の他端開口から前記ハンダ非付着膜に至る領域と前記第2貫通ビアの内孔の他端開口から前記ハンダ非付着膜に至る領域は何れも空の状態となっている。   On the other hand, the interposer for a multilayer ceramic capacitor of the present invention is an interposer for a multilayer ceramic capacitor used when the multilayer ceramic capacitor is mounted on a circuit board or the like. (1) The multilayer ceramic capacitor has a length> width and height. A substantially rectangular parallelepiped capacitor body having a capacity forming portion having a structure in which a plurality of internal electrode layers are stacked via a dielectric layer, and a length of the capacitor body. A substantially rectangular end surface portion covering each of the end surfaces in the direction, and a substantially rectangular tubular wraparound portion covering a part of the four side surfaces of the capacitor body continuously with each end surface portion, and the plurality of internal portions It has two external electrodes in which a part of the electrode layer is connected to one side and the remaining part is connected to the other. (2) The interposer satisfies the relationship of length> width and height A substantially rectangular parallelepiped-shaped insulating substrate, and a substantially rectangular-shaped insulating substrate provided on one surface in the thickness direction of the insulating substrate so as to face one surface of the wraparound portion of the two external electrodes. From two connection electrodes, two substantially rectangular mounting electrodes provided on the other surface in the thickness direction of the insulating substrate so as to face each of the two connection electrodes, and an end surface in the length direction of the insulating substrate Also, one of the two connection electrodes and one of the two mounting electrodes are connected inside, and one end of an inner hole is opened on one surface of the two connection electrodes, and the other end is mounted on the two mounting electrodes. A cylindrical first through via provided to open on one surface of the electrode, and the other of the two connection electrodes and the other of the two mounting electrodes on the inner side of the end surface in the length direction of the insulating substrate And so on A cylindrical second through via provided so that one end of the first connection hole is opened on the other surface of the two connection electrodes and the other end is opened on the other surface of the two mounting electrodes; A solder non-adhesion film provided to close one end opening of the inner hole and one end opening of the inner hole of the second through-via, and (3) each of the surfaces of the two connection electrodes of the interposer For joining each one surface of the wraparound portion of the two external electrodes of the multilayer ceramic capacitor via solder, (4) from the other end opening of the inner hole of the first through via of the interposer The region reaching the adhesion film and the region extending from the other end opening of the inner hole of the second through via to the solder non-adhesion film are both empty.

本発明によれば、回路基板等に実装した状態においてコンデンサ本体の電歪現象を原因として発生し得る音鳴きを確実に抑制できるインターポーザ付き積層セラミックコンデンサ、及び積層セラミックコンデンサ用インターポーザを提供することができる。   According to the present invention, it is possible to provide a multilayer ceramic capacitor with an interposer and an interposer for a multilayer ceramic capacitor that can surely suppress the noise that may occur due to the electrostriction phenomenon of the capacitor body when mounted on a circuit board or the like. it can.

本発明の前記目的及び他の目的と、各目的に応じた特徴と効果は、以下の説明と添付図面によって明らかとなる。   The above and other objects of the present invention, and the features and effects according to the respective objects will become apparent from the following description and the accompanying drawings.

図1は本発明を適用したインターポーザ付き積層セラミックコンデンサ(第1実施形態)の上面図である。FIG. 1 is a top view of a multilayer ceramic capacitor with an interposer to which the present invention is applied (first embodiment). 図2は図1のX1−X1線に沿う断面図である。2 is a cross-sectional view taken along line X1-X1 of FIG. 図3は図1に示した積層セラミックコンデンサの上面図である。FIG. 3 is a top view of the multilayer ceramic capacitor shown in FIG. 図4は図3のX2−X2線に沿う断面図である。4 is a cross-sectional view taken along line X2-X2 of FIG. 図5は図1に示したインターポーザの上面図である。FIG. 5 is a top view of the interposer shown in FIG. 図6は図1に示したインターポーザの下面図である。FIG. 6 is a bottom view of the interposer shown in FIG. 図7は図5のX3−X3線に沿う断面図である。FIG. 7 is a cross-sectional view taken along line X3-X3 in FIG. 図8は図1に示したインターポーザ付き積層セラミックコンデンサを回路基板に実装した状態を示す図4対応の断面図である。8 is a cross-sectional view corresponding to FIG. 4 showing a state in which the multilayer ceramic capacitor with an interposer shown in FIG. 1 is mounted on a circuit board. 図9は本発明を適用したインターポーザ付き積層セラミックコンデンサ(第2実施形態)におけるインターポーザの上面図である。FIG. 9 is a top view of the interposer in the multilayer ceramic capacitor with an interposer to which the present invention is applied (second embodiment). 図10は図9のX4−X4線に沿う断面図である。10 is a cross-sectional view taken along line X4-X4 of FIG. 図11はインターポーザ付き積層セラミックコンデンサ(第2実施形態)の図2対応の断面図である。FIG. 11 is a cross-sectional view of a multilayer ceramic capacitor with an interposer (second embodiment) corresponding to FIG. 図12は本発明を適用したインターポーザ付き積層セラミックコンデンサ(第3実施形態)におけるインターポーザの上面図である。FIG. 12 is a top view of an interposer in a multilayer ceramic capacitor with an interposer to which the present invention is applied (third embodiment). 図13は図12のX5−X5線に沿う断面図である。13 is a cross-sectional view taken along line X5-X5 in FIG. 図14はインターポーザ付き積層セラミックコンデンサ(第3実施形態)の図2対応の断面図である。FIG. 14 is a cross-sectional view corresponding to FIG. 2 of the multilayer ceramic capacitor with an interposer (third embodiment). 図15は本発明を適用したインターポーザ付き積層セラミックコンデンサ(第4実施形態)におけるインターポーザの上面図である。FIG. 15 is a top view of an interposer in a multilayer ceramic capacitor with an interposer to which the present invention is applied (fourth embodiment). 図16は図15に示したインターポーザの下面図である。FIG. 16 is a bottom view of the interposer shown in FIG. 図17は図15のX6−X6線に沿う断面図である。17 is a cross-sectional view taken along line X6-X6 in FIG. 図18はインターポーザ付き積層セラミックコンデンサ(第4実施形態)の図2対応の断面図である。18 is a cross-sectional view corresponding to FIG. 2 of a multilayer ceramic capacitor with an interposer (fourth embodiment). 図19は本発明を適用したインターポーザ付き積層セラミックコンデンサ(第5実施形態)におけるインターポーザの上面図である。FIG. 19 is a top view of an interposer in a multilayer ceramic capacitor with an interposer to which the present invention is applied (fifth embodiment). 図20は図19のX7−X7線に沿う断面図である。20 is a cross-sectional view taken along line X7-X7 in FIG. 図21はインターポーザ付き積層セラミックコンデンサ(第5実施形態)の図2対応の断面図である。FIG. 21 is a cross-sectional view of a multilayer ceramic capacitor with an interposer (fifth embodiment) corresponding to FIG. 図22は本発明を適用したインターポーザ付き積層セラミックコンデンサ(第6実施形態)における積層セラミックコンデンサの上面図である。FIG. 22 is a top view of the multilayer ceramic capacitor in the multilayer ceramic capacitor with an interposer to which the present invention is applied (sixth embodiment). 図23は図22のX8−X8線に沿う断面図である。23 is a cross-sectional view taken along line X8-X8 in FIG. 図24はインターポーザ付き積層セラミックコンデンサ(第6実施形態)の図2対応の断面図である。FIG. 24 is a cross-sectional view of the multilayer ceramic capacitor with an interposer (sixth embodiment) corresponding to FIG.

尚、以下の説明で用いた「長さ」、「幅」、「高さ」、「厚さ」、「寸法」及び「距離」は何れも設計上の基準値を指すものであって、基準値±公差の中の特定値を指すものではない。   The “length”, “width”, “height”, “thickness”, “dimension”, and “distance” used in the following description all indicate design standard values. It does not indicate a specific value within the value ± tolerance.

《第1実施形態(図1〜図8)》
図1及び図2に示したインターポーザ付き積層セラミックコンデンサ(符号無し)は、積層セラミックコンデンサ10にインターポーザ20が取り付けられたものである。
<< 1st Embodiment (FIGS. 1-8) >>
The multilayer ceramic capacitor with an interposer (no symbol) shown in FIGS. 1 and 2 is obtained by attaching an interposer 20 to the multilayer ceramic capacitor 10.

図3及び図4に示したように、積層セラミックコンデンサ10は、長さL10>幅W10及び高さH10の関係を満足する略直方体状を成している。この積層セラミックコンデンサ10は、複数の内部電極層11a1が誘電体層11a2を介して積層された構造の容量形成部11aを有する略直方体状のコンデンサ本体11と、コンデンサ本体11の長さ方向の端面それぞれを覆う略矩形状の端面部12a及び該各端面部12aと連続してコンデンサ本体11の4側面の一部を覆う略4角筒状の回り込み部12bを有し、且つ、複数の内部電極層11a1の一部が一方に接続され残部が他方に接続された2つの外部電極12を備えている。   As shown in FIGS. 3 and 4, the multilayer ceramic capacitor 10 has a substantially rectangular parallelepiped shape that satisfies the relationship of length L10> width W10 and height H10. The multilayer ceramic capacitor 10 includes a capacitor body 11 having a substantially rectangular parallelepiped shape having a capacitance forming portion 11a having a structure in which a plurality of internal electrode layers 11a1 are stacked via a dielectric layer 11a2, and an end face in the length direction of the capacitor body 11 A substantially rectangular end surface portion 12a covering each of them, and a substantially rectangular tube-shaped wraparound portion 12b covering a part of the four side surfaces of the capacitor body 11 continuously with each end surface portion 12a, and a plurality of internal electrodes Two external electrodes 12 having a part of the layer 11a1 connected to one side and the remaining part connected to the other are provided.

補足すれば、コンデンサ本体11は、容量形成部11aと、複数の誘電体層(符号無し)が高さ方向に積層された構造の保護部11bを、高さ方向の一側から他側に向かって、保護部11b−容量形成部11a−保護部11bの順に有している。   If it supplements, the capacitor | condenser main body 11 will go from the one side of a height direction to the other side by the capacity | capacitance formation part 11a and the protection part 11b of the structure where several dielectric material layers (no code | symbol) were laminated | stacked in the height direction. The protective portion 11b, the capacitance forming portion 11a, and the protective portion 11b are provided in this order.

容量形成部11aに含まれる複数の内部電極層11a1の厚さは等しく、且つ、複数の内部電極層11a1の輪郭(略矩形)を規定する寸法も等しい。また、容量形成部11aに含まれる複数の内部電極層11a1は同じ材料から成り、該材料にはニッケル、銅、パラジウム、白金、銀、金、これらの合金等の金属が用いられている。さらに、容量形成部11aに含まれる複数の内部電極層11a1は長さ方向に交互にずれていて、図4中の上から奇数番目の端縁は図4中の左側の外部電極12に接続され、図4中の上から偶数番目の端縁は図4中の右側の外部電極12に接続されている。   The thicknesses of the plurality of internal electrode layers 11a1 included in the capacitance forming portion 11a are equal, and the dimensions that define the outline (substantially rectangular) of the plurality of internal electrode layers 11a1 are also equal. The plurality of internal electrode layers 11a1 included in the capacitance forming portion 11a are made of the same material, and a metal such as nickel, copper, palladium, platinum, silver, gold, or an alloy thereof is used as the material. Further, the plurality of internal electrode layers 11a1 included in the capacitance forming portion 11a are alternately shifted in the length direction, and the odd-numbered end edges from the top in FIG. 4 are connected to the left external electrode 12 in FIG. The even-numbered edge from the top in FIG. 4 is connected to the right external electrode 12 in FIG.

容量形成部11aに含まれる複数の誘電体層11a2の厚さは等しく、保護部11bを構成する誘電体層の厚さは等しい。また、容量形成部11aに含まれる複数の誘電体層11a2と保護部11bを構成する誘電体層は同じ材料から成り、該材料にはチタン酸バリウム、チタン酸ストロンチウム、チタン酸カルシウム、チタン酸マグネシウム、ジルコン酸カルシウム、チタン酸ジルコン酸カルシウム、ジルコン酸バリウム、酸化チタン等の誘電体セラミックス、好ましくはε>1000又はクラス2(高誘電率系)の誘電体セラミックスが用いられている。   The plurality of dielectric layers 11a2 included in the capacitance forming portion 11a are equal in thickness, and the dielectric layers constituting the protection portion 11b are equal in thickness. The plurality of dielectric layers 11a2 included in the capacitance forming portion 11a and the dielectric layers constituting the protective portion 11b are made of the same material, and the materials include barium titanate, strontium titanate, calcium titanate, and magnesium titanate. Dielectric ceramics such as calcium zirconate, calcium zirconate titanate, barium zirconate, and titanium oxide, and preferably dielectric ceramics of ε> 1000 or class 2 (high dielectric constant) are used.

2つの外部電極12の厚さは等しく、各外部電極12はコンデンサ本体11の長さ方向の端面を覆う略矩形状の端面部12aと該端面部12aと連続してコンデンサ本体11の4側面の一部を覆う略4角筒状の回り込み部12bを有している。また、各外部電極12の長さL12は積層セラミックコンデンサ10の長さL10の1/7〜1/3の範囲内にあり、各外部電極12の幅W12は積層セラミックコンデンサ10の幅W12を規定し、各外部電極12の高さH12は積層セラミックコンデンサ10の高さH10を規定している。   The thicknesses of the two external electrodes 12 are equal, and each external electrode 12 has a substantially rectangular end surface portion 12a covering the end surface in the length direction of the capacitor main body 11, and four end surfaces of the capacitor main body 11 continuous with the end surface portion 12a. It has a substantially quadrangular cylindrical wraparound portion 12b that covers a part. The length L12 of each external electrode 12 is in the range of 1/7 to 1/3 of the length L10 of the multilayer ceramic capacitor 10, and the width W12 of each external electrode 12 defines the width W12 of the multilayer ceramic capacitor 10. The height H12 of each external electrode 12 defines the height H10 of the multilayer ceramic capacitor 10.

図示を省略したが、各外部電極12は、コンデンサ本体11の外面に密着した下地膜と該下地膜の外面に密着した表面膜との2層構造、或いは、下地膜と表面膜との間に少なくとも1つの中間膜を有する多層構造を有している。下地膜は例えば焼付け金属膜から成り、その材料にはニッケル、銅、パラジウム、白金、銀、金、これらの合金等の金属が用いられている。表面膜は例えばメッキ金属膜から成り、その材料にはスズ、パラジウム、金、亜鉛等の金属が用いられている。中間膜は例えばメッキ金属膜から成り、その材料には白金、パラジウム、金、銅、ニッケル等の金属が用いられている。   Although not shown, each external electrode 12 has a two-layer structure of a base film that is in close contact with the outer surface of the capacitor body 11 and a surface film that is in close contact with the outer surface of the base film, or between the base film and the surface film. It has a multilayer structure having at least one intermediate film. The base film is made of, for example, a baked metal film, and a metal such as nickel, copper, palladium, platinum, silver, gold, or an alloy thereof is used as the material. The surface film is made of, for example, a plated metal film, and a metal such as tin, palladium, gold, or zinc is used as the material. The intermediate film is made of, for example, a plated metal film, and a metal such as platinum, palladium, gold, copper, or nickel is used as the material.

一方、図5〜図7に示したように、インターポーザ20は、長さL20>幅W20及び高さH20の関係を満足する略直方体状を成している。このインターポーザ20は、略直方体状の絶縁基板21と、絶縁基板21の厚さ方向の一面(上面)に前記2つの外部電極12の回り込み部12bの一面それぞれと向き合うように設けられた略矩形状の2つの接続電極22と、絶縁基板21の厚さ方向の他面(下面)に2つの接続電極22それぞれと向き合うように設けられた略矩形状の2つの実装電極23と、絶縁基板21の長さ方向の端面よりも内側において2つの接続電極22の一方と2つの実装電極23の一方を接続するように、且つ、内孔24aの一端(上端)が2つの接続電極22の一方の表面で開口し他端(下端)が2つの実装電極23の一方の表面で開口するように設けられた略円筒状の第1貫通ビア24と、絶縁基板21の長さ方向の端面よりも内側において2つの接続電極22の他方と2つの実装電極23の他方を接続するように、且つ、内孔24aの一端(上端)が2つの接続電極22の他方の表面で開口し他端(下端)が2つの実装電極23の他方の表面で開口するように設けられた略円筒状の第2貫通ビア24と、第1貫通ビア24の内孔24aの一端開口(上端開口)と第2貫通ビア24の内孔24aの一端開口(上端開口)を塞ぐように設けられた略矩形状のハンダ非付着膜25を備えている。   On the other hand, as shown in FIGS. 5 to 7, the interposer 20 has a substantially rectangular parallelepiped shape that satisfies the relationship of length L20> width W20 and height H20. The interposer 20 has a substantially rectangular parallelepiped insulating substrate 21 and a substantially rectangular shape provided on one surface (upper surface) in the thickness direction of the insulating substrate 21 so as to face one surface of the wraparound portion 12b of the two external electrodes 12. The two connecting electrodes 22, two substantially rectangular mounting electrodes 23 provided on the other surface (lower surface) of the insulating substrate 21 in the thickness direction so as to face the two connecting electrodes 22, and the insulating substrate 21. One of the two connection electrodes 22 and one of the two mounting electrodes 23 are connected inside the end face in the length direction, and one end (upper end) of the inner hole 24a is one surface of the two connection electrodes 22 The first through-via 24 having a substantially cylindrical shape provided so that the other end (lower end) is opened on one surface of the two mounting electrodes 23, and on the inner side of the end surface in the length direction of the insulating substrate 21. 2 connections One end (upper end) of the inner hole 24a is opened on the other surface of the two connection electrodes 22 and the other end (lower end) is two mounted so as to connect the other of the poles 22 and the other of the two mounting electrodes 23. A substantially cylindrical second through via 24 provided so as to open on the other surface of the electrode 23, one end opening (upper end opening) of the inner hole 24 a of the first through via 24, and an inner hole of the second through via 24. A substantially rectangular solder non-adhesion film 25 is provided so as to close one end opening (upper end opening) of 24a.

補足すれば、絶縁基板21の厚さは略一定であり、絶縁基板21の長さL21はインターポーザ20の長さL20を規定し、絶縁基板21の幅W21はインターポーザ20の幅W20を規定している。また、絶縁基板21の材料には二酸化ケイ素、酸化アルミニウム、窒化ケイ素等のセラミックス、或いは、エポキシ樹脂、フェノール樹脂、ポリイミド樹脂、ユリア樹脂、メラミン樹脂、不飽和ポリエステル樹脂、ビスマレイミド樹脂、ポリウレタン樹脂、ジアリルフタレート樹脂、シリコーン樹脂、シアネート樹脂等の熱硬化性プラスチック又はこれらに補強フィラーを含有させた熱硬化性プラスチックが用いられている。   In other words, the thickness of the insulating substrate 21 is substantially constant, the length L21 of the insulating substrate 21 defines the length L20 of the interposer 20, and the width W21 of the insulating substrate 21 defines the width W20 of the interposer 20. Yes. The insulating substrate 21 may be made of ceramics such as silicon dioxide, aluminum oxide, silicon nitride, or epoxy resin, phenol resin, polyimide resin, urea resin, melamine resin, unsaturated polyester resin, bismaleimide resin, polyurethane resin, Thermosetting plastics such as diallyl phthalate resin, silicone resin, and cyanate resin, or thermosetting plastics containing these with reinforcing fillers are used.

2つの接続電極22の厚さは等しく、且つ、2つの接続電極22の輪郭を規定する寸法(長さL22及び幅W22を含む)も等しい。また、2つの実装電極23の厚さは等しく、且つ、2つの実装電極23の輪郭を規定する寸法(長さL23及び幅W23を含む)も等しい。さらに、第1及び第2貫通ビア24の厚さと内孔24aの口径は等しく、第1及び第2貫通ビア24は絶縁基板21の長さ方向の端面から極力離れた位置、換言すれば、絶縁基板21の長さ方向の中心寄りに設けられている。因みに、各接続電極22の内側縁中央に略半円状の張出部22aが在り、これらと向き合うように各実装電極23の内側縁中央に略半円状の張出部23aが在るのは、第1及び第2貫通ビア24を絶縁基板21の長さ方向の中心寄りに位置させるための工夫である。さらに、各接続電極22と各実装電極23と第1及び第2貫通ビア24の材料はニッケル、銅、パラジウム、白金、銀、金、これらの合金等の金属が用いられている。   The thicknesses of the two connection electrodes 22 are equal, and the dimensions (including the length L22 and the width W22) that define the contours of the two connection electrodes 22 are also equal. Further, the thicknesses of the two mounting electrodes 23 are equal, and the dimensions (including the length L23 and the width W23) that define the contours of the two mounting electrodes 23 are also equal. Furthermore, the thickness of the first and second through vias 24 is equal to the diameter of the inner hole 24a, and the first and second through vias 24 are located as far as possible from the end face in the length direction of the insulating substrate 21, in other words, insulating. The substrate 21 is provided near the center in the length direction. Incidentally, there is a substantially semicircular protruding portion 22a at the center of the inner edge of each connection electrode 22, and there is a substantially semicircular protruding portion 23a at the center of the inner edge of each mounting electrode 23 so as to face these. Is a device for positioning the first and second through vias 24 closer to the center in the length direction of the insulating substrate 21. Furthermore, the connection electrodes 22, the mounting electrodes 23, and the first and second through vias 24 are made of metal such as nickel, copper, palladium, platinum, silver, gold, and alloys thereof.

ハンダ非付着膜25は、第1及び第2貫通ビア24の内孔24aそれぞれの一端開口(上端開口)を塞ぐように、2つの接続電極22の表面それぞれの一部(内側部分)と絶縁基板21の厚さ方向の一面(上面)の一部(2つの接続電極22間の部分)に連続的に形成されている。つまり、第1及び第2貫通ビア24の内孔24aそれぞれの他端開口(下端開口)からハンダ非付着膜25に至る領域は何れも空の状態となっている。しかも、各接続電極22の表面それぞれの一部(内側部分)がハンダ非付着膜25によって覆われていることから、各接続電極22の表面においてハンダ非付着膜25が形成されてない略矩形状の残部(外側部分)が該各接続電極22の有効接続領域22bとなっている。また、ハンダ非付着膜25の表面は略平坦であり、各接続電極22の表面上の厚さは絶縁基板21の厚さ方向の一面(上面)上の厚さよりも薄い。さらに、ハンダ非付着膜25の材料には後記ハンダSOLが付着しない材料、例えば(1)周知のソルダレジスト、(2)エポキシ樹脂、フェノール樹脂、ポリイミド樹脂、ユリア樹脂、メラミン樹脂、不飽和ポリエステル樹脂、ビスマレイミド樹脂、ポリウレタン樹脂、ジアリルフタレート樹脂、シリコーン樹脂、シアネート樹脂等の熱硬化性プラスチック、或いは、(3)二酸化ケイ素、酸化アルミニウム、窒化ケイ素等の無機絶縁材、即ち、金属成分を含まない絶縁材料が用いられている。   The solder non-adhesion film 25 is formed on a part (inner part) of each of the surfaces of the two connection electrodes 22 and the insulating substrate so as to block one end opening (upper end opening) of each of the inner holes 24a of the first and second through vias 24. 21 is continuously formed on a part of one surface (upper surface) in the thickness direction 21 (a portion between two connection electrodes 22). That is, the region from the other end opening (lower end opening) of each of the inner holes 24a of the first and second through vias 24 to the solder non-adhering film 25 is empty. In addition, since a part (inner part) of the surface of each connection electrode 22 is covered with the solder non-adhesion film 25, the surface of each connection electrode 22 has a substantially rectangular shape where the solder non-adhesion film 25 is not formed. The remaining part (outer part) is an effective connection region 22 b of each connection electrode 22. Further, the surface of the solder non-adhesion film 25 is substantially flat, and the thickness on the surface of each connection electrode 22 is thinner than the thickness on one surface (upper surface) in the thickness direction of the insulating substrate 21. Further, the material of the solder non-adhering film 25 is a material to which solder SOL described later does not adhere, for example, (1) a well-known solder resist, (2) epoxy resin, phenol resin, polyimide resin, urea resin, melamine resin, unsaturated polyester resin. , Thermosetting plastics such as bismaleimide resin, polyurethane resin, diallyl phthalate resin, silicone resin, cyanate resin, or (3) inorganic insulating materials such as silicon dioxide, aluminum oxide, silicon nitride, ie, no metal components Insulating material is used.

ここで、積層セラミックコンデンサ10の寸法とインターポーザ20の寸法との関係について説明する。インターポーザ20の長さL20(=絶縁基板21の長さL21)は積層セラミックコンデンサ10の長さL10よりも僅かに長く、インターポーザ20の幅W20(=絶縁基板21の幅W21)は積層セラミックコンデンサ10の幅W10よりも僅かに広く、インターポーザ20の高さH20は積層セラミックコンデンサ10の高さH10の1/8〜1/2の範囲内にある。また、インターポーザ20の2つの接続電極22の長さ方向に沿う外側縁間の距離D22は積層セラミックコンデンサ10の長さL10と等しく、各接続電極22の幅W22は積層セラミックコンデンサ10の幅W10と等しく、各接続電極22の有効接続領域22bの長さL22bは積層セラミックコンデンサ10の各外部電極の長さL12よりも僅かに短い。さらに、インターポーザ20のハンダ非付着膜25の長さは第1及び第2貫通ビア24の内孔24aそれぞれの一端開口(上端開口)を塞ぐのに十分な長さを有しており、ハンダ非付着膜25の幅は絶縁基板21の幅W21と等しい。さらに、インターポーザ20の2つの実装電極23の長さ方向に沿う外側縁間の距離D23は積層セラミックコンデンサ10の長さL10と等しく、各実装電極23の幅W23は積層セラミックコンデンサ10の幅W10と等しい。   Here, the relationship between the dimension of the multilayer ceramic capacitor 10 and the dimension of the interposer 20 will be described. The length L20 of the interposer 20 (= the length L21 of the insulating substrate 21) is slightly longer than the length L10 of the multilayer ceramic capacitor 10, and the width W20 of the interposer 20 (= the width W21 of the insulating substrate 21) is the multilayer ceramic capacitor 10. The height H20 of the interposer 20 is in a range of 1/8 to 1/2 of the height H10 of the multilayer ceramic capacitor 10. The distance D22 between the outer edges along the length direction of the two connection electrodes 22 of the interposer 20 is equal to the length L10 of the multilayer ceramic capacitor 10, and the width W22 of each connection electrode 22 is equal to the width W10 of the multilayer ceramic capacitor 10. Equally, the length L22b of the effective connection region 22b of each connection electrode 22 is slightly shorter than the length L12 of each external electrode of the multilayer ceramic capacitor 10. Further, the length of the solder non-adhesion film 25 of the interposer 20 is long enough to close one end opening (upper end opening) of each of the inner holes 24a of the first and second through vias 24. The width of the adhesion film 25 is equal to the width W21 of the insulating substrate 21. Furthermore, the distance D23 between the outer edges along the length direction of the two mounting electrodes 23 of the interposer 20 is equal to the length L10 of the multilayer ceramic capacitor 10, and the width W23 of each mounting electrode 23 is equal to the width W10 of the multilayer ceramic capacitor 10. equal.

参考までに積層セラミックコンデンサ10が2125サイズの場合の具体値を例示すれば、積層セラミックコンデンサ10の長さL10は2.0mmで幅W10は1.25mmで高さH10は1.25mmであり、各外部電極12の長さL12は0.5mmである。一方、インターポーザ20の長さL20(=絶縁基板21の長さL21)は2.2mmで幅W20(=絶縁基板21の幅W21)は1.45mmで高さH20は0.45mmである。また、各接続電極22の長さL22は0.7mmで幅W22は1.25mmであり、距離D22は2.0mmであり、有効接続領域22bの長さL22bは0.4mmである。さらに、各実装電極23の長さL23は0.7mmで幅W23は1.25mmであり、距離D23は2.0mmである。さらに、ハンダ非付着膜25の長さ(D22−2×L22b)は1.2mmで幅は1.45mmである。   For example, if the specific value when the multilayer ceramic capacitor 10 is 2125 size is shown as an example, the length L10 of the multilayer ceramic capacitor 10 is 2.0 mm, the width W10 is 1.25 mm, and the height H10 is 1.25 mm. The length L12 of each external electrode 12 is 0.5 mm. On the other hand, the length L20 of the interposer 20 (= the length L21 of the insulating substrate 21) is 2.2 mm, the width W20 (= the width W21 of the insulating substrate 21) is 1.45 mm, and the height H20 is 0.45 mm. The length L22 of each connection electrode 22 is 0.7 mm, the width W22 is 1.25 mm, the distance D22 is 2.0 mm, and the length L22b of the effective connection region 22b is 0.4 mm. Further, the length L23 of each mounting electrode 23 is 0.7 mm, the width W23 is 1.25 mm, and the distance D23 is 2.0 mm. Further, the length (D22-2 × L22b) of the solder non-adhering film 25 is 1.2 mm and the width is 1.45 mm.

因みに、積層セラミックコンデンサ10の各外部電極12の厚さは0.01mmである。また、インターポーザ20の絶縁基板21の厚さは0.3mmであり、各接続電極22と各実装電極23と第1及び第2貫通ビア24の厚さは0.05mmであり、第1及び第2貫通ビア24の内孔24aの口径は0.25mmであり、ハンダ非付着膜25の各接続電極22の表面上の厚さは0.05mmである。   Incidentally, the thickness of each external electrode 12 of the multilayer ceramic capacitor 10 is 0.01 mm. Further, the thickness of the insulating substrate 21 of the interposer 20 is 0.3 mm, and the thicknesses of the connection electrodes 22, the mounting electrodes 23, and the first and second through vias 24 are 0.05 mm. The diameter of the inner hole 24a of the two through vias 24 is 0.25 mm, and the thickness on the surface of each connection electrode 22 of the solder non-adhering film 25 is 0.05 mm.

図1及び図2に示したインターポーザ付き積層セラミックコンデンサを作製するときには、インターポーザ20の各接続電極22の有効接続領域22bの表面にクリームハンダを塗布し、塗布されたクリームハンダに各外部電極12の回り込み部12bの一面が接するように積層セラミックコンデンサ10を搭載した後、リフローハンダ付け法等の熱処理によってクリームハンダを一旦溶融してから硬化させ、積層セラミックコンデンサ10の各外部電極12をハンダSOLを介してインターポーザ20の各接続電極22に接合する。   When the multilayer ceramic capacitor with an interposer shown in FIGS. 1 and 2 is manufactured, cream solder is applied to the surface of the effective connection region 22b of each connection electrode 22 of the interposer 20, and each external electrode 12 is applied to the applied cream solder. After mounting the multilayer ceramic capacitor 10 so that one surface of the wraparound portion 12b is in contact, the cream solder is once melted and cured by a heat treatment such as a reflow soldering method, and each external electrode 12 of the multilayer ceramic capacitor 10 is soldered with the solder SOL. To each connection electrode 22 of the interposer 20.

インターポーザ20の第1及び第2貫通ビア24の内孔24aそれぞれの一端開口(上端開口)はハンダ非付着膜25によって塞がれているため、前記搭載時にクリームハンダが各内孔24aに侵入することを防止して、該各内孔24aを空の状態のままとすることができる。しかも、ハンダ非付着膜25にハンダSOLが付着しない材料が用いられているため、前記熱処理時に溶融ハンダがハンダ非付着膜25の表面に濡れ上がることはない。   Since one end opening (upper end opening) of each of the inner holes 24a of the first and second through vias 24 of the interposer 20 is blocked by the solder non-adhering film 25, the cream solder enters the inner holes 24a at the time of mounting. This can be prevented, and each inner hole 24a can be left empty. In addition, since a material that does not adhere the solder SOL to the solder non-adhering film 25 is used, the molten solder does not wet the surface of the solder non-adhering film 25 during the heat treatment.

また、インターポーザ20の各接続電極22の有効接続領域22bの長さL22が積層セラミックコンデンサ10の各外部電極の長さL12よりも僅かに短いため、各有効接続領域22bの表面に塗布されるクリームハンダの量如何では、前記搭載時に各外部電極12の回り込み部12bの一面をハンダ非付着膜25の表面に当接させることによって、各外部電極12の回り込み部12bの一面と各接続電極22の有効接続領域22bの表面との隙間、即ち、各外部電極12の回り込み部12bの一面と各接続電極22の有効接続領域22bの表面との間に介在するハンダSOLの厚さを管理することもできる。   Further, since the length L22 of the effective connection region 22b of each connection electrode 22 of the interposer 20 is slightly shorter than the length L12 of each external electrode of the multilayer ceramic capacitor 10, the cream applied to the surface of each effective connection region 22b Depending on the amount of solder, one surface of the wrap portion 12b of each external electrode 12 is brought into contact with the surface of the solder non-adhering film 25 at the time of mounting, so that one surface of the wrap portion 12b of each external electrode 12 and each connection electrode 22 are connected. It is also possible to manage the gap between the surface of the effective connection region 22b, that is, the thickness of the solder SOL interposed between one surface of the wraparound portion 12b of each external electrode 12 and the surface of the effective connection region 22b of each connection electrode 22. it can.

図1及び図2に示したインターポーザ付き積層セラミックコンデンサを図8に示した回路基板30に実装するときには、基板本体31の表面に設けられた2つの導体パッド32それぞれの表面にクリームハンダを塗布し、塗布されたクリームハンダに各実装電極23の表面が接するようにインターポーザ付き積層セラミックコンデンサを搭載した後、リフローハンダ付け法等の熱処理によってクリームハンダを一旦溶融してから硬化させ、インターポーザ付き積層セラミックコンデンサの各実装電極23をハンダSOLを介して回路基板30の各導体パッド32に接合する。因みに、回路基板30の各導体パッド32は、各実装電極23よりも僅かに大きな略矩形状輪郭を有している。   When the multilayer ceramic capacitor with an interposer shown in FIGS. 1 and 2 is mounted on the circuit board 30 shown in FIG. 8, cream solder is applied to the surfaces of the two conductor pads 32 provided on the surface of the board body 31. After mounting the multilayer ceramic capacitor with an interposer so that the surface of each mounting electrode 23 is in contact with the applied cream solder, the cream solder is once melted and cured by a heat treatment such as a reflow soldering method, and the multilayer ceramic with an interposer Each mounting electrode 23 of the capacitor is bonded to each conductor pad 32 of the circuit board 30 via solder SOL. Incidentally, each conductor pad 32 of the circuit board 30 has a substantially rectangular outline slightly larger than each mounting electrode 23.

インターポーザ20の第1及び第2貫通ビア24の内孔24aそれぞれの他端開口(下端開口)が開放していて、しかも、各内孔24aは空の状態となっているため、前記搭載時にクリームハンダの余剰分を積極的に各内孔24aに侵入させることできる。つまり、前記搭載時にクリームハンダの余剰分が各実装電極23の表面よりも外側にはみ出ることを極力回避できるので、前記熱処理時に溶融ハンダが絶縁基板21の長さ方向の端面を経由して積層セラミックコンデンサ10の各外部電極12の端面に濡れ上がること、即ち、前記熱処理後に回路基板30の各導体パッド32から積層セラミックコンデンサ10の各外部電極12の端面に至るハンダSOLのフィレットが形成されることはない。   Since the other end opening (lower end opening) of each of the inner holes 24a of the first and second through vias 24 of the interposer 20 is open and each inner hole 24a is in an empty state, The surplus solder can be positively penetrated into each inner hole 24a. That is, it is possible to avoid as much as possible that the excess amount of cream solder protrudes outside the surface of each mounting electrode 23 during the mounting, so that the molten solder passes through the end face in the length direction of the insulating substrate 21 during the heat treatment. Wetting on the end face of each external electrode 12 of the capacitor 10, that is, a solder SOL fillet extending from each conductor pad 32 of the circuit board 30 to the end face of each external electrode 12 of the multilayer ceramic capacitor 10 after the heat treatment. There is no.

依って、インターポーザ付き積層セラミックコンデンサを回路基板30に実装した状態において積層セラミックコンデンサ10に電圧、特に交流電圧が印加されてコンデンサ本体11に電歪現象を生じても、該電歪現象に伴って回路基板30に生じ得る反り及びその復元を低減して音鳴きを確実に抑制することができる。   Therefore, even when a voltage, particularly an AC voltage is applied to the multilayer ceramic capacitor 10 in a state where the multilayer ceramic capacitor with an interposer is mounted on the circuit board 30, an electrostriction phenomenon occurs in the capacitor body 11. The warp that can occur in the circuit board 30 and its restoration can be reduced, and the noise can be reliably suppressed.

また、積層セラミックコンデンサ10の各外部電極12がハンダSOLを介してインターポーザ20の各接続電極22のみに接合され、且つ、インターポーザ20の各実装電極23がハンダSOLを介して回路基板30の各導体パッド32のみに接合された構造を実現できるため、コンデンサ本体11に電歪現象を生じたときに積層セラミックコンデンサ10から回路基板30に伝達される応力を積層セラミックコンデンサ10と回路基板30との間に介在するインターポーザ20によって緩和することができ、これにより前記音鳴きをより一層確実に抑制することができる。   In addition, each external electrode 12 of the multilayer ceramic capacitor 10 is bonded only to each connection electrode 22 of the interposer 20 via the solder SOL, and each mounting electrode 23 of the interposer 20 is connected to each conductor of the circuit board 30 via the solder SOL. Since the structure bonded only to the pad 32 can be realized, the stress transmitted from the multilayer ceramic capacitor 10 to the circuit board 30 when the electrostriction phenomenon occurs in the capacitor body 11 is caused between the multilayer ceramic capacitor 10 and the circuit board 30. Can be mitigated by the interposer 20 interposed between the two, thereby making it possible to more reliably suppress the noise.

さらに、インターポーザ20の第1及び第2貫通ビア24が絶縁基板21の長さ方向の中心寄りに位置していて、しかも、積層セラミックコンデンサ10の各外部電極12の長さ方向の中心よりも内側に在るため、コンデンサ本体11に電歪現象を生じたときに積層セラミックコンデンサ10からインターポーザ20に伝達される応力を絶縁基板31の各外部電極12が向き合う部分によって緩和することができ、これにより前記音鳴きをより一層確実に抑制することができる。   Furthermore, the first and second through vias 24 of the interposer 20 are located closer to the center in the length direction of the insulating substrate 21, and more inside than the center in the length direction of each external electrode 12 of the multilayer ceramic capacitor 10. Therefore, the stress transmitted from the multilayer ceramic capacitor 10 to the interposer 20 when an electrostriction phenomenon occurs in the capacitor body 11 can be relieved by the portions where the external electrodes 12 of the insulating substrate 31 face each other. The squealing can be more reliably suppressed.

《第2実施形態(図9〜図11)》
図11に示したインターポーザ付き積層セラミックコンデンサ(符号無し)は、図1及び図2に示したインターポーザ付き積層セラミックコンデンサと、
・インターポーザ20の代わりに、各接続電極22の長さL22を僅かに短くして距離D 22を積層セラミックコンデンサ10の長さL10よりも僅かに短くしたインターポー ザ20-1を用いた点(図9及び図10を参照)
において構成を異にする。
<< 2nd Embodiment (FIGS. 9-11) >>
The multilayer ceramic capacitor with an interposer (not shown) shown in FIG. 11 includes the multilayer ceramic capacitor with an interposer shown in FIG. 1 and FIG.
In place of the interposer 20, an interposer 20-1 in which the length L22 of each connection electrode 22 is slightly shortened and the distance D22 is slightly shorter than the length L10 of the multilayer ceramic capacitor 10 is used ( (See FIGS. 9 and 10)
The configuration is different.

参考までに積層セラミックコンデンサ10が2125サイズの場合の具体値を例示すれば、第1実施形態欄で例示した具体値とは、インターポーザ20-1の各接続電極22の長さL22が0.6mmであり、距離D22が1.8mmであり、有効接続領域22bの長さL22bが0.3mmである点で異なる。   For reference, if the specific value when the multilayer ceramic capacitor 10 is 2125 size is shown as an example, the specific value illustrated in the first embodiment column is 0.6 mm in length L22 of each connection electrode 22 of the interposer 20-1. The distance D22 is 1.8 mm, and the length L22b of the effective connection region 22b is 0.3 mm.

このインターポーザ付き積層セラミックコンデンサ、及び積層セラミックコンデンサ用インターポーザでも、第1実施形態欄で述べた作用及び効果と同様の作用及び効果を得ることができる。   This multilayer ceramic capacitor with an interposer and the multilayer ceramic capacitor interposer can also provide the same operations and effects as the operations and effects described in the first embodiment.

尚、各接続電極22と同様に、インターポーザ20-1の各実装電極23の長さL23を僅かに短くして距離D23を積層セラミックコンデンサ10の長さL10よりも僅かに短くしても良い。   As with each connection electrode 22, the length L23 of each mounting electrode 23 of the interposer 20-1 may be slightly shortened to make the distance D23 slightly shorter than the length L10 of the multilayer ceramic capacitor 10.

《第3実施形態(図12〜図14)》
図14に示したインターポーザ付き積層セラミックコンデンサ(符号無し)は、図1及び図2に示したインターポーザ付き積層セラミックコンデンサと、
・インターポーザ20の代わりに、各接続電極22の長さL22を僅かに長くして距離D 22を積層セラミックコンデンサ10の長さL10よりも僅かに長く、且つ、絶縁基板 21の長さL21と等しくしたインターポーザ20-2を用いた点(図12及び図13を 参照)
において構成を異にする。
<< 3rd Embodiment (FIGS. 12-14) >>
The multilayer ceramic capacitor with an interposer shown in FIG. 14 (without reference numeral) is a multilayer ceramic capacitor with an interposer shown in FIG. 1 and FIG.
Instead of the interposer 20, the length L22 of each connection electrode 22 is slightly increased so that the distance D22 is slightly longer than the length L10 of the multilayer ceramic capacitor 10 and equal to the length L21 of the insulating substrate 21. Points using the interposer 20-2 (see Fig. 12 and Fig. 13)
The configuration is different.

参考までに積層セラミックコンデンサ10が2125サイズの場合の具体値を例示すれば、第1実施形態欄で例示した具体値とは、インターポーザ20-2の各接続電極22の長さL22が0.8mmであり、距離D22が2.2mmであり、有効接続領域22bの長さL22bが0.5mmである点で異なる。   For reference, if the specific value when the multilayer ceramic capacitor 10 is 2125 size is shown as an example, the specific value exemplified in the first embodiment column is that the length L22 of each connection electrode 22 of the interposer 20-2 is 0.8 mm. The distance D22 is 2.2 mm, and the length L22b of the effective connection region 22b is 0.5 mm.

このインターポーザ付き積層セラミックコンデンサ、及び積層セラミックコンデンサ用インターポーザでも、第1実施形態欄で述べた作用及び効果と同様の作用及び効果を得ることができる。   This multilayer ceramic capacitor with an interposer and the multilayer ceramic capacitor interposer can also provide the same operations and effects as the operations and effects described in the first embodiment.

尚、各接続電極22と同様に、インターポーザ20-2の各実装電極23の長さL23を僅かに長くして距離D23を積層セラミックコンデンサ10の長さL10よりも僅かに長く、且つ、絶縁基板21の長さL21と等しくしても良い。   Similarly to each connection electrode 22, the length L23 of each mounting electrode 23 of the interposer 20-2 is slightly increased so that the distance D23 is slightly longer than the length L10 of the multilayer ceramic capacitor 10, and the insulating substrate. 21 may be equal to the length L21.

《第4実施形態(図15〜図18)》
図18に示したインターポーザ付き積層セラミックコンデンサ(符号無し)は、図1及び図2に示したインターポーザ付き積層セラミックコンデンサと、
・インターポーザ20の代わりに、各接続電極22から略半円状の張出部22aを除外し て各々の内側縁を直線状とし、且つ、各実装電極23から略半円状の張出部23aを除 外して各々の内側縁を直線状としたインターポーザ20-3を用いた点(図15〜図17 を参照)
において構成を異にする。
<< 4th Embodiment (FIGS. 15-18) >>
The multilayer ceramic capacitor with an interposer shown in FIG. 18 (without reference numeral) is a multilayer ceramic capacitor with an interposer shown in FIG. 1 and FIG.
Instead of the interposer 20, the substantially semicircular protruding portions 22a are excluded from the connection electrodes 22 to make each inner edge straight, and from the mounting electrodes 23, the approximately semicircular protruding portions 23a The point of using the interposer 20-3 with the inner edges straight, excluding the points (see FIGS. 15 to 17)
The configuration is different.

参考までに積層セラミックコンデンサ10が2125サイズの場合の具体値を例示すれば、インターポーザ20-3の各接続電極22の長さL22(0.7mm)と距離D22(2.0mm)と有効接続領域22bの長さL22b(0.4mm)、並びに、各実装電極23の長さL23(0.7mm)と距離D23(2.0mm)は、第1実施形態欄で例示した具体値と同じである。   For reference, specific values when the multilayer ceramic capacitor 10 is 2125 size are shown as an example. The length L22 (0.7 mm) and distance D22 (2.0 mm) of each connection electrode 22 of the interposer 20-3 and the effective connection region. The length L22b (0.4 mm) of 22b and the length L23 (0.7 mm) and the distance D23 (2.0 mm) of each mounting electrode 23 are the same as the specific values exemplified in the first embodiment column. .

このインターポーザ付き積層セラミックコンデンサ、及び積層セラミックコンデンサ用インターポーザでも、第1実施形態欄で述べた作用及び効果と同様の作用及び効果を得ることができる。   This multilayer ceramic capacitor with an interposer and the multilayer ceramic capacitor interposer can also provide the same operations and effects as the operations and effects described in the first embodiment.

《第5実施形態(図19〜図21)》
図21に示したインターポーザ付き積層セラミックコンデンサ(符号無し)は、図1及び図2に示したインターポーザ付き積層セラミックコンデンサと、
・インターポーザ20の代わりに、略矩形状の2つのハンダ非付着膜25を、第1及び第 2貫通ビア24の内孔24aそれぞれの一端開口(上端開口)を塞ぐように、各接続電 極22の表面の一部(内側部分)と絶縁基板21の厚さ方向の一面(上面)の一部(各 接続電極22に近い部分)に個別に形成したインターポーザ20-4を用いた点(図19 及び図20を参照)
において構成を異にする。
<< 5th Embodiment (FIGS. 19-21) >>
The multilayer ceramic capacitor with an interposer shown in FIG. 21 (without reference numeral) is a multilayer ceramic capacitor with an interposer shown in FIG. 1 and FIG.
Instead of the interposer 20, each of the connection electrodes 22 is configured so that the two solder non-adhering films 25 having a substantially rectangular shape close the one end openings (upper end openings) of the inner holes 24 a of the first and second through vias 24. 19 using the interposer 20-4 individually formed on a part of the surface (inner part) and part of one surface (upper surface) in the thickness direction of the insulating substrate 21 (part close to each connection electrode 22) (FIG. 19). And see FIG. 20)
The configuration is different.

参考までに積層セラミックコンデンサ10が2125サイズの場合の具体値を例示すれば、インターポーザ20-4の各接続電極22の長さL22(0.7mm)と距離D22(2.0mm)と有効接続領域22bの長さL22b(0.4mm)は、第1実施形態欄で例示した具体値と同じである。また、第1実施形態欄で例示した具体値とは、各ハンダ非付着膜25の長さが0.3mmである点で異なる。   For reference, if the specific value when the multilayer ceramic capacitor 10 is 2125 size is shown as an example, the length L22 (0.7 mm) and distance D22 (2.0 mm) of each connection electrode 22 of the interposer 20-4 and the effective connection area The length L22b (0.4 mm) of 22b is the same as the specific value exemplified in the first embodiment column. Moreover, it differs from the specific values exemplified in the first embodiment column in that the length of each solder non-adhesion film 25 is 0.3 mm.

このインターポーザ付き積層セラミックコンデンサ、及び積層セラミックコンデンサ用インターポーザでも、第1実施形態欄で述べた作用及び効果と同様の作用及び効果を得ることができる。   This multilayer ceramic capacitor with an interposer and the multilayer ceramic capacitor interposer can also provide the same operations and effects as the operations and effects described in the first embodiment.

《第6実施形態(図22〜図24)》
図24に示したインターポーザ付き積層セラミックコンデンサ(符号無し)は、図1及び図2に示したインターポーザ付き積層セラミックコンデンサと、
・積層セラミックコンデンサ10の代わりに、各外部電極12の長さL12をインターポ ーザ20の各接続電極22の有効接続領域22bの長さL22b(図5を参照)よりも 僅かに短くした積層セラミックコンデンサ10-1を用いた点(図22及び図23を参照 )
において、換言すれば、インターポーザ20の代わりに、各接続電極22の有効接続領域22bの長さL22bを積層セラミックコンデンサ10の各外部電極12の長さL12よりも僅かに長くしたインターポーザを用いた点において構成を異にする。
<< 6th Embodiment (FIGS. 22-24) >>
The multilayer ceramic capacitor with an interposer shown in FIG. 24 (without reference numeral) is a multilayer ceramic capacitor with an interposer shown in FIG. 1 and FIG.
A multilayer ceramic in which the length L12 of each external electrode 12 is slightly shorter than the length L22b (see FIG. 5) of the effective connection region 22b of each connection electrode 22 of the interposer 20, instead of the multilayer ceramic capacitor 10. Points using capacitor 10-1 (See Figs. 22 and 23)
In other words, instead of the interposer 20, an interposer in which the length L22b of the effective connection region 22b of each connection electrode 22 is slightly longer than the length L12 of each external electrode 12 of the multilayer ceramic capacitor 10 is used. The configuration is different.

参考までに積層セラミックコンデンサ10-1が2125サイズの場合の具体値を例示すれば、第1実施形態欄で例示した具体値とは、積層セラミックコンデンサ10-1の各外部電極12の長さL12が0.35mmである点で異なる。   For reference, if the specific value in the case where the multilayer ceramic capacitor 10-1 is 2125 is shown as an example, the specific value illustrated in the first embodiment column is the length L12 of each external electrode 12 of the multilayer ceramic capacitor 10-1. Is 0.35 mm.

このインターポーザ付き積層セラミックコンデンサ、及び積層セラミックコンデンサ用インターポーザでも、第1実施形態欄で述べた作用及び効果と同様の作用及び効果を得ることができる。   This multilayer ceramic capacitor with an interposer and the multilayer ceramic capacitor interposer can also provide the same operations and effects as the operations and effects described in the first embodiment.

《他の実施形態(図無し)》
前記第1〜第6実施形態では、インターポーザ20、20-1、20-2、20-3及び20-4として略矩形状のハンダ非付着膜25の幅を絶縁基板21の幅W21と等しくしたものを示したが、第1及び第2貫通ビア24の内孔24aそれぞれの一端開口(上端開口)を塞ぐことができれば、ハンダ非付着膜25の幅を絶縁基板21の幅W21よりも狭くしても、第1実施形態欄で述べた作用及び効果と同様の作用及び効果を得ることができる。
<< Other embodiments (not shown) >>
In the first to sixth embodiments, the width of the solder non-adhesion film 25 having a substantially rectangular shape as the interposers 20, 20-1, 20-2, 20-3 and 20-4 is made equal to the width W21 of the insulating substrate 21. Although shown, if the one end opening (upper end opening) of each of the inner holes 24a of the first and second through vias 24 can be closed, the width of the solder non-adhering film 25 is made smaller than the width W21 of the insulating substrate 21. However, the same operations and effects as those described in the first embodiment can be obtained.

また、前記第1〜第6実施形態では、インターポーザ20、20-1、20-2、20-3及び20-4としてハンダ非付着膜25の輪郭形を略矩形状としたものを示したが、第1及び第2貫通ビア24の内孔24aそれぞれの一端開口(上端開口)を塞ぐことができれば、ハンダ非付着膜25の輪郭形を略矩形状以外の多角形状や円形状や楕円形状等としても、第1実施形態欄で述べた作用及び効果と同様の作用及び効果を得ることができる。   Further, in the first to sixth embodiments, the interposers 20, 20-1, 20-2, 20-3, and 20-4 have been shown in which the outline of the solder non-adhering film 25 is substantially rectangular. If the one end opening (upper end opening) of each of the inner holes 24a of the first and second through vias 24 can be closed, the contour shape of the solder non-adhering film 25 may be a polygonal shape other than a substantially rectangular shape, a circular shape, an elliptical shape, or the like. However, the same operations and effects as those described in the first embodiment can be obtained.

さらに、前記第1〜第6実施形態では、インターポーザ20、20-1、20-2、20-3及び20-4として各接続電極22の幅W22を積層セラミックコンデンサ10の幅W10と等しくしたものを示したが、各接続電極22の幅W22を積層セラミックコンデンサ10の幅W10よりも僅かに狭くしても、或いは、僅かに広くしても、第1実施形態欄で述べた作用及び効果と同様の作用及び効果を得ることができる。   Furthermore, in the first to sixth embodiments, the interposers 20, 20-1, 20-2, 20-3 and 20-4 have the width W22 of each connection electrode 22 equal to the width W10 of the multilayer ceramic capacitor 10. However, even if the width W22 of each connection electrode 22 is slightly narrower or slightly wider than the width W10 of the multilayer ceramic capacitor 10, the operations and effects described in the first embodiment column can be obtained. Similar actions and effects can be obtained.

さらに、前記第1〜第6実施形態では、インターポーザ20、20-1、20-2、20-3及び20-4として略円筒状の第1及び第2導体ビア24を設けたものを示したが、該第1及び第2導体ビア24の3次元形状を略円筒状以外の略楕円筒状や略多角筒状等としても、第1実施形態欄で述べた作用及び効果と同様の作用及び効果を得ることができる。   Furthermore, in the first to sixth embodiments, the interposers 20, 20-1, 20-2, 20-3 and 20-4 are provided with the first and second conductive vias 24 having substantially cylindrical shapes. However, even if the three-dimensional shape of the first and second conductor vias 24 is a substantially elliptical cylinder shape or a substantially polygonal cylinder shape other than a substantially cylindrical shape, the same actions and effects as those described in the first embodiment column and An effect can be obtained.

さらに、前記第1〜第6実施形態では、インターポーザ20、20-1、20-2、20-3及び20-4として第1及び第2導体ビア24を1つずつ設けたものを示したが、第1及び第2導体ビア24の少なくとも一方を2つ以上としても、第1実施形態欄で述べた作用及び効果と同様の作用及び効果を得ることができる。   Further, in the first to sixth embodiments, the interposers 20, 20-1, 20-2, 20-3 and 20-4 are provided with the first and second conductor vias 24 one by one. Even if at least one of the first and second conductor vias 24 is two or more, the same operation and effect as those described in the first embodiment can be obtained.

10,10-1…積層セラミックコンデンサ、11…コンデンサ本体、11a…容量形成部、11a1…内部電極層、11a2…誘電体層、12…外部電極、12a…端面部、12b…回り込み部、20,20-1,20-2,20-3,20-4…インターポーザ、21…絶縁基板、22…接続電極、23…実装電極、24…第1及び第2貫通ビア、24a…第1及び第2貫通ビアの内孔、25…ハンダ非付着膜、SOL…ハンダ。   DESCRIPTION OF SYMBOLS 10,10-1 ... Multilayer ceramic capacitor, 11 ... Capacitor main body, 11a ... Capacity | capacitance formation part, 11a1 ... Internal electrode layer, 11a2 ... Dielectric layer, 12 ... External electrode, 12a ... End surface part, 12b ... Rounding part, 20, 20-1, 20-2, 20-3, 20-4 ... interposer, 21 ... insulating substrate, 22 ... connection electrode, 23 ... mounting electrode, 24 ... first and second through vias, 24a ... first and second Inner hole of through-via, 25 ... solder non-adhering film, SOL ... solder.

Claims (10)

積層セラミックコンデンサにインターポーザが取り付けられたインターポーザ付き積層セラミックコンデンサであって、
(1)前記積層セラミックコンデンサは長さ>幅及び高さの関係を満足する略直方体状を成していて、複数の内部電極層が誘電体層を介して積層された構造の容量形成部を有する略直方体状のコンデンサ本体と、前記コンデンサ本体の長さ方向の端面それぞれを覆う略矩形状の端面部及び該各端面部と連続して前記コンデンサ本体の4側面の一部を覆う略4角筒状の回り込み部を有し、且つ、前記複数の内部電極層の一部が一方に接続され残部が他方に接続された2つの外部電極を備えており、
(2)前記インターポーザは長さ>幅及び高さの関係を満足する略直方体状を成していて、略直方体状の絶縁基板と、前記絶縁基板の厚さ方向の一面に前記2つの外部電極の回り込み部の一面それぞれと向き合うように設けられた略矩形状の2つの接続電極と、前記絶縁基板の厚さ方向の他面に前記2つの接続電極それぞれと向き合うように設けられた略矩形状の2つの実装電極と、前記絶縁基板の長さ方向の端面よりも内側において前記2つの接続電極の一方と前記2つの実装電極の一方を接続するように、且つ、内孔の一端が前記2つの接続電極の一方の表面で開口し他端が前記2つの実装電極の一方の表面で開口するように設けられた筒状の第1貫通ビアと、前記絶縁基板の長さ方向の端面よりも内側において前記2つの接続電極の他方と前記2つの実装電極の他方を接続するように、且つ、内孔の一端が前記2つの接続電極の他方の表面で開口し他端が前記2つの実装電極の他方の表面で開口するように設けられた筒状の第2貫通ビアと、前記第1貫通ビアの内孔の一端開口と前記第2貫通ビアの内孔の一端開口を塞ぐように設けられたハンダ非付着膜を備えており、
(3)前記インターポーザの前記2つの接続電極の表面それぞれには、前記積層セラミックコンデンサの前記2つの外部電極の回り込み部の一面それぞれがハンダを介して接合されており、
(4)前記インターポーザの前記第1貫通ビアの内孔の他端開口から前記ハンダ非付着膜に至る領域と前記第2貫通ビアの内孔の他端開口から前記ハンダ非付着膜に至る領域は何れも空の状態となっている、
ことを特徴とするインターポーザ付き積層セラミックコンデンサ。
A multilayer ceramic capacitor with an interposer in which an interposer is attached to the multilayer ceramic capacitor,
(1) The multilayer ceramic capacitor has a substantially rectangular parallelepiped shape satisfying a relationship of length> width and height, and a capacitance forming portion having a structure in which a plurality of internal electrode layers are stacked via a dielectric layer. A substantially rectangular parallelepiped capacitor body, a substantially rectangular end surface portion covering each end surface in the length direction of the capacitor body, and a substantially four corners covering a part of the four side surfaces of the capacitor body continuously with the end surface portions. It has a cylindrical wraparound part, and includes two external electrodes in which a part of the plurality of internal electrode layers is connected to one side and the remaining part is connected to the other,
(2) The interposer has a substantially rectangular parallelepiped shape that satisfies the relationship of length> width and height, and the two external electrodes on one surface in the thickness direction of the insulating substrate. Two substantially rectangular connection electrodes provided to face one surface of each wraparound portion, and a substantially rectangular shape provided to face each of the two connection electrodes on the other surface in the thickness direction of the insulating substrate The two mounting electrodes are connected to one of the two mounting electrodes and one of the two mounting electrodes on the inner side of the end surface in the length direction of the insulating substrate, and one end of the inner hole is connected to the 2 A cylindrical first through via provided on one surface of one of the connection electrodes and the other end opening on one surface of the two mounting electrodes; and a lengthwise end surface of the insulating substrate In addition to the two connection electrodes on the inside So that one end of an inner hole is opened on the other surface of the two connection electrodes and the other end is opened on the other surface of the two mounting electrodes. A cylindrical second through-via provided, a solder non-adhesion film provided to close one end opening of the inner hole of the first through via and one end opening of the inner hole of the second through via; ,
(3) Each surface of the two external electrodes of the multilayer ceramic capacitor is joined to each of the surfaces of the two connection electrodes of the interposer via solder,
(4) A region from the other end opening of the inner hole of the first through via of the interposer to the solder non-adhesion film and a region from the other end opening of the inner hole of the second through via to the solder non-adhesion film Both are empty.
A multilayer ceramic capacitor with an interposer.
前記インターポーザの前記ハンダ非付着膜は、前記第1貫通ビアの内孔の一端開口と前記第2貫通ビアの内孔の一端開口を塞ぐように少なくとも前記2つの接続電極の表面それぞれの一部に形成されており、
前記ハンダは前記2つの接続電極の表面それぞれの残部と前記積層セラミックコンデンサの前記2つの外部電極の回り込み部の一面それぞれとの間に介在している、
ことを特徴とする請求項1に記載のインターポーザ付き積層セラミックコンデンサ。
The solder non-adhesion film of the interposer is formed on at least a part of each of the surfaces of the two connection electrodes so as to block one end opening of the inner hole of the first through via and one end opening of the inner hole of the second through via. Formed,
The solder is interposed between the remaining portions of the surfaces of the two connection electrodes and one surface of the wraparound portion of the two external electrodes of the multilayer ceramic capacitor,
The multilayer ceramic capacitor with an interposer according to claim 1.
前記インターポーザの前記ハンダ非付着膜は、前記2つの接続電極の表面それぞれの一部に加えて前記絶縁基板の厚さ方向の一面の一部に連続的に形成されている、
ことを特徴とする請求項2に記載のインターポーザ付き積層セラミックコンデンサ。
The solder non-adhesion film of the interposer is continuously formed on a part of one surface in the thickness direction of the insulating substrate in addition to a part of each of the surfaces of the two connection electrodes.
The multilayer ceramic capacitor with an interposer according to claim 2.
前記インターポーザの前記2つの接続電極の長さ方向に沿う外側縁間の距離をD22とし、前記インターポーザの前記絶縁基板の長さをL21としたとき、両者はD22≦L21の関係を満足している、
ことを特徴とする請求項1〜3の何れか1項に記載のインターポーザ付き積層セラミックコンデンサ。
When the distance between the outer edges along the length direction of the two connection electrodes of the interposer is D22 and the length of the insulating substrate of the interposer is L21, the two satisfy the relationship of D22 ≦ L21. ,
The multilayer ceramic capacitor with an interposer according to any one of claims 1 to 3.
前記インターポーザの前記2つの接続電極の長さ方向に沿う外側縁間の距離をD22とし、前記積層セラミックコンデンサの長さをL10としたとき、両者はD22≦L10の関係を満足している、
ことを特徴とする請求項1〜4の何れか1項に記載のインターポーザ付き積層セラミックコンデンサ。
When the distance between the outer edges along the length direction of the two connection electrodes of the interposer is D22 and the length of the multilayer ceramic capacitor is L10, both satisfy the relationship of D22 ≦ L10.
The multilayer ceramic capacitor with an interposer according to any one of claims 1 to 4, wherein the multilayer ceramic capacitor has an interposer.
積層セラミックコンデンサを回路基板等に実装する際に用いられる積層セラミックコンデンサ用インターポーザであって、
(1)前記積層セラミックコンデンサは長さ>幅及び高さの関係を満足する略直方体状を成していて、複数の内部電極層が誘電体層を介して積層された構造の容量形成部を有する略直方体状のコンデンサ本体と、前記コンデンサ本体の長さ方向の端面それぞれを覆う略矩形状の端面部及び該各端面部と連続して前記コンデンサ本体の4側面の一部を覆う略4角筒状の回り込み部を有し、且つ、前記複数の内部電極層の一部が一方に接続され残部が他方に接続された2つの外部電極を備えており、
(2)前記インターポーザは長さ>幅及び高さの関係を満足する略直方体状を成していて、略直方体状の絶縁基板と、前記絶縁基板の厚さ方向の一面に前記2つの外部電極の回り込み部の一面それぞれと向き合うように設けられた略矩形状の2つの接続電極と、前記絶縁基板の厚さ方向の他面に前記2つの接続電極それぞれと向き合うように設けられた略矩形状の2つの実装電極と、前記絶縁基板の長さ方向の端面よりも内側において前記2つの接続電極の一方と前記2つの実装電極の一方を接続するように、且つ、内孔の一端が前記2つの接続電極の一方の表面で開口し他端が前記2つの実装電極の一方の表面で開口するように設けられた筒状の第1貫通ビアと、前記絶縁基板の長さ方向の端面よりも内側において前記2つの接続電極の他方と前記2つの実装電極の他方を接続するように、且つ、内孔の一端が前記2つの接続電極の他方の表面で開口し他端が前記2つの実装電極の他方の表面で開口するように設けられた筒状の第2貫通ビアと、前記第1貫通ビアの内孔の一端開口と前記第2貫通ビアの内孔の一端開口を塞ぐように設けられたハンダ非付着膜を備えており、
(3)前記インターポーザの前記2つの接続電極の表面それぞれは、前記積層セラミックコンデンサの前記2つの外部電極の回り込み部の一面それぞれをハンダを介して接合するためのものであり、
(4)前記インターポーザの前記第1貫通ビアの内孔の他端開口から前記ハンダ非付着膜に至る領域と前記第2貫通ビアの内孔の他端開口から前記ハンダ非付着膜に至る領域は何れも空の状態となっている、
ことを特徴とする積層セラミックコンデンサ用インターポーザ。
An interposer for a multilayer ceramic capacitor used for mounting a multilayer ceramic capacitor on a circuit board or the like,
(1) The multilayer ceramic capacitor has a substantially rectangular parallelepiped shape satisfying a relationship of length> width and height, and a capacitance forming portion having a structure in which a plurality of internal electrode layers are stacked via a dielectric layer. A substantially rectangular parallelepiped capacitor body, a substantially rectangular end surface portion covering each end surface in the length direction of the capacitor body, and a substantially four corners covering a part of the four side surfaces of the capacitor body continuously with the end surface portions. It has a cylindrical wraparound part, and includes two external electrodes in which a part of the plurality of internal electrode layers is connected to one side and the remaining part is connected to the other,
(2) The interposer has a substantially rectangular parallelepiped shape that satisfies the relationship of length> width and height, and the two external electrodes on one surface in the thickness direction of the insulating substrate. Two substantially rectangular connection electrodes provided to face one surface of each wraparound portion, and a substantially rectangular shape provided to face each of the two connection electrodes on the other surface in the thickness direction of the insulating substrate The two mounting electrodes are connected to one of the two mounting electrodes and one of the two mounting electrodes on the inner side of the end surface in the length direction of the insulating substrate, and one end of the inner hole is connected to the 2 A cylindrical first through via provided on one surface of one of the connection electrodes and the other end opening on one surface of the two mounting electrodes; and a lengthwise end surface of the insulating substrate In addition to the two connection electrodes on the inside So that one end of an inner hole is opened on the other surface of the two connection electrodes and the other end is opened on the other surface of the two mounting electrodes. A cylindrical second through-via provided, a solder non-adhesion film provided to close one end opening of the inner hole of the first through via and one end opening of the inner hole of the second through via; ,
(3) Each of the surfaces of the two connection electrodes of the interposer is for joining one surface of the wraparound portion of the two external electrodes of the multilayer ceramic capacitor via solder,
(4) A region from the other end opening of the inner hole of the first through via of the interposer to the solder non-adhesion film and a region from the other end opening of the inner hole of the second through via to the solder non-adhesion film Both are empty.
An interposer for multilayer ceramic capacitors.
前記インターポーザの前記ハンダ非付着膜は、前記第1貫通ビアの内孔の一端開口と前記第2貫通ビアの内孔の一端開口を塞ぐように少なくとも前記2つの接続電極の表面それぞれの一部に形成されている、
ことを特徴とする請求項6に記載の積層セラミックコンデンサ用インターポーザ。
The solder non-adhesion film of the interposer is formed on at least a part of each of the surfaces of the two connection electrodes so as to block one end opening of the inner hole of the first through via and one end opening of the inner hole of the second through via. Formed,
The interposer for a multilayer ceramic capacitor according to claim 6.
前記インターポーザの前記ハンダ非付着膜は、前記2つの接続電極の表面それぞれの一部に加えて前記絶縁基板の厚さ方向の一面の一部に連続的に形成されている、
ことを特徴とする請求項7に記載の積層セラミックコンデンサ用インターポーザ。
The solder non-adhesion film of the interposer is continuously formed on a part of one surface in the thickness direction of the insulating substrate in addition to a part of each of the surfaces of the two connection electrodes.
The interposer for multilayer ceramic capacitors according to claim 7.
前記インターポーザの前記2つの接続電極の長さ方向に沿う外側縁間の距離をD22とし、前記インターポーザの前記絶縁基板の長さをL21としたとき、両者はD22≦L21の関係を満足している、
ことを特徴とする請求項6〜8の何れか1項に記載の積層セラミックコンデンサ用インターポーザ。
When the distance between the outer edges along the length direction of the two connection electrodes of the interposer is D22 and the length of the insulating substrate of the interposer is L21, the two satisfy the relationship of D22 ≦ L21. ,
The multilayer ceramic capacitor interposer according to any one of claims 6 to 8, wherein the interposer is a multilayer ceramic capacitor.
前記インターポーザの前記2つの接続電極の長さ方向に沿う外側縁間の距離をD22とし、前記積層セラミックコンデンサの長さをL10としたとき、両者はD22≦L10の関係を満足している、
ことを特徴とする請求項6〜9の何れか1項に記載の積層セラミックコンデンサ用インターポーザ。
When the distance between the outer edges along the length direction of the two connection electrodes of the interposer is D22 and the length of the multilayer ceramic capacitor is L10, both satisfy the relationship of D22 ≦ L10.
The interposer for multilayer ceramic capacitors according to any one of claims 6 to 9.
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