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JP2015008191A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

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Publication number
JP2015008191A
JP2015008191A JP2013132311A JP2013132311A JP2015008191A JP 2015008191 A JP2015008191 A JP 2015008191A JP 2013132311 A JP2013132311 A JP 2013132311A JP 2013132311 A JP2013132311 A JP 2013132311A JP 2015008191 A JP2015008191 A JP 2015008191A
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Prior art keywords
semiconductor wafer
adhesive tape
semiconductor
annular
semiconductor device
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Japanese (ja)
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田中 陽子
Yoko Tanaka
陽子 田中
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Fuji Electric Co Ltd
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Fuji Electric Co Ltd
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Priority to JP2013132311A priority Critical patent/JP2015008191A/en
Priority to CN201410261080.6A priority patent/CN104253018B/en
Publication of JP2015008191A publication Critical patent/JP2015008191A/en
Withdrawn legal-status Critical Current

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    • H10P54/00
    • H10P72/7402
    • H10P72/7416

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  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Dicing (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device capable of reducing man hours when an annular reinforcement part of a semiconductor wafer is removed, and of reducing cracks and falls of broken pieces.SOLUTION: Provided is a method of manufacturing a semiconductor device of dividing a semiconductor wafer into a plurality of semiconductor devices. The semiconductor wafer has: a recessed part provided on a rear face of the semiconductor wafer; an annular reinforcement part provided at an outer peripheral part; a semiconductor element region provided at the recessed part and in which a plurality of semiconductor devices are formed; and an excessive region consisting of the recessed part other than the semiconductor element region. The method of manufacturing a semiconductor device includes: an attachment step 101 for attaching a dicing frame onto a rear face of the semiconductor wafer via an adhesive tape; a cutting step 102 of placing on a stage having a convex part that is smaller than the recessed part on the rear face of the semiconductor wafer attached to the dicing frame, and individualizing the semiconductor wafer into a plurality of semiconductor devices by cutting a semiconductor element formation region from a front surface side; an adhesive force reduction step 103 for reducing an adhesive force of the adhesive tape; a peeling step 104 of peeling off the annular reinforcement part from the adhesive tape; and a removal step 105 of removing the annular reinforcement part and the excessive region.

Description

本発明は、裏面に円形凹部を有する半導体ウエハを用いた半導体装置の製造方法に関する。   The present invention relates to a method for manufacturing a semiconductor device using a semiconductor wafer having a circular recess on a back surface.

近年、IGBT(Insulated Gate Bipolar Transistor)は、高性能化および低コスト化の必要から半導体ウエハの薄化が進められている。このため、例えば、半導体ウエハの厚さを50μm〜100μm程度、またはそれ以下の厚さまで薄化する必要がある。   In recent years, IGBTs (Insulated Gate Bipolar Transistors) are being thinned due to the need for high performance and low cost. For this reason, for example, it is necessary to reduce the thickness of the semiconductor wafer to a thickness of about 50 μm to 100 μm or less.

半導体ウエハの薄化は、半導体ウエハの表面に素子構造を形成した後、所定の厚さになるまで半導体ウエハの裏面の研削を行う。
しかしながら、薄化した半導体ウエハは、機械的な強度が低下するため、割れや欠けなどが発生しやすくなり、搬送等の取り扱いが困難となる。
In thinning a semiconductor wafer, after the element structure is formed on the surface of the semiconductor wafer, the back surface of the semiconductor wafer is ground until a predetermined thickness is obtained.
However, since the mechanical strength of the thinned semiconductor wafer decreases, cracks and chips are easily generated, and handling such as conveyance becomes difficult.

よって、半導体ウエハの表面に素子構造を形成した後、半導体ウエハ裏面から半導体ウエハの中央部にある素子構造部を研削し、半導体ウエハの外周部を所定の幅で残して補強部とすることで、半導体ウエハの機械的な強度が向上し、半導体ウエハの割れや欠けを低減することができる。   Therefore, after forming the element structure on the surface of the semiconductor wafer, the element structure part in the central part of the semiconductor wafer is ground from the back side of the semiconductor wafer, and the outer peripheral part of the semiconductor wafer is left with a predetermined width as a reinforcing part. As a result, the mechanical strength of the semiconductor wafer is improved, and cracking and chipping of the semiconductor wafer can be reduced.

そして、半導体ウエハの補強部を除去した後に、半導体ウエハを素子構造ごとにダイシングして個々の半導体装置に切断を行う。
図18に半導体ウエハの中央部を薄化して、外周部を補強部とした半導体ウエハを示す。図18(a)は、半導体ウエハの平面図であり、図18(b)は、図18(a)のA−A’断面図である。
Then, after removing the reinforcing portion of the semiconductor wafer, the semiconductor wafer is diced for each element structure and cut into individual semiconductor devices.
FIG. 18 shows a semiconductor wafer in which the central portion of the semiconductor wafer is thinned and the outer peripheral portion is a reinforcing portion. FIG. 18A is a plan view of the semiconductor wafer, and FIG. 18B is a cross-sectional view taken along line AA ′ of FIG.

図18(b)より、半導体ウエハ1の裏面には、外周部にウエハの厚さが厚い環状補強部2と中央部にウエハの厚さが薄い裏面凹部3が形成されている。
図18(a)より、裏面凹部3には、半導体装置4が形成されている素子形成領域6があり、素子形成領域6には、素子形成領域6を切断して半導体装置4に個片化するためのチップ分割ライン7が形成されている。また、裏面凹部3の素子形成領域6以外の領域は、余剰領域5となる。
18B, on the back surface of the semiconductor wafer 1, an annular reinforcing portion 2 having a thick wafer thickness is formed on the outer peripheral portion, and a back recess portion 3 having a small wafer thickness is formed on the central portion.
As shown in FIG. 18A, the back surface recess 3 has an element formation region 6 in which the semiconductor device 4 is formed, and the element formation region 6 is cut into pieces into the semiconductor device 4 by cutting the element formation region 6. A chip dividing line 7 is formed for this purpose. Further, the region other than the element formation region 6 of the back surface recess 3 is a surplus region 5.

半導体ウエハの外周に形成した環状補強部を除去する方法としては、ダイシングフレームに紫外線硬化型の粘着テープを介して、裏面に円形凹部を有する半導体ウエハを貼付けてチャックテーブルに載置し、半導体ウエハ外周の環状補強部を切断した後、粘着テープの環状補強部に貼りついている部分の粘着テープの粘着力を弱め、爪を粘着テープと環状補強部の境界に差し込み環状補強部を除去している。(例えば、特許文献1)
ダイシングフレームに紫外線硬化型の粘着テープを介して、裏面凹部を有する半導体ウエハを貼付けて裏面凹部に嵌めあうチャックステージに載置し、ウエハのストリートに沿って切断することでウエハのデバイス領域は切断され、環状補強部は環状の状態が維持され、粘着テープの環状補強部に貼りついている部分の粘着テープの粘着力を弱めて環状補強部を除去している。(例えば、特許文献2)
また、ダイシングフレームに紫外線硬化型の粘着テープを介して、裏面凹部を有する半導体ウエハを貼付け、ウエハのデバイス領域は個片化され、環状補強部は個片化されない状態となるようにダイシングを行い、環状補強部の粘着テープの粘着力を弱めてダイシングフレームを裏面凹部に嵌めあうステージに載置し、ステージを上下に移動させて環状補強部を粘着テープから除去している。(例えば、特許文献3)
As a method of removing the annular reinforcing portion formed on the outer periphery of the semiconductor wafer, a semiconductor wafer having a circular concave portion on the back surface is attached to the dicing frame via an ultraviolet curable adhesive tape and placed on the chuck table. After cutting the outer annular reinforcing part, the adhesive strength of the adhesive tape of the part attached to the annular reinforcing part of the adhesive tape is weakened, and the nail is inserted into the boundary between the adhesive tape and the annular reinforcing part to remove the annular reinforcing part. . (For example, Patent Document 1)
The wafer wafer device area is cut by affixing a semiconductor wafer with a backside recess to the dicing frame via a UV curable adhesive tape and placing it on a chuck stage that fits into the backside recess and cutting along the wafer street. The annular reinforcing portion is maintained in an annular state, and the annular reinforcing portion is removed by weakening the adhesive force of the adhesive tape in the portion attached to the annular reinforcing portion of the adhesive tape. (For example, Patent Document 2)
In addition, a semiconductor wafer having a back surface concave portion is attached to the dicing frame via an ultraviolet curable adhesive tape, and dicing is performed so that the device region of the wafer is separated into pieces and the annular reinforcing portion is not separated into pieces. The adhesive strength of the adhesive tape of the annular reinforcement portion is weakened and the dicing frame is placed on the stage that fits into the recess on the back surface, and the stage is moved up and down to remove the annular reinforcement portion from the adhesive tape. (For example, Patent Document 3)

特開2011−61137号公報JP 2011-61137 A 特開2010−62375号公報JP 2010-62375 A 特開2011−210858号公報JP 2011-210858 A

しかしながら、半導体ウエハ外周の環状補強部を予め切断して除去する場合は、環状補強部を切断するための工数がかかる。
また、環状補強部を除去工程において、半導体ウエハと粘着テープの境界に爪などを差し込んで除去する場合、爪が半導体ウエハ外周の環状補強部の側面に触れるおそれがあり、このとき環状補強部と素子領域とが接触し、欠けが発生する可能性がある。さらに、環状補強部を持ち上げる際に欠けが発生した箇所から破片が落下することが懸念される。
However, when the annular reinforcing portion on the outer periphery of the semiconductor wafer is cut and removed in advance, man-hours for cutting the annular reinforcing portion are required.
Further, when removing the annular reinforcing portion by inserting a nail or the like at the boundary between the semiconductor wafer and the adhesive tape in the removal step, the nail may touch the side surface of the annular reinforcing portion on the outer periphery of the semiconductor wafer. There is a possibility of chipping due to contact with the element region. Furthermore, there is a concern that debris may fall from a location where chipping occurs when lifting the annular reinforcing portion.

本発明は、半導体ウエハ外周の環状補強部の除去の工数を少なく、欠けやこれによる破片の落下を低減する半導体装置の製造方法を提供する。   The present invention provides a method for manufacturing a semiconductor device that reduces the number of steps for removing an annular reinforcing portion on the outer periphery of a semiconductor wafer and reduces chipping and debris falling.

半導体ウエハ裏面の中央部の厚さを外周部よりも薄くした凹部と、外周部に環状補強部を備え、凹部に複数の半導体装置が形成された半導体素子領域と、半導体素子領域以外の凹部からなる余剰領域を有する半導体ウエハを前記複数の半導体装置に分割する半導体装置の製造方法において、前記半導体ウエハの裏面に粘着テープを介してダイシングフレームに装着する装着工程と、前記ダイシングフレームに装着された前記半導体ウエハの裏面の凹部よりも小さい凸部を有するステージに載置し、前記半導体ウエハを表面側から前記半導体素子形成領域を切断して前記複数の半導体装置に個片化する切断工程と、粘着テープの粘着力を低下させる粘着力低下工程と、粘着テープから環状補強部を剥離する剥離工程と、余剰領域を除去する除去工程を含むことを特徴とする半導体装置の製造方法を提供する。   From a recess in which the thickness of the central portion of the backside of the semiconductor wafer is made thinner than that of the outer periphery, an annular reinforcing portion in the outer periphery, a plurality of semiconductor devices formed in the recess, and a recess other than the semiconductor element region In a manufacturing method of a semiconductor device in which a semiconductor wafer having a surplus region is divided into a plurality of semiconductor devices, a mounting step of mounting the semiconductor wafer on a dicing frame via an adhesive tape on the back surface of the semiconductor wafer, and mounting on the dicing frame A cutting step of placing the semiconductor wafer on a stage having a convex portion smaller than the concave portion on the back surface of the semiconductor wafer, cutting the semiconductor element forming region from the front surface side, and dividing the semiconductor wafer into pieces. Adhesive strength reduction process to reduce the adhesive strength of the adhesive tape, peeling process to peel the annular reinforcing part from the adhesive tape, and removal to remove the excess area To provide a method of manufacturing a semiconductor device which comprises an extent.

本発明では、半導体ウエハの環状の補強部を除去する際の工数を低減し、欠けや破片の落下を低減する半導体装置の製造方法を提供する。   The present invention provides a method for manufacturing a semiconductor device that reduces the man-hour when removing the annular reinforcing portion of the semiconductor wafer, and reduces chipping and falling of fragments.

本発明実施の形態を示すフロー図である。It is a flowchart which shows embodiment of this invention. 本発明実施の形態のダイシングフレーム装着工程を示す断面図である。It is sectional drawing which shows the dicing frame mounting | wearing process of embodiment of this invention. 本発明実施の形態のダイシングフレームに装着された半導体ウエハを示す平面図とB−B’断面図である。FIG. 4 is a plan view and a B-B ′ sectional view showing a semiconductor wafer mounted on a dicing frame according to an embodiment of the present invention. 本発明実施の形態の切断工程を示す断面図である。It is sectional drawing which shows the cutting process of embodiment of this invention. 本発明実施の形態の切断工程後の半導体ウエハを示す平面図である。It is a top view which shows the semiconductor wafer after the cutting process of embodiment of this invention. 本発明実施の形態の粘着力低下工程を示す断面図である。It is sectional drawing which shows the adhesive force fall process of embodiment of this invention. 本発明実施の形態の剥離工程を示す断面図である。It is sectional drawing which shows the peeling process of embodiment of this invention. 本発明実施の形態の環状剥離治具を示す斜視図である。It is a perspective view which shows the cyclic | annular peeling jig | tool of embodiment of this invention. 本発明実施の形態の環状剥離治具を示す平面図とC−C’断面図である。It is the top view which shows the cyclic | annular peeling jig | tool of this invention embodiment, and C-C 'sectional drawing. 本発明実施の形態の除去工程を示す断面図である。It is sectional drawing which shows the removal process of embodiment of this invention. 本発明実施の形態の除去治具を示す斜視図である。It is a perspective view which shows the removal jig | tool of embodiment of this invention. 本発明実施の形態の拡張工程を示す断面図である。It is sectional drawing which shows the expansion process of embodiment of this invention. 本発明実施の形態の拡張工程を示す断面図である。It is sectional drawing which shows the expansion process of embodiment of this invention. 本発明実施の形態の拡張工程を示す断面図である。It is sectional drawing which shows the expansion process of embodiment of this invention. 本発明実施の形態の拡張工程を示す断面図である。It is sectional drawing which shows the expansion process of embodiment of this invention. 本発明実施の形態拡張工程後の半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device after the embodiment expansion process of this invention. 本発明実施の形態の剥離工程と除去工程の変形例を示す断面図である。It is sectional drawing which shows the modification of the peeling process of the embodiment of this invention, and a removal process. 半導体ウエハの平面図とA−A’断面図である。It is the top view and A-A 'cross section figure of a semiconductor wafer.

以下に添付図面を参照してこの発明にかかる半導体装置の製造方法の好適な実施の形態を詳細に説明する。
(実施の形態)
図18に中央部を薄化して外周部を環状補強部2とした半導体ウエハ1を示す。図18(a)は、半導体ウエハ1の平面図であり、図18(b)は図18(a)のA−A’断面図である。
Exemplary embodiments of a method for manufacturing a semiconductor device according to the present invention will be described below in detail with reference to the accompanying drawings.
(Embodiment)
FIG. 18 shows a semiconductor wafer 1 in which the central portion is thinned and the outer peripheral portion is an annular reinforcing portion 2. FIG. 18A is a plan view of the semiconductor wafer 1, and FIG. 18B is a cross-sectional view taken along the line AA ′ of FIG.

図18(b)より、半導体ウエハ1の裏面には、外周部にウエハの厚さが厚い環状補強部2と中央部にウエハの厚さが薄い裏面凹部3が形成されている。
図18(a)より、裏面凹部3には、半導体装置4が形成された素子形成領域6があり、素子形成領域6には、素子形成領域6を切断して半導体装置4に個片化するためのチップ分割ライン7が形成されている。また、裏面凹部3の素子形成領域6以外の領域は、余剰領域5となる。
18B, on the back surface of the semiconductor wafer 1, an annular reinforcing portion 2 having a thick wafer thickness is formed on the outer peripheral portion, and a back recess portion 3 having a small wafer thickness is formed on the central portion.
As shown in FIG. 18A, the back surface recess 3 has an element formation region 6 in which the semiconductor device 4 is formed. The element formation region 6 is cut into pieces into the semiconductor device 4 by cutting the element formation region 6. Chip division lines 7 are formed for this purpose. Further, the region other than the element formation region 6 of the back surface recess 3 is a surplus region 5.

環状補強部2の厚さは、例えば、100〜725μmであり、裏面凹部3の厚さは、例えは、50〜400μmである。
なお、裏面凹部3は半導体ウエハ1の裏面から所定の厚さに研削を行って形成し、環状補強部2は半導体ウエハ1の外周から、例えば、1.0〜5.0mm程度の幅で研削を行わない。
The thickness of the annular reinforcing portion 2 is, for example, 100 to 725 μm, and the thickness of the back surface concave portion 3 is, for example, 50 to 400 μm.
The back surface recess 3 is formed by grinding to a predetermined thickness from the back surface of the semiconductor wafer 1, and the annular reinforcing portion 2 is ground from the outer periphery of the semiconductor wafer 1 to a width of about 1.0 to 5.0 mm, for example. Do not do.

図1に本発明のフロー図を示す。裏面を研削して裏面凹部3と環状補強部2が形成された図18に示す半導体ウエハ1は、ダイシングフレーム装着工程101において後述する図2に示すように粘着テープ13を介してダイシングフレーム14に装着される。ダイシングフレーム14に装着された半導体ウエハ1は、切断工程102において後述する図4に示すように半導体ウエハ1の素子形成領域6を半導体装置4に個片化するチップ分割ライン7に沿って切断し、素子形成領域6を半導体装置4に個片化される。粘着テープ粘着力低下工程103は、後述する図6に示すように切断された半導体ウエハ1裏面の全面の粘着テープ13の粘着力を低下させ、剥離工程104において後述する図7に示すように粘着テープ13から半導体ウエハ1の環状補強部2が剥離される。さらに、除去工程105において後述する図10に示すように環状補強部2と余剰領域5とを除去をする。また、個片化された半導体装置4は、拡張工程106において後述する図12のように隣り合う半導体装置4の間隔をひろげられる。   FIG. 1 shows a flowchart of the present invention. The semiconductor wafer 1 shown in FIG. 18 in which the back surface recess 3 and the annular reinforcing portion 2 are formed by grinding the back surface is applied to the dicing frame 14 via the adhesive tape 13 as shown in FIG. Installed. The semiconductor wafer 1 mounted on the dicing frame 14 is cut along a chip dividing line 7 that separates the element formation region 6 of the semiconductor wafer 1 into the semiconductor device 4 as shown in FIG. The element formation region 6 is separated into semiconductor devices 4. The adhesive tape adhesive strength reduction step 103 reduces the adhesive strength of the adhesive tape 13 on the entire back surface of the semiconductor wafer 1 that has been cut as shown in FIG. 6 to be described later, and in the peeling step 104, as shown in FIG. The annular reinforcing portion 2 of the semiconductor wafer 1 is peeled off from the tape 13. Further, in the removing step 105, the annular reinforcing portion 2 and the surplus region 5 are removed as shown in FIG. In addition, the separated semiconductor devices 4 can increase the interval between adjacent semiconductor devices 4 as shown in FIG.

図2に本発明のダイシングフレーム装着工程101の断面図を示す。
図2(a)に示すように、上室43と下室44を備えた真空のチャンバ40内に粘着テープ13の貼り付け面である半導体ウエハ1の裏面凹部3を上にして、ゴムシート42上に設置された半導体ウエハ1の外周部のみが接触する形状の座繰ステージ41に載置する。載置した半導体ウエハ1の上部に、粘着テープ13を貼り付けたダイシングフレーム14を設置し、上室43と下室33ともに真空引き45を行う。このとき、座繰ステージ41を用いることで半導体ウエハ1の素子形成領域6に接触することなく保持することができ、半導体ウエハ1表面に傷が入るのを防ぐことができる。
FIG. 2 shows a cross-sectional view of the dicing frame mounting step 101 of the present invention.
As shown in FIG. 2A, the rubber sheet 42 is placed with the back surface recess 3 of the semiconductor wafer 1 on which the adhesive tape 13 is attached in the vacuum chamber 40 having the upper chamber 43 and the lower chamber 44. It is mounted on a countersink stage 41 having a shape in which only the outer peripheral portion of the semiconductor wafer 1 placed thereon is in contact. A dicing frame 14 with an adhesive tape 13 attached is placed on the top of the semiconductor wafer 1 placed, and the upper chamber 43 and the lower chamber 33 are evacuated 45. At this time, by using the counter-rotating stage 41, the semiconductor wafer 1 can be held without contacting the element forming region 6, and the surface of the semiconductor wafer 1 can be prevented from being damaged.

次に図2(b)に示すように、下室44を大気開放46して、ゴムシート42を上室43側へ押し上げ、粘着テープ13と半導体ウエハ1の環状補強部2を密着させる。
次に図2(c)に示すように、上室43を大気開放46して、粘着テープ13を半導体ウエハ1の裏面凹部3に密着させる。上室43と下室44の差圧によって、粘着テープ13は、半導体ウエハ1の裏面に貼り付けられる。
Next, as shown in FIG. 2B, the lower chamber 44 is opened to the atmosphere 46, and the rubber sheet 42 is pushed up to the upper chamber 43 side, so that the adhesive tape 13 and the annular reinforcing portion 2 of the semiconductor wafer 1 are brought into close contact with each other.
Next, as shown in FIG. 2C, the upper chamber 43 is opened to the atmosphere 46, and the adhesive tape 13 is brought into close contact with the back surface recess 3 of the semiconductor wafer 1. The adhesive tape 13 is attached to the back surface of the semiconductor wafer 1 by the differential pressure between the upper chamber 43 and the lower chamber 44.

図3に本発明のダイシングフレーム装着工程101において、半導体ウエハ1が粘着テープ13を介してダイシングフレーム14に装着されている状態を示す。図3(a)は、平面図であり、図3(b)は、B−B’断面図である。   FIG. 3 shows a state in which the semiconductor wafer 1 is mounted on the dicing frame 14 via the adhesive tape 13 in the dicing frame mounting step 101 of the present invention. 3A is a plan view, and FIG. 3B is a B-B ′ cross-sectional view.

粘着テープ13は、裏面凹部3に沿って貼り付けられているため、後述する図4の切断工程において使用する切削水が半導体ウエハ1と粘着テープ13との間へ浸入して粘着テープ13の剥れることを抑制し、粘着テープ13が剥れはがれることで半導体ウエハ1の固定が不安定になるために発生する欠けを抑制することができる。このとき、粘着テープ13は、後に粘着力を低下させることができる紫外線硬化型の粘着剤が塗布されているものが望ましい。   Since the adhesive tape 13 is affixed along the back surface recess 3, the cutting water used in the cutting process of FIG. 4 to be described later enters between the semiconductor wafer 1 and the adhesive tape 13 and peels off the adhesive tape 13. It is possible to suppress chipping that occurs because the fixing of the semiconductor wafer 1 becomes unstable due to peeling of the adhesive tape 13. At this time, it is desirable that the adhesive tape 13 is coated with an ultraviolet curable adhesive capable of reducing the adhesive force later.

図4に本発明の切断工程102の断面図を示す。ダイシングフレーム装着工程101でダイシングフレーム14に装着された半導体ウエハ1は、半導体ウエハ裏面の裏面凹部3に嵌めあう凸形状を持つポーラスチャック(図示しない)を備えた凸型ステージ11に載置され、真空吸着によって固定される。   FIG. 4 shows a cross-sectional view of the cutting process 102 of the present invention. The semiconductor wafer 1 mounted on the dicing frame 14 in the dicing frame mounting step 101 is placed on a convex stage 11 including a porous chuck (not shown) having a convex shape that fits into the back surface recess 3 on the back surface of the semiconductor wafer. Fixed by vacuum suction.

凸型ステージ11に載置された半導体ウエハ1は、切削ブレード20によってチップ分割ライン7に沿って切断される。このとき、半導体ウエハ1は、厚さの薄い裏面凹部3が切断され、環状補強部2は余剰領域5とつながった状態となっている。   The semiconductor wafer 1 placed on the convex stage 11 is cut along the chip dividing line 7 by the cutting blade 20. At this time, the semiconductor wafer 1 is in a state where the thin back surface recess 3 is cut and the annular reinforcing portion 2 is connected to the surplus region 5.

よって、環状補強部2と余剰領域5が1つにつながっていることで、除去工程105で環状補強部2と余剰領域5とを少ない工数で除去することができる。なお、切断にはレーザ光を用いても良い。   Therefore, since the annular reinforcing portion 2 and the surplus region 5 are connected to one, the annular reinforcing portion 2 and the surplus region 5 can be removed with a small number of man-hours in the removing step 105. Note that laser light may be used for cutting.

図5に本発明の切断工程102後の半導体ウエハ1を示す。切断工程102後の半導体ウエハ1は、切断工程102で素子形成領域6が個片化された半導体装置4と、環状補強部2および余剰領域5とに分けられる。   FIG. 5 shows the semiconductor wafer 1 after the cutting step 102 of the present invention. The semiconductor wafer 1 after the cutting step 102 is divided into a semiconductor device 4 in which the element forming regions 6 are separated into pieces in the cutting step 102, an annular reinforcing portion 2, and a surplus region 5.

図6に粘着力低下工程103の断面図を示す。紫外線硬化型の粘着剤を塗布した粘着テープ13に紫外線発生ランプ21を用いて、半導体ウエハ1の裏面から紫外線を照射して半導体ウエハ1と粘着テープ13が接している面の粘着力を低下させる。   FIG. 6 shows a cross-sectional view of the adhesive strength reducing step 103. An ultraviolet ray generation lamp 21 is used for the adhesive tape 13 coated with an ultraviolet curable adhesive to irradiate ultraviolet rays from the back surface of the semiconductor wafer 1 to reduce the adhesive force of the surface where the semiconductor wafer 1 and the adhesive tape 13 are in contact. .

半導体ウエハ1全面に紫外線照射して粘着力を低下させることで、半導体ウエハ1の環状補強部2と余剰領域5を除去しやすくするとともに、環状補強部2と余剰領域5を除去後、個片化した半導体装置4をピックアップする際に、再度紫外線照射を行う必要がなくなり工程を削減することができる。   By irradiating the entire surface of the semiconductor wafer 1 with ultraviolet rays to reduce the adhesive force, the annular reinforcing portion 2 and the surplus region 5 of the semiconductor wafer 1 are easily removed, and after the annular reinforcing portion 2 and the surplus region 5 are removed, the individual pieces are removed. When picking up the converted semiconductor device 4, it is not necessary to irradiate ultraviolet rays again, and the number of processes can be reduced.

図7に剥離工程104の断面図を示す。図7(a)には、切断工程102で切断されたダイシングフレーム14に粘着テープ13を介して貼り付けられた半導体ウエハ1を載置して固定した状態の断面図を示し、図7(b)には、環状剥離治具31を用いて半導体ウエハ1の環状補強部2を粘着テープ13から剥離した状態の断面図を示す。   FIG. 7 shows a cross-sectional view of the peeling process 104. FIG. 7A shows a cross-sectional view of a state in which the semiconductor wafer 1 attached via the adhesive tape 13 is placed and fixed to the dicing frame 14 cut in the cutting step 102, and FIG. ) Shows a cross-sectional view of the state where the annular reinforcing portion 2 of the semiconductor wafer 1 is peeled from the adhesive tape 13 using the annular peeling jig 31.

図7(a)に示すように、ダイシングフレーム14に粘着テープ13を介して貼り付けられた半導体ウエハ1が、半導体ウエハ1の裏面凹部3と嵌め合うか、半導体ウエハの素子形成領域6が載置できる大きさの保持ステージ12に載置され、ダイシングフレーム14は、ダイシングフレームクランプ治具15によって固定される。   As shown in FIG. 7A, the semiconductor wafer 1 attached to the dicing frame 14 via the adhesive tape 13 fits with the back surface recess 3 of the semiconductor wafer 1 or the element formation region 6 of the semiconductor wafer is mounted. The dicing frame 14 is mounted on a holding stage 12 having a size that can be placed, and the dicing frame 14 is fixed by a dicing frame clamp jig 15.

また、保持ステージ12にはポーラスチャックを有しており(図示しない)、吸着によって半導体ウエハ1の裏面凹部3を固定している。
さらに、図7(b)に示すように、半導体ウエハ1の外径より大きく、ダイシングフレーム14の内径より小さい直径の環状剥離治具31を半導体ウエハ1の中心と環状剥離治具31の中心を一致させて半導体ウエハ1の表面側から下降させて粘着テープ13に押し下げる。環状剥離治具31を下降させて粘着テープ13に押し下げることで半導体ウエハ1の環状補強部2から粘着テープ13が剥離する。
Further, the holding stage 12 has a porous chuck (not shown), and the back surface recess 3 of the semiconductor wafer 1 is fixed by suction.
Further, as shown in FIG. 7B, an annular peeling jig 31 having a diameter larger than the outer diameter of the semiconductor wafer 1 and smaller than the inner diameter of the dicing frame 14 is placed between the center of the semiconductor wafer 1 and the center of the annular peeling jig 31. The same is lowered from the surface side of the semiconductor wafer 1 and pushed down to the adhesive tape 13. The pressure-sensitive adhesive tape 13 is peeled from the ring-shaped reinforcing portion 2 of the semiconductor wafer 1 by lowering the ring-shaped peeling jig 31 and pushing it down to the pressure-sensitive adhesive tape 13.

保持ステージ12とダイシングフレーム14が水平に載置されている場合は、保持ステージ12に対して垂直方向から、環状剥離治具31を下降させて粘着テープ13を押し下げる。   When the holding stage 12 and the dicing frame 14 are placed horizontally, the annular peeling jig 31 is lowered from the direction perpendicular to the holding stage 12 to push down the adhesive tape 13.

このとき、保持ステージ12上に載置されている余剰領域5は、粘着テープ13から剥離されず、粘着テープ13に接した状態である。
よって、環状補強部2を粘着テープ13から剥離しても、環状補強部2とつながっている余剰領域5は粘着テープ13から剥離されていないため、余剰領域5が素子形成領域6に接触することがなく、欠けの発生を防ぐことができる。
At this time, the surplus area 5 placed on the holding stage 12 is not peeled off from the adhesive tape 13 and is in contact with the adhesive tape 13.
Therefore, even if the annular reinforcing portion 2 is peeled off from the adhesive tape 13, the surplus region 5 connected to the annular reinforcing portion 2 is not peeled off from the adhesive tape 13, so that the surplus region 5 contacts the element forming region 6. And the occurrence of chipping can be prevented.

図8に環状剥離治具31の形状を示す。図8(a)は、円形のリング状プレート52に環状に複数のピン51を取り付けた環状剥離治具31である。環状に並んだ複数のピン51を粘着テープ13の上面から下降させ、粘着テープ13から環状補強部2を剥離する。ピン51は等間隔に配置することで環状補強部2を傾けることなく剥離することができる。なお、ピン51の間隔は狭く本数が多くなるほど粘着テープ13を下側に押し下げる力を分散することができ、環状補強部2にかかる応力を緩和することができる。応力を緩和することで半導体ウエハ1の余剰領域5と素子形成領域6の破損を防ぐことができる。   FIG. 8 shows the shape of the annular peeling jig 31. FIG. 8A shows an annular peeling jig 31 in which a plurality of pins 51 are annularly attached to a circular ring-shaped plate 52. The plurality of pins 51 arranged in a ring shape are lowered from the upper surface of the adhesive tape 13, and the annular reinforcing portion 2 is peeled from the adhesive tape 13. By arranging the pins 51 at equal intervals, the annular reinforcing portion 2 can be peeled off without being inclined. In addition, the space | interval of the pin 51 is so narrow that the force which pushes down the adhesive tape 13 below can be disperse | distributed, and the stress concerning the cyclic | annular reinforcement part 2 can be relieve | moderated. By relieving the stress, it is possible to prevent the excess region 5 and the element formation region 6 of the semiconductor wafer 1 from being damaged.

ピン51の形状は、ピンの角部に粘着テープ13を押し下げる力が集中して粘着テープ13が破れるのを防ぐため、円柱状であることが望ましい。
図8(b)は、円形のリング状プレート52に環状に複数のピン51に円形のリング状プレート52をさら取り付け、粘着テープ13に下降させる面の形状を円形のリング状にした環状剥離治具31である。粘着テープ13に接する面を円形のリング状とすることで、環状剥離治具31を下降させた際の粘着テープ13を下側に押し下げる力を分散することができ、環状補強部2にかかる応力を緩和することができる。
The shape of the pin 51 is desirably a columnar shape in order to prevent the adhesive tape 13 from being broken due to the concentration of the pressing force of the adhesive tape 13 at the corners of the pin.
FIG. 8B shows an annular exfoliation treatment in which a circular ring plate 52 is further attached to a plurality of pins 51 in a circular shape on a circular ring plate 52, and the surface of the adhesive tape 13 is lowered into a circular ring shape. Tool 31. By making the surface in contact with the adhesive tape 13 into a circular ring shape, it is possible to disperse the force of pushing down the adhesive tape 13 when the annular peeling jig 31 is lowered, and the stress applied to the annular reinforcing portion 2 Can be relaxed.

図8(c)に示す環状剥離治具31は円筒形をしており、粘着テープ13面に下降させる面は図8(b)と同様に円形のリング状となっている。このため、環状剥離治具31を下降させた際に粘着テープ13を下側に押し下げる力を分散することができ、環状補強部2にかかる応力を緩和することができる。   The annular peeling jig 31 shown in FIG. 8C has a cylindrical shape, and the surface to be lowered to the surface of the adhesive tape 13 has a circular ring shape as in FIG. For this reason, when the annular peeling jig 31 is lowered, the force for pressing the adhesive tape 13 downward can be dispersed, and the stress applied to the annular reinforcing portion 2 can be relaxed.

図8(b)、(c)のように粘着テープ13を下側に押し下げる力を分散することで環状補強部2かかる応力を緩和することができ、環状補強部2が傾くことなく剥離することが可能となり、半導体ウエハ1の素子形成領域6と余剰領域5との接触による破損を防ぐことができるため、環状剥離治具31の形状は粘着テープ13下降する面は、図8(b)、(c)に示すような円形のリング形状であることが望ましい。   As shown in FIGS. 8B and 8C, the stress applied to the annular reinforcing portion 2 can be reduced by dispersing the force that pushes the adhesive tape 13 downward, and the annular reinforcing portion 2 is peeled off without being inclined. Since the damage due to the contact between the element formation region 6 and the surplus region 5 of the semiconductor wafer 1 can be prevented, the shape of the annular peeling jig 31 is as shown in FIG. A circular ring shape as shown in FIG.

なお、環状剥離治具31の材質は金属や樹脂であることが望ましい。また、図8(b)、(c)の場合、粘着テープ13に接する面は半導体ウエハ1の外形と同じまたは近似した形状であれば良い。   The material of the annular peeling jig 31 is preferably metal or resin. In the case of FIGS. 8B and 8C, the surface in contact with the adhesive tape 13 may be the same as or similar to the outer shape of the semiconductor wafer 1.

図9に図8(c)の環状剥離治具31の端部の形状を示す。図9(a)は、環状剥離治具31の外形を示し、図9(b)〜(d)に、C−C’断面図を示す。
粘着テープ13に接する面は図9(b)に示すように角状や、図9(c)に示すように角部を面取りした形状や、図9(d)に示すように角部をR形状としても良い。図9(c)、図9(d)に示すように、面取りした形状や、R形状とすることで環状剥離治具31を下降させ押し下げる際に粘着テープ13の破れを防止することができる。
FIG. 9 shows the shape of the end of the annular peeling jig 31 shown in FIG. Fig.9 (a) shows the external shape of the cyclic | annular peeling jig | tool 31, and CC 'sectional drawing is shown to FIG.9 (b)-(d).
The surface in contact with the adhesive tape 13 has a square shape as shown in FIG. 9 (b), a shape with chamfered corner portions as shown in FIG. 9 (c), and a corner portion with a rounded corner shape as shown in FIG. 9 (d). It is good also as a shape. As shown in FIG. 9C and FIG. 9D, the adhesive tape 13 can be prevented from being broken when the annular peeling jig 31 is lowered and pushed down by using a chamfered shape or an R shape.

なお、図9(b)〜(d)に示す端部の形状は、図8(a)、図8(b)に示す粘着テープ13と接する面のピン51、および円形のリング状プレート52の形状に用いても同様の効果を得ることができる。   The end portions shown in FIGS. 9B to 9D have the shapes of the pin 51 on the surface in contact with the adhesive tape 13 shown in FIGS. 8A and 8B, and the circular ring-shaped plate 52. Even if it is used for the shape, the same effect can be obtained.

図10に除去工程105の断面図を、図11に除去治具32の斜視図を示す。図11に示すように、除去治具32は円筒形であり、吸着部33を備えている。吸着部33の外径は、半導体ウエハ1の環状補強部2を吸着するため、環状補強部2の外径と同等かそれ以下の外径であるのが好ましい。吸着部33の内径は素子形成領域6よりも大きいことが好ましい。   FIG. 10 is a sectional view of the removing step 105, and FIG. 11 is a perspective view of the removing jig 32. As shown in FIG. As shown in FIG. 11, the removal jig 32 has a cylindrical shape and includes a suction portion 33. The outer diameter of the adsorbing portion 33 is preferably equal to or smaller than the outer diameter of the annular reinforcing portion 2 in order to adsorb the annular reinforcing portion 2 of the semiconductor wafer 1. The inner diameter of the suction portion 33 is preferably larger than the element formation region 6.

図10(a)に示すように、環状補強部2から粘着テープ13を剥離後、環状剥離治具31を下降させた状態で、除去治具32を下降させ除去治具32の吸着部33により環状補強部2を吸着する。このとき、保持ステージ12は素子形成領域6の裏面を保持ステージ12によって吸着している。   As shown in FIG. 10A, after peeling the adhesive tape 13 from the annular reinforcing portion 2, the removal jig 32 is lowered while the annular peeling jig 31 is lowered, and the suction portion 33 of the removal jig 32 is used. The annular reinforcing portion 2 is adsorbed. At this time, the holding stage 12 sucks the back surface of the element forming region 6 by the holding stage 12.

図10(b)に示すように、除去治具32に上昇させることにより、半導体ウエハ1の余剰領域5が持ち上げられ除去される。環状補強部2は、環状剥離治具31によって粘着テープ13より剥離されており、余剰領域5は、図6に示したように紫外線発生ランプ21で紫外線を照射して粘着テープ13の粘着力を低下させてあるため、環状補強部2と余剰領域5を容易に取り除くことができる。   As shown in FIG. 10B, the surplus region 5 of the semiconductor wafer 1 is lifted and removed by raising the removal jig 32. The annular reinforcing portion 2 is peeled off from the adhesive tape 13 by an annular peeling jig 31, and the surplus region 5 is irradiated with ultraviolet rays by an ultraviolet ray generating lamp 21 as shown in FIG. Since it is lowered, the annular reinforcing portion 2 and the excess region 5 can be easily removed.

また、除去治具32は吸着部33によって吸着して環状補強部2と余剰領域5を除去するため、半導体ウエハ1の余剰領域5と素子形成領域6とが接触することなく除去することができる。   Further, since the removal jig 32 is adsorbed by the adsorbing portion 33 and removes the annular reinforcing portion 2 and the surplus region 5, the surplus region 5 of the semiconductor wafer 1 and the element forming region 6 can be removed without contact. .

余剰領域5を素子形成領域6から接触させることなく除去できることで、余剰領域5と素子領域6の接触による欠けや、その破片の落下、およびパーティクルの落下を抑制することができる。   Since the surplus region 5 can be removed without being brought into contact with the element forming region 6, chipping due to contact between the surplus region 5 and the element region 6, dropping of fragments thereof, and dropping of particles can be suppressed.

図12に拡張工程106の断面図を示す。図12は除去工程105で環状補強領域2と余剰領域5を除去した後に、保持ステージ12の真空吸着を解除し、粘着テープ13に環状剥離治具31を押し付けた状態で、保持ステージ12を、例えば5〜30mm程度上昇させ、切断工程102で個片化された素子形成領域6の半導体装置4間の間隔を拡張している。   FIG. 12 shows a cross-sectional view of the expansion process 106. FIG. 12 shows that after removing the annular reinforcing region 2 and the surplus region 5 in the removing step 105, the vacuum suction of the holding stage 12 is released, and the holding stage 12 is pressed with the annular peeling jig 31 pressed against the adhesive tape 13. For example, the distance between the semiconductor devices 4 in the element forming region 6 separated in the cutting step 102 is increased by raising the height by about 5 to 30 mm.

半導体装置4間を拡張して一定の間隔にひろげることで、半導体装置4を粘着テープ13から取りはずす際に、半導体装置4の接触を抑制し、半導体装置4の欠けを防ぐことができる。   By expanding the space between the semiconductor devices 4 and spreading them at a fixed interval, when the semiconductor device 4 is removed from the adhesive tape 13, contact of the semiconductor device 4 can be suppressed and chipping of the semiconductor device 4 can be prevented.

図13と図14にグリップリングを用いた拡張工程106の断面図を示す。図13に示すように、半導体装置4間の間隔を拡張させる際に、粘着テープ13に環状剥離治具31を押し付けた状態でグリップリング22a、22bを用いて粘着テープ13をグリップしても良い。グリップリング22aは、保持ステージ12と共に上昇し、粘着テープ13上面に固定されたグリップリング22bにはめ込まれる。このとき、図14に示すように、グリップリング22bを粘着テープ13上面から下降させても良い。グリップリングを用いて半導体装置4の間隔を拡張させることで半導体装置4の間隔を拡張した状態を保持することができる。   13 and 14 are sectional views of the expansion process 106 using the grip ring. As shown in FIG. 13, when expanding the interval between the semiconductor devices 4, the adhesive tape 13 may be gripped using the grip rings 22 a and 22 b in a state where the annular peeling jig 31 is pressed against the adhesive tape 13. . The grip ring 22 a rises together with the holding stage 12 and is fitted into the grip ring 22 b fixed to the upper surface of the adhesive tape 13. At this time, as shown in FIG. 14, the grip ring 22 b may be lowered from the upper surface of the adhesive tape 13. By extending the distance between the semiconductor devices 4 using the grip ring, the state in which the distance between the semiconductor devices 4 is expanded can be maintained.

また、図12〜図14のように環状剥離治具31を使用せず、図15に示す拡張工程106の断面図のように、保持ステージ12を5〜50mm上昇させることによって、半導体装置4の間隔をひろげることができる。半導体装置4間を拡張して一定の間隔にひろげることで、半導体装置4を粘着テープ13から取りはずす際に、半導体装置4の接触を抑制し、半導体装置4の欠け欠けを防ぐことができる。このとき、図13、図14と同様にグリップリング22a、22bを用いても良い。   Also, the annular peeling jig 31 is not used as shown in FIGS. 12 to 14, and the holding stage 12 is raised by 5 to 50 mm as shown in the sectional view of the expansion process 106 shown in FIG. You can widen the interval. By expanding the space between the semiconductor devices 4 and spreading them at a fixed interval, when the semiconductor device 4 is removed from the adhesive tape 13, the contact of the semiconductor device 4 can be suppressed and chipping of the semiconductor device 4 can be prevented. At this time, the grip rings 22a and 22b may be used as in FIGS.

図16に、グリップリング22a、22b外周の粘着テープ13をカットし、ダイシングフレーム14と切り離した状態を示す。ダイシングフレーム14と切り離すことで、グリップリング22a、22bによって半導体装置4の間隔がひろげられたまま保持することができる。   FIG. 16 shows a state in which the adhesive tape 13 on the outer periphery of the grip rings 22 a and 22 b is cut and separated from the dicing frame 14. By separating from the dicing frame 14, the gap between the semiconductor devices 4 can be held with the grip rings 22a and 22b widened.

隣り合う間隔をひろげられた半導体装置4は、真空ピンセット、または吸着コレットなどの吸着治具34を用いて、粘着テープ13から取りはずされる。粘着テープ13から取りはずされた半導体装置4は、チップトレイ、またはテーピング装置のリールに収納されたり、ダイボンディング装置などのチップボンド装置に移送され、所定の処理が行われる。
(実施の形態の変形例)
図17は、本発明実施の形態の変形例の断面図である。図17(a)に剥離工程104前に除去治具32を環状補強部2に吸着させた状態を示し、図17(b)に除去治具32を環状補強部2に吸着させた状態で環状剥離治具32を用いて環状補強部2から粘着テープ13を剥離させた状態を示す。
The adjacent semiconductor devices 4 are removed from the adhesive tape 13 using a suction jig 34 such as vacuum tweezers or suction collet. The semiconductor device 4 removed from the adhesive tape 13 is stored in a chip tray or a reel of a taping device, or transferred to a chip bonding device such as a die bonding device, and subjected to predetermined processing.
(Modification of the embodiment)
FIG. 17 is a cross-sectional view of a modification of the embodiment of the present invention. 17A shows a state in which the removal jig 32 is adsorbed to the annular reinforcing portion 2 before the peeling step 104, and FIG. 17B shows an annular state in which the removal jig 32 is adsorbed to the annular reinforcing portion 2. The state which peeled the adhesive tape 13 from the cyclic | annular reinforcement part 2 using the peeling jig | tool 32 is shown.

本発明の実施の形態では、剥離工程104で環状剥離治具31を半導体ウエハ1上面から粘着テープ13に向かって押し込み、環状補強部2と粘着テープ13を剥離した後、除去工程105で吸着部33を備えた除去治具32を環状補強部2に吸着させたが、図17(a)に示すように、剥離工程104の前に除去治具32を環状補強部2に吸着させた後に図17(b)に示すように、環状剥離治具31を半導体ウエハ1上面から粘着テープ13に向かって押し込み、環状補強部2と粘着テープ13とを剥離させても同様の効果を得ることができる。   In the embodiment of the present invention, the annular peeling jig 31 is pushed from the upper surface of the semiconductor wafer 1 toward the adhesive tape 13 in the peeling step 104, and the annular reinforcing portion 2 and the adhesive tape 13 are peeled off. Although the removal jig 32 provided with 33 is adsorbed to the annular reinforcing portion 2, as shown in FIG. 17A, the removal jig 32 is adsorbed to the annular reinforcing portion 2 before the peeling step 104. As shown in FIG. 17B, the same effect can be obtained even if the annular peeling jig 31 is pushed from the upper surface of the semiconductor wafer 1 toward the adhesive tape 13 and the annular reinforcing portion 2 and the adhesive tape 13 are peeled off. .

1 半導体ウエハ
2 環状補強部
3 裏面凹部
4 半導体装置
5 余剰領域
6 素子形成領域
7 チップ分割ライン
11 凸型ステージ
12 保持ステージ
13 粘着テープ
14 ダイシングフレーム
15 ダイシングフレームクランプ治具
20 切削ブレード
21 紫外線発生ランプ
22a、22b グリップリング
31 環状剥離治具
32 除去治具
33 吸着部
34 吸着治具
40 真空チャンバ
41 座繰ステージ
42 ゴムシート
43 上室
44 下室
45 真空引き
46 大気開放
51 ピン
52 リング状プレート
101 ダイシングフレーム装着工程
102 切断工程
103 粘着テープ粘着力低下工程
104 剥離工程
105 除去工程
106 拡張工程
DESCRIPTION OF SYMBOLS 1 Semiconductor wafer 2 Annular reinforcement part 3 Back surface recessed part 4 Semiconductor device 5 Surplus area 6 Element formation area 7 Chip dividing line 11 Convex stage 12 Holding stage 13 Adhesive tape 14 Dicing frame 15 Dicing frame clamp jig 20 Cutting blade 21 Ultraviolet ray generation lamp 22a, 22b Grip ring 31 Annular peeling jig 32 Removal jig 33 Adsorption part 34 Adsorption jig 40 Vacuum chamber 41 Counter feed stage 42 Rubber sheet 43 Upper chamber 44 Lower chamber 45 Vacuum drawing 46 Atmospheric release 51 Pin 52 Ring-shaped plate 101 Dicing frame mounting process 102 Cutting process 103 Adhesive tape adhesive power reduction process 104 Peeling process 105 Removal process 106 Expansion process

Claims (6)

半導体ウエハの裏面の中央部の厚さを外周端部よりも薄くして形成された凹部と、
前記凹部の外周に形成された環状補強部と
前記凹部に分割ラインにより区画形成された複数の半導体素子領域と、
前記複数の半導体素子領域を除く前記凹部からなる余剰領域と、
を有する前記半導体ウエハを分割する半導体装置の製造方法において、
前記半導体ウエハの裏面に粘着テープを介してダイシングフレームを装着する装着工程と、
前記ダイシングフレームに装着された前記半導体ウエハの裏面を前記凹部よりも小さい凸部を有するステージに載置し、
前記分割ラインに沿って前記半導体ウエハの表面側から前記複数の半導体素子領域を切断して前記複数の半導体素子領域を個片化する切断工程と、
前記半導体ウエハの裏面側から前記粘着テープの粘着力を低下させる粘着力低下工程と、
前記半導体ウエハの裏面を前記凹部よりも小さく前記複数の半導体素子領域よりも大きい保持ステージに載置し、前記粘着テープから前記環状補強部を剥離する剥離工程と、
前記環状補強部および前記余剰領域を除去する除去工程と、
を含むことを特徴とする半導体装置の製造方法。
A concave portion formed by making the thickness of the central portion of the back surface of the semiconductor wafer thinner than the outer peripheral end portion;
An annular reinforcing portion formed on the outer periphery of the concave portion, and a plurality of semiconductor element regions defined by dividing lines in the concave portion,
A surplus region consisting of the recesses excluding the plurality of semiconductor element regions;
In a method of manufacturing a semiconductor device for dividing the semiconductor wafer having
A mounting step of mounting a dicing frame on the back surface of the semiconductor wafer via an adhesive tape;
Placing the back surface of the semiconductor wafer mounted on the dicing frame on a stage having a convex portion smaller than the concave portion;
A cutting step of cutting the plurality of semiconductor element regions from the surface side of the semiconductor wafer along the dividing line to separate the plurality of semiconductor element regions;
An adhesive strength reduction step of reducing the adhesive strength of the adhesive tape from the back side of the semiconductor wafer;
A peeling step of placing the back surface of the semiconductor wafer on a holding stage smaller than the recess and larger than the plurality of semiconductor element regions, and peeling the annular reinforcing portion from the adhesive tape;
A removal step of removing the annular reinforcing portion and the excess region;
A method for manufacturing a semiconductor device, comprising:
前記除去工程を実施後に、前記粘着テープを拡張して前記切断工程において個片化された前記半導体素子領域の隙間を広げる拡張工程を含む請求項1に記載の半導体装置の製造方法。   The method for manufacturing a semiconductor device according to claim 1, further comprising an expansion step of expanding the pressure-sensitive adhesive tape and expanding a gap between the semiconductor element regions separated in the cutting step after the removing step. 前記剥離工程は、前記半導体ウエハと前記ダンシングフレームとの間に環状剥離治具を前記半導体ウエハの表面側から下降させ、前記粘着テープを押し下げて前記粘着テープから前記環状補強部を剥離することを特徴とする請求項1または2に記載の半導体装置の製造方法。   In the peeling step, an annular peeling jig is lowered from the surface side of the semiconductor wafer between the semiconductor wafer and the dancing frame, and the pressure-sensitive adhesive tape is pushed down to peel the annular reinforcing portion from the pressure-sensitive adhesive tape. The method for manufacturing a semiconductor device according to claim 1, wherein the method is a semiconductor device manufacturing method. 前記剥離工程は、前記粘着テープと接する面が円形のリング形状である前記環状剥離治具を用いることを特徴とする請求項3に記載の半導体装置の製造方法。   The method of manufacturing a semiconductor device according to claim 3, wherein the peeling step uses the annular peeling jig whose surface in contact with the adhesive tape has a circular ring shape. 前記除去工程は、前記環状剥離治具を下降させた状態で前記半導体ウエハの表面側から前記環状補強部を吸着して除去することを特徴とする請求項3に記載の半導体装置の製造方法。   4. The method of manufacturing a semiconductor device according to claim 3, wherein in the removing step, the annular reinforcing portion is adsorbed and removed from the surface side of the semiconductor wafer in a state where the annular peeling jig is lowered. 前記粘着力低下工程は、前記半導体ウエハの裏面に紫外線照射を行うことを特徴とする請求項1に記載の半導体装置の製造方法。

2. The method of manufacturing a semiconductor device according to claim 1, wherein in the step of reducing the adhesive strength, the back surface of the semiconductor wafer is irradiated with ultraviolet rays.

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JP2016157903A (en) * 2015-02-26 2016-09-01 株式会社ディスコ Wafer dividing method and chuck table
JP2022092883A (en) * 2020-12-11 2022-06-23 株式会社ディスコ Processing device
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