JP2015065294A - Semiconductor device and power amplifier - Google Patents

Abstract

A semiconductor device including a bipolar transistor with improved temperature characteristics and a power amplifier to which the semiconductor device is applied.
In a semiconductor device including a bipolar transistor BT, a p-type base layer 4 is formed of a p-type GaAsSb base layer 4a and a p-type GaAs base layer 4b. An n-type InGaP emitter layer 5 is formed in contact with the p-type GaAs base layer 4b. The n-type InGaP emitter layer 5 is ordered and has a tensile strain (1.36%).
[Selection] Figure 2

Description

  The present invention relates to a semiconductor device and a power amplifier, and particularly to a semiconductor device including a heterojunction bipolar transistor and a power amplifier to which such a semiconductor device is applied.

  In recent years, heterojunction bipolar transistors have been applied as transistors constituting power amplifier modules such as portable terminals. This type of bipolar transistor is called HBT (Hetero junction Bipolar Transistor).

  Here, as an example of a semiconductor device including such a bipolar transistor, a semiconductor device described in Patent Document 1 will be described. As shown in FIG. 32, in the bipolar transistor, an n-type GaAs subcollector layer 102 is formed in contact with the semi-insulating GaAs substrate 101, and an n-type GaAs collector layer is in contact with the n-type GaAs subcollector layer 102. 103 is formed. A p-type GaAs base layer 104 is formed so as to be in contact with the n-type GaAs collector layer 103, and an n-type InGaP emitter layer 105 is formed so as to be in contact with the p-type GaAs base layer 104.

  An n-type GaAs layer 106 is formed in contact with the n-type InGaP emitter layer 105, and an n-type AlGaAs ballast resistor layer 107 is formed in contact with the n-type GaAs layer 106. An n-type GaAs contact layer 108 is formed so as to be in contact with the n-type AlGaAs ballast resistor layer 107, and an n-type InGaAs contact layer 109 is formed so as to be in contact with the n-type GaAs contact layer 108. An emitter electrode 113 is formed in contact with the n-type InGaAs contact layer 109.

  One end of an emitter wiring 116 is electrically connected to the emitter electrode 113, and the other end of the emitter wiring 116 is electrically connected to a metal pad 117. The metal pad 117 is formed on the surface of the semi-insulating GaAs substrate 101. A base electrode 112 is formed in contact with the p-type base layer 104, and a collector electrode 111 is formed in contact with the n-type GaAs subcollector layer 102. A collector wiring 114 is electrically connected to the collector electrode 111. The semiconductor device according to an example of the background art is configured as described above.

  In a heterojunction bipolar transistor, an n-type InGaP emitter layer 105 contains In—P and Ga—P in order to reduce the energy barrier against electron injection from the emitter layer to the base layer and lower the operating voltage. It is required to be an ordered layer that is arranged alternately adjacent.

  As a technique for reducing the operating voltage of the bipolar transistor, there is a technique of adding antimony (Sb) to the base layer. Patent Document 2 proposes a bipolar transistor having a base layer to which antimony (Sb) is added.

JP 2011-155281 A International Publication WO03 / 009339

  Electronic devices such as portable terminals, to which heterojunction bipolar transistors are applied, are being reduced in size, and in order to meet this demand, there is a strong demand for reduction in chip size including bipolar transistors. . As the chip size is reduced, the density of heat generated in the bipolar transistor (heat generation density) increases and the temperature of the bipolar transistor rises. For this reason, the bipolar transistor is required to perform a desired operation even when the temperature rises. That is, it is required to improve the temperature characteristics of the bipolar transistor.

  The present invention has been made as part of such development, and one object is to provide a semiconductor device including a bipolar transistor that can improve temperature characteristics, and another object is to provide such a device. A power amplifier to which a simple semiconductor device is applied is provided.

  A semiconductor device according to the present invention is a semiconductor device including a heterojunction bipolar transistor, and the bipolar transistor has a collector layer, a base layer, and an emitter layer. The base layer is formed on the collector layer. The emitter layer is formed on the base layer. The base layer includes a first base layer containing antimony (Sb) as a constituent element. The emitter layer contains at least indium (In), gallium (Ga) and phosphorus (P) as constituent elements and has tensile strain.

  According to the semiconductor device of the present invention, the temperature characteristics can be improved because the emitter layer has tensile strain.

  The base layer includes a second base layer that is formed on the first base layer and contains gallium (Ga) and arsenic (As) as constituent elements and does not contain antimony (Sb). It is preferably formed on the base layer.

  Thereby, it is possible to prevent the emitter layer from being ordered and the operating voltage from being increased.

  Specifically, the emitter layer is preferably formed of an indium gallium phosphorus (InGaP) layer.

  The molar ratio of indium phosphide (InP) in the indium gallium phosphide (InGaP) layer is preferably set to be smaller than 0.48.

Thereby, the emitter layer can have a tensile strain.
The molar ratio is more preferably 0.46 or less.

Thereby, the emitter layer can surely have tensile strain.
It is preferable to include a charge compensation layer formed on the emitter layer so as to be in contact with the emitter layer and having an impurity concentration higher than the impurity concentration of the impurity defining the conductivity type of the emitter layer.

  Thereby, the polarization accompanying the tensile strain of the emitter layer can be relaxed and the emitter resistance can be prevented from increasing.

  Specifically, the charge compensation layer is preferably formed of a gallium arsenide (GaAs) layer.

The impurity concentration of other impurities is preferably 1 × 10 ¹⁸ / cm ⁻³ or more.
Thereby, the polarization of the emitter layer accompanying the tensile strain can be surely relaxed.

  Preferably, a plurality of bipolar transistors are provided, and the plurality of bipolar transistors are electrically connected in parallel.

Thereby, large power can be handled as a semiconductor device.
The power amplifier according to the present invention is a power amplifier in which the above-described semiconductor device is mounted.

  According to the power amplifier of the present invention, it is possible to cope with a large power.

It is a top view of the semiconductor device provided with the bipolar transistor based on Embodiment 1 of this invention. FIG. 2 is a cross-sectional view taken along a cross-sectional line II-II shown in FIG. 1 in the same embodiment. In the same embodiment, it is a figure which shows typically the energy band of a heterojunction type bipolar transistor. In the same embodiment, it is a figure showing the relation between tensile strain and band offset amount. FIG. 5A is a perspective view schematically showing a unit crystal lattice, and FIG. 5B is a growth diagram for explaining an ordered InGaP emitter layer in the embodiment. It is a figure which shows typically the crystal structure seen from the direction orthogonal to a direction. In the same embodiment, it is a figure showing the relation between critical film thickness and tensile strain. It is a top view of the semiconductor device provided with the bipolar transistor based on Embodiment 2 of this invention. FIG. 8 is a cross-sectional view taken along a cross-sectional line VIII-VIII shown in FIG. 7 in the same embodiment. It is a top view of the semiconductor device provided with the bipolar transistor based on Embodiment 3 of this invention. FIG. 10 is a cross-sectional view taken along a cross-sectional line XX shown in FIG. 9 in the same embodiment. It is a top view of the semiconductor device provided with the bipolar transistor based on Embodiment 4 of this invention. FIG. 12 is a cross sectional view taken along a cross sectional line XII-XII shown in FIG. 11 in the same embodiment. In the same embodiment, it is sectional drawing which shows typically the mode of polarization by tensile strain. It is a top view of the semiconductor device provided with the bipolar transistor based on Embodiment 5 of this invention. FIG. 15 is a cross sectional view taken along a cross sectional line XV-XV shown in FIG. 14 in the same embodiment. It is a top view of the semiconductor device provided with the bipolar transistor based on Embodiment 6 of this invention. FIG. 17 is a cross-sectional view taken along a cross-sectional line XVII-XVII shown in FIG. 16 in the same embodiment. It is a circuit diagram which shows the connection aspect of the bipolar transistor in the semiconductor device provided with the several bipolar transistor based on Embodiment 7 of this invention. In the same embodiment, it is a top view of the semiconductor device provided with the some bipolar transistor. FIG. 20 is a cross sectional view taken along a full cross section XX-XX shown in FIG. 19 in the same embodiment. It is sectional drawing which shows 1 process of the manufacturing method of the semiconductor device provided with the several bipolar transistor based on Embodiment 8 of this invention. FIG. 22 is a cross-sectional view showing a step performed after the step shown in FIG. 21 in the same embodiment. FIG. 23 is a cross-sectional view showing a step performed after the step shown in FIG. 22 in the same embodiment. FIG. 24 is a cross-sectional view showing a step performed after the step shown in FIG. 23 in the same embodiment. FIG. 25 is a cross-sectional view showing a step performed after the step shown in FIG. 24 in the same embodiment. FIG. 26 is a cross-sectional view showing a step performed after the step shown in FIG. 25 in the same embodiment. FIG. 27 is a cross-sectional view showing a step performed after the step shown in FIG. 26 in the same embodiment. FIG. 28 is a cross-sectional view showing a step performed after the step shown in FIG. 27 in the same embodiment. FIG. 29 is a cross-sectional view showing a step performed after the step shown in FIG. 28 in the same embodiment. It is a block diagram which shows the structure of the power amplifier with which the semiconductor device provided with the several bipolar transistor based on Embodiment 9 of this invention was applied. 4 is a partial cross-sectional view schematically showing a semiconductor device mounted on a power amplifier and its peripheral portion in the embodiment. It is sectional drawing which shows the semiconductor device provided with the bipolar transistor based on background art.

Embodiment 1
Here, a first example of a semiconductor device including a heterojunction bipolar transistor will be described.

As shown in FIGS. 1 and 2, in the semiconductor device including the bipolar transistor BT, the n-type GaAs subcollector layer 2 (Si concentration: 5 × 10 ¹⁸ cm ⁻³⁾ is in contact with the surface of the semi-insulating GaAs substrate 1. , Film thickness: 0.6 μm). An n-type GaAs collector layer 3 (Si concentration: 1 × 10 ¹⁶ cm ⁻³ , film thickness: 1.0 μm) is formed so as to be in contact with the n-type GaAs subcollector layer 2.

A p-type base layer 4 is formed in contact with the n-type GaAs collector layer 3. The p-type base layer 4 includes a p-type GaAsSb base layer 4a (GaSb molar ratio: 0.1, C concentration: 4 × 10 ¹⁹ cm ⁻³ , film thickness: 50 nm) as a first base layer, and a second base layer P-type GaAs base layer 4b (C concentration: 4 × 10 ¹⁹ cm ⁻³ , film thickness: 50 nm). The p-type GaAsSb base layer 4 a is in contact with the n-type GaAs collector layer 3.

An n-type InGaP emitter layer 5 (InP molar ratio: 0.30, Si concentration: 3 × 10 ¹⁷ cm ⁻³ , film thickness: 15 nm) is in contact with the p-type base layer 4 (p-type GaAs base layer 4b). Is formed. The n-type InGaP emitter layer 5 is ordered and has a tensile strain (1.36%). Ordering and tensile strain will be described later.

An n-type GaAs layer 6 (Si concentration: 3 × 10 ¹⁷ cm ⁻³ , film thickness: 90 nm) is formed so as to be in contact with the n-type InGaP emitter layer 5. An n-type AlGaAs ballast resistor layer 7 (AlAs molar ratio: 0.33, Si concentration: 1 × 10 ¹⁷ cm ⁻³ , film thickness: 120 nm) is formed so as to be in contact with the n-type GaAs layer 6. The n-type AlGaAs ballast resistor layer 7 prevents the bipolar transistor BT from being damaged due to thermal runaway.

An n-type GaAs contact layer 8 (Si concentration: 1 × 10 ¹⁹ cm ⁻³ , film thickness: 50 nm) is formed so as to be in contact with the n-type AlGaAs ballast resistor layer 7. An n-type InGaAs contact layer 9 (InAs molar ratio: 0.5, Si concentration: 1 × 10 ¹⁶ cm ⁻³ , film thickness: 50 nm) is formed so as to be in contact with the n-type GaAs contact layer 8. The emitter size is 3 μm × 20 μm and is a rectangular emitter.

  An emitter electrode 13 is formed so as to be in contact with the n-type InGaAs contact layer 9. A collector electrode 11 is formed in contact with the n-type GaAs subcollector layer 2. A base electrode 12 is formed in contact with the p-type base layer 4. The collector electrode 11 is formed by stacking an AuGe film (film thickness: 60 nm) / Ni film (film thickness: 10 nm) / Au film (film thickness: 200 nm). The base electrode 12 is formed by laminating a Ti film (film thickness: 50 nm) / Pt film (film thickness: 50 nm) / Au film (film thickness: 200 nm). The emitter electrode 13 is formed of a WSi film (Si molar ratio: 0.3, film thickness: 0.3 μm).

  Metal pads 17, 18, and 19 are formed on the periphery of the semi-insulating GaAs substrate 1 for electrical connection with the outside of the bipolar transistor BT. The collector electrode 11 and the metal pad 19 are electrically connected by the collector wiring 14. The base electrode 12 and the metal pad 18 are electrically connected by the base wiring 15. The emitter electrode 13 and the metal pad 17 are electrically connected by the emitter wiring 16.

  In the semiconductor device including the bipolar transistor BT described above, the ordered n-type InGaP emitter layer 5 has tensile strain, so that at the interface between the p-type base layer 4 and the n-type InGaP emitter layer 5, The band offset amount ΔEv at the valence band edge (upper end) can be increased, and thereby the temperature characteristics of the bipolar transistor BT can be improved. This will be described in detail.

  First, in the heterojunction bipolar transistor, a large factor (parameter) that determines the temperature dependence of the direct current amplification factor (hfe) is a valence band formed at the interface between the n-type emitter layer and the p-type base layer. This is the band offset amount ΔEv at the end (upper end). When this band offset amount ΔEv is small, when the temperature of the bipolar transistor rises and becomes high, holes are easily injected back from the p-type base layer to the n-type emitter layer. The temperature dependency of (hfe) increases.

  On the other hand, when the band offset amount ΔEv is large, the reverse injection of holes from the p-type base layer to the n-type emitter layer is suppressed even at a high temperature, so that the direct current amplification factor (hfe) The temperature dependency is reduced, and fluctuations in the DC current gain (hfe) can be suppressed even when the temperature rises. As a result, the temperature characteristics of the bipolar transistor can be improved. Thus, in order to obtain a heterojunction bipolar transistor having excellent temperature characteristics, it is necessary to increase the band offset amount ΔEv at the valence band edge (upper end).

  In the bipolar transistor BT of the semiconductor device described above, since the ordered InGaP emitter layer 5 has tensile strain, the band offset amount ΔEv at the valence band edge (upper end) can be increased.

  Here, FIG. 4 shows a specific relationship (graph) between the tensile strain (%) of the InGaP emitter layer 5 and the band offset amount ΔEv (eV) at the valence band edge (upper end). In FIG. 4, the case of holes with a large effective mass is shown in graph A, and the case of holes with a low effective mass is shown in graph B. As shown in graphs A and B, it can be seen that the band offset amount ΔEv at the valence band edge (upper end) increases as the tensile strain increases.

  Next, the tensile strain that increases the band offset amount ΔEv will be described. The n-type InGaP emitter layer 5 having tensile strain is formed by changing the composition of indium (In) and gallium (Ga) in the n-type InGaP emitter layer 5. That is, the tensile strain can be applied to the n-type InGaP emitter layer 5 by changing the molar ratio of InP and the molar ratio of GaP.

  Here, the molar ratio of InP in the n-type InGaP emitter layer 5 is x, and the molar ratio of GaP is 1-x. The n-type InGaP emitter layer 5 of the bipolar transistor BT described above is formed so that the molar ratio x is 0.3. By forming the molar ratio x to be smaller than 0.48, the lattice constant of the n-type InGaP emitter layer 5 becomes smaller than the lattice constant of the underlying p-type GaAs base layer 4b, so that the n-type The InGaP emitter layer 5 has a tensile strain.

  Thus, in the semiconductor device described above, since the n-type InGaP emitter layer 5 has tensile strain, the band offset amount ΔEv at the valence band edge (upper end) can be increased, and the temperature of the heterojunction bipolar transistor BT is increased. The characteristics can be improved.

  Further, the n-type InGaP emitter layer 5 having tensile strain is ordered. Next, the ordering will be described. In general, in a semiconductor device including a bipolar transistor, the emitter layer is required to be an ordered layer in order to reduce an energy barrier against electron injection from the emitter to the base. FIG. 5A shows a schematic diagram of the unit crystal lattice in the case where the emitter layer is formed of an n-type InGaP layer as a group III-V mixed crystal semiconductor. In the unit crystal lattice, group III elements gallium (Ga) and indium (In) are usually arranged in a disordered manner in a crystal lattice made of only the group elements.

  However, it is known that gallium (Ga) and indium (In) are ordered (ordered) in the crystal lattice depending on the growth conditions. FIG. 5B shows a schematic diagram of the crystal structure of the ordered unit crystal lattice as viewed from the normal direction of the plane including the dotted frame (direction orthogonal to the growth direction). As shown in FIG. 5B, in the ordered crystal structure of InGaP, the bond (arrangement) of indium (In) and phosphorus (P), and the bond (arrangement) of gallium (Ga) and phosphorus (P). Are adjacent to each other. In the bipolar transistor BT described above, since the n-type InGaP emitter layer 5 is ordered, the energy barrier against the injection of electrons from the emitter to the base can be reduced, and the operating voltage can be lowered.

  As will be described later, the n-type InGaP layer serving as the n-type InGap emitter layer 5 is formed on the surface of the p-type GaAs layer serving as the p-type GaAs base layer 4b. Thereby, when forming the n-type InGaP layer, the p-type GaAsSb layer 4a is not brought into contact with the antimony (Sb) of the p-type GaAsSb layer, and the n-type InGaP layer is prevented from being disordered and ordered. Can contribute to lowering the operating voltage.

  Note that the ordered n-type InGaP emitter layer 5 is not necessarily essential. Even if the n-type InGaP emitter layer 5 is not ordered, the temperature characteristics of the bipolar transistor BT can be obtained as long as it has tensile strain. It is possible to improve.

  Further, the p-type base layer 4b is not always essential, and the temperature characteristics of the bipolar transistor BT can be improved even in the configuration in which the n-type InGaP emitter layer 5 having tensile strain is formed on the p-type GaAsSb base layer 4a. Is possible.

  However, it is needless to say that the bipolar transistor BT preferably includes an ordered n-type InGaP emitter layer 5 and a p-type base layer 4b.

In the n-type InGaP emitter layer 5 having tensile strain, misfit dislocations may occur when the film thickness is increased. For this reason, it is necessary to form the n-type InGaP emitter layer 5 so as to be thinner than the critical film thickness. The critical film thickness d is ^required to be a film thickness satisfying d = 49.9 ^ε -1.18 when the tensile strain is ε (%). The relationship (graph) between the critical film thickness d (nm) and the tensile strain is shown in FIG. In order to prevent misfit dislocations from occurring in the n-type InGaP emitter layer 5, the film thickness of the n-type InGaP emitter layer 5 is set to a film thickness in a region below the graph with respect to the tensile strain (%). There is a need.

Embodiment 2
Here, as a second example of a semiconductor device including a heterojunction bipolar transistor, a semiconductor device having a structure in which the n-type GaAs layer 6 in the semiconductor device according to the first example is omitted will be described.

As shown in FIGS. 7 and 8, in the semiconductor device including the bipolar transistor BT, the n-type InGaP emitter layer 5 (InP molar ratio: 0.3, Si concentration: 3 ×) is in contact with the p-type base layer 4. 10 ¹⁷ cm ⁻³ , film thickness: 15 nm). An n-type AlGaAs ballast resistor layer 7 (AlAs molar ratio: 0.33, Si concentration: 1 × 10 ¹⁷ cm ⁻³ , film thickness: 120 nm) is formed in contact with the n-type InGaP emitter layer 5.

An n-type GaAs contact layer 8 (Si concentration: 1 × 10 ¹⁹ cm ⁻³ , film thickness: 50 nm) is formed in contact with the n-type AlGaAs ballast resistor layer 7. Since other configurations are similar to those of the semiconductor device shown in FIGS. 1 and 2, the same members are denoted by the same reference numerals, and the description thereof will not be repeated unless necessary.

  In the semiconductor device described above, the n-type InGaP emitter layer 5 has a tensile strain (about 1.36%). Thereby, as explained in the first embodiment, the band offset amount ΔEv at the valence band edge (upper end) can be increased. As a result, even if the temperature of the heterojunction bipolar transistor BT rises, fluctuations in the direct current amplification factor are suppressed, and the temperature characteristics of the bipolar transistor BT can be improved.

  Further, the n-type InGaP layer that becomes the n-type InGap emitter layer 5 having the tensile strain is formed on the surface of the p-type GaAs layer that becomes the p-type GaAs base layer 4b. Thereby, it does not contact the antimony (Sb) of the p-type GaAsSb layer to be the p-type GaAsSb layer 4a, and the n-type InGaP layer can be prevented from being disordered. As a result, the n-type InGaP emitter layer 5 is ordered, and the operating voltage of the bipolar transistor BT can be lowered.

  Further, as described above, in order to prevent misfit dislocations from occurring in the n-type InGap emitter layer 5 having tensile strain, the n-type InGaP emitter layer 5 exceeds the critical film thickness d (see FIG. 6). It is necessary to form so that there is no.

Embodiment 3
Here, a semiconductor device having a structure in which the n-type AlGaAs ballast resistor layer 7 in the semiconductor device according to the first example is omitted will be described as a third example of a semiconductor device including a heterojunction bipolar transistor.

As shown in FIGS. 9 and 10, in the semiconductor device including the bipolar transistor BT, the n-type InGaP emitter layer 5 (InP molar ratio: 0.3, Si concentration: 3 ×) is in contact with the p-type base layer 4. 10 ¹⁷ cm ⁻³ , film thickness: 15 nm). An n-type GaAs layer 6 (Si concentration: 3 × 10 ¹⁷ cm ⁻³ , film thickness: 90 nm) is formed so as to be in contact with the n-type InGaP emitter layer 5.

An n-type GaAs contact layer 8 (Si concentration: 1 × 10 ¹⁹ cm ⁻³ , film thickness: 50 nm) is formed in contact with the n-type GaAs layer 6. Since other configurations are similar to those of the semiconductor device shown in FIGS. 1 and 2, the same members are denoted by the same reference numerals, and the description thereof will not be repeated unless necessary.

  In the semiconductor device described above, the n-type InGaP emitter layer 5 has tensile strain. Thereby, as explained in the first embodiment, the band offset amount ΔEv at the valence band edge (upper end) can be increased. As a result, even if the temperature of the heterojunction bipolar transistor BT rises, fluctuations in the direct current amplification factor are suppressed, and the temperature characteristics of the bipolar transistor BT can be improved.

  Further, the n-type InGaP layer that becomes the n-type InGap emitter layer 5 having the tensile strain is formed on the surface of the p-type GaAs layer that becomes the p-type GaAs base layer 4b. Thereby, it does not contact the antimony (Sb) of the p-type GaAsSb layer to be the p-type GaAsSb layer 4a, and the n-type InGaP layer can be prevented from being disordered. As a result, the n-type InGaP emitter layer 5 is ordered, and the operating voltage of the bipolar transistor BT can be lowered.

  Further, as described above, in order to prevent misfit dislocations from occurring in the n-type InGap emitter layer 5 having tensile strain, the n-type InGaP emitter layer 5 exceeds the critical film thickness d (see FIG. 6). It is necessary to form so that there is no.

  The semiconductor device according to the third example, which omits the n-type AlGaAs ballast resistor layer, is scheduled to be mounted on a portable terminal that is required to perform more advanced information communication.

Embodiment 4
Here, a semiconductor device including a charge compensation layer will be described as a fourth example of a semiconductor device including a heterojunction bipolar transistor.

As shown in FIGS. 11 and 12, in the semiconductor device including the bipolar transistor BT, the n-type InGaP emitter layer 5 (InP molar ratio: 0.3, Si concentration: 3 ×) is in contact with the p-type base layer 4. 10 ¹⁷ cm ⁻³ , film thickness: 15 nm). An n-type GaAs charge compensation layer 20 (Si concentration: 3 × 10 ¹⁸ cm ⁻³ , film thickness: 5 nm) is formed in contact with the n-type InGaP emitter layer 5. An n-type GaAs layer 6 (Si concentration: 3 × 10 ¹⁷ cm ⁻³ , film thickness: 90 nm) is formed so as to be in contact with the n-type GaAs charge compensation layer 20.

An n-type AlGaAs ballast resistor layer 7 (AlAs molar ratio: 0.33, Si concentration: 1 × 10 ¹⁷ cm ⁻³ , film thickness: 120 nm) is formed so as to be in contact with the n-type GaAs layer 6. An n-type GaAs contact layer 8 (Si concentration: 1 × 10 ¹⁹ cm ⁻³ , film thickness: 50 nm) is formed in contact with the n-type AlGaAs ballast resistor layer 7. Since other configurations are similar to those of the semiconductor device shown in FIGS. 1 and 2, the same members are denoted by the same reference numerals, and the description thereof will not be repeated unless necessary.

  In the semiconductor device described above, since the n-type GaAs charge compensation layer 20 is formed between the n-type InGaP emitter layer 5 and the n-type GaAs layer 6, the temperature characteristics can be improved without increasing the emitter resistance. Can be improved. This will be described.

  As described above, the n-type InGaP emitter layer 5 has tensile strain in order to increase the band offset amount ΔEv at the valence band edge (upper end). Then, it is assumed that polarization occurs in the n-type InGaP emitter layer 5 due to a piezoelectric effect (piezo effect) accompanying tensile strain. In this case, as shown in FIG. 13, a positive charge is generated in the vicinity of the interface with the p-type base layer 4 (p-type GaAs layer 4b) in the n-type InGaP emitter layer 5, and a negative charge is generated in the vicinity of the interface with the n-type GaAs layer 6. It is assumed that an electric charge is generated.

  When polarization occurs in the n-type InGaP emitter layer 5, the n-type GaAs layer 6 formed on the n-type InGaP emitter layer 5 is reduced in carriers and depleted, leading to an increase in emitter resistance.

In the semiconductor device described above, an n-type GaAs charge containing a relatively high concentration (3 × 10 ¹⁸ cm ⁻³ ) of silicon (Si) as an impurity between the n-type InGaP emitter layer 5 and the n-type GaAs layer 6. A compensation layer 20 is formed. As a result, even if polarization occurs in the n-type InGaP emitter layer 5, carrier reduction and depletion in the n-type GaAs layer 6 on the n-type InGaP emitter layer 5 are compensated, and the emitter The increase in resistance can be suppressed.

  In addition to this, in the semiconductor device described above, since the n-type InGaP emitter layer 5 has a tensile strain, the fluctuation of the DC current amplification factor also varies with the temperature rise of the heterojunction bipolar transistor BT. Thus, the temperature characteristics of the bipolar transistor BT can be improved. Thus, in the semiconductor device described above, the temperature characteristics can be improved without increasing the emitter resistance.

  Further, as already described, the n-type InGaP layer that becomes the n-type InGap emitter layer 5 having the tensile strain is formed on the surface of the p-type GaAs layer that becomes the p-type GaAs base layer 4b. The n-type InGaP emitter layer 5 can be ordered by suppressing disordering of the InGaP layer, and the operating voltage of the bipolar transistor BT can be lowered.

The concentration (3 × 10 ¹⁸ cm ⁻³ ) of silicon (Si) contained as an impurity that defines the conductivity type of the n-type GaAs charge compensation layer 20 described above is an example, and is not limited to this. According to the evaluation of the inventors, it has been found that the function as the charge compensation layer can be exhibited if the concentration is about 1 × 10 ¹⁸ cm ⁻³ or more.

  Further, as described above, in order to prevent misfit dislocations from occurring in the n-type InGap emitter layer 5 having tensile strain, the n-type InGaP emitter layer 5 exceeds the critical film thickness d (see FIG. 6). It is necessary to form so that there is no.

Embodiment 5
Here, a semiconductor device having a structure in which the n-type GaAs layer 6 (see FIG. 12) in the semiconductor device according to the fourth example is omitted will be described as a fifth example of the semiconductor device including the heterojunction bipolar transistor.

As shown in FIGS. 14 and 15, in the semiconductor device including the bipolar transistor BT, the n-type InGaP emitter layer 5 (InP molar ratio: 0.3, Si concentration: 3 ×) is in contact with the p-type base layer 4. 10 ¹⁷ cm ⁻³ , film thickness: 15 nm). An n-type GaAs charge compensation layer 20 (Si concentration: 3 × 10 ¹⁸ cm ⁻³ , film thickness: 5 nm) is formed in contact with the n-type InGaP emitter layer 5. An n-type AlGaAs ballast resistor layer 7 (AlAs molar ratio: 0.33, Si concentration: 1 × 10 ¹⁷ cm ⁻³ , film thickness: 120 nm) is formed so as to be in contact with the n-type GaAs charge compensation layer 20.

An n-type GaAs contact layer 8 (Si concentration: 1 × 10 ¹⁹ cm ⁻³ , film thickness: 50 nm) is formed in contact with the n-type AlGaAs ballast resistor layer 7. Since other configurations are the same as those of the semiconductor device shown in FIGS. 11 and 12, the same members are denoted by the same reference numerals, and the description thereof will not be repeated unless necessary.

  In the semiconductor device described above, the n-type GaAs charge compensation layer 20 is formed between the n-type InGaP emitter layer 5 and the n-type GaAs layer 6. As a result, as described in the fourth embodiment, even if polarization occurs in the n-type InGaP emitter layer 5, carrier reduction in the n-type GaAs layer 6 on the n-type InGaP emitter layer 5 The depletion is compensated, and the emitter resistance can be prevented from increasing.

  In addition to this, since the n-type InGaP emitter layer 5 has a tensile strain (about 1.36%), the DC current amplification factor can be increased even when the temperature of the heterojunction bipolar transistor BT rises. Variations can be suppressed and the temperature characteristics of the bipolar transistor BT can be improved. As a result, the bipolar transistor BT can improve the temperature characteristics without increasing the emitter resistance.

  Further, as already described, the n-type InGaP layer that becomes the n-type InGap emitter layer 5 having the tensile strain is formed on the surface of the p-type GaAs layer that becomes the p-type GaAs base layer 4b. The n-type InGaP emitter layer 5 can be ordered by suppressing disordering of the InGaP layer, and the operating voltage of the bipolar transistor BT can be lowered.

  In order to prevent misfit dislocations from occurring in the n-type InGap emitter layer 5 having tensile strain, the n-type InGaP emitter layer 5 must be formed so as not to exceed the critical film thickness d (see FIG. 6). There is.

Embodiment 6
Here, as a sixth example of a semiconductor device including a heterojunction bipolar transistor, a semiconductor device having a structure in which the n-type AlGaAs ballast resistor layer 7 (see FIG. 12) in the semiconductor device according to the fourth example is omitted will be described. .

As shown in FIGS. 16 and 17, in the semiconductor device including the bipolar transistor BT, the n-type InGaP emitter layer 5 (InP molar ratio: 0.3, Si concentration: 3 ×) is in contact with the p-type base layer 4. 10 ¹⁷ cm ⁻³ , film thickness: 15 nm). An n-type GaAs charge compensation layer 20 (Si concentration: 3 × 10 ¹⁸ cm ⁻³ , film thickness: 5 nm) is formed in contact with the n-type InGaP emitter layer 5.

An n-type GaAs layer 6 (Si concentration: 3 × 10 ¹⁷ cm ⁻³ , film thickness: 90 nm) is formed so as to be in contact with the n-type GaAs charge compensation layer 20. An n-type GaAs contact layer 8 (Si concentration: 1 × 10 ¹⁹ cm ⁻³ , film thickness: 50 nm) is formed in contact with the n-type GaAs layer 6. Since other configurations are the same as those of the semiconductor device shown in FIGS. 11 and 12, the same members are denoted by the same reference numerals, and the description thereof will not be repeated unless necessary.

  In the semiconductor device described above, the n-type GaAs charge compensation layer 20 is formed between the n-type InGaP emitter layer 5 and the n-type GaAs layer 6. As a result, as described in the fourth embodiment, even if polarization occurs in the n-type InGaP emitter layer 5, carrier reduction in the n-type GaAs layer 6 on the n-type InGaP emitter layer 5 The depletion is compensated, and the emitter resistance can be prevented from increasing.

  In addition to this, since the n-type InGaP emitter layer 5 has a tensile strain (about 1.36%), the DC current amplification factor can be increased even when the temperature of the heterojunction bipolar transistor BT rises. Variations can be suppressed and the temperature characteristics of the bipolar transistor BT can be improved. As a result, the bipolar transistor BT can improve the temperature characteristics without increasing the emitter resistance.

  Further, as already described, the n-type InGaP layer that becomes the n-type InGap emitter layer 5 having the tensile strain is formed on the surface of the p-type GaAs layer that becomes the p-type GaAs base layer 4b. The n-type InGaP emitter layer 5 can be ordered by suppressing disordering of the InGaP layer, and the operating voltage of the bipolar transistor BT can be lowered.

  In order to prevent misfit dislocations from occurring in the n-type InGap emitter layer 5 having tensile strain, the n-type InGaP emitter layer 5 must be formed so as not to exceed the critical film thickness d (see FIG. 6). There is.

Embodiment 7
Here, as a seventh example of a semiconductor device including a heterojunction bipolar transistor, a semiconductor device including a plurality of semiconductor devices according to the first example will be described.

  In a power amplifier of a portable terminal that handles relatively large power, the power amplifier is composed of a plurality of bipolar transistors connected in parallel. In this case, as shown in FIG. 18, in the plurality of bipolar transistors BT, their bases, emitters and collectors are connected in parallel in such a manner that they are electrically connected to each other.

  Next, the bipolar transistor BT of the semiconductor device according to the first example is used as a unit bipolar transistor, and a semiconductor device including a plurality of bipolar transistors BT will be specifically described.

As shown in FIGS. 19 and 20, in each of the plurality of bipolar transistors BT, an n-type InGaP emitter layer 5 (InP molar ratio: 0.3; Si concentration: 3 × 10 ¹⁷ cm ⁻³ , film thickness: 15 nm). An n-type GaAs layer 6 (Si concentration: 3 × 10 ¹⁷ cm ⁻³ , film thickness: 90 nm) is formed in contact with the n-type InGaP layer 5.

An n-type AlGaAs ballast resistor layer 7 (AlAs molar ratio: 0.33, Si concentration: 1 × 10 ¹⁷ cm ⁻³ , film thickness: 120 nm) is formed so as to be in contact with the n-type GaAs layer 6. An n-type GaAs contact layer 8 (Si concentration: 1 × 10 ¹⁹ cm ⁻³ , film thickness: 50 nm) is formed in contact with the n-type AlGaAs ballast resistor layer 7. Metal pads 17, 18, and 19 are formed on the periphery of the semi-insulating GaAs substrate 1.

  Each collector electrode 11 of the plurality of bipolar transistors BT is electrically connected to a metal pad 19 by a collector wiring 14. Each base electrode 12 of the plurality of bipolar transistors BT is electrically connected to a metal pad 18 by a base wiring 15. Each emitter electrode 13 of the plurality of bipolar transistors BT is electrically connected to a metal pad 17 by an emitter wiring 16. Since other configurations are the same as those of the semiconductor device shown in FIGS. 1 and 2, the same members are denoted by the same reference numerals, and description thereof will not be repeated unless necessary.

  In the semiconductor device including the plurality of bipolar transistors BT described above, a large amount of power can be handled as a semiconductor device because the plurality of bipolar transistors BT are connected in parallel.

  In each of the bipolar transistors BT, the n-type InGaP emitter layer 5 has a tensile strain (about 1.36%). Thereby, as explained in the first embodiment, the band offset amount ΔEv at the valence band edge (upper end) can be increased. As a result, even if the temperature of the heterojunction bipolar transistor BT rises, fluctuations in the direct current amplification factor are suppressed, and the temperature characteristics of the bipolar transistor BT can be improved.

  Further, the n-type InGaP layer that becomes the n-type InGap emitter layer 5 having the tensile strain is formed on the surface of the p-type GaAs layer that becomes the p-type GaAs base layer 4b. Thereby, it does not contact the antimony (Sb) of the p-type GaAsSb layer to be the p-type GaAsSb layer 4a, and the n-type InGaP layer can be prevented from being disordered. As a result, the n-type InGaP emitter layer 5 is ordered, and the operating voltage of the bipolar transistor BT can be lowered.

  Further, as described above, in order to prevent misfit dislocations from occurring in the n-type InGap emitter layer 5 having tensile strain, the n-type InGaP emitter layer 5 exceeds the critical film thickness d (see FIG. 6). It is necessary to form so that there is no.

  Further, as each of the plurality of bipolar transistors BT in the semiconductor device described above, the bipolar transistor BT of the semiconductor device described in the first embodiment has been described as an example, but has been described in the second to sixth embodiments. The same effect can be obtained even when the bipolar transistor BT of the semiconductor device is applied.

Embodiment 8
Here, an example of a method for manufacturing the semiconductor device described in Embodiment 7 will be described.

  First, predetermined layers to be a subcollector layer, a collector layer, a base layer, an emitter layer, a contact layer, and the like are formed on the surface of a semi-insulating GaAs substrate, respectively, by metal organic chemical vapor deposition (MOCVD). ) Method or the like.

As shown in FIG. 21, an n-type GaAs layer 2a (Si concentration: 5 × 10 ¹⁸ cm ⁻³ , film thickness: 0.6 μm) serving as a subcollector layer is formed on a semi-insulating GaAs substrate 1. . An n-type GaAs layer 3a (Si concentration: 1 × 10 ¹⁶ cm ⁻³ , film thickness: 1.0 μm) serving as a collector layer is formed in contact with the n-type GaAs layer 2a. A p-type GaAsSb layer 4aa (GaSb molar ratio: 0.1, C concentration: 4 × 10 ¹⁹ cm ⁻³ , film thickness: 50 nm) and a p-type GaAs layer serving as a base layer so as to be in contact with the n-type GaAs layer 3a 4bb (C concentration: 4 × 10 ¹⁹ cm ⁻³ , film thickness: 50 nm) is formed.

Next, an n-type InGaP layer 5a (Si concentration: 3 × 10 ¹⁷ cm ⁻³ , film thickness: 15 nm) serving as an emitter layer is formed in contact with the p-type GaAs layer 4bb. Here, by forming the n-type InGaP layer 5a so that the InP molar ratio is 0.30, the n-type InGaP layer 5a has a tensile strain of about 1.36%. Moreover, the n-type InGaP layer 5a can be ordered by forming the n-type InGaP layer 5a on the surface of the p-type GaAs layer 4bb containing no antimony (Sb).

An n-type GaAs layer 6a (Si concentration: 3 × 10 ¹⁷ cm ⁻³ , film thickness: 90 nm) is formed in contact with the n-type InGaP layer 5a. An n-type AlGaAs layer 7a (AlAs molar ratio: 0.33, Si concentration: 1 × 10 ¹⁷ cm ⁻³ , film thickness: 120 nm) serving as a ballast resistance layer is formed in contact with the n-type GaAs layer 6a. An n-type GaAs layer 8a (Si concentration: 1 × 10 ¹⁹ cm ⁻³ , film thickness: 50 nm) serving as a part of the contact layer is formed so as to be in contact with the n-type AlGaAs layer 7a. An n-type InGaAs layer 9a (InAs molar ratio: 0.5, Si concentration: 1 × 10 ¹⁹ cm ⁻³ , film thickness: 50 nm), which is another part of the contact layer, is in contact with the n-type GaAs layer 8a. It is formed.

Next, as shown in FIG. 22, a tungsten silicide (WSi) film (Si molar ratio: 0.3, film thickness: 0.3 μm) 13a is formed on the entire surface of the n-type InGaAs layer 9a by high frequency sputtering. Is deposited. Next, by performing a predetermined photolithography process and a dry etching process using a gas containing CF ₄ , the emitter electrodes 13 of the plurality of bipolar transistors BT are formed as shown in FIG.

  Next, by performing a predetermined photolithography process and a wet etching process, as shown in FIG. 24, an n-type InGaAs contact layer 9, an n-type GaAs contact layer 8, and an n-type AlGaAs ballast resistor layer 7 to become emitters. Then, the n-type GaAs layer 6 is patterned into a desired shape. Here, for example, a chemical solution in which phosphoric acid, hydrogen peroxide solution and water are mixed is used as the wet etching solution, and the composition ratio thereof is, for example, phosphoric acid: hydrogen peroxide solution: water = 1: 2: 40. Set to

  Next, as shown in FIG. 25, the base electrode 12 is formed by vapor deposition and lift-off so as to penetrate the n-type InGaP layer 5a in contact with the p-type GaAs layer 4bb. The base electrode 12 has a laminated structure of Ti (film thickness: 50 nm) / Pt (film thickness: 50 nm) / Au (film thickness: 200 nm).

  Next, by performing a predetermined photolithography process and a wet etching process, as shown in FIG. 26, each of the n-type InGaP emitter layer 5, the p-type base layer 4 and the n-type GaAs of each of the plurality of bipolar transistors BT. Collector layer 3 is formed. Here, hydrochloric acid is used as an etchant for etching the n-type InGaP layer 5a. As an etchant for etching the p-type GaAsSb layer 4aa, the p-type GaAs layer 4bb, and the n-type GaAs layer 3a, a chemical solution in which phosphoric acid, hydrogen peroxide solution, and water are mixed is used. , Phosphoric acid: hydrogen peroxide solution: water = 1: 2: 40.

  Next, as shown in FIG. 27, the collector electrodes 11 of the plurality of bipolar transistors BT are formed by vapor deposition and lift-off. Thereafter, alloying is performed at a temperature of 350 ° C. for 30 minutes. The collector electrode 11 is made of a laminate of AuGe (film thickness: 60 nm) / Ni (film thickness: 10 nm) / Au (film thickness: 200 nm). Thereby, each of the plurality of bipolar transistors BT is formed.

  Next, by performing a predetermined wet etching process, the isolation groove 10 is formed as shown in FIG. Here, as the wet etching solution, a chemical solution in which phosphoric acid, hydrogen peroxide solution and water are mixed is used, and the composition ratio is set to, for example, phosphoric acid: hydrogen peroxide solution: water = 1: 2: 40. Is done. Next, metal pads 17, 18, and 19 (see FIG. 13) are formed in predetermined regions on the semi-insulating GaAs substrate.

  Next, as shown in FIG. 29, an emitter wiring 16 that electrically connects each emitter electrode 13 of the bipolar transistor BT and the metal pad 17 is formed. Base wiring 15 for electrically connecting base electrode 12 and metal pad 18 (see FIG. 19) is formed. A collector wiring 14 that electrically connects the collector electrode 11 and the metal pad 19 (see FIG. 19) is formed. As a result, a main part of the semiconductor device including a plurality of bipolar transistors BT is formed.

  In the semiconductor device manufacturing method described above, a semiconductor device capable of handling high power can be manufactured by connecting a plurality of bipolar transistors BT in parallel.

  In each of the bipolar transistors BT, the n-type InGaP emitter layer 5 has a tensile strain (about 1.36%). Thereby, as explained in the first embodiment, the band offset amount ΔEv at the valence band edge (upper end) can be increased. As a result, even if the temperature of the heterojunction bipolar transistor BT rises, fluctuations in the direct current amplification factor are suppressed, and the temperature characteristics of the bipolar transistor BT can be improved.

  Further, the n-type InGaP layer that becomes the n-type InGap emitter layer 5 having the tensile strain is formed on the surface of the p-type GaAs layer that becomes the p-type GaAs base layer 4b. Thereby, it does not contact the antimony (Sb) of the p-type GaAsSb layer to be the p-type GaAsSb layer 4a, and the n-type InGaP layer can be prevented from being disordered. As a result, the n-type InGaP emitter layer 5 is ordered, and the operating voltage of the bipolar transistor BT can be lowered.

In the semiconductor device manufacturing method described above, the bipolar transistor BT of the semiconductor device according to the first example is given as an example of the bipolar transistor. However, the bipolar transistor BT of the semiconductor device is also manufactured in the second to sixth examples. Is possible. In particular, in a bipolar transistor BT having a charge compensation layer, such as the bipolar transistor BT according to the fourth example, after the n-type InGaP layer 5a serving as the emitter layer is formed and before the n-type GaAs layer 6a is formed, An n-type GaAs layer (Si concentration: 3 × 10 ¹⁸ cm ⁻³ , film thickness: 5 nm) serving as a compensation layer is formed.

Embodiment 9
Here, a power amplifier in which the semiconductor device described in Embodiment 7 is mounted will be described.

  FIG. 30 shows a block diagram of a circuit of the power amplifier (module) 30. As shown in FIG. 30, the power amplifier 30 includes a two-stage amplifier circuit including a first amplifier circuit 34 and a second amplifier circuit 35. A semiconductor device in which a plurality of bipolar transistors BT are connected in parallel is applied to each of the first amplifier circuit 34 and the second amplifier circuit 35.

  In the power amplifier 30, the high frequency signal input from the high frequency input terminal 32 is amplified through the first amplification circuit 34 and the second amplification circuit 35, and the amplified high frequency signal is output from the high frequency output terminal 33.

  In order to achieve impedance matching, an input matching circuit 36 is provided between the high-frequency input terminal 32 and the first amplifier circuit 34, and interstage matching is provided between the first amplifier circuit 34 and the second amplifier circuit 35. A circuit 37 is provided, and an output matching circuit 38 is provided between the second amplifier circuit 35 and the high frequency output terminal 33.

  Next, a structure around the bipolar transistor BT of the semiconductor device applied to the first amplifier circuit 34 and the second amplifier circuit 35 will be briefly described. As shown in FIG. 31, in the power amplifier 30, a plurality of mounting boards 41, 42, and 43 are stacked. A bipolar transistor BT is formed on the mounting substrate 42.

  Further, passive elements 48 and 49 such as capacitors and inductors are formed on the mounting substrate 43 so as to achieve impedance matching. Furthermore, predetermined conductive layers 44, 45, 46, 47 for electrically connecting the bipolar transistor BT and the passive elements 48, 49 are formed on the mounting boards 41, 42, 43. In FIG. 31, a plurality of bipolar transistors BT are represented by one bipolar transistor BT.

  In the power amplifier 30 described above, a semiconductor device in which a plurality of bipolar transistors BT are connected in parallel is applied to each of the first amplifier circuit 34 and the second amplifier circuit 35. Thus, as described in Embodiment 7, a large amount of power can be handled as a semiconductor device.

  In each of the bipolar transistors BT, since the n-type InGaP emitter layer 5 has a tensile strain (about 1.36%), even if the temperature of the heterojunction bipolar transistor BT rises, the direct current The fluctuation of the amplification factor is suppressed, and the temperature characteristics of the bipolar transistor BT can be improved.

  Furthermore, the n-type InGaP layer that becomes the n-type InGap emitter layer 5 having tensile strain is formed on the surface of the p-type GaAs layer that becomes the p-type GaAs base layer 4b, so that the n-type InGaP emitter layer 5 is ordered. Thus, the operating voltage of the bipolar transistor BT can be lowered.

  The n-type InGaP emitter layer 5 having a tensile strain of 1.36% has been described as an example of the emitter layer of the bipolar transistor BT according to each embodiment described above. According to the inventors' evaluation, in the n-type InGaP emitter layer 5 having a tensile strain of 1.36%, the molar ratio of InP is 0.3.

  The molar ratio of InP in the n-type InGaP emitter layer 5 is not limited to 0.3. From the viewpoint of improving the temperature characteristics by increasing the band offset amount ΔEv, the molar ratio of InP is preferably smaller than 0.48. In order to improve the temperature characteristics more reliably, the molar ratio of InP is 0.46. The following is preferable.

  In addition, the n-type InGaP emitter layer 5 has been exemplified as the emitter layer, but the emitter layer only needs to contain at least indium (In), gallium (Ga), and phosphorus (P) as constituent elements, In addition, for example, an InGaNP layer containing nitrogen (N) may be included.

  Further, in the p-type GaAsSb base layer 4a in the p-type base layer 4, the case where the molar ratio of GaSb is 0.1 has been described. The molar ratio of GaAs in the p-type GaAsSb base layer 4a may be higher than 0 and 0.1 or lower (0 <GaAs molar ratio ≦ 0.1).

  The embodiment disclosed this time is an example, and the present invention is not limited to this. The present invention is defined by the terms of the claims, rather than the scope described above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  The present invention is effectively used for a semiconductor device including a heterojunction bipolar transistor.

  BT bipolar transistor, 1 semi-insulating GaAs substrate, 2 n-type GaAs subcollector layer, 2a n-type GaAs layer, 3 n-type GaAs collector layer, 3a n-type GaAs layer, 4 p-type base layer, 4a p-type GaAsSb base layer 4aa p-type GaAsSb layer, 4b p-type GaAs base layer, 4bb p-type GaAs layer, 5n type InGaP emitter layer, 5a n type InGaP layer, 6n type GaAs layer, 6a n type GaAs layer, 7n type AlGaAs ballast Resistance layer, 7a n-type AlGaAs layer, 8n type GaAs contact layer, 8a n type GaAs layer, 9n type InGaAs contact layer, 9a n type InGaAs layer, 10 isolation groove, 11 collector electrode, 12 base electrode, 13 emitter Electrode, 13a tungsten silicide film, 14 Rector wiring, 15 Base wiring, 16 Emitter wiring, 17, 18, 19 Metal pad, 20 n-type GaAs charge compensation layer, 30 Power amplifier, 31 Power amplification circuit block, 32 High frequency input terminal, 33 High frequency output terminal, 34 1st Amplifier circuit, 35 Second amplifier circuit, 36 Input matching circuit, 37 Interstage matching circuit, 38 Output matching circuit, 41, 42, 43 Mounting substrate, 44, 45, 46, 47 Conductive layer, 48, 49 Passive element.

Claims (10)

A semiconductor device including a heterojunction bipolar transistor,
The bipolar transistor is:
A collector layer;
A base layer formed on the collector layer;
An emitter layer formed on the base layer;
The base layer includes a first base layer containing antimony (Sb) as a constituent element,
The emitter layer contains at least indium (In), gallium (Ga), and phosphorus (P) as constituent elements, and has a tensile strain. The base layer includes a second base layer formed on the first base layer, containing gallium (Ga) and arsenic (As) as constituent elements and not containing antimony (Sb),
The semiconductor device according to claim 1, wherein the emitter layer is formed on the second base layer.   The semiconductor device according to claim 1, wherein the emitter layer is formed of an indium gallium phosphorus (InGaP) layer.   The semiconductor device according to claim 3, wherein a molar ratio of indium phosphorus (InP) in the indium gallium phosphorus (InGaP) layer is set to be smaller than 0.48.   The semiconductor device according to claim 4, wherein the molar ratio is 0.46 or less.   The charge compensation layer according to claim 1, further comprising a charge compensation layer formed on the emitter layer so as to be in contact with the emitter layer and having an impurity concentration higher than an impurity concentration of an impurity defining a conductivity type of the emitter layer. A semiconductor device according to 1.   The semiconductor device according to claim 6, wherein the charge compensation layer is formed of a gallium arsenide (GaAs) layer. The semiconductor device according to claim 7, wherein the impurity concentration of the other impurities is 1 × 10 ¹⁸ / cm ⁻³ or more. A plurality of the bipolar transistors;
The semiconductor device according to claim 1, wherein the plurality of bipolar transistors are electrically connected in parallel.   A power amplifier on which the semiconductor device according to claim 1 is mounted.

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