JP2002076015A - Heterojunction bipolar transistor - Google Patents

Abstract

(57) [Problem] To provide a heterojunction bipolar transistor capable of obtaining good element characteristics and high reliability. SOLUTION: An n-type In is formed on a p ⁺ -type GaAs base layer 104.
GaP first emitter layer 105, n-type Al _x Ga _1-x As (x =
0.3) Second emitter layer 106 and n-type Al _x Ga _{1 -x} As
(x = 0.3) The third emitter layer 107 is sequentially stacked. The n-type Al _x Ga _{1 -x} As (x = 0.3) second emitter layer 106
Of the n-type InGaP first emitter layer 105 and the n-type Al _x Ga _{1 -x} As (x = 0.3) third emitter layer 10.
7 is made higher than the impurity concentration. Thereby, the n-type Al _x Ga _{1 -x} As (x = 0.3) second emitter layer 1 having a high impurity concentration
From 06, carriers are supplied to the hetero interface with the n-type InGaP first emitter layer 105 to suppress a decrease in carrier concentration at the interface.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a heterojunction bipolar transistor.

[0002]

2. Description of the Related Art In recent years, in heterojunction bipolar transistors, the emitter / base junction has InGaP / Ga.
Heterojunction bipolar transistors, which are As, are being actively researched and developed from the viewpoint of improving device characteristics and reliability. However, when a GaAs layer or the like of the same conductivity type is continuously grown as a cap layer on the InGaP emitter layer, carriers are remarkably depleted at the hetero interface, a high resistance layer is formed, and the emitter resistance increases. In addition, there arises a problem that device characteristics such as high-frequency characteristics are deteriorated. In order to reduce the emitter resistance by compensating for such carrier depletion, a heterojunction bipolar transistor having a structure in which a planar doping layer is provided at a hetero interface has been proposed (Japanese Patent Laid-Open No. 8-293505).
Publication).

FIG. 5 is a cross-sectional view showing the structure of a heterojunction bipolar transistor in which a planar doping layer is provided at the heterointerface. As shown in FIG. 5, an n-type GaAs substrate is formed on a semi-insulating GaAs substrate 501. A sub-collector layer 502, a GaAs collector layer 503, a p-type GaAs base layer 504, an n-type InGaP emitter layer 505, a Si planar doping layer 506, and an n-type GaAs emitter cap layer 507 are sequentially stacked. Next, a part of the p-type GaAs base layer 504 and the n-type GaAs
While exposing a part of the As subcollector layer 502,
By forming the emitter electrode 508, the base electrode 509, and the collector electrode 510, a heterojunction bipolar transistor is completed. In this heterojunction type bipolar transistor, the InGaP emitter layer 505 and the GaAs cap layer 50 are formed by the planar doping layer 506.
Since the depletion of carriers at the heterointerface of No. 7 can be compensated, the emitter resistance can be reduced and the high frequency characteristics can be improved. In the heterojunction bipolar transistor, the resistivity of the emitter in the stacking direction is 9 × 1.
It becomes about 0 ^-7 Ωcm ² .

[0004]

However, a heterojunction bipolar transistor in which a planar doping layer is provided at the heterointerface is manufactured and subjected to a conduction test. As a result, the emitter resistance is gradually increased by the conduction, and the emitter resistance is high. A new issue of unreliability has emerged. In the heterojunction bipolar transistor, impurities must be doped at a very high concentration in order to compensate for carrier depletion by the planar doping layer. Since a steep impurity concentration profile is formed in the portion, it is considered that the impurity diffused and the emitter resistance increased.

Another heterojunction bipolar transistor has a structure in which the surface of a base layer is covered with a completely depleted thin emitter layer called an edge thinning layer or a guard ring in order to improve device characteristics and reliability. Have been. However, with the conventional structure, InGa
When a heterojunction bipolar transistor having a structure in which an edge thinning layer for protecting the base surface is formed by etching the emitter mesa while leaving the P layer and a base electrode is formed on the edge thinning layer to form a heterojunction bipolar transistor having a high impurity concentration, , The InGaP edge thinning layer is hard to be completely depleted, and a leak current is generated between the emitter and base electrodes via the edge thinning layer, resulting in that good device characteristics and high reliability cannot be obtained.

SUMMARY OF THE INVENTION An object of the present invention is to provide a heterojunction bipolar transistor having good device characteristics and high reliability.

[0007]

In order to achieve the above object, a heterojunction bipolar transistor according to the present invention has a structure in which a first emitter layer, a second emitter layer, and a third emitter layer are sequentially stacked on a base layer. A junction type bipolar transistor, wherein the first emitter layer is formed of In
The second and third emitter layers are composed of at least a compound semiconductor, and the impurity concentration of the second emitter layer is higher than the impurity concentration of the first and third emitter layers. I have.

According to the heterojunction bipolar transistor having the above structure, the first emitter layer made of InGaP and the second emitter layer made of at least a compound semiconductor having an impurity concentration higher than that of the first emitter layer and the third emitter layer. Carriers are supplied to the hetero interface of
A decrease in carrier concentration at the interface can be suppressed, and emitter resistance can be reduced.

In one embodiment of the present invention, the second emitter layer is made of one of AlGaAs and GaAs, and the third emitter layer is made of one of AlGaAs and GaAs. And

According to the heterojunction bipolar transistor of the above embodiment, the second and third emitter layers between the InGaP first emitter layer and the emitter cap layer are made of Al.
When a GaAs layer or a GaAs layer is used, since the lattice constant is substantially equal to that of the InGaP first emitter layer, a good crystal can be easily obtained, and etching can be easily performed selectively with the InGaP first emitter layer. Note that the second and third
One of the emitter layers may be AlGaAs and the other may be GaAs.

In one embodiment of the present invention, the thickness of the second emitter layer is 10n.
m to 50 nm.

According to the present applicant, when the impurity concentration of the second emitter layer is 5 × 10 ¹⁷ cm ⁻³ to 15 × 10 ¹⁷ cm ⁻³ and the thickness is 10 nm to 70 nm, the resistivity of the emitter in the stacking direction is reduced. As a result of an experiment, it was found that the resistivity in the stacking direction was sufficiently low when the thickness of the second emitter layer was 10 nm to 50 nm. When the thickness of the second emitter layer is less than 10 nm, the decrease in carrier concentration is not sufficiently compensated, and the resistivity in the stacking direction cannot be sufficiently reduced. When the thickness exceeds 50 nm, the carrier is excessively compensated, the energy at the bottom of the conduction band in the AlGaAs layer is lowered, and the layer acts as a barrier for electrons. Therefore, the resistivity in the stacking direction cannot be sufficiently reduced. it is conceivable that.

Therefore, according to the heterojunction bipolar transistor of the above embodiment, the emitter resistance can be sufficiently reduced by setting the thickness of the second emitter layer to 10 nm to 50 nm.

In one embodiment of the present invention, the impurity concentration of the second emitter layer is 7 × 10 ¹⁷ cm ^{−3 to} 13 × 10 ¹⁷ cm ⁻³ .

According to the present applicant, when the impurity concentration of the second emitter layer is 5 × 10 ¹⁷ cm ⁻³ to 15 × 10 ¹⁷ cm ⁻³ and the film thickness is 10 nm to 70 nm, the resistivity in the stacking direction of the emitter is reduced. As a result of the investigation, the impurity concentration of the second emitter layer was set to 7
It was found that the resistivity in the laminating direction was reduced when the ^density was set to × 10 ¹⁷ cm ⁻³ or more. Among them, the impurity concentration is 7 × 1
When it is 0 ¹⁷ cm ^{−3 to} 13 × 10 ¹⁷ cm ⁻³ , the resistivity is sufficiently reduced. When the impurity concentration of the second emitter layer is less than 7 × 10 ¹⁷ cm ⁻³ , the decrease in the carrier concentration is not sufficiently compensated, so that the resistivity in the stacking direction cannot be sufficiently reduced. When the impurity concentration of the emitter layer exceeds 13 × 10 ¹⁷ cm ⁻³ , the carrier is excessively compensated, the energy at the bottom of the conduction band in the AlGaAs layer decreases, and the layer acts as a barrier for electrons. It is probable that the rate could not be reduced sufficiently.

Therefore, according to the hetero-junction bipolar transistor of the above embodiment, the impurity concentration of the second emitter layer is 7 × 10 ¹⁷ cm ^{−3 to} 13 × 10 ¹⁷ cm ^−3.
By doing so, the emitter resistance can be sufficiently reduced.

In one embodiment of the heterojunction bipolar transistor, the second emitter layer is a gradient concentration layer in which the impurity concentration gradually increases from the third emitter layer toward the first emitter layer. It is characterized by:

According to the heterojunction bipolar transistor of the above embodiment, the second emitter layer is a gradient concentration layer in which the impurity concentration gradually increases from the third emitter layer toward the first emitter layer. By
The carrier concentration distribution of the emitter changes from the first emitter layer to the third
Since the carrier concentration becomes smooth and almost uniform over the emitter layer and the energy at the bottom of the conduction band in the emitter layer becomes almost uniform, the emitter resistance is further reduced and high device characteristics can be obtained.

In one embodiment of the present invention, the impurity concentration of the second emitter layer, which is the gradient concentration layer, is 7 × 10 ¹⁷ cm ^{−3 to} 13 × at the interface with the first emitter layer. It is characterized by being 10 ¹⁷ cm ^-3 .

According to the heterojunction bipolar transistor of the above embodiment, the impurity concentration of the second emitter layer, which is the graded concentration layer, is set to 7 at the interface with the first emitter layer.
By setting the carrier density to be from × 10 ¹⁷ cm ^{−3 to} 13 × 10 ¹⁷ cm ⁻³ , the decrease in carrier concentration at the interface between the first emitter layer and the second emitter layer can be compensated, and the emitter resistance can be further reduced.

In one embodiment of the present invention, the impurity concentration of the second emitter layer, which is the gradient concentration layer, is substantially equal to the impurity concentration of the third emitter layer at the interface with the third emitter layer. It is characterized by being equal.

According to the heterojunction bipolar transistor of the above embodiment, the impurity concentration of the second emitter layer, which is the gradient concentration layer, is made substantially equal to the impurity concentration of the third emitter layer at the interface with the third emitter layer. Thereby, the carrier concentration can be made smoother and uniform from the second emitter layer to the third emitter layer.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a heterojunction bipolar transistor according to the present invention will be described in detail with reference to the illustrated embodiments.

(First Embodiment) FIG. 1 is a sectional view showing the structure of a heterojunction bipolar transistor according to a first embodiment of the present invention.

As shown in FIG. 1, a semi-insulating GaAs substrate 1
The n ⁺ -type GaAs sub-collector layer 102 (impurity concentration 5 × 10 ¹⁸ cm ⁻³ , film thickness 500 nm) and the n-type GaAs collector layer 103 (impurity concentration 3 × 10 ¹⁶ cm ⁻³ , film thickness 7)
00 nm), p ⁺ -type GaAs base layer 104 (impurity concentration 4
× 10 ¹⁹ cm ⁻³ , film thickness 70 nm), n-type InGaP first emitter layer 105 (impurity concentration 5 × 10 ¹⁷ cm ⁻³ , film thickness 4)
0 nm), n-type Al _x Ga _{1 -x} As second emitter layer 106 (x
= 0.3, impurity concentration 1 × 10 ¹⁸ cm ⁻³ , thickness 30n
m), n-type Al _x Ga _1-x As third emitter layer 107 (x = 0.
3, impurity concentration 5 × 10 ¹⁷ cm ⁻³ , film thickness 20 nm), n
Type Al _x Ga _{1 -x} As composition gradient fourth emitter layer 108 (x =
0.3 → 0, impurity concentration 5 × 10 ¹⁷ cm ^-3 , film thickness 50n
m), n ⁺ -type GaAs emitter cap layer 109, n ⁺ -type In
The GaAs emitter cap layers 110 are sequentially stacked by MOCVD (metal organic chemical vapor deposition). In addition, MOCVD
Alternatively, the layers may be similarly stacked by using an MBE (Molecular Beam Epitaxial) method or the like. The Al _x Ga _{1 -x} As graded composition fourth emitter layer 108 is provided in order to prevent an increase in emitter resistance by conduction band discontinuity between Al _x Ga _1-x As third emitter layer 107 and the GaAs emitter cap layer 109 It is. Note that the Al _x Ga _1-x As third emitter layer and the n-type Al _x Ga
_{In the 1-} xAs composition gradient fourth emitter layer 108, when the impurity concentration is increased, a leak current tends to occur, and a current gain tends to decrease.

The InGaP first emitter layer 105 and Ga
As emitter layer (10) between As emitter cap layer 109
6, 107 and 108) are made of an AlGaAs layer or a GaAs layer, so that the lattice constant of the InGaP first emitter layer 105 becomes substantially equal to that of the InGaP first emitter layer 105, so that a good crystal can be easily obtained. Can be easily etched.

Next, a method for forming the above heterojunction bipolar transistor will be described.

First, a portion serving as an emitter is masked by photolithography, and the other region is etched with a mixed solution of citric acid and hydrogen peroxide. Since this mixture does not etch InGaP, the first mixture of InGaP is not used.
When the emitter layer 105 is exposed on the surface, the etching stops there.

Next, by photolithography, a mask is formed on a portion serving as an emitter and a base, and the other region is etched. At this time, InGaP is etched with hydrochloric acid, and GaAs is etched with a mixture of citric acid and hydrogen peroxide to expose the surface of the GaAs subcollector layer 102.

Subsequently, an emitter electrode 111 is formed on the InGaAs cap layer 110, a base electrode 112 is formed on the InGaP first emitter layer 105, and a collector electrode 113 is formed on the GaAs subcollector layer 102. The materials of the emitter electrode 111, the base electrode 112 and the collector electrode 113 include Pt / Ti / Pt / Au and Au.
Ge / Ni / Au or the like is used. Then, alloying (alloying) is performed to bring the base electrode 112 and the base layer 104 into ohmic contact, and to make the collector electrode 113 and the subcollector layer 102 into ohmic contact. After that, isolation between elements is performed by etching or the like, an interlayer insulating film is formed, and wiring (not shown) is formed by plating or vapor deposition. Since the high impurity concentration layer is etched, the InGaP first emitter layer 105 exposed on the surface is completely depleted and functions as an edge thinning layer, so that no leak current occurs between the emitter and the base through the edge thinning layer. .

In the heterojunction bipolar transistor of the first embodiment, the impurity concentration of the Al _x Ga _{1 -x} As (x = 0.3) second emitter layer 106 is set to 5 × 10 ¹⁷ cm ⁻³ to 5 × 10 ¹⁷ cm ⁻³ .
The following Table 1 shows the results of an experiment in which the resistivity of the emitter in the stacking direction when the film thickness was 15 × 10 ¹⁷ cm ⁻³ and the film thickness was 10 nm to 70 nm was examined.

[0032]

[Table 1]

As can be seen from Table 1, when the impurity concentration of the second emitter layer is set to 7 × 10 ¹⁷ cm ⁻³ or more, the resistivity in the stacking direction decreases. Among them, the impurity concentration is 7 × 10 ¹⁷ cm ^{−3 to} 13 × 10 ¹⁷ cm
^{At -3} , the resistivity is sufficiently low. Further, it can be seen that the resistivity in the stacking direction is sufficiently low when the film thickness is 10 nm to 50 nm. Therefore, the impurity concentration of the second emitter layer is 7 × 10 ¹⁷ cm ^{−3 to} 13 × 10 ¹⁷
cm ^-3 and a film thickness of preferably 10 nm to 50 nm.

When the impurity concentration is less than 7 × 10 ¹⁷ cm ⁻³ and when the film thickness is less than 10 nm, the decrease in the carrier concentration is not sufficiently compensated, and the resistivity in the stacking direction is sufficiently reduced. Probably not. Conversely, when the impurity concentration exceeds 13 × 10 ¹⁷ cm ^-3 and when the film thickness exceeds 50 nm, carriers are excessively compensated, the energy at the bottom of the conduction band in the AlGaAs layer decreases, and the electron It is considered that the layer acted as a barrier and could not sufficiently reduce the resistivity in the stacking direction.

Further, in Table 1, Al _x Ga _{1 -x} As (x = 0.
3) The impurity concentration of the second emitter layer is 7 × 10 ¹⁷ cm ⁻³ or more.
In all cases where the thickness was set to 15 × 10 ¹⁷ cm ⁻³ and the film thickness was set to 10 nm to 70 nm, an energization test was performed to check the reliability of the device. The test conditions were as follows: the junction temperature of the heterojunction bipolar transistor was 270 ° C., the emitter current density was 25 kAcm ⁻² , and the voltage between the emitter and collector was 3.4 V. Then, an energization test was performed for 1000 hours. The increase rate of the emitter resistance was within 5% and the decrease rate of the current gain was within 10%.

As described above, according to the first embodiment,
A heterojunction bipolar transistor having good element characteristics and high reliability can be realized.

(Second Embodiment) A heterojunction bipolar transistor according to a second embodiment of the present invention is the same as that of the first embodiment except for the impurity concentration of the AlGaAs second emitter layer.
Has the same configuration as the heterojunction bipolar transistor shown in FIG.

This heterojunction bipolar transistor
Is, as shown in FIG._xGa_1-xAs second emitter layer
At the interface with the InGaP first emitter layer.
× 10¹⁸cm^-3, Al_xGa_1-xAs (x = 0.1) Third Emi
5 × 10 at the interface with the¹⁷cm^-3Gradient density,
Al_xGa_1-xThe first point is that the composition ratio of As is set to x = 0.1.
Different from the heterojunction bipolar transistor of the embodiment
You. Also, Al_xGa_1-xAs (x = 0.1) of the second emitter layer
The thickness is 30 nm. Heterojunction fabricated in this way
Resistance of Stacked Bipolar Transistor in Stacking Direction
The rate is 8 × 10 ^-7Ωcm^TwoAnd compared to the first embodiment.
Lower and higher device characteristics can be obtained
You.

FIG. 3 shows the carrier concentration distribution of the emitter of the heterojunction bipolar transistor. 3 As is clear, it can be seen that _{InGaP Al x Ga 1-x As} (x = 0.1) from the first emitter layer carrier concentration toward the 3AlGaAs emitter layer is smoothly almost uniform. It is considered that the emitter resistance was further reduced because the carrier concentration became smooth and uniform, and the energy at the bottom of the conduction band in the emitter layer became almost uniform. Therefore, in order to smooth the carrier concentration from the second emitter layer to the third emitter layer, the impurity concentration of the second emitter layer should be substantially equal to the impurity concentration of the third emitter layer at the interface with the third emitter layer. preferable. Further, in order to compensate for the decrease in carrier concentration at the interface between the first emitter layer and the second emitter layer and to lower the emitter resistance, the impurity concentration of the second emitter layer must be equal to the first emitter layer as in the first embodiment. At the interface with the emitter layer, it is preferably 7 × 10 ¹⁷ cm ^{−3 to} 13 × 10 ¹⁷ cm ⁻³ . Further, the thickness of the second emitter layer is 10
nm to 50 nm. The heterojunction bipolar transistor was subjected to a conduction test for 1000 hours under the same conditions as in the first embodiment. The increase rate of the emitter resistance was within 5% and the decrease rate of the current gain was 10%.
%.

As described above, similar to the first embodiment, good device characteristics and high reliability can be obtained.

(Third Embodiment) FIG. 4 is a sectional view showing the structure of a heterojunction bipolar transistor according to a third embodiment of the present invention. The heterojunction bipolar transistor according to the third embodiment is different from the heterojunction bipolar transistor according to the first embodiment in that the second and third emitter layers are GaAs layers. The base electrode is formed on the surface of the base layer.

As shown in FIG. 4, the semi-insulating GaAs substrate 4
The n ⁺ -type GaAs sub-collector layer 402 (impurity concentration 5 × 10 ¹⁸ cm ⁻³ , thickness 500 nm) and the n-type GaAs collector layer 403 (impurity concentration 3 × 10 ¹⁶ cm ⁻³ , thickness 7)
00 nm), p ⁺ -type GaAs base layer 404 (impurity concentration 4
× 10 ¹⁹ cm ⁻³ , film thickness 70 nm), n-type InGaP first emitter layer 405 (impurity concentration 5 × 10 ¹⁷ cm ⁻³ , film thickness 4)
0 nm) n-type GaAs second emitter layer 406 (impurity concentration 1
× 10 ¹⁸ cm ⁻³ , thickness 30 nm) n-type GaAs third emitter layer 407 (impurity concentration 5 × 10 ¹⁷ cm ⁻³ , thickness 70 n)
m), n ⁺ -type GaAs emitter cap layer 408, n ⁺ -type In
GaAs emitter cap layers 409 are sequentially laminated by MOCVD. The GaAs third emitter layer 407
When the impurity concentration is increased, a leak current is likely to occur, and a current gain is likely to decrease. After that, the mesa etching and the respective electrodes are formed as in the first embodiment. The base electrode forming portion of the n-type InGaP first emitter layer 405 is etched to form a base electrode 411 on the GaAs base layer 404.
Is provided with an InGaP guard ring layer on the surface thereof.

Also in the heterojunction bipolar transistor of the third embodiment, the resistivity in the stacking direction of the emitter is 1 × 10 ⁻⁶ Ωcm ² , and the emitter resistance can be sufficiently reduced. Also, as in the first embodiment,
An energization test was performed at an emitter current density of 25 kAcm ^-2 for 1000 hours. The increase rate of the emitter resistance was within 5% and the decrease rate of the current gain was within 10%.

As described above, similar to the first embodiment, good device characteristics and high reliability can be obtained.

In the first to third embodiments, an npn-type heterojunction bipolar transistor has been described. However, the present invention may be applied to a pnp-type heterojunction bipolar transistor.

[0046]

As is apparent from the above, according to the heterojunction bipolar transistor of the present invention, the heterojunction bipolar transistor of the present invention does not degrade the device characteristics such as an increase in the emitter resistance due to energization and can obtain high device characteristics and high reliability. A junction type bipolar transistor can be provided.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a structure of a heterojunction bipolar transistor according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram showing an impurity doping concentration at the time of forming an emitter layer of a heterojunction bipolar transistor according to a second embodiment of the present invention.

FIG. 3 is an explanatory diagram showing a carrier concentration in an emitter layer of the heterojunction bipolar transistor.

FIG. 4 is a sectional view showing a structure of a heterojunction bipolar transistor according to a third embodiment of the present invention.

FIG. 5 is a cross-sectional view showing a structure of a conventional heterojunction bipolar transistor.

[Explanation of symbols]

101,401 ... a semi-insulating GaAs substrate, 102,402 ... n ⁺ type GaAs subcollector layer, 103,403 ... n type GaAs collector layer, 104,404 ... p ⁺ type GaAs base layer, 105,405 ... n type InGaP the first emitter layer, 106 ... n-type Al _x Ga _1-x As second emitter layer, 406 ... n-type GaAs second emitter layer, 107 ... n-type Al _x Ga _1-x As third emitter layer, 407 ... n N-type Al _x Ga _{1 -x} As composition gradient fourth emitter layer, 109,408... N ⁺ -type GaAs emitter cap layer, 110,409... N ⁺ -type InGaAs emitter cap layer, 111. , 410 ... emitter electrode, 112,411 ... base electrode, 113,412 ... collector electrode, 501 ... semi-insulating GaAs substrate, 502 ... n-type GaAs subcollector layer, 503 ... GaAs collector layer, 50 4 ... p-type GaAs base layer, 505 ... n-type InGaP emitter layer, 506 ... Si planar doping layer, 507 ... n-type GaAs emitter cap layer, 508 ... emitter electrode, 509 ... base electrode, 510 ... collector electrode.

Claims (7)

[Claims] 1. A hetero-junction bipolar transistor in which a first emitter layer, a second emitter layer and a third emitter layer are sequentially stacked on a base layer, wherein the first emitter layer is made of InGaP and the first emitter layer is made of InGaP. 2. A hetero-junction bipolar transistor, wherein the third emitter layer is made of at least a compound semiconductor, and the impurity concentration of the second emitter layer is higher than the impurity concentrations of the first emitter layer and the third emitter layer. 2. The heterojunction bipolar transistor according to claim 1, wherein the second emitter layer is made of one of AlGaAs and GaAs, and the third emitter layer is made of one of AlGaAs and GaAs. Heterojunction bipolar transistor characterized by the above-mentioned. 3. The heterojunction bipolar transistor according to claim 1, wherein said second emitter layer has a thickness of 10 nm to 50 nm. 4. The heterojunction bipolar transistor according to claim 1, wherein said second emitter layer has an impurity concentration of 7 × 10 ¹⁷ cm ⁻³ or more.
A heterojunction bipolar transistor, characterized by having a density of 13 × 10 ¹⁷ cm ⁻³ . 5. The heterojunction bipolar transistor according to claim 1, wherein the second emitter layer has an impurity concentration from the third emitter layer side toward the first emitter layer side. A heterojunction bipolar transistor, characterized in that the concentration is gradually increased. 6. The hetero-junction bipolar transistor according to claim 5, wherein an impurity concentration of the second emitter layer as the gradient concentration layer is:
7 × 10 ¹⁷ cm ^{−3 at} the interface with the first emitter layer
A heterojunction bipolar transistor, characterized by having a size of １３13 × 10 ¹⁷ cm ⁻³ . 7. The heterojunction bipolar transistor according to claim 5, wherein the impurity concentration of the second emitter layer, which is the gradient concentration layer, is:
A heterojunction bipolar transistor, wherein an impurity concentration at an interface with the third emitter layer is substantially equal to an impurity concentration of the third emitter layer.