JP2014116067A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory device having compatibility with DRAM.SOLUTION: A semiconductor memory device receives a row address RA and a column address CA at the same time in synchronization with an active command; and receives a page address PA in synchronization with a read command or write command. Word drivers 31to 31select a word line WL on the basis of the row address RA; and column switches 32-32select bit lines BL on the basis of the column address CA. A page address decoder 43 selects any one of read/write amplifiers 33-33corresponding to each of pages P0 to P511, on the basis of the page address PA. Thus, DRAM specs such as an access cycle can be satisfied without providing an amplifier for each bit line, thereby enabling compatibility with a DRAM to be ensured while reducing a chip area.

Description

  The present invention relates to a semiconductor memory device and a data processing system including the same, and more particularly to a semiconductor memory device to which an address signal is input in a plurality of times and a data processing system including the semiconductor memory device.

  A DRAM (Dynamic Random Access Memory), which is a typical semiconductor memory device, has a very large address space. Therefore, an address multiplex system in which address signals are input in two portions is adopted. Thereby, the number of address buses and the number of address terminals are reduced.

  Specifically, a block address (mat address) and a row address are input in synchronization with an active command, and then a column address is input in synchronization with a read command or a write command. Identified. As a result, the memory cell array (also referred to as a mat or block) and the word line included in the selected memory cell array are selected by the block address and the row address input the first time, and the bit address is selected by the column address input the second time. A line is selected.

  Such an address input method is determined by specifications. For this reason, in order to make a semiconductor memory device other than the DRAM compatible with the DRAM, it is essential to adopt the above address input method for the semiconductor memory device. However, in a semiconductor memory device having a slower read operation or write operation than a DRAM, for example, a semiconductor memory device such as a PRAM (Phase change Random Access Memory) using a phase change material for a memory cell, other DRAMs are used as they are. There was a problem that the specifications (particularly the access cycle) could not be satisfied and compatibility could not be ensured only by matching the address input method.

  As a method for solving such a problem, Patent Document 1 discloses a time-consuming memory cell setting operation (an operation for changing a phase change material from a high-resistance amorphous state to a low-resistance crystal state) in the background. A way to do it has been proposed.

JP 2005-158199 A

  However, in order to realize the method described in Patent Document 1, it is necessary to provide a write amplifier for each bit line, and there is a problem that the area occupied by the write amplifier on the chip becomes very large. That is, in the PRAM write operation, it is necessary to apply a high voltage to the bit line and supply a relatively large write current, so that the occupied area per one is very large compared to a DRAM sense amplifier. . For this reason, it is not practical to provide a write amplifier for each bit line.

  Note that the above problem is not limited to the PRAM, and similarly occurs in other semiconductor memory devices that require a long write operation.

  A semiconductor memory device according to the present invention includes a plurality of memory cells having a plurality of word lines, a plurality of bit lines, and a plurality of memory cells connected to intersections of the word lines and the bit lines, respectively, and in synchronization with a first command. Based on the input first and second addresses, one of the plurality of word lines and one of the plurality of bit lines is selected for each of the plurality of memory cell arrays, and issued after the first command. And an address selection circuit for selecting one of the plurality of memory cell arrays based on a third address input in synchronization with the second command.

  The data processing system according to the present invention supplies the first and second addresses simultaneously in synchronization with the issuance of the first command, and after issuing the first command, synchronizes with the issuance of the second command. A data processing system including a memory controller that supplies a third address and the semiconductor memory device connected to the memory controller, wherein the semiconductor memory device accepts the first address as a row address, The second address is accepted as a column address, and the third address is accepted as a page address.

  According to the present invention, the address signal input for the first time is handled as a row address and a column address, and the address signal input for the second time is handled as a page address. The storage device can be handled in exactly the same way as a DRAM. In addition, the word line and the bit line included in each memory cell array are selected by the address signal input at the first time, and the memory cell array is selected by the address signal input at the second time. Therefore, it is possible to satisfy DRAM specifications such as an access cycle. Therefore, according to the present invention, it is possible to provide a semiconductor memory device in which compatibility with DRAM is ensured and the chip area is reduced.

1 is a block diagram of a semiconductor memory device 10 according to a first embodiment of the present invention. 3 is a block diagram showing the structure of bank 0 of the memory cell array 20. FIG. It is a circuit diagram which shows the structure of the memory cell array P0. (A) is a figure for demonstrating the address allocation of the semiconductor memory device 10, (b) is a figure for demonstrating the address allocation of a general DRAM. (A) is a timing chart for explaining the operation control timing of the semiconductor memory device 10, and (b) is a timing chart for explaining the operation control timing of a general DRAM. FIG. 10 is a timing diagram showing an operation when a write command is continuously input after an active command is input. It is a figure which shows preferable 2nd Embodiment of this invention. It is a figure which shows preferable 3rd Embodiment of this invention. It is a figure which shows preferable 4th Embodiment of this invention. It is a timing diagram for demonstrating the write operation in 4th Embodiment. It is a timing diagram for demonstrating another example of the write operation in 4th Embodiment. It is a timing diagram for demonstrating another example of the write operation in 4th Embodiment. 1 is a block diagram of a data processing system according to a preferred embodiment of the present invention.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a block diagram of a semiconductor memory device 10 according to a first embodiment of the present invention. The semiconductor memory device 10 according to the present embodiment is a PRAM, and compatibility with the DRAM is ensured. Therefore, from the memory controller side, the semiconductor memory device 10 according to the present embodiment can be handled in the same way as a DRAM.

  As shown in FIG. 1, the semiconductor memory device 10 according to the present embodiment includes a memory cell array 20 including banks 0 to 3, a word driver 31 that performs row selection for the memory cell array 20, and a memory cell array 20. A column switch 32 that selects a column system and a read / write amplifier 33 that performs a read operation and a write operation on the memory cell array 20 are provided. Bank 0 to bank 3 constituting the memory cell array 20 can be operated independently based on different commands, and are selected by bank addresses BA0 and BA1.

  The word driver 31 performs row-related selection based on the decode signal RAa supplied from the row address decoder 41. The decode signal RAa is a signal obtained by decoding the row address RA by the row address decoder 41. The row address RA is a part of addresses A0 to A12 input from the outside, and is an address (first address) input in synchronization with an active command.

  The column switch 32 selects a column system based on the decode signal CAa supplied from the column address decoder 42. The decode signal CAa is a signal obtained by decoding the column address CA by the column address decoder 42. The column address CA is another part of the addresses A0 to A12 input from the outside and is an address (second address) input in synchronization with the active command.

  The read / write amplifier 33 activates the amplifier of the page selected based on the decode signal PAa supplied from the page address decoder 43. The decode signal PAa is a signal obtained by decoding the page address PA by the page address decoder 43. The page address PA is a part of addresses A0 to A12 input from the outside, and is an address (third address) input in synchronization with a read command or a write command.

  In the present embodiment, the word driver 31, the column switch 32, and the decoders 41 to 43 constitute an address selection circuit for the memory cell array 20.

  Read data DQ read by the read / write amplifier 33 is output to the outside via the data input / output circuit 50. The write data DQ input from the outside is supplied to the read / write amplifier 33 via the data input / output circuit 50.

  The active command, the read command, and the write command described above are expressed by a combination of a chip select signal / CS, a row address strobe signal / RAS, a column address strobe signal / CAS, and a write enable signal / WE input from the outside. 60. A slash (/) added to the beginning of a signal name means that the signal is a low active signal.

  Each signal (address and command), read data, and write data DQ input from the outside are input / output in synchronization with the clock signals CK and / CK. The clock signals CK and / CK are supplied to the internal clock generation circuit 70, and various internal clocks ICLK are generated by the internal clock generation circuit 70. The internal clock ICLK is supplied to the various internal circuits described above, and these internal circuits operate in synchronization with the corresponding internal clock ICLK.

  FIG. 2 is a block diagram showing the structure of bank 0 of the memory cell array 20. Other banks 1 to 3 have the same structure as bank 0.

As shown in FIG. 2, one bank of the memory cell array 20 is composed of 512 memory cell arrays P0 to P511. The word driver 31, the column switch 32, and the read / write amplifier 33 are also provided for each of the memory cell arrays P0 to P511. Here, the decode signals RAa are commonly supplied to the word drivers 31 _{0 to} 31 _511, and the decode signal CAa is commonly supplied to the column switches 32 _{0 to} 32 ₅₁₁ . Accordingly, when the row address RA and the column address CA are determined, memory cells to which the same row address and column address are assigned are selected in the memory cell arrays P0 to P511.

In contrast, the corresponding bits of the decode signal PAa are supplied to the read / write amplifiers 33 _{0 to} 33 ₅₁₁ , respectively. Accordingly, when the page address PA is determined, any one read / write amplifier assigned to each of the memory cell arrays P0 to P511 is selected. Input / output nodes of the read / write amplifiers 33 _{0 to} 33 ₅₁₁ are commonly connected to the data input / output circuit 50.

  FIG. 3 is a circuit diagram showing the structure of the memory cell array P0. The other memory cell arrays P1 to P511 have the same structure as the memory cell array P0.

As shown in FIG. 3, the memory cell array P0 includes a plurality of word lines WL _{0 to} WL ₅₁₁ , a plurality of bit lines BL _{0 to} BL _15, and a plurality of memories connected to the intersections of the word lines WL and the bit lines BL. Cell MC. The memory cell MC includes a select transistor ST and a phase change memory element PC connected in series between the corresponding bit line BLi (i = 0 to 15) and the plate wiring PL. The gate electrode of the select transistor ST is connected to the corresponding word line WLj (j = 0 to 511). As a result, when a predetermined word line WLj is activated, the corresponding selection transistor ST is turned on, and a current path via the phase change memory element PC is formed between each of the bit lines BL _{0 to} BL ₁₅ and the plate wiring PL. Will be. In the memory cell MC shown in FIG. 3, the select transistor ST is arranged on the bit line BL side and the phase change memory element PC is arranged on the plate wiring PL side. However, these may be reversed. .

The phase change memory element PC is a kind of variable resistance element. The phase change material constituting the phase change memory element PC is not particularly limited as long as it is a material that takes two or more phase states and has different electric resistances depending on the phase states, but it is preferable to select a so-called chalcogenide material. The chalcogenide material refers to an alloy containing at least one element such as germanium (Ge), antimony (Sb), tellurium (Te), indium (In), and selenium (Se). As an example, binary elements such as GaSb, InSb, InSe, Sb ₂ Te ₃ and GeTe, ternary elements such as Ge ₂ Sb ₂ Te ₅ , InSbTe, GaSeTe, SnSb ₂ Te ₄ and InSbGe, AgInSbTe, (GeSn ) Quaternary elements such as SbTe, GeSb (SeTe), Te ₈₁ Ge ₁₅ Sb ₂ S _{2 and the} like.

  Phase change materials including chalcogenide materials can take either an amorphous phase (amorphous phase) or a crystalline phase. The amorphous phase has a relatively high resistance state and the crystalline phase has a relatively low resistance. It becomes a state.

In order to make the phase change material amorphous (reset), the phase change material may be heated to a temperature equal to or higher than the melting point by applying a write current and then rapidly cooled. On the other hand, in order to crystallize (set) the phase change material, the phase change material may be heated to a temperature higher than the crystallization temperature and lower than the melting point by applying a write current, and then gradually cooled. Application of such a write current is supplied by the read / write amplifier 33 _0. As described above, in order to write data to the memory cell MC, it is necessary to change the phase state of the phase change memory element PC. Therefore, the PRAM requires a longer write operation than the DRAM. have.

On the other hand, data is read by passing a read current through the phase change memory element PC. Application of the read current is also supplied by the read / write amplifier 33 _0. The read current is set to a value sufficiently smaller than the write current so as not to cause a phase change. Therefore, unlike the DRAM, the memory cell MC can be read nondestructively. In addition, since the phase state of the phase change material does not change unless high heat is applied, data is not lost even when the power is turned off.

As shown in FIG. 3, word lines _WL 0 _{to WL 511} is connected to a word driver 31 _0, either one on the basis of a decode signal RAa is activated. The bit lines _BL 0 _{to BL 15} is connected to the read / write amplifier 33 ₀ via the switch ₃₂ 0 -0～32 ₀ -15 that constitute the column switch 32 _0. The control electrode of switch ₃₂ 0 -0～32 ₀ -15 are associated respective bits is supplied decode signal CAa, Therefore, one is turned on either on the basis of a decode signal CAa.

With such a configuration, when the row address RA and the column address CA are determined, any word line WLj and any bit line BLi included in the memory cell array P0 are selected. one memory cell MCij is to be connected to the read / write amplifier 33 ₀ or. As described above, the other memory cell arrays P1 to P511 also have the same structure as the memory cell array P0, and are supplied with the same decode signals RAa and CAa. Therefore, the same addresses are assigned to the other memory cell arrays P1 to P511. The allocated memory cell MCij is connected to the read / write amplifiers 33 _{1 to} 33 ₅₁₁ .

  FIG. 4A is a diagram for explaining address assignment of the semiconductor memory device 10 according to the present embodiment, and FIG. 4B is a diagram for explaining address assignment of a general DRAM. 4A and 4B, the address terminal has a 15-bit configuration including A0 to A12, BA0, and BA1. FIG. 5A is a timing chart for explaining operation control timing of the semiconductor memory device 10, and FIG. 5B is a timing chart for explaining operation control timing of a general DRAM.

  As shown in FIGS. 4A and 5A, the semiconductor memory device 10 according to the present embodiment employs the address multiplex method, and the addresses are inputted in two portions. Specifically, the row address RA (A0 to A8), the column address CA (A9 to A12), and the bank address (BA0, BA1) are input in synchronization with the active command, and the page is synchronized with the read command or write command. Address PA (A1 to A9) and bank address (BA0, BA1) are input. As a result, the memory cells MC are selected one by one from the memory cell arrays P0 to P511 in the corresponding bank according to the address input at the first time, and the memory cell arrays P0 to P511 in the corresponding bank are selected according to the address input at the second time. Is selected.

  As a result, any one memory cell MC included in the memory cell array 20 is selected. Therefore, if the read operation is performed, the read data DQ read from the selected memory cell MC via the read / write amplifier 33 is output to the outside. If the write operation is performed, the externally input write data DQ is read. / Writing into the selected memory cell MC via the write amplifier 33.

  Such address assignment is completely compatible with DRAM address assignment. That is, as shown in FIGS. 4B and 5B, in the DRAM, the row address (A0 to A8), the block address (A9 to A12), and the bank address (BA0, BA1) are synchronized with the active command. ), And column addresses (A1 to A9) and bank addresses (BA0, BA1) are input in synchronization with the read command or write command.

  As described above, in the present embodiment, the column address CA is received using the address terminal at the timing when the block address should be input in the DRAM, and the address terminal is set at the timing when the column address should be input in the DRAM. The page address PA is accepted. In other words, the block address output from the DRAM memory controller is interpreted as the column address CA, and the column address is interpreted as the page address PA. Therefore, from the memory controller side, the semiconductor memory device 10 according to the present embodiment can be handled in the same manner as a DRAM.

  As described above, the reason why the block address is interpreted as the column address CA and the column address is interpreted as the page address PA is that the array configuration of the semiconductor memory device 10 according to the present embodiment is different from the array configuration of the DRAM. .

That is, in a general DRAM, the number of bit lines allocated to one memory block (memory mat) is relatively large, and 512 (= 2 ⁹ ) are allocated in the example shown in FIG. Yes. For this reason, the number of bits of an address for selecting a bit line is relatively large. On the other hand, the number of memory blocks (memory mats) included in one bank is relatively small, and is 16 (= 2 ⁴ ) in the example shown in FIG. For this reason, the number of bits of an address for selecting a memory block (memory mat) is relatively small. Such an array configuration is adopted because the area occupied by one sense amplifier in a DRAM is small, and a sense amplifier can be assigned to each bit line pair.

  On the other hand, in the semiconductor memory device 10 according to the present embodiment, the number of bit lines assigned to one memory cell array (page) is relatively small at 16, and therefore, a column address for selecting a bit line. The number of CA bits is only 4 bits. On the other hand, the number of memory cell arrays (pages) included in one bank is relatively large at 512, and therefore, the number of bits of the page address PA for selecting the memory cell array (page) is 9 bits. The reason why such an array configuration is adopted is that it is impractical to allocate a read / write amplifier for each bit line pair because the area occupied by one read / write amplifier is large in this embodiment. This is because one read / write amplifier is assigned to each memory cell array.

  Due to the difference in the array configuration, in the semiconductor memory device 10 according to the present embodiment, the number of bits of the page address PA (9 bits) is larger than the number of bits of the column address CA (4 bits). It is reasonable to perform access control by interpreting the block address in the DRAM as the column address CA and interpreting the column address as the page address PA.

  Moreover, since the semiconductor memory device 10 according to the present embodiment takes a longer time for the write operation than the DRAM, in the array configuration of the present embodiment in which a plurality of bit lines share one read / write amplifier, an address similar to that of the DRAM is used. When the allocation is performed, continuous access by switching the column address CA becomes difficult. On the other hand, in the semiconductor memory device 10 according to the present embodiment, access control is performed by interpreting the column address in the DRAM as the page address PA. Therefore, as in the DRAM, after an active command is input, a read command or write Commands can be entered continuously.

  FIG. 6 is a timing chart showing an operation when a write command is continuously input after an active command is input.

  As shown in FIG. 6, when an active command ACT, a row address RA, and a column address CA are input and then a write command W0 and a page address PA0 are input, write data DQ is stored in a predetermined memory cell MC included in the memory cell array P0. Written. After that, if write commands W1, W2, W3... And page addresses PA1, PA2, PA3... Are continuously input, the read / write amplifier 33 by the page address decoder 43 maintains the selected state of the column switch 32. Are successively switched, write data DQ is successively written to predetermined memory cells MC included in the memory cell arrays P1, P2, P3.

As described above, according to the address assignment according to the present embodiment, the write data DQ to be continuously written is always assigned to different memory cell arrays (pages) P0 to P511, so that one read / write amplifier 33 _{0 to} 33 _{511 is provided.} However, different read / write amplifiers 33 _{0 to} 33 ₅₁₁ always operate in parallel. For this reason, it is possible to continuously input a write command as in the case of the DRAM, although it takes time to perform one write operation as compared with the DRAM. Of course, continuous input is also possible for the read command.

  As described above, the semiconductor memory device 10 according to the present embodiment can ensure compatibility with the DRAM even though a plurality of bit lines share one read / write amplifier. .

  FIG. 7 is a diagram showing a second preferred embodiment of the present invention.

  As shown in FIG. 7, in this embodiment, the word lines are hierarchized into main word lines MWL and sub word lines SWL, and the main word lines MWL are shared by the memory cell arrays P0 to P511. Main word line MWL is driven by main word driver 31M based on predecode signal RAa1. Sub word line SWL is driven by sub word driver 31S based on predecode signal RAa2. If such a hierarchical structure is adopted, the circuit scale of the word driver 31 can be greatly reduced.

  FIG. 8 is a diagram showing a third preferred embodiment of the present invention.

  As shown in FIG. 8, in this embodiment, the corresponding bits of the decode signal PAa are supplied to the sub word drivers 31S corresponding to the memory cell arrays P0 to P511, respectively. Since the other points are the same as those of the second embodiment shown in FIG. 7, the same elements are denoted by the same reference numerals, and redundant description is omitted.

  The sub word driver 31S drives the sub word line SWL when the corresponding bit of the decode signal PAa is activated. Therefore, the sub word line SWL is activated in synchronization with the selection of the read / write amplifier 33 by the page address decoder 43 after the page address PA is determined. According to such a configuration, only the sub-word driver 31S of the page that actually performs the read operation or the write operation selectively operates, so that power consumption can be reduced compared to the configuration illustrated in FIG. Become.

  FIG. 9 is a diagram showing a fourth preferred embodiment of the present invention.

As shown in FIG. 9, in the present embodiment, the read / write amplifiers 33 _{0 to} 33 ₅₁₁ are provided with a precharge circuit PRE. Since the other points are the same as those of the third embodiment shown in FIG. 8, the same elements are denoted by the same reference numerals, and redundant description is omitted. The precharge circuit PRE is a circuit for precharging the bit line BL connected to the write target memory cell MC, and starts a precharge operation in response to the issuance of a write command.

  FIG. 10 is a timing chart for explaining the write operation in the present embodiment.

  As shown in FIG. 10, in this embodiment, when a write command is issued, the bit line is precharged to a level (set voltage Vset) required for the set operation regardless of the logic level of the write data DQ. The set voltage Vset is a voltage to be applied to the bit line when the phase change memory element PC is crystallized, and is a voltage higher than a voltage (read voltage) to be applied to the bit line during the read operation. In the present embodiment, the selected bit line is precharged to the set voltage Vset regardless of the logic level of the write data DQ, and then the set operation or reset operation is performed according to the logic level of the write data DQ.

  As a result, when the logical level of the write data DQ actually indicates the set operation, the bit line has already been precharged up to the set voltage Vset, so that the memory cell MC can be set quickly. Become.

  On the other hand, when the logic level of the write data DQ indicates a reset operation, it is necessary to change the bit line to a level (reset voltage Vreset) necessary for the reset operation. The reset voltage Vreset is a voltage to be applied to the bit line when the phase change memory element PC is made amorphous, and is higher than the set voltage Vset. However, even in this case, since the bit line is already precharged to the set voltage Vset, the read / write amplifier 33 only needs to change the bit line from the set voltage Vset to the reset voltage Vreset. Since the difference between the set voltage Vset and the reset voltage Vreset is about 1 V, the memory cell MC can be quickly reset.

  Such a bit line can be precharged because the column address CA is fixed when the active command is issued. That is, unlike the DRAM, since the column address CA is determined before the write command is issued, the bit line can be immediately precharged in response to the issue of the write command. As a result, it is possible to shorten the time from when the write command for the bit line is issued until the write data DQ is actually written.

  In this embodiment, the selected bit line is precharged to the set voltage Vset regardless of the logic level of the write data DQ. However, as shown in FIG. 11, regardless of the logic level of the write data DQ. The selected bit line may be precharged to the reset voltage Vreset. In this case, when the logic level of the write data DQ indicates the set operation, it is necessary to lower the bit line to the set voltage Vset. As described above, the difference between the set voltage Vset and the reset voltage Vreset is 1V. Therefore, the set voltage Vset can be quickly changed.

  Furthermore, as shown in FIG. 12, the selected bit line may be precharged to a voltage Vp different from the set voltage Vset and the reset voltage Vreset regardless of the logic level of the write data DQ. In the example shown in FIG. 12, precharging is performed to a voltage slightly lower than the set voltage Vset. In this case, after the logic level of the write data DQ is determined, it is necessary to change the bit line from the precharge voltage Vp to the set voltage Vset or the reset voltage, but the precharge voltage Vp is in the vicinity of the set voltage Vset or the reset voltage Vreset. If it is set to, it is possible to quickly change to the set voltage Vset or the reset voltage.

  FIG. 13 is a block diagram of a data processing system according to a preferred embodiment of the present invention.

  The data processing system shown in FIG. 13 includes the semiconductor memory device (PRAM) 10, the semiconductor memory device (DRAM) 11, and the memory controller 12 that controls them. The memory controller 12, the PRAM 10, and the DRAM 11 are connected to each other by an address bus ABUS, a command bus CBUS, and a data bus DBUS. That is, the address bus ABUS, the command bus CBUS, and the data bus DBUS are provided in common for the PRAM 10 and the DRAM 11. Of course, wiring for supplying some signals such as a chip selection signal is individually wired in the PRAM 10 and the DRAM 11.

  As described above, since the semiconductor memory device (PRAM) 10 according to the present embodiment is compatible with the DRAM 11, it can be used in combination. The address assignment of the DRAM 11 is as described with reference to FIG. That is, one of a plurality of memory cell arrays and one of a plurality of word lines included in a selected memory cell array are each based on a block address (mat address) and a row address that are simultaneously input in synchronization with an active command. One of the plurality of bit lines is selected based on the column address selected and input in synchronization with the read command or write command.

  Of course, it is not essential to use the PRAM 10 and the DRAM 11 together, and a memory module may be configured by a plurality of PRAMs 10. Even in this case, it is possible to use a memory controller for DRAM as the memory controller 12. In this way, since it is not necessary to use a memory controller dedicated to PRAM, it is possible to reduce development costs and design costs.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

  For example, in the above embodiment, the case where the present invention is applied to the PRAM has been described as an example. However, the application target of the present invention is not limited to this, and other types of semiconductor memory devices such as RRAM (Resistance Random Access) It is also possible to apply to (Memory). An RRAM memory cell has a variable resistance element made of a magnetoresistive material whose electric resistance is changed by application of a voltage pulse. Therefore, when the present invention is applied to the RRAM, a write voltage may be used instead of the write current supplied to the memory cell MC in the above embodiment. In the present invention, the write current and the write voltage are collectively referred to as “write signal”.

  In the above embodiment, one read / write amplifier is provided for each page. However, it is not essential that the amplifier provided for each page is a read / write amplifier. It doesn't matter. For example, one write amplifier may be provided for each page, and a read amplifier may be provided for each bit line.

10 Semiconductor memory device (PRAM)
11 Semiconductor memory device (DRAM)
12 memory controller 20 memory cell array 31 word driver 31M main word driver 31S sub word driver 32 column switch 33 write amplifier 41 row address decoder 42 column address decoder 43 page address decoder 50 data input / output circuit 60 command decoder 70 internal clock generation circuits P0 to P511 Memory cell array (page)
BL bit line WL word line MWL main word line SWL sub word line MC memory cell PC phase change memory element ST selection transistor PRE precharge circuit

Claims (1)

A plurality of banks and an address selection circuit;
Each of the plurality of banks includes a plurality of memory cell arrays,
Each of the plurality of memory cell arrays includes a plurality of memory cells;
The address selection circuit selects one of the plurality of banks based on a first address input in synchronization with a first command, and a second input in synchronization with the first command. At least one memory cell is selected from each of the plurality of memory cell arrays included in the selected bank based on an address, and the plurality of the plurality of memory cells are selected based on a third address input in synchronization with a second command. Selecting one of the banks, and selecting one of the memory cells selected from the plurality of memory cell arrays based on a fourth address input in synchronization with the second command. A semiconductor memory device.

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