JP2014099240A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform high-speed data reading in a semiconductor memory device of the type, such as PRAM, that takes time for a sensing operation.SOLUTION: A semiconductor memory device includes: a sense amplifier start circuit 42 that sequentially starts a plurality of sense amplifiers, in response to a request for a continuous read operation to a plurality of memory cells in a state where a predetermined word line is selected; and an address determination circuit 34 that temporarily stops the operation of the sense amplifier start circuit 42, in response to a request for the continuous read operation to the same memory cells in a state where the predetermined word line is selected. Thus, the read operation to the plurality of memory cells can be performed in parallel, thereby allowing a high-speed read operation. In addition, if the read operation is requested to the same memory cells successively, the address determination circuit 34 temporarily stops the start of the sense amplifiers, thereby not causing data corruption.

Description

  The present invention relates to a semiconductor memory device and a control method thereof, and more particularly to a semiconductor memory device having a plurality of sense amplifiers connectable to any of a plurality of bit lines and a control method thereof.

  Currently, there are various types of semiconductor memory devices, and a typical semiconductor memory device is a DRAM (Dynamic Random Access Memory). Many DRAMs are of a synchronous type that inputs and outputs data in synchronization with a clock signal, and can be randomly accessed in a cycle of about 7 ns.

  However, the DRAM is a volatile memory, and the stored data is lost when the power is turned off. Therefore, the DRAM is not suitable for storing a program or data to be stored for a long time. In addition, since it is necessary to perform a refresh operation periodically to keep data even when the power is turned on, there is a limit to reducing power consumption, and there is a problem that complicated control by the controller is necessary. Yes.

  A flash memory is known as a large-capacity nonvolatile semiconductor memory. However, the flash memory has a demerit that a large current is required for data writing and data erasing, and the writing time and erasing time are very long. Therefore, it is inappropriate to replace the DRAM as the main memory. In addition, nonvolatile memories such as MRAM (Magnetoresistive Random Access Memory) and FRAM (Ferroelectric Random Access Memory) have been proposed, but it is difficult to obtain a storage capacity equivalent to that of DRAM.

  On the other hand, PRAM (Phase change Random Access Memory) that performs recording using a phase change material has been proposed as a semiconductor memory that replaces DRAM (see Patent Documents 1 to 4). The PRAM stores data according to the phase state of the phase change material included in the recording layer. That is, the phase change material has a large difference in electrical resistance in the crystalline phase and in the amorphous phase, so that data can be recorded using this.

  The change in phase state is performed by passing a write current through the phase change material, thereby heating the phase change material. On the other hand, data is read by passing a read current through the phase change material and measuring its resistance value. The read current is set to a value sufficiently smaller than the write current so as not to cause a phase change. For this reason, the PRAM is capable of nondestructive reading unlike the DRAM. In addition, since the phase state of the phase change material does not change unless high heat is applied, data is not lost even when the power is turned off.

JP 2006-24355 A JP 2005-158199 A JP 2006-31795 A JP 2006-294181 A JP-A-5-303891

  Since a DRAM is a voltage sense type semiconductor memory device, data is read by amplifying a potential difference generated in a bit line pair with a sense amplifier. On the other hand, since the PRAM is a current sense type semiconductor memory device, in reading data, it is necessary to convert the stored contents into a potential difference by flowing a read current through the memory cell, and to further amplify the potential difference. .

  For this reason, the circuit scale of the PRAM sense amplifier is much larger than that of the DRAM sense amplifier. Therefore, it is not practical to provide a sense amplifier for each bit line as in a DRAM, and the same sense amplifier needs to be shared for a plurality of bit lines.

  However, if the same sense amplifier is shared for a plurality of bit lines, it is necessary to start the next sense operation after the completion of the current sense operation when a continuous read operation is required. The data read cycle is limited by the operation speed. For this reason, the data read cycle is significantly longer than that of the DRAM, and there is a problem that compatibility with the DRAM cannot be maintained.

  Such a problem occurs not only in the PRAM but also in other types of semiconductor memory devices (for example, RRAM: Resistive Random Access Memory) that require a long sensing operation.

  Accordingly, an object of the present invention is to provide a semiconductor memory device capable of reading data at high speed and a control method thereof.

  Another object of the present invention is a semiconductor memory device of a type in which a plurality of bit lines share the same sense amplifier, which can read data at high speed, and a control method therefor Is to provide.

  A semiconductor memory device according to the present invention includes a plurality of word lines, a plurality of bit lines, a plurality of memory cells arranged at intersections of the word lines and the bit lines, and a word driver that selects any one of the plurality of word lines. In a state where a predetermined word line is selected by a plurality of sense amplifiers that can be connected to any of a plurality of bit lines and a word driver, a continuous read operation is performed on a plurality of memory cells connected to the predetermined word line. In response to a request, a sense amplifier activation circuit that sequentially activates a plurality of sense amplifiers and the same memory cell connected to the predetermined word line in a state where the predetermined word line is selected by the word driver. And an address determination circuit that temporarily stops the operation of the sense amplifier activation circuit in response to the requested read operation being requested. To.

  According to another aspect of the present invention, there is provided a method for controlling a semiconductor memory device comprising: a plurality of word lines; a plurality of bit lines; a plurality of memory cells arranged at intersections of the word lines and the bit lines; A method of controlling a semiconductor memory device comprising a word driver to be selected and a plurality of sense amplifiers connectable to any of a plurality of bit lines, wherein a predetermined word line is selected by the word driver In response to a request for continuous read operation for a plurality of memory cells connected to a word line, a plurality of sense amplifiers are sequentially activated, and a predetermined word line is selected by a word driver. In response to a request for a continuous read operation to the same memory cell connected to the word line, the activation of the sense amplifier is temporarily stopped. .

  According to the present invention, since the plurality of sense amplifiers that can be connected to any of the plurality of bit lines are provided, it is possible to execute a read operation on a plurality of memory cells connected to the same word line in parallel. . As a result, even when the sensing operation takes time, data can be read at high speed by the parallel operation.

  In addition, when a read operation is continuously requested for the same memory cell, the activation of the sense amplifier is temporarily stopped by the address determination circuit, so that a plurality of sense amplifiers are connected in parallel to the same memory cell. Will not work. Thereby, it is possible to avoid data destruction caused by a plurality of sense amplifiers operating in parallel on the same memory cell.

  As a result, since a high-speed read operation can be performed on an arbitrary address, for example, even if the object of the present invention is a PRAM, compatibility with a DRAM can be ensured.

1 is a block diagram showing a structure of a semiconductor memory device according to a preferred embodiment of the present invention. 2 is a circuit diagram for explaining the structure of a memory cell array 11 in more detail. FIG. 3 is a circuit diagram of a memory cell MC. FIG. 3 is a circuit diagram of a first sense amplifier 61. FIG. FIG. 6 is a timing chart for explaining the operation of the first sense amplifier 61. 3 is a circuit diagram of a determination output control circuit 43. FIG. 3 is a circuit diagram of an address determination circuit 34. FIG. 3 is a circuit diagram of a sense amplifier starting circuit 42. FIG. 4 is a timing chart for explaining the operation of the semiconductor memory device 10. FIG. FIG. 6 is a schematic timing diagram for explaining parallel operations of sense amplifiers 61 and 62; It is a schematic timing diagram for explaining the parallel operation of the sense amplifiers 61-63.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a block diagram showing a structure of a semiconductor memory device according to a preferred embodiment of the present invention.

  As shown in FIG. 1, the semiconductor memory device 10 according to the present embodiment includes a memory cell array 11 including a plurality of memory cells, a plurality of address terminals 21 that receive an address signal ADD, and a plurality of command terminals 22 that receive a command signal CMD. And a clock terminal 23 for receiving the external clock signal CK and a data terminal 24 for inputting / outputting data DQ. Although not particularly limited, the semiconductor memory device 10 according to the present embodiment is a synchronous semiconductor memory device that operates in synchronization with the external clock signal CK.

  An address signal ADD input via the address terminal 21 is supplied to the address buffer 31. Among the address signals ADD supplied to the address buffer 31, the row address XAD is supplied to the row decoder 32, and the column address is supplied to the column decoder 33 and the address determination circuit 34. Details of the memory cell array 11 and the address determination circuit 34 will be described later.

  The row decoder 32 is a circuit that decodes a row address XAD and supplies a decoding result to a word driver (WD) in the memory cell array 11. As a result, one of the plurality of word lines included in the memory cell array 11 is selected.

  The column decoder 33 is a circuit that decodes the column address YAD and supplies the decoding result to the column switch (YSW) in the memory cell array 11. As a result, one of the plurality of column switches becomes conductive.

  A command signal CMD input via the command terminal 22 is supplied to the command decoder 41. The command decoder 41 is a circuit that generates various internal commands by analyzing the command signal CMD. The command decoder 41 generates various internal commands. FIG. 1 shows only the read enable signal CYE, the reset signal RST, and the sense amplifier selection signals SA1 and SA2. Since other internal commands are not directly related to the gist of the present invention, description thereof is omitted.

  The read enable signal CYE is supplied to the sense amplifier activation circuit 42 and the determination output control circuit 43. The reset signal RST is supplied to the determination output control circuit 43, and the sense amplifier selection signals SA 1 and SA 2 are supplied to the sense amplifier activation circuit 42. Details of the sense amplifier activation circuit 42 and the determination output control circuit 43 will be described later.

  An external clock signal CK input via the clock terminal 23 is supplied to the clock control circuit 51. The clock control circuit 51 is a circuit that generates various internal clocks based on the external clock signal CK. Although the clock control circuit 51 generates various internal clocks, only the latch clock CLK is shown in FIG. Since other internal clocks are not directly related to the gist of the present invention, description thereof is omitted. The latch clock CLK is supplied to the address determination circuit 34 and the determination output control circuit 43.

  Data read from the memory cell array 11 is amplified by the first and second sense amplifiers 61 and 62. The sense amplifiers 61 and 62 are activated by sense amplifier activation signals SAE1 and SAE2, respectively. The sense amplifier activation signals SAE1 and SAE2 are signals supplied from the sense amplifier activation circuit 42. Although details will be described later, these sense amplifiers 61 and 62 can operate in parallel with each other, thereby shortening the read cycle.

  The outputs of the sense amplifiers 61 and 62 are supplied to the output control circuit 70 via the data bus BUS. The output control circuit 70 includes a FIFO circuit 71 and an output circuit 72, and outputs read data DQ supplied via the data bus BUS from the data terminal 24. The output of the read data DQ is performed in synchronization with the external clock signal CK. In addition, a latch circuit 73 is provided on the data bus BUS, so that the data on the data bus BUS maintains the previous state unless the read data output from the sense amplifiers 61 and 62 changes accordingly.

  In FIG. 1, only one data terminal 24 is shown. However, the present invention is not limited to this, and a plurality of (for example, 16) data terminals 24 may be provided according to specifications. Absent. For example, when 16 data terminals 24 are provided, 16 sets of circuit groups including the sense amplifiers 61 and 62, the data bus BUS, and the output control circuit 70 may be provided. As a result, 16-bit read data can be output at a time.

  FIG. 2 is a circuit diagram for explaining the structure of the memory cell array 11 in more detail.

As shown in FIG. 2, the memory cell array 11 includes a plurality of memory mats MAT ₁₁ , MAT ₁₂ , MAT ₁₃ ..., And first and second transfer lines assigned in common to the plurality of memory mats. TRL1 and TRL2 are included. The transfer lines TRL1 and TRL2 are connected to the first and second sense amplifiers 61 and 62, respectively.

Each of the memory mats MAT ₁₁ , MAT ₁₂ , MAT ₁₃ ... Is configured by a plurality of word lines WL1 to WLm, a plurality of bit lines BL1 to BLn, and memory cells MC arranged at intersections thereof. . The selection of the word lines WL1 to WLm is performed by the word driver WD, and any one of the word lines WL1 to WLm is activated. The operation of the word driver WD is controlled by the row decoder 32 as described above. The bit lines BL1 to BLn are configured to be connectable to the global bit line GBL via the corresponding column switch YSW. The operation of the column switch YSW is controlled by the column decoder 33 as described above.

  In this embodiment, two global bit lines GBL are provided per memory mat. More specifically, one global bit line GBL1 (or GBL3) is assigned to odd-numbered bit lines BL1, BL3,... BLn-1, and even-numbered bit lines BL2, BL4,. Is assigned the other global bit line GBL2 (or GBL4). With such a configuration, it is possible to execute the read operation via the even-numbered bit lines in parallel during the read operation via the odd-numbered bit lines. Of course, the reverse is also possible.

  In contrast, during a read operation via an odd-numbered bit line (for example, BL1), a read operation via another odd-numbered bit line (for example, BL3) cannot be executed in parallel. Similarly, during a read operation via an even-numbered bit line (for example, BL2), a read operation via another even-numbered bit line (for example, BL4) cannot be executed in parallel. This is because such a bit line selection causes data collision on the same global bit line. However, if any bit line is selected from the odd-numbered or even-numbered bit lines depending on the row address, the odd-numbered or even-numbered bit lines are not continuously selected. .

Although not particularly limited, in the present embodiment, among the memory mats MAT sharing the transfer lines TRL1, TRL2, the same row address is assigned to two memory mats adjacent in the row direction. For example, the same row address is supplied to the word drivers WD corresponding to the memory mats MAT ₁₂ and MAT ₂₂ . Therefore, the word lines included in the memory mat MAT ₁₂ and the word lines included in the MAT ₂₂ are selected at the same time. Therefore, the word lines selected at the same time may be short-circuited in advance.

  With this configuration, it is possible to select four bit lines in succession using the four global bit lines GBL1 to GBL4. In other words, it is possible to continuously execute the read operation through the four bit lines in a state where the row address is determined and a predetermined word line is selected. However, the present invention is not limited to this, and, for example, it is possible to configure to enable continuous access of 8 bits or 16 bits.

  FIG. 3 is a circuit diagram of the memory cell MC.

  As shown in FIG. 3, the memory cell MC includes a phase change memory element PC made of a phase change material and a selection transistor Tr, which are connected in series between a bit line BL and a source line VSS.

The phase change material constituting the phase change memory element PC is not particularly limited as long as it is a material that takes two or more phase states and has different electric resistances depending on the phase states, but it is preferable to select a so-called chalcogenide material. The chalcogenide material refers to an alloy containing at least one element such as germanium (Ge), antimony (Sb), tellurium (Te), indium (In), and selenium (Se). As an example, binary elements such as GaSb, InSb, InSe, Sb ₂ Te ₃ and GeTe, ternary elements such as Ge ₂ Sb ₂ Te ₅ , InSbTe, GaSeTe, SnSb ₂ Te ₄ and InSbGe, AgInSbTe, (GeSn ) Quaternary elements such as SbTe, GeSb (SeTe), Te ₈₁ Ge ₁₅ Sb ₂ S _{2 and the} like.

  Phase change materials including chalcogenide materials can take either an amorphous phase (amorphous phase) or a crystalline phase. The amorphous phase has a relatively high resistance state and the crystalline phase has a relatively low resistance. It becomes a state.

  The selection transistor Tr is composed of an N-channel MOS transistor, and its gate electrode is connected to the corresponding word line WL. Thereby, when the word line WL is activated, the phase change memory element PC is connected between the bit line BL and the source line VSS.

  In order to make the phase change material amorphous (reset), the phase change material may be heated to a temperature equal to or higher than the melting point by applying a write current, and then rapidly cooled. On the other hand, in order to crystallize (set) the phase change material, the phase change material may be heated to a temperature higher than the crystallization temperature and lower than the melting point by applying a write current, and then gradually cooled. Such application of the write current is supplied by a write circuit (not shown). However, since the data write operation is not directly related to the present invention, the description related to the data write is omitted.

  On the other hand, data is read by turning on the selection transistor Tr to connect the phase change memory element PC to the bit line BL and supplying a read current in this state. The read current is set to a value sufficiently smaller than the write current so as not to cause a phase change. Therefore, unlike the DRAM, the memory cell MC can be read nondestructively. In addition, since the phase state of the phase change material does not change unless high heat is applied, data is not lost even when the power is turned off. A circuit related to data reading and its operation will be described in detail later.

  Returning to FIG. 2, the transfer switch TSW includes a first transfer switch TSW1 connected to the first transfer line TRL1 and a second transfer switch TSW2 connected to the second transfer line TRL2. . These transfer switches TSW1 and TSW2 are exclusively turned on in response to the transfer signal S30. Therefore, the selected memory cell MC is connected to the first sense amplifier 61 when the first transfer switch TSW1 is turned on, and is connected to the second sense amplifier 62 when the second transfer switch TSW2 is turned on. It will be.

As described above, transfer lines TRL1, TRL2 is assigned in common to a plurality of memory mats _{MAT 11, MAT 12, MAT 13} ···. Therefore, the first and second sense amplifiers 61 and 62 are also commonly assigned to the plurality of memory mats MAT ₁₁ , MAT ₁₂ , MAT ₁₃ . That is, two readout circuits are provided for the plurality of memory mats MAT ₁₁ , MAT ₁₂ , MAT ₁₃ .

In a general semiconductor memory device such as a DRAM, a sense amplifier is assigned to each bit line pair, so that the sense amplifier is often arranged inside a cell array. However, in the PRAM, when reading data, it is necessary to convert the content held in the memory cell MC into a potential difference by flowing a read current through the phase change memory element PC, and to amplify the potential difference. For this reason, the circuit scale of the PRAM sense amplifier is much larger than that of the DRAM sense amplifier. For this reason, in this embodiment, the sense amplifiers 61 and 62 are commonly assigned to the plurality of memory mats MAT ₁₁ , MAT ₁₂ , MAT ₁₃ .

  FIG. 4 is a circuit diagram of the first sense amplifier 61.

  As shown in FIG. 4, the first sense amplifier 61 includes a conversion circuit 100, an amplification circuit 200, and a timing signal generation circuit 300. The conversion circuit 100 is a circuit that converts the content held in the memory cell MC into a potential difference, and the amplifier circuit 200 is a circuit that amplifies the potential difference generated by the conversion circuit 100. The timing signal generation circuit 300 is a circuit that generates the precharge signal S11, the sense activation signal S12, and the latch signal S13, and responds to the activation of the sense amplifier activation signal SAE1 supplied from the sense amplifier activation circuit 42. Thus, these signals S11 to S13 are generated.

  As shown in FIG. 4, the conversion circuit 100 is connected between the internal node A and the ground wiring, and the read transistor 101 and the precharge transistor 102 connected in parallel between the internal node A and the power supply wiring. And a reset transistor 103.

  The read transistor 101 is a P-channel MOS transistor, and plays a role of supplying a read current to the transfer line TRL1 via the diode-connected transistor 111 and the current limiting circuit 120. The precharge transistor 102 is also a P-channel MOS transistor, and plays a role of precharging the transfer line TRL1 via the diode-connected transistor 112 and the current limiting circuit 120. This is because, since the transfer line TRL1 is lowered to the ground level in the period before reading, it is necessary to quickly increase the potential to a readable level. Therefore, the current supply capability of the precharge transistor 102 is designed to be sufficiently higher than the current supply capability of the read transistor 101.

  The reset transistor 103 is an N-channel MOS transistor and plays a role of lowering the transfer line TRL1 to the ground level after the reading is completed.

  A precharge signal S 11 is supplied to the gate of the precharge transistor 102. For this reason, when the precharge signal S11 becomes the active level (low level), the transfer line TRL1 is quickly precharged. The sense activation signal S12 is commonly supplied to the gates of the read transistor 101 and the reset transistor 103. Therefore, when the sense activation signal S12 becomes active level (low level), a read current is supplied to the transfer line TRL1, and when it becomes inactive level (high level), the transfer line TRL1 is connected to the ground level.

  On the other hand, the amplifier circuit 200 includes a differential circuit unit 210, a latch unit 220, and an output circuit 230.

  The differential circuit unit 210 compares the potential of the internal node A with the reference potential Vref. When the sense activation signal S12 becomes an active level, the differential circuit unit 210 performs a comparison operation and generates a large potential difference between the internal nodes B and C. Let The latch unit 220 is a circuit that holds the output of the differential circuit unit 210, and executes a latch operation when the latch signal S13 becomes an active level (high level). Furthermore, the output circuit 230 is a circuit that drives the data bus BUS based on the output of the differential circuit unit 210, and executes an output operation when the latch signal S13 becomes an active level.

  The above is the circuit configuration of the first sense amplifier 61. The second sense amplifier 62 is shown in FIG. 4 except that the conversion circuit 100 is connected to the second transfer line TRL2 and the sense amplifier activation signal SAE2 is supplied to the timing signal generation circuit 300. The first sense amplifier 61 has the same circuit configuration.

  FIG. 5 is a timing diagram for explaining the operation of the first sense amplifier 61.

  In a state before reading data using the first sense amplifier SA1 (before time t1), both the precharge signal S11 and the sense activation signal S12 are at a high level. As a result, the reset transistor 103 is turned on, so that the transfer line TRL1 is kept at the ground level.

  When the precharge signal S11 and the sense activation signal S12 are activated to a low level at time t1, the reset transistor 103 is turned off and the read transistor 101 and the precharge transistor 102 are turned on, so that the transfer line TRL1 is precharged. Charged. As a result, the potential of the internal node A rises to near the reference potential Vref.

  Next, at time t2, a predetermined transfer signal S30 is activated. As a result, the first transfer switch TSW1 corresponding to the memory mat MAT to be read is turned on. As a result, the capacitance of the transfer line TRL1 as viewed from the sense amplifier SA1 increases, so that the potential of the internal node A rapidly decreases. However, since the read transistor 101 and the precharge transistor 102 are on, the precharge operation proceeds and the potential of the internal node A rises again to the vicinity of the reference potential Vref.

  Next, at time t3 when the precharge is completed, the precharge signal S11 is deactivated to a high level. The sense activation signal S12 is kept active. Thus, the current supplied to the transfer line TRL1 is only the read current via the read transistor 101.

  Therefore, if the memory cell MC to be read is in a high resistance state, that is, if the phase change memory element PC is in an amorphous state (reset state), the potential of the internal node A becomes higher than the reference potential Vref. On the other hand, if the memory cell MC to be read is in a low resistance state, that is, if the phase change memory element PC is in a crystalline state (set state), the potential of the internal node A is lower than the reference potential Vref.

  Thus, a predetermined potential difference is generated between the internal node A and the reference potential Vref according to the contents held in the memory cell MC. In response to this, the differential circuit unit 210 included in the amplifier circuit 200 causes a large potential difference between the internal nodes B and C.

  Next, at time t4, the sense activation signal S12 is deactivated to a high level, and the latch signal S13 is activated to a high level. As a result, the latch unit 220 included in the amplifier circuit 200 raises one of the internal nodes B and C to the power supply potential and lowers the other to the ground level, and maintains this state. The held information is output to the data bus BUS via the output circuit 230.

  Since the read data is held after the latch unit 220 included in the amplifier circuit 200 is activated, the connection between the memory cell MC and the sense amplifier SA1 is unnecessary. For this reason, the transfer signal S30 is inactivated at time t5, which is immediately after time t4.

  Then, after the reading of data via the data bus BUS is completed, the latch signal S13 is deactivated to a low level at time t6. As a result, the state of each signal returns to the state before time t1, so that the next read operation using the same sense amplifier 61 can be started.

  The above is the operation of the sense amplifier 61. In the present embodiment, since two such sense amplifiers are provided, these two sense amplifiers can be operated in parallel. The parallel operation of the sense amplifier will be described later.

  FIG. 6 is a circuit diagram of the determination output control circuit 43.

  As shown in FIG. 6, the determination output control circuit 43 includes two latch circuits 43a and 43b connected in cascade and an AND circuit 43c. Each of the latch circuits 43a and 43b has an input node D, an output node Q, a clock node C, and a reset node R, and the logic of the input node D is synchronized with the latch clock CLK supplied to the clock node C. Latch the level. The latched logic level is output from the output node Q. The reset signal RST is supplied to the reset node R. When the reset signal RST is activated, the latch contents of the latch circuits 43a and 43b are reset to a low level. The reset signal RST is a signal that is activated when the power is turned on or reset.

  A read enable signal CYE is supplied to the input node D of the preceding latch circuit 43a. The output node Q is connected to the input node D of the latch circuit 43b at the subsequent stage. The AND circuit 43c is a circuit that generates the determination permission signal CMPEN, and the read enable signal CYE is supplied to one input node, and the output of the latch circuit 43b in the subsequent stage is supplied to the other input node.

  With such a circuit configuration, the determination output control circuit 43 activates the determination permission signal CMPEN when the read enable signal CYE is generated twice consecutively in synchronization with the latch clock CLK. The determination permission signal CMPEN generated by the determination output control circuit 43 is supplied to the address determination circuit 34 shown in FIG.

  FIG. 7 is a circuit diagram of the address determination circuit 34.

As shown in FIG. 7, the address determination circuit 34 includes a comparator circuit ₃₄ 0 to 34C _k equal in number to the number of bits of the column address YAD (k + 1 bit), and a NAND circuit 34d. The comparison circuits 34 _{0 to} 34 _k are supplied with the bits YAD _{0 to} YADk constituting the column address YAD, respectively.

The comparison circuits 34 _{0 to} 34 _k have the same circuit configuration, and as shown in FIG. 7, are configured by two latch circuits 34 a and 34 b connected in cascade and an EXNOR (exclusive non-OR) circuit 34 c. Has been. Each of the latch circuits 34a and 34b has an input node D, an output node Q, and a clock node C, and latches the logic level of the input node D in synchronization with the latch clock CLK supplied to the clock node C. . The latched logic level is output from the output node Q.

  A corresponding bit of the column address YAD is supplied to the input node D of the latch circuit 34a in the previous stage. The output node Q is connected to the input node D of the latch circuit 34b at the subsequent stage. The EXNOR circuit 34c is a circuit that generates the coincidence signal HIT, and the corresponding bit of the column address YAD is supplied to one input node, and the output of the subsequent latch circuit 34b is supplied to the other input node. .

With such a circuit configuration, each of the comparison circuits 34 _{0 to} 34 _k activates the coincidence signal HIT when the corresponding bits of the column address YAD are at the same logical level twice in succession. All the coincidence signals HIT from the comparison circuits 34 _{0 to} 34 _k are supplied to the NAND circuit 34 d. Further, the determination permission signal CMPEN generated by the determination output control circuit 43 is input to the NAND circuit 34d.

  Thereby, the address determination circuit 34 activates the sense stop signal SASTP to a low level when the condition that the determination permission signal CMPEN is activated and the column address YAD is continuously the same value is satisfied. .

  This condition is satisfied when the row address is fixed and the same column address YAD is specified and read commands are issued continuously (case 1), or the row address is fixed. In this state, a case where the read command is issued by designating the same column address as the last column address YAD of the burst operation (Case 2) is applicable. Here, the condition is that the “row address is fixed” because the determination permission signal CMPEN is not activated unless a continuous read operation is performed with the row address fixed. . In the state where the row address is fixed, the predetermined word line is kept selected.

  The sense stop signal SASTP generated in this way is supplied to the sense amplifier activation circuit 42 shown in FIG.

  FIG. 8 is a circuit diagram of the sense amplifier starting circuit 42.

  As shown in FIG. 8, the sense amplifier starting circuit 42 includes two AND circuits 42a and 42b. The AND circuits 42a and 42b are commonly supplied with a sense stop signal SASTP and a read enable signal CYE, and individually supplied with sense amplifier selection signals SA1 and SA2. The sense amplifier selection signals SA1 and SA2 are used to select which of the sense amplifiers 61 and 62 is used during a read operation, and are alternately activated at least during a continuous read operation.

  With such a configuration, during the read operation, one of the sense amplifier activation signals SAE1 and SAE2 is activated to a high level in synchronization with the read enable signal CYE. However, when the sense stop signal SASTP is at a low level, the sense amplifier selection signals SA1 and SA2 are masked, and the sense amplifier activation signals SAE1 and SAE2 are both held at a low level. The conditions for the sense stop signal SASTP to be at the low level are as described above.

  The above is the configuration of the semiconductor memory device 10 according to the present embodiment. Next, the operation of the semiconductor memory device 10 according to the present embodiment will be explained.

  FIG. 9 is a timing chart for explaining the operation of the semiconductor memory device 10.

  In the example shown in FIG. 9, a read command is issued in synchronization with the active edges CK0, CK1, CK2, CK4, and CK5 of the external clock signal CK, and the designated column address YAD has the value shown in FIG. Show. Although not shown in FIG. 9, the active command is issued before the active edge CK0. As a result, at least after the active edge CK0, the row address is determined. That is, a state where a predetermined word line is selected is maintained.

  As shown in FIG. 9, every time a read command (READ) is issued, the read enable signal CYE is activated. Further, the sense amplifier activation signals SAE1 and SAE2 are alternately activated with respect to the external clock signal CK or the read enable signal CYE, whereby the sense amplifiers 61 and 62 are alternately selected. For example, as shown in FIG. 9, when the sense amplifier activation signals SAE1 and SAE2 are alternately activated with respect to the external clock signal CK, the sense amplifier is applied to a read command synchronized with the active edges CK0, CK2 and CK4. The activation signal SAE1 is activated, whereby the sense amplifier 61 is selected. For a read command synchronized with the active edge CK1, the sense amplifier activation signal SAE2 is activated, thereby selecting the sense amplifier 62. In contrast, when the sense amplifier activation signals SAE1 and SAE2 are activated alternately with respect to the read enable signal CYE, the sense amplifier activation signal SAE1 is activated and activated for a read command synchronized with the active edges CK0 and CK2. The sense amplifier activation signal SAE2 is activated in response to a read command synchronized with the edges CK1 and CK4. Although FIG. 9 shows an example in which the sense amplifier activation signals SAE1 and SAE2 are activated alternately with respect to the clock signal CK, the present invention is not limited to this.

  Further, since the read command synchronized with the active edges CK1, CK2, and CK5 corresponds to the second (or more) consecutive read commands, the determination permission signal CMPEN is activated in response thereto. As described above, when the determination permission signal CMPEN is activated, the determination operation by the address determination circuit 34 is permitted.

  However, in the read command synchronized with the active edge CK1, the column address YAD (0001) different from the column address YAD (0000) specified in the immediately preceding (CK0) read operation is specified. SASTP is not activated and maintains a high level. Similarly, in the read command synchronized with the active edge CK2, since the column address YAD (0002) different from the column address YAD (0001) specified in the immediately preceding read operation (CK1) is specified, the sense stop is performed. The signal SASTP is not activated and maintains a high level.

  As described above, even when the read command is issued continuously, if the designated column address YAD is different, the sense stop signal SASTP is held at the high level, so that the sense amplifier activation signal SAE1, SAE2 is activated alternately, and the parallel operation by the sense amplifiers 61 and 62 is executed. The parallel operation of the sense amplifiers 61 and 62 will be described later.

  On the other hand, in the read command synchronized with the active edge CK4, the same column address YAD (0002) as the column address YAD (0002) specified in the previous (CK2) read operation is specified, but immediately before (CK3). Since the synchronized read enable signal CYE is not generated, the determination permission signal CMPEN is inactive. As a result, the sense stop signal SASTP maintains a high level.

  On the other hand, in the read command synchronized with the active edge CK5, the same column address YAD (0002) as the column address YAD (0002) specified in the immediately preceding (CK4) read operation is specified. For this reason, the sense stop signal SASTP is activated to a low level. As a result, the sense amplifier selection signal (SA2 in this case) is masked, and the sense amplifier activation signal SAE2 that should have been activated remains at the low level. As a result, the sensing operation for the designated column address YAD (0002) is not performed.

  However, in this embodiment, since the latch circuit 73 is provided on the data bus and the immediately preceding read data is held, correct read data (DATA0002) can be output without performing a sensing operation. It becomes possible.

  As described above, in the present embodiment, when a condition occurs in which the two sense amplifiers 61 and 62 operate in parallel with respect to the same memory cell, the sense amplifier selected later (in the example shown in FIG. 9). The operation of the sense amplifier 62) is stopped. Therefore, it is possible to output correct read data while preventing data destruction due to a plurality of sense amplifiers operating in parallel on the same memory cell.

  Patent Document 5 describes a semiconductor memory device that outputs previous read data without accessing a memory cell when a continuous read operation is requested for the same address. However, the semiconductor memory device described in Patent Document 5 does not have a configuration in which a plurality of sense amplifiers can be connected to any of a plurality of bit lines, and therefore a plurality of sense amplifiers are used in parallel. It is impossible to perform high speed operation. Further, since the semiconductor memory device described in Patent Document 5 does not have the above-described configuration, no data is destroyed even if the read operation is continuously performed on the same address. In other words, the semiconductor memory device described in Patent Document 5 is different from the premise in the configuration of the present invention.

  FIG. 10 is a schematic timing diagram for explaining the parallel operation of the sense amplifiers 61 and 62.

  As shown in FIG. 10, the operation period T0 of the sense amplifiers 61 and 62 is composed of a precharge period T1, a conversion period T2, and an amplification period T3.

  The precharge period T1 is a period in which the potential of the transfer line TRL1 or the transfer line TRL2 is raised from the ground level to the precharge level, and corresponds to the period of time t1 to t3 shown in FIG. Therefore, this operation is executed by the conversion circuit 100.

  The conversion period T2 is a period in which the content held in the memory cell is converted into a potential difference by flowing a read current to the memory cell MC via the transfer line TRL1 or the transfer line TRL2. It corresponds to a period. Therefore, this operation is also executed by the conversion circuit 100.

  The amplification period T3 is a period for amplifying the potential difference between the potential of the internal node A and the reference potential Vref, and corresponds to the period of time t4 to t6 shown in FIG. Therefore, this operation is executed by the amplifier circuit 200.

  In this embodiment, since the sense amplifiers 61 and 62 can be operated in parallel, the read cycle is shortened to ½ of the operation period T0. However, as shown in FIG. 10, in this embodiment, since one sense amplifier starts the read operation of the other sense amplifier before entering the amplification period T3, the bit line connected to the same global bit line GBL is used. Cannot be selected in succession.

However, as already described, if different row addresses are assigned to a plurality of bit lines connected to the same global bit line GBL, the bit lines connected to the same global bit line GBL are not continuously selected. In the example shown in FIG. 2, since the global bit line GBL1~GBL4 the total of four are provided in the two memory mats same row address is assigned (e.g., memory mats _{MAT 12} and _{MAT 22),} column By switching the address YAD, a 4-bit read operation can be performed continuously.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

  For example, in the above-described embodiment, the case where the present invention is applied to the PRAM has been described as an example. However, the application target of the present invention is not limited to this, and may be applied to other types of semiconductor memory devices. Is possible. Therefore, instead of the phase change memory element PC included in the memory cell MC, another memory element (for example, a variable resistance element used in the RRAM) may be used. Further, it is not essential that the memory cell is non-volatile, and it may be volatile.

  Further, although it is not essential that the memory cell is a variable resistance element, a memory cell using a variable resistance element takes a longer time for sensing operation than a DRAM cell or the like. Application to a semiconductor memory device using this is very suitable. As described above, in such a type of semiconductor memory device, the circuit scale of the sense amplifier becomes very large, and therefore it is not practical to provide a sense amplifier for each bit line as in a DRAM.

  In the above embodiment, the two sense amplifiers 61 and 62 are operated in parallel. However, three or more sense amplifiers can be used in parallel. FIG. 11 is a diagram for explaining the operation when three sense amplifiers 61 to 63 are used in parallel. As shown in FIG. 11, if the three sense amplifiers 61 to 63 are used in parallel, the read cycle can be shortened to 1/3 of the operation period T0. Of course, if four or more sense amplifiers are used in parallel, the read cycle can be further shortened.

10 semiconductor memory device 11 the memory cell array 21 address terminal 22 a command terminal 23 a clock terminal 24 data terminal 31 an address buffer 32 row decoder 33 column decoder 34 address determination circuit ₃₄ 0 to 34C _k comparator circuit 34a, 34b, 43a, 43b latch circuit 34c EXNOR Circuit 34d AND circuit 41 Command decoder 42 Sense amplifier activation circuit 42a, 42b, 43c AND circuit 43 Determination output control circuit 51 Clock control circuit 61, 62 Sense amplifier 70 Output control circuit 71 FIFO circuit 72 Output circuit 73 Latch circuit 100 Conversion circuit 101 Read transistor 102 Precharge transistor 103 Reset transistor 111, 112 Transistor 120 Current limiting circuit 200 Amplifying circuit 210 Differential circuit section 220 Latch unit 230 Output circuit 300 Timing signal generation circuit BL Bit line BUS Data bus CMPEN Determination enable signal CYE Read enable signal GBL Global bit line MAT Memory mat MC Memory cell PC Phase change memory elements SAE1, SAE2 Sense amplifier activation signal SASTP Sense stop signal TRL1, TRL2 Transfer line TSW1, TSW2 Transfer switch WL Word line YSW Column switch

Claims (1)

Global bit lines,
First and second bit lines connected exclusively to the global bit line;
First and second memory cells connected to the first and second bit lines;
First and second sense amplifiers connected to the global bit line,
In response to a request for a read operation on the first memory cell, the first bit line is connected to the global bit line and the first sense amplifier is activated,
In response to a request for a read operation on the second memory cell during activation of the first sense amplifier, the second bit line is connected to the global bit line and the first bit is connected. 2. A semiconductor memory device, wherein two sense amplifiers are activated.

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