JP2014158189A - Optical device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an optical device capable of obtaining a stable power source voltage.SOLUTION: An optical device includes: a power source pin 11 which is connected with a power source circuit 80 including capacitors C10 and C11; a PD20 which generates photoelectric current in response to input light; and a microstrip line 28 which is serially connected with a power supply path between the power source pin 11 and the PD 20. The invention provides the optical device which obtains a stable power source voltage.

Description

  The present invention relates to an optical device.

  In an optical device that receives an optical signal, a light receiving element such as a photodiode (PD) that converts the optical signal into an electric signal is used. In order to transmit an electrical signal, a transmission path such as a strip line and a micro strip line is connected to the light receiving element. Patent Document 1 describes a light receiving device including a PD and a transimpedance amplifier.

JP 2012-69681 A

  The light receiving element is applied with a DC power supply voltage and converts an optical signal into a high-frequency electric signal. However, when the power supply voltage fluctuates, the characteristics of the optical device deteriorate. In view of the above problems, an object of the present invention is to provide an optical device capable of obtaining a stable power supply voltage.

  The present invention is connected in series to a power supply terminal connected to a constant power supply having a bypass capacitor, an optical element that generates a photocurrent with respect to input light, and a power supply path between the power supply terminal and the optical element. An optical device having a distributed constant line.

  In the above configuration, the optical element is connected between the power supply path and a ground potential, and the ground potential is connected to a ground-side terminal of the optical element via a ground pattern provided on a surface of an insulating material. The insulating material is provided on a casing connected to a ground potential, and the ground pattern is electrically connected to the casing by via wiring provided in the insulating material. It can be set as the structure which becomes.

  In the above configuration, the output terminal of the optical element may be connected to a ground potential via a resistor.

  In the above configuration, the distributed constant line may be a microstrip line.

  According to the present invention, it is possible to provide an optical device capable of obtaining a stable power supply voltage.

FIG. 1A is a cross-sectional view illustrating an optical device according to the first embodiment. FIG. 1B is a cross-sectional view illustrating a cross section taken along line AA in FIG. FIG. 2 is a circuit diagram illustrating an equivalent circuit of the optical device. FIG. 3 is a plan view illustrating an optical device according to a comparative example. FIG. 4 is a circuit diagram illustrating an equivalent circuit of the optical device.

  Examples of the present invention will be described.

  FIG. 1A is a plan view illustrating an optical device 100 according to the first embodiment. FIG. 1B is a cross-sectional view illustrating a cross section along the line AA in the vicinity of the carrier 14 of FIG.

  As shown in FIGS. 1A and 1B, the housing 10 of the optical device 100 houses a metal block 12 (conductor layer), a carrier 14, and a PD carrier 16 therein. The housing 10 is provided with a power supply pin 11 and a ground pin 13. A metal block 12 is provided on the inner bottom surface of the housing 10, and a carrier 14 and a PD carrier 16 are provided on the upper surface of the metal block 12. The metal block 12 is fixed to the inner bottom surface of the housing 10 connected to the ground potential by, for example, brazing.

  The carrier 14 has a function of a wiring board, and a ground pattern 18, a signal wiring 19, and a resistor R1 (load resistance) are provided on the upper surface thereof. The signal wiring 19, the ground pattern 18, and the metal block 12 constitute a transmission line for transmitting a high-frequency signal that is an output signal of the PD 20. Specifically, a coplanar line is formed in a region where the ground pattern 18 is disposed on both sides of the signal wiring 19. In the region where the ground pattern 18 is not disposed on both sides of the signal wiring 19, the signal wiring 19 and the metal block 12 on the lower surface thereof constitute a microstrip line. The signal wiring 19 is electrically connected to the ground pattern 18 via a resistor R1 provided on both sides thereof. Capacitors C1 and C2 are provided on the ground pattern 18. The ground pattern 18 is electrically connected to the metal block 12 through the via wiring 15 penetrating the carrier 14.

  On the upper surface of the PD carrier 16, wiring patterns 24, 25 and 26 and a resistor R2 are provided. Although not shown, the wiring patterns 24 and 25 on the upper surface of the PD carrier 16 are extended to the side surface of the PD carrier 16. Further, the wiring patterns 24 arranged on both sides of the wiring pattern 25 on the upper surface of the PD carrier 16 are commonly connected to the PD 20 and the resistor R2 on the side surface of the PD carrier 16. The wiring patterns 24 and 25 extended to the side surface of the PD carrier 16 are connected to the PD 20 on the side surface of the PD carrier 16. The cathode side electrode of the PD 20 is connected to the wiring pattern 24, and the anode side electrode (ground side terminal) of the PD 20 is connected to the wiring pattern 25. As will be described later, the cathode side electrode functions as an output terminal. The resistor R2 provided in the PD carrier 20 functions as a damping resistor for stabilizing the ground potential. The wiring pattern 25 is connected to the signal wiring 19 by a wire 70.

  The power supply pin 11 (power supply terminal) is electrically connected to one end (upper surface electrode) of the capacitor C <b> 1 via the wires 30 and 34 and the microstrip line 28. The microstrip line 28 has a structure in which a wiring pattern 28a is provided on the upper surface of an insulating material. The microstrip line 28 is provided on a conductive base 29. The pedestal 29 is electrically connected to the inner bottom surface of the metallic casing 10 by brazing. Since the base 29 is electrically connected to the ground pin 13 via the wire 32, the inner bottom surface of the housing 10 is connected to the ground potential. Further, the metal block 12 provided on the inner bottom surface of the housing 10 is also connected to the ground potential.

  One end (upper surface electrode) of the capacitor C1 is connected to one end (upper surface electrode) of the capacitor C2 via a wire 36, and one end of the capacitor C2 is connected to the wiring pattern 26 via a wire 38. The wiring pattern 26 is electrically connected to the cathode of the PD 20 via the resistor R2 and the wiring pattern 24. The other ends (lower surface electrodes) of the capacitors C1 and C2 are connected to the ground pattern 18. In this embodiment, the capacitors C1 and C2, the resistor R2, and the wiring patterns 24 and 26 are provided in pairs so as to be symmetric with respect to the line B.

  The signal wiring 19 is connected to the wiring 40 of the coaxial connector via the capacitor C3. The ground pattern 18 is connected to the wiring 42 of the coaxial connector via the resistor R3 (termination resistor), the transmission line 23, and the capacitor C4. The capacitors C3 and C4 function as a filter that cuts a direct current (DC) component of the signal. The wirings 40 and 42 are central conductors of a coaxial connector (not shown) provided on the side surface of the housing 10. This coaxial connector is connected to a differential circuit, which will be described later, provided outside the optical device 100.

  The optical signal enters the PD 20 through the lens 21 provided in the housing 10. The PD 20 converts an optical signal into an electric signal (photocurrent) and outputs it. A signal output from the cathode electrode of the PD 20 is input to the wiring 40 via the signal wiring 19 and the capacitor C3. The wiring 40 outputs a signal to a differential circuit provided outside the optical device 100. The wiring 42 outputs a ground potential to the differential circuit.

  FIG. 2 is a circuit diagram illustrating an equivalent circuit of the optical device 100. The power supply circuit 80 includes a power supply unit V1 and capacitors C10 and C11 which are bypass capacitors. The positive output of the power supply circuit 80 is connected to the power supply pin 11, and the negative output is connected to the ground pin 13. Capacitors C10 and C11 are capacitors connected in parallel to the positive side and the negative side of the power supply unit, and have a function for stabilizing the power supply output. In the example of FIG. 2, there are two bypass capacitors C10 and C11. However, the bypass capacitor may be a single capacitor or may be connected more. In the example of FIG. 2, the capacitor C11 has a capacitance value of 1 μF, and C13 has a capacitance value of 0.1 μF. The bypass capacitor is incorporated as a power supply circuit 80 integrally with the power supply unit V1, and may be provided on a circuit board different from the power supply unit V1.

  The inductor L1 corresponds to the wire 30. The inductor L2 corresponds to the wiring pattern 28a, and the capacitor Ca corresponds to the dielectric constant of the insulating material of the microstrip line 28. The inductor L3 corresponds to the wire 34, the inductor L4 corresponds to the wire 36, and the inductor L5 corresponds to the wire 38. On the other hand, a signal wiring 19 is connected to the output side of the PD 20. In the region where the ground pattern 18 is provided on both sides of the signal wiring 19, a transmission line by the coplanar line 22a is formed. Further, in a region where the ground pattern 18 is not provided on both sides of the signal wiring 19, a transmission line by the microstrip line 22b is configured. The inductor L6 corresponds to the signal line 19 in the coplanar line 22a, and the capacitor C5 is a capacitance between the signal line 19 and the ground pattern 18. The inductor L7 corresponds to the signal wiring 19 in the microstrip line 22b, and the capacitor C7 is a capacitance between the signal wiring 19 and the metal block 12. The wiring 40 is a transmission line connected to the output end (corresponding to the output terminal Out1) on the coaxial connector side, and is configured by the inductor L8 and the capacitor C8 between the inductor L8 and the housing 10 (or the metal block 12). Is done. The wiring 42 is a transmission line connected to the output end (corresponding to the output terminal Out2) on the coaxial connector side, and is configured by the inductor L8 and the capacitor C8 between the inductor L8 and the housing 10 (or the metal block 12). Is done. The wiring 42 is connected to the ground pattern 18 via the capacitor C4 and the resistor R3. A transmission line 23 is provided between the capacitor C4 and the resistor R3. The transmission line 23 includes an inductor L7 and a capacitor C7 between the inductor L7 and the metal block 12. The inductor L12 corresponds to the via wiring 15. That is, since the diameter of the via wiring 15 is small, the inductor L12 is interposed between the ground pattern 18 and the metal block 12. Since the metal block 12 and the inner bottom surface of the housing 10 are electrically connected with a large area, the inductance between them is negligible. As shown in FIG. 2, the resistor R <b> 3 is connected to the ground pattern 18 in this embodiment.

  As shown in FIG. 1A, when the power supply pin 11 is arranged at a position away from the PD 20, the length of the wiring for supplying power is increased according to the distance. If power is supplied using the microstrip line 28 which is a distributed constant line as in this embodiment, only a certain characteristic impedance (for example, 50Ω) is interposed in the section of the distributed constant line regardless of the distance. It becomes.

  Incidentally, noise may flow out to the power supply pin 11 side (positive potential side) when viewed from the PD 20 because the PD 20 detects the optical input signal. Since this noise fluctuates the power supply potential of the PD 20, it causes the operation of the PD 20 to become unstable.

  In this embodiment, there is a section in which power is supplied by the distributed constant line between the noise source PD20 and the power supply pin 11, so that the impedance is lower than that in the case where the section is connected by a bonding wire. Can be connected. For this reason, even if noise is applied from the PD 20 to the positive potential side, the noise is stabilized by the bypass capacitor in the power supply circuit 80. As a result, the potential on the positive potential side can be maintained stably. This effect is more advantageous as the section of the distributed constant line is longer. Further, sections other than the distributed constant line are connected by wires, but shorter wires are advantageous from the viewpoint of reducing inductance. The physical length of the distributed constant line is preferably the longest of the single or plural wires connected from the power supply pin 11 to the PD 20.

  Capacitors C1 and C2 can be expected to function as a bypass capacitor in the same manner as capacitors C10 and C11. However, in order to realize a large capacity, the size of the capacitor component increases, which is not realistic. Further, when the ground potential sides of the capacitors C1 and C2 are connected to the ground pattern 18 on the carrier 14 as in this embodiment, the capacitors C1 and C2 may not function as a bypass capacitor. That is, as shown in FIGS. 1A and 2, the inductor L <b> 12 including the via wiring 15 is interposed between the ground pattern 18 and the potential (ground potential) of the metal block 12 (or the housing 10). The impedance of the inductor L12 increases particularly on the high frequency side, and the degree of separation from the stable ground potential of the metal block 12 increases. In this case, if the path connecting between the capacitors C1 and C2 and the metal block having a stable potential has a high impedance, the capacitors C1 and C2 are difficult to function as bypass capacitors. On the other hand, even in such a case, if a section of distributed constant lines is prepared for power supply as shown in the present embodiment, the power supply is stabilized. In order for the capacitors C10 and C11 to function as bypass capacitors, the capacitance values of the capacitors C10 and C11 are preferably larger than the capacitors C1 and C2.

  FIG. 3 is a plan view illustrating an optical device 100R according to a comparative example. In FIG. 3, parts corresponding to those in FIG. As shown in FIG. 3, in the comparative example, a section between the power supply pin 11 and the capacitor C <b> 1 is connected by a wire 30. The ground pin 13 is connected to the bonding point 10 a of the housing 10.

  FIG. 4 is an equivalent circuit of the optical device 100R. As shown in FIG. 4, an inductor L1 made of a wire 30 is interposed between the power supply pin 11 and the capacitor C1. Since the section to which the wire 30 is connected is largely separated, the wire 30 is also long, so the inductance of the inductor L1 is large.

  As described above, the wire 30 having a large inductance has a high impedance. Since the wire 30 has a high impedance, the capacitors C10 and C11 do not function effectively as a bypass capacitor against noise from the PD 20 side. For this reason, the power supply voltage becomes unstable.

The metal block 12 and the via wiring 15 shown in FIGS. 1A and 1B are made of a metal such as Kovar, gold (Au), and copper (Cu). The ground pattern 18 and the wiring patterns 24 and 26 are made of a metal such as Au or aluminum (Al). The carrier 14 and the PD carrier 16 are formed of an insulator such as aluminum oxide (Al ₂ O ₃ ). The wire is made of a metal such as Au. As a distributed constant line for supplying power between the power supply pin 11 and the PD 20, a coplanar line can be adopted in addition to the microstrip line 28 shown in the embodiment. A distributed constant line may be connected in series to the power supply path between the power supply pin 11 and the PD 20.

  Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. It can be changed.

DESCRIPTION OF SYMBOLS 10 Housing | casing 11 Power supply pin 12 Metal block 13 Ground pin 14 Carrier 15 Via wiring 16 PD carrier 18 Ground pattern 19 Signal wiring 20 PD
28 Microstrip line 40, 42 Wiring 80 Power supply circuit 100, 100R Optical device R1-R3 Resistance C1-C5, C7, C8, C10, C11, Ca capacitor Out1, Out2 Output terminal

Claims (4)

A power supply terminal connected to a constant power supply with a bypass capacitor;
An optical element that generates a photocurrent with respect to input light;
An optical device comprising: a distributed constant line connected in series to a power supply path between the power supply terminal and the optical element. The optical element is connected between the power supply path and a ground potential,
The ground potential is connected to the ground side terminal of the optical element via a ground pattern provided on the surface of the insulating material,
The insulating material is provided on a housing connected to a ground potential,
The optical device according to claim 1, wherein the ground pattern is electrically connected to the casing by via wiring provided in the insulating material.   The optical device according to claim 1, wherein an output terminal of the optical element is connected to the ground potential via a resistor. The optical device according to any one of claims 1 to 3, wherein the distributed constant line is a microstrip line.

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