JP2014038898A - Semiconductor device - Google Patents

Abstract

A semiconductor device having a high well breakdown voltage without causing deterioration of on-current is provided.
A gate electrode 6 is provided on a side surface of a channel region 3c provided in a convex semiconductor layer F on a semiconductor substrate 1 via a gate insulating film 5, and the side surface of the convex semiconductor layer F is provided. A field effect is applied to the channel region 3c. In addition, diffusion block layers 4p and 4n made of a material layer having a band gap larger than that of the convex semiconductor layer F are provided inside the convex semiconductor layer F. The diffusion block layers 4p and 4n prevent the majority carriers from diffusing from the source region and the drain region into the semiconductor substrate without increasing the impurity concentration of the channel region 3c, thereby improving the well breakdown voltage.
[Selection] Figure 1

Description

  Embodiments described herein relate generally to a semiconductor device.

  2. Description of the Related Art In recent years, with the miniaturization of semiconductor elements, three-dimensional elements such as Fin-type MOSFETs (hereinafter referred to as FinFETs) have attracted attention in place of planar MOSFETs (Metal Oxide Semiconductor Field Effect Transistors).

  The FinFET is formed on a surface portion of a semiconductor substrate, and has a convex semiconductor layer (fin: Fin) having a longitudinal direction and a short direction, and gate insulating films on both side surfaces of the semiconductor layer in the short direction. It has a structure including a formed gate electrode. A portion of the semiconductor layer sandwiched between the gate electrodes becomes a channel region. In the semiconductor layer, source / drain regions are formed on both sides of the channel region.

  FinFETs can be broadly classified into those using a bulk substrate and those using an SOI (Silicon On Insulator) substrate. A FinFET using a bulk substrate has an advantage that the transistor performance is less deteriorated due to self-heating, in addition to the advantage that the wafer cost is lower than that using an SOI substrate. On the other hand, the FinFET using a bulk substrate has a problem in that the off-leakage current is increased because the punch-through between the source and the drain becomes obvious at the bottom of the fin channel.

  As a technique for avoiding this problem, a technique for forming a punch-through stopper (PTS) made of an impurity layer at the bottom of the fin channel has been proposed.

JP 2002-118255 A

  The problem to be solved by the present invention is to provide a semiconductor device having a high well breakdown voltage without causing deterioration of on-current.

  According to one embodiment of the present invention, a source region and a drain region are provided in a convex semiconductor layer provided on a semiconductor substrate. A gate electrode is provided on the side surface of the convex semiconductor layer corresponding to the channel region formed between the source region and the drain region via a gate insulating film, and the channel region is formed via the side surface of the convex semiconductor layer. A field effect is given. A diffusion block layer made of a material having a band gap larger than that of the convex semiconductor layer is provided inside the convex semiconductor layer. This diffusion block layer prevents majority carriers from diffusing into the semiconductor substrate from the source and drain regions.

FIG. 1 is a perspective view showing a schematic configuration of a FinFET which is a semiconductor device according to the first embodiment. FIG. 2-1 is a plan view schematically showing the FinFET. FIG. 2-2 is a cross-sectional view schematically showing the FinFET, and is a cross-sectional view taken along line XX of FIG. 2-1. FIG. 2-3 is a cross-sectional view schematically showing the FinFET, and is a YY cross-sectional view of FIG. 2-1. FIG. 3A is a plan view schematically showing the FinFET for explaining the operation. 3-2 is a cross-sectional view schematically showing the FinFET for explaining the operation, and is a cross-sectional view taken along the line XX of FIG. 3-1. FIG. 4A is an explanatory diagram of a potential barrier for hole movement from a P-type semiconductor to an N-type semiconductor. FIG. 4B is an explanatory diagram of a potential barrier for electron transfer from the N-type semiconductor to the P-type semiconductor. FIG. 5A is a diagram illustrating a simulation result (PTS concentration dependency) of the well breakdown voltage. FIG. 5B is a diagram illustrating a simulation result (PTS concentration dependency) of the well breakdown voltage. FIG. 6A is a diagram illustrating a leakage current (electron current) distribution in the well in the well breakdown voltage simulation. FIG. 6B is a diagram illustrating a leakage current (hole current) distribution in the well in the well breakdown voltage simulation. FIG. 7 is a diagram showing a potential distribution in the well in the well breakdown voltage simulation. FIG. 8A is a diagram illustrating a potential distribution of a PQ cross section in FIG. 7. FIG. 8-2 is a diagram showing a potential distribution of the QR cross section in FIG. FIG. 9A is a diagram illustrating a potential distribution in the PQ cross section of FIG. 8A when the PTS concentration is 1 × 10 ¹⁷ (atoms / cm ³ ). FIG. 9B is a diagram illustrating a potential distribution in the PQ cross section of FIG. 8A when the PTS concentration is 1 × 10 ¹⁸ (atoms / cm ³ ). FIG. 9C is a diagram illustrating a potential distribution in the PQ cross section of FIG. 8A when the PTS concentration is 3 × 10 ¹⁸ (atoms / cm ³ ). FIG. 9-4 is a diagram showing a potential distribution in the PQ cross section of FIG. 8-1 when the PTS concentration is 5 × 10 ¹⁸ (atoms / cm ³ ). FIGS. 10A and 10B show a manufacturing process of the semiconductor device according to the first embodiment of the present invention, in which FIGS. 10A and 10B are sectional views, FIG. 10C is a plan view, and FIG. FIG. 6A is a cross-sectional view taken along the line AA in FIG. 10-2 shows the manufacturing process of the semiconductor device according to the first embodiment of the present invention, in which (a) and (b) are cross-sectional views, (c) is a plan view, and (a) is (c). FIG. 6A is a cross-sectional view taken along the line AA in FIG. FIGS. 10-3 shows the manufacturing process of the semiconductor device of the 1st Embodiment of this invention, (a) And (b) is sectional drawing, (c) is a top view, (a) is (c). FIG. 6A is a cross-sectional view taken along the line AA in FIG. FIGS. 10-4 shows a manufacturing process of the semiconductor device according to the first embodiment of the present invention, in which (a) and (b) are cross-sectional views, (c) are plan views, and (a) is (c). FIG. 6A is a cross-sectional view taken along the line AA in FIG. FIG. 10-5 illustrates a manufacturing process of the semiconductor device according to the first embodiment of the present invention, in which (a) and (b) are cross-sectional views, (c) is a plan view, and (a) is (c). FIG. 6A is a cross-sectional view taken along the line AA in FIG. FIG. 10-6 illustrates a manufacturing process of the semiconductor device according to the first embodiment of the present invention, in which (a) and (b) are cross-sectional views, (c) is a plan view, and (a) is (c). FIG. 6A is a cross-sectional view taken along the line AA in FIG. FIGS. 10-7 show the manufacturing steps of the semiconductor device of the first embodiment of the present invention, (a) and (b) are cross-sectional views, (c) are plan views, and (a) is (c). FIG. 6A is a cross-sectional view taken along the line AA in FIG. FIG. 10-8 illustrates a manufacturing process of the semiconductor device according to the first embodiment of the present invention, in which (a) and (b) are cross-sectional views, (c) is a plan view, and (a) is (c). FIG. 6A is a cross-sectional view taken along the line AA in FIG. 10-9 show the manufacturing steps of the semiconductor device according to the first embodiment of the present invention, in which (a) and (b) are cross-sectional views, (c) are plan views, and (a) is (c). FIG. 6A is a cross-sectional view taken along the line AA in FIG. 10-10 show the manufacturing steps of the semiconductor device according to the first embodiment of the present invention, in which (a) and (b) are cross-sectional views, (c) are plan views, and (a) is (c). FIG. 6A is a cross-sectional view taken along the line AA in FIG. FIGS. 10-11 show the manufacturing steps of the semiconductor device according to the first embodiment of the present invention, in which (a) and (b) are cross-sectional views, (c) are plan views, and (a) is (c). FIG. 6A is a cross-sectional view taken along the line AA in FIG. 10-12 show the manufacturing steps of the semiconductor device according to the first embodiment of the present invention, in which (a) and (b) are cross-sectional views, (c) are plan views, and (a) is (c). FIG. 6A is a cross-sectional view taken along the line AA in FIG. 10-13 show the manufacturing steps of the semiconductor device according to the first embodiment of the present invention, in which (a) and (b) are cross-sectional views, (c) are plan views, and (a) is (c). FIG. 6A is a cross-sectional view taken along the line AA in FIG. FIGS. 10-14 show the manufacturing process of the semiconductor device of the first embodiment of the present invention, (a) and (b) are cross-sectional views, (c) are plan views, and (a) is (c). FIG. 6A is a cross-sectional view taken along the line AA in FIG. 10-15 show the manufacturing steps of the semiconductor device according to the first embodiment of the present invention, in which (a) and (b) are cross-sectional views, (c) are plan views, and (a) is (c). FIG. 6A is a cross-sectional view taken along the line AA in FIG. 10-16 illustrate the manufacturing steps of the semiconductor device according to the first embodiment of the present invention, in which (a) and (b) are cross-sectional views, (c) are plan views, and (a) is (c). FIG. 6A is a cross-sectional view taken along the line AA in FIG. 10-17 show the manufacturing process of the semiconductor device according to the first embodiment of the present invention, in which (a) and (b) are cross-sectional views, (c) are plan views, and (a) is (c). FIG. 6A is a cross-sectional view taken along the line AA in FIG. 10-18 show the manufacturing steps of the semiconductor device according to the first embodiment of the present invention, in which (a) and (b) are cross-sectional views, (c) are plan views, and (a) is (c). FIG. 6A is a cross-sectional view taken along the line AA in FIG. 10-19 show the manufacturing steps of the semiconductor device according to the first embodiment of the present invention, in which (a) and (b) are cross-sectional views, (c) are plan views, and (a) is (c). FIG. 6A is a cross-sectional view taken along the line AA in FIG. 10-20 show the manufacturing steps of the semiconductor device according to the first embodiment of the present invention, in which (a) and (b) are cross-sectional views, (c) are plan views, and (a) is (c). FIG. 6A is a cross-sectional view taken along the line AA in FIG. FIG. 11 is a perspective view showing a semiconductor device according to the second embodiment of the present invention. FIG. 12 is a sectional view showing a semiconductor device according to the second embodiment of the present invention. FIG. 13 is a perspective view showing a semiconductor device according to the third embodiment of the present invention. FIG. 14 is a sectional view showing a semiconductor device according to the third embodiment of the present invention. FIG. 15 is a perspective view showing a semiconductor device according to the fourth embodiment of the present invention. FIG. 16 is a sectional view showing a semiconductor device according to the fourth embodiment of the present invention. FIG. 17 is a perspective view showing a semiconductor device according to the fifth embodiment of the present invention. FIG. 18 is a sectional view showing a semiconductor device according to the fifth embodiment of the present invention.

  Exemplary embodiments of a semiconductor device and a method for manufacturing the same will be described below in detail with reference to the accompanying drawings. Note that the present invention is not limited to these embodiments.

(First embodiment)
FIG. 1 is a perspective view illustrating a schematic configuration of a FinFET that is a semiconductor device according to the first embodiment, and FIG. 2A is a plan view schematically illustrating the FinFET. FIG. 2-2 is a cross-sectional view schematically showing the FinFET, and is a cross-sectional view taken along line XX of FIG. 2-1. FIG. 2-3 is a cross-sectional view schematically showing the FinFET, and is a YY cross-sectional view of FIG. 2-1. FIG. 3A is a plan view schematically showing the FinFET for explaining the operation, and FIG. 3-2 is a cross-sectional view schematically showing the FinFET for explaining the operation. 3-2 is a cross-sectional view taken along line XX in FIG. FIG. 4A is an explanatory diagram of a potential barrier for hole movement from a P-type semiconductor to an N-type semiconductor. FIG. 4B is an explanatory diagram of a potential barrier for electron transfer from the N-type semiconductor to the P-type semiconductor.

  The semiconductor device 100 of the present embodiment is a CMOSFET in which a first FinFET 10n constituting an N-channel FET and a second FinFET 10p constituting a P-channel FET are formed on the same substrate. In each of the first and second FinFETs 10n and 10p, in the FinFET (Bulk FinFET) formed on the surface of the bulk silicon substrate 1, silicon carbide (SiC) serving as diffusion block layers 4p and 4n, respectively, at the channel bottom. By forming the layer, the well breakdown voltage is improved without degrading the performance of the FinFET such as a decrease in on-current due to an increase in channel impurity concentration. Silicon carbide is a wide band gap material with a wider band gap than silicon. On the other hand, in the conventional Bulk FinFET, an impurity layer called a punch-through stopper (PTS) is formed at the channel bottom to suppress the punch-through current between the source and drain and improve the well breakdown voltage. There is a problem that impurities are implanted. With the configuration of this embodiment, it is possible to suppress the punch-through current between the source and drain and improve the well breakdown voltage without using PTS. Therefore, in the present embodiment, it is possible to suppress the punch-through current between the source and the drain and improve the well breakdown voltage without causing the performance degradation of the FinFET such as a decrease in the on-current due to the increase in the channel impurity concentration.

  In the semiconductor device 100 according to the present embodiment, a P well 2p and an N well 2n are formed on the surface of a p-type silicon substrate 1 as a semiconductor substrate, and convex semiconductor layers (in the P well 2p and the N well 2n, respectively) The fin) F includes a first FinFET (N channel FET) 10n and a second FinFET (P channel FET) 10p. In the first and second FinFETs 10n and 10p, the majority carriers diffuse from the source region 3s and the drain region 3d provided in the fin F into the substrate (here, the P well 2p and the N well 2n). Diffusion block layers 4p and 4n for preventing are provided. The diffusion block layers 4p and 4n are made of silicon carbide which is a material having a band gap larger than that of the silicon constituting the fin F. The impurity concentration of the diffusion block layers 4p and 4n is not zero, but is doped with a low concentration impurity. The impurity concentration is lower than the impurity concentration of the channel region 3c of the fin F or is different from that of the channel region 3c. It is about the same. Accordingly, the diffusion block layer 4p is formed of p-type lightly doped silicon carbide, while the diffusion block layer 4n is formed of n-type lightly doped silicon carbide.

  The first FinFET 10n is a fin corresponding to a source region 3s and a drain region 3d provided in a fin F made of a P-type silicon layer, and a channel region 3c formed between the source region 3s and the drain region 3d. A gate electrode 6 is provided on the side surface of F via the gate insulating film 5 and applies a field effect to the channel region 3c via the side surface of the fin F. Reference numeral 7 denotes an element isolation insulating layer (STI). Here, at the bottom of the fin F, a diffusion block layer 4p made of low-concentration P-type doped silicon carbide is formed. In the first FinFET 10n, the source region 3s and the drain region 3d are formed of an N-type silicon diffusion layer.

  The second FinFET 10p includes a fin corresponding to a source region 3s and a drain region 3d provided in a fin F made of an N-type silicon layer, and a channel region 3c formed between the source region 3s and the drain region 3d. A gate electrode 6 is provided on the side surface of F via the gate insulating film 5 and applies a field effect to the channel region 3c via the side surface of the fin F. Here, at the bottom of the fin F, a diffusion block layer 4n made of low-concentration N-type doped silicon carbide is formed. In the second FinFET 10p, the source region 3s and the drain region 3d are formed of a P-type silicon diffusion layer.

Fins F are formed on a P-well 2p and N-well formed on the single crystal silicon substrate 1 of p-type 2n, longitudinal and transverse direction (D ₁ direction in FIG. 1) (D ₂ direction in FIG. 1) And a semiconductor layer.

  The gate electrode 6 is made of titanium nitride (TiN), and is formed on the lateral side surface and the upper surface of the fin F via the gate insulating film 5 made of hafnium silicon oxynitride (HfSiON). The gate electrode 6 is also formed on the upper insulating film 8 made of silicon nitride formed on the fin F. The gate electrode 6 crosses over the element isolation insulating layer 7 and is common to the first and second FinFETs 10n and 10p. A side wall insulating film 9 covers the side surface of the gate electrode 6.

  In the fin F, both outer portions of the gate electrode 6 are a source region 3s and a drain region 3d. A portion of the fin F where the gate electrode 6 is formed between the source region 3s and the drain region 3d, that is, via the gate insulating film 5 is a channel region 3c. The source region 3s and the drain region 3d are covered with an epitaxial layer 3e formed by selective epitaxial growth (SEG) to reduce the source / drain parasitic resistance, and are thick. Similarly, the two fins F on both sides provided for the substrate contact are also thickly covered with the epitaxial layer 3e.

  An element isolation insulating layer 7 is formed between the gate electrode 6 and the silicon substrate 1 on the side surface in the short direction of the fin F. This element isolation insulating layer 7 is formed by a deposition method such as a plasma CVD method or a coating method after etching for fin formation. In the case of a coating method, for example, a coating film such as polysilazane is formed and then baked.

  The fin F is a silicon region having diffusion block layers 4p and 4n made of silicon carbide at the bottom of the fin channel.

  The diffusion block layers 4p and 4n made of silicon carbide function as a potential barrier against the diffusion of majority carriers in the source region 3s and the drain region 3d formed in the fin F into the P well 2p or the N well 2n. The diffusion block layers 4p and 4n are doped at a low concentration in the P-type and N-type on the P-well and N-well, respectively. This operation will be described later. Since silicon carbide constituting the diffusion block layers 4p and 4n has a wide band gap as compared with silicon, there is an effect of increasing the potential barrier accordingly. That is, the potential barrier increases by the band offset (ΔEv) of the valence band with respect to the movement of holes from the P-type semiconductor region to the N-type semiconductor region (FIG. 4A). On the other hand, with respect to the movement of electrons from the N-type semiconductor region to the P-type semiconductor region, the potential barrier increases by the band offset (ΔEc) of the conduction band (FIG. 4-2). Therefore, the potential barrier can be increased without increasing the impurity concentration, and the diffusion of majority carriers in the source region 3s and the drain region 3d formed in the fin F into the P well 2p or the N well 2n can be suppressed. Therefore, the well breakdown voltage can be improved. Further, since the diffusion block layers 4p and 4n made of silicon carbide, which is a wide band gap material, may have a low impurity concentration, the diffusion of impurities into the channel region 3c of the fin F is also suppressed. Therefore, an increase in the impurity concentration in the channel region 3c of the fin F can be prevented, and the performance degradation of the FinFET such as a decrease in on-current can be suppressed.

  As described above, in the semiconductor device 100 according to the present embodiment, the diffusion block layers 4p and 4n made of silicon carbide doped with low-concentration impurities are formed instead of the PTS made of the impurity layer. Thereby, the diffusion of majority carriers in the source region 3s and the drain region 3d formed in the fin F to the P well 2p or the N well 2n can be suppressed, and at the same time, the punch-through current between the source and the drain can be suppressed. . Therefore, in the present embodiment, it is possible to suppress the punch-through current between the source and the drain and improve the well breakdown voltage without causing the performance degradation of the FinFET such as a decrease in the on-current due to the increase in the channel impurity concentration.

  In addition to the above effects, silicon carbide has a high thermal conductivity. Therefore, even with an SOI FinFET or a Bulk FinFET, there is an effect that the influence of self-heating, which becomes a problem when the fin width is reduced, can be reduced.

  Next, the operation of the semiconductor device 100 of this embodiment will be described. FIG. 4A shows an energy band diagram of a heterojunction of a P-type semiconductor having a small band gap and an N-type semiconductor having a large band gap. FIG. 4B is an energy band diagram of a heterojunction between an N-type semiconductor with a small band gap and a P-type semiconductor with a large band gap. In FIGS. 4A and 4B, the semiconductor with a small band gap corresponds to the source region 3s and the drain region 3d formed in the fin F, and the semiconductor with a large band gap (here, silicon carbide) is formed at the bottom of the fin channel. Corresponds to the diffusion block layer formed. Here, the P-type semiconductor and the N-type semiconductor having a small band gap are silicon. Here, the P-type semiconductor and the N-type semiconductor with a small band gap are here silicon carbide.

  In the N-channel FinFET, as shown in FIG. 4B, electrons from the N-type silicon layer constituting the source region 3s and the drain region 3d formed in the fin F to the P-type silicon carbide layer constituting the diffusion block layer 4p are transferred. With respect to the movement, the potential barrier becomes higher by the band offset (ΔEc) of the conduction band, and electrons do not flow easily.

  On the other hand, in the P-channel FinFET, as shown in FIG. 4A, from the P-type silicon layer constituting the source and drain regions 3s and 3d formed in the fin F to the N-type silicon carbide layer constituting the diffusion block layer 4n. With respect to the movement of holes, the potential barrier becomes higher by the band offset (ΔEv) of the valence band, and the holes do not flow easily.

  As described above, instead of the conventional PTS made of the impurity layer, the diffusion barrier layers 4p and 4n made of the wide band gap material are formed at the bottom of the fin channel to increase the potential barrier of the fin bottom and increase the P well 2p and Leakage current due to majority carriers to N well 2n can be suppressed. In the case of the P-type diffusion layer, the diffusion of holes in the P-type diffusion layer to the silicon substrate 1 is blocked by the diffusion block layer 4n. In the case of the N-type diffusion layer, electrons in the N-type diffusion layer enter the silicon substrate 1. Diffusion is blocked by the diffusion block layer 4p, and in any case, the leakage current is suppressed and the well breakdown voltage can be improved. Further, since the effect of suppressing the punch-through current between the source and the drain can be expected by forming the wide band gap layer at the bottom of the fin channel, the impurity layer considered to be essential in the conventional Bulk FinFET according to the present embodiment. The formation of PTS made of is not necessary.

  Next, the manufacturing process of the semiconductor device of this embodiment will be described. 10-1 to 10-20 are views showing the manufacturing process of the semiconductor device of this embodiment. 10-1 to 10-20, (c) is a plan view, (a) is a sectional view taken along line AA in (c), and (b) is a sectional view taken along line BB in (c). It corresponds to. In order to facilitate understanding of the display position, (c) shows a completed state in all drawings. In the process diagram, two fins are omitted.

  In this method, a silicon carbide layer 4 for forming diffusion block layers 4p and 4n is epitaxially grown on a P-type silicon substrate 1 constituting a semiconductor substrate. Next, a non-doped silicon epitaxial layer 3 is formed on the silicon carbide layer to obtain a stacked structure of Si / SiC / Si. Then, after forming wells of each conductivity type in this laminated structure, the laminated structure of Si / SiC / Si is processed into fins, followed by formation of element isolation insulating layer 7, formation of gate insulating film 5, and formation of gate electrode 6. The FinFET is formed according to a normal FinFET formation process.

  First, the silicon carbide layer 4 for forming the diffusion block layers 4p and 4n is epitaxially grown on the p-type silicon substrate 1 constituting the semiconductor substrate by using the CVD method. Note that specifically, 3C—SiC (β-SiC) can be used as the silicon carbide layer. Doping into the silicon carbide layer can be performed by adding a doping gas during silicon carbide epitaxial growth or by ion implantation after growth. Next, a non-doped silicon epitaxial layer 3 is formed on the silicon carbide layer 4 using a CVD method, thereby forming a Si / SiC / Si stacked structure (FIG. 10-1).

  Next, as shown in FIG. 10-2, a mask pattern made of the first resist R1 is formed on the non-doped silicon epitaxial layer 3. Then, boron ions are implanted through the mask pattern to form a P well 2p. At this time, boron is implanted also into the non-doped silicon epitaxial layer 3 and the silicon carbide layer as in the P well. The silicon carbide layer into which boron has been implanted becomes the diffusion block layer 4P. However, at this time, in silicon carbide, boron is trapped by defects, and the carrier concentration is significantly lower than in silicon.

  Then, as shown in FIG. 10-3, a mask pattern made of the second resist R2 is formed. Then, phosphorus ions are implanted through this mask pattern to form an N well 2n. At this time, phosphorus is also implanted into the non-doped silicon epitaxial layer 3 and the silicon carbide layer as in the N well. This phosphorus-implanted silicon carbide layer becomes the diffusion block layer 4P. However, at this time, in silicon carbide, phosphorus is trapped by defects, and the carrier concentration is significantly lower than in silicon.

  Thereafter, as shown in FIG. 10-4, a silicon nitride layer is formed by a CVD method, and this silicon nitride layer is patterned by photolithography and RIE (Reactive Ion Etching) to form a hard mask HR.

  Then, as shown in FIG. 10-5, with the hard mask HR as a mask, the non-doped silicon epitaxial layer 3, the diffusion block layers 4p and 4n made of a silicon carbide layer, the P well 2p, and the N well 2n are brought to a predetermined height. Etching is removed to form fins F.

  Thereafter, as shown in FIG. 10-6, a TEOS film for forming the element isolation insulating layer 7 is deposited by plasma CVD.

  Next, as shown in FIG. 10-7, planarization is performed by a CMP (Chemical Mechanical Polish) method using a hard mask HR made of a silicon nitride layer as a stopper.

  Further, as shown in FIG. 10-8, the element isolation insulating layer 7 is formed by RIE processing so that the upper surface position of the TEOS film is substantially the same as the upper surface position of the diffusion block layers 4p and 4n made of the silicon carbide layer. It is formed.

  If necessary, the N channel FET side and the P channel FET side are sequentially coated with resist on the upper surface of the element isolation insulating layer 7, and boron or phosphorus is ion-implanted vertically. At this time, a part of boron or phosphorus recoiled on the STI surface may be injected into the silicon carbide layer at the fin channel bottom to form the diffusion block layers 4p and 4n.

  Thereafter, as shown in FIG. 10-9, hafnium silicon oxynitride to be the gate insulating film 5 is formed on the surface of the fin F by an ALD (Atomic Layer Deposition) method.

  Then, as shown in FIG. 10-10, titanium nitride to be the gate electrode 6 is formed by a CVD method. Thus, by using a material having a work function in the center of the silicon band gap, such as titanium nitride, as the gate electrode 6, the gate electrode can be shared between the N-channel FinFET and the P-channel FinFET.

  Thereafter, as shown in FIGS. 10-11, a silicon nitride film is formed and patterned by photolithography and RIE to form a hard mask HR2.

  Thereafter, as shown in FIG. 10-12, the gate electrode 6 is processed by RIE using the hard mask HR2 as a mask. At this time, the gate electrode material in the source / drain regions is removed by RIE. In the RIE of the gate electrode material in the source / drain regions, the gate insulating film 5 functions as an etching stopper.

  Thereafter, as shown in FIG. 10-13, the gate insulating film 5 in the source / drain regions is selectively removed by wet etching.

  Thereafter, as shown in FIGS. 10-14, a silicon nitride film to be the sidewall insulating film 9 is formed by the CVD method.

  Then, as shown in FIG. 10-15, RIE is performed to completely remove the silicon nitride on the side surfaces of the fins F in the source / drain regions, while leaving the silicon nitride on the side surfaces of the gate electrode 6 to remain. 9 is formed (the side wall insulating film is not visible in FIGS. 10-15 and is not shown).

  Thereafter, as shown in FIG. 10-16, a silicon epitaxial layer 3e is formed on the surface of the fin F not covered with the gate electrode 6 and the sidewall insulating film 9 by selective epitaxial growth. By this step, the fin width of the source / drain region can be increased, so that the parasitic resistance of the source / drain can be reduced.

  Then, as shown in FIG. 10-17, a silicon epitaxial layer 3e is formed, and impurity ions are implanted into the thickened fin F to form source / drain regions 3s, 3d. First, the P-channel FET side is covered with the third resist R3, and N-type impurities such as phosphorus or arsenic are ion-implanted into the N-channel FET side.

  Then, as shown in FIG. 10-18, the N-channel FET side is covered with the fourth resist R4, and P-type impurities such as boron are ion-implanted into the P-channel FET side.

  Thereafter, as shown in FIG. 10-19, annealing is performed in an inert gas atmosphere to activate the impurities implanted in the source / drain regions 3s and 3d. Further, by the annealing here, the impurity implanted into the source / drain region in FIGS. 10-17 and 10-18 diffuses in the center of the fin and in the channel direction, whereby the source / drain extension can be formed. . For this reason, the extension ion implantation used in normal transistor formation is omitted here.

  Thereafter, as shown in FIG. 10-20, a metal film is formed in the source / drain regions 3s and 3d by sputtering and then heat treatment is performed to form silicide 3M. Here, it is necessary to prevent the source / drain regions 3s and 3d from being completely silicided when the silicide is formed. If silicidation is complete, the contact area between Si and silicide, which is the main cause of source / drain parasitic resistance, decreases, and the interface resistance increases. Therefore, complete silicidation must be avoided. As the silicide material, nickel silicide, cobalt silicide, titanium silicide, or the like can be used.

  Thus, the semiconductor device (FinFET) having the configuration shown in FIG. 1 is completed. Here, the hard mask HR on the fin is left as it is to form the upper insulating film 8.

  As described above, by forming the diffusion block layers 4p and 4n made of silicon carbide having a large band gap at the bottom of the fin channel, it is possible to suppress a decrease in well breakdown voltage. This also makes it possible to suppress the punch-through current between the source region 3s and the drain region 3d at the fin channel bottom without using PTS made of impurities. Further, since the impurity concentration in the diffusion block layers 4p and 4n is low, an increase in the impurity concentration in the channel can be suppressed. As a result, it is possible to suppress degradation of FinFET performance such as a decrease in on-current due to an increase in channel impurity concentration.

In addition, when the diffusion block layers 4p and 4n made of silicon carbide are used in the bottom region of the fin channel, the self-heating effect can be suppressed because the thermal conductivity of silicon carbide is high. In FinFETs using SOI substrates (SOI FinFETs), BOX (Buried Oxide: SiO ₂ ) exists under the fin channel of silicon, and since the thermal conductivity of SiO ₂ is small, performance degradation due to self-heating has been reported. . On the other hand, Bulk FinFET does not have BOX and is less susceptible to self-heating than SOI FinFET. However, if the fin width becomes fine due to device miniaturization, it is difficult to transport heat from the silicon fin channel to the silicon substrate. Become more susceptible to self-heating. Therefore, the use of a material having high thermal conductivity such as silicon carbide for the fin channel bottom is advantageous in terms of suppressing performance deterioration due to self-heating.

  Further, in this embodiment, at least a part of the diffusion block layers 4p and 4n is covered with the element isolation insulating layer 7, and the element isolation insulating layer 7 is silicon with the position in contact with the diffusion block layers 4p and 4n as the upper surface. The P well 2p and the N well 2n on the substrate 1 are formed. For this reason, in the FinFET of this embodiment, the channel width can be defined by the position of the upper surface of the diffusion block layers 4p and 4n by sufficiently increasing the band gap of the diffusion block layers 4p and 4n. Therefore, even when the position of the upper surface of the element isolation insulating layer 7 is changed, the channel width can be kept constant by being within the diffusion block layers 4p and 4n. In the conventional Bulk FinFET, the problem is that the channel width fluctuates because the position of the upper surface of the element isolation insulating layer 7 fluctuates due to process variations, but this embodiment can solve this problem.

  In the semiconductor device according to the present embodiment, the CMOSFET in which the P-channel FinFET and the N-channel FinFET are formed on the same silicon substrate has been described. However, when three or more FinFETs having different conductivity types are formed. Also effective. In addition, the wide band gap layer raises the potential barrier regardless of whether the majority carrier is an electron or a hole, and the source region 3s, the drain is drained in both cases of individual P-channel FinFET and N-channel FinFET. This is effective for suppressing the diffusion of majority carriers in the region 3d into the substrate. In particular, since this diffusion block layer is effective for both the P-channel FinFET and the N-channel FinFET, for example, the same laminated structure such as Si / SiC / Si can be used for the manufacturing process. Can be simplified.

A structural example of well breakdown voltage evaluation in a CMOS circuit using a Bulk FinFET is shown in FIGS. 3-1 and 3-2. In FIGS. 3A and 3B, the potential of the terminal D is swept while the substrate contact terminal A and the terminal B of the P well are set to the GND potential and the terminal C is floated, and the N ⁺ diffusion layer and the N well are The leakage current is evaluated. The leakage current between the P ⁺ diffusion layer and the P well can be evaluated by sweeping the potential of the terminal A while the terminal C and the terminal D are in the GND potential and the terminal B is in the floating state.

Next, the dependence of the well breakdown voltage on the impurity concentration in the PTS when the conventional PTS is used will be described. FIGS. 5A and 5B show the results of simulating the PTS concentration dependence of the well breakdown voltage using a semiconductor device having the same structure as FIGS. 3A and 3B. The vertical axis represents the leakage current, and the horizontal axis represents the well bias (corresponding to the potential applied to the terminal D under the structure of FIG. 3-2 and the bias condition of each terminal). The broken line in the figure indicates the specification (allowable upper limit value) of the leakage current. FIG. 5-1 shows the results when the STI width is 120 nm, and FIG. 5-2 shows the results when the STI width is 150 nm. In Figure 5-1 and Figure 5-2, a to e is the simulation result when the each PTS concentration ^{1x10 17, 1x10 18, 3x10 18} , 5x10 18, 1x10 19 (atoms / cm 3). 5A and 5B, the well breakdown voltage is improved by increasing the PTS concentration and the STI width.

FIG. 6A shows the leakage current (electron current) distribution in the well when a potential of 3 V is applied to the terminal D with the terminal A and the terminal B being in the GND potential and the terminal C in the floating state. Fig. 6-2 shows the leakage current (hole current) distribution in the well when a potential of -3V is applied to the terminal A with the terminal C and terminal D in the GND potential and the terminal B in the floating state. It is. From this result, the leakage current flowing through the well when the well bias is applied is between terminals B and D (N ⁺ diffusion layer / N well) in FIG. 6-1, and between terminals A and C (P ⁺ diffusion layer / It can be seen that the current flowing in the (P well) is dominant.

FIG. 7 shows the result of simulating the potential distribution in the well in order to investigate the origin of the well leakage current. Here, only the case of FIG. 6A corresponding to the evaluation of the breakdown voltage between the N ⁺ diffusion layer / N well is shown. In FIG. 7, potential distributions in the route from the point P to the point Q and from the point Q to the point R are as shown in FIGS. 8-1 and 8-2, respectively. The energy of the electrons is lower toward the upper side of the graph, and when electrons in the N ⁺ diffusion layer get over the potential barrier in the PTS region and reach the point Q, they can flow into the point R so as to go down the potential barrier slope. Recognize. The current flowing in this way is the origin of the well leakage current shown in FIG. For this reason, it is expected that the potential barrier in the PTS region is related to the well leakage current.

Next, the same potential distribution was examined by changing the PTS concentration. 9A to 9D show potential distributions when the PTS concentrations are 1 × 10 ¹⁷ , 1 × 10 ¹⁸ , 3 × 10 ¹⁸ , and 5 × 10 ¹⁸ (atoms / cm ³ ), respectively. As shown in FIGS. 9-1 to 9-4, the potential barrier of the PTS region is increased by increasing the PTS concentration. Thus, it can be seen that the decrease in well leakage current (improvement of breakdown voltage) due to the increase in PTS concentration shown in FIGS. 5A and 5B is caused by the increase in the potential barrier.

  The PTS region is necessary for suppressing the punch-through current between the source and the drain flowing through the bottom of the fin channel of the Bulk FinFET, but it can be seen that it is also effective for suppressing the well leak current as described above.

  However, as described above, if the PTS concentration is increased to improve the well breakdown voltage, the channel impurity concentration of the FinFET increases, 1) deterioration of on-current, 2) increase in characteristic variation due to impurity fluctuations, and 3) fins in the source / drain regions. There are problems such as an increase in junction leakage current at the bottom.

  The above is not the diffusion block layer used in the semiconductor device of the present embodiment, but a PTS made of an impurity layer, but the rest of the configuration is the same FinFET having a diffusion block layer. It was performed using.

  On the other hand, by using a diffusion block layer made of a wide band gap material as in this embodiment, the well breakdown voltage can be improved without forming a PTS made of an impurity layer. On the other hand, it has been confirmed in the above simulation that an increase in STI width and an increase in Fin width are effective in improving the well breakdown voltage. However, these methods are not suitable for high integration of LSI. Therefore, it can be seen that, as a technique for improving the well breakdown voltage of Bulk FinFET, the semiconductor device of this embodiment is an effective technique for high integration of LSI while avoiding the problems when PTS is used.

  In the embodiment, the case where the fin channel is made of silicon has been described. However, silicon germanium SiGe or germanium Ge may be used.

  As the wide band gap material constituting the diffusion block layer, other materials such as gallium phosphide (GaP) and gallium nitride (GaN) can be used in addition to silicon carbide (SiC). Thus, when the fin is made of silicon, GaP is extremely effective as a diffusion block layer from the viewpoint of lattice matching. This is because the lattice constant of GaP is 5.45Å, so that it is very close to 5.43Å of silicon, the lattice mismatch with Si is small, and crystal defects at the heterojunction are less likely to occur.

Furthermore, in the above embodiment, the diffusion block layer is composed of a single layer of silicon carbide. However, a composition gradient layer is interposed between the fin composed of silicon and silicon carbide, or a buffer layer is interposed. The lattice mismatch (misfit) with Si may be alleviated, and the generation of crystal defects at the heterojunction may be suppressed. The composition gradient layer is represented by a composition formula of Si _1-x C _x (0 <x <0.5), and the concentration of carbon contained therein is low at the interface with the silicon layer and becomes higher as it approaches silicon carbide. The composition is as follows. The buffer layer may be composed of a plurality of layers whose composition is not continuous. Also in this case, the lattice constant of the layer located on the diffusion block layer side is closer to the lattice constant of the diffusion block layer than the lattice constant of the layer located on the convex semiconductor layer side, and is located on the convex semiconductor layer side. It is desirable that the lattice constant of the layer to be formed is closer to the lattice constant of the convex semiconductor layer than the lattice constant of the layer located on the diffusion block layer side.

(Second Embodiment)
Next, a second embodiment of the present invention will be described. FIG. 11 is a perspective view illustrating a schematic configuration of a FinFET that is a semiconductor device according to the second embodiment, and FIG. 12 is a cross-sectional view taken along line AA of FIG. In this embodiment, an N-channel FinFET will be described. Although it is almost the same as the N-channel FinFET used in the CMOS FinFET of the first embodiment, in this embodiment, as shown in FIGS. 11 and 12, the diffusion block layer composed of the silicon carbide layer 4 and the P constituting the fin F are formed. The composition gradient layer Si _1-x C _x (0 <x <0.5) 4G having a continuously changing carbon concentration is interposed between the well 2p and the well 2p. In the present embodiment, the composition gradient layer 4G is formed between the fin F on the channel region 3c side and the diffusion block layer 4. The carbon concentration in the composition gradient layer 4G is low at the interface with the silicon layer, and increases as it approaches the silicon carbide layer. The composition gradient layer 4G is formed by controlling the carbon concentration during film formation so that the carbon concentration is low at the interface with the silicon constituting the fin F, and the carbon concentration increases as the distance from the interface increases. Others are the same as those of the N-channel FinFET of the CMOS FinFET of the first embodiment, and the description is omitted here.

When silicon carbide is used for the wide band gap material formed in the bottom region of the fin channel, for example, 3C—SiC can be used. However, since the lattice constant is 5.43５ for Si and 4.36Å for 3C-SiC and the lattice misfit is large, compressive strain may occur in Si. In addition, crystal defects (misfit dislocations) may occur in order to reduce lattice misfit. In the FinFET, the Si / SiC stacked structure generates a compressive stress in the source / drain direction in the Si fin channel to improve the hole mobility in the PMOS channel, but decreases the electron mobility in the NMOS channel. On the other hand, in the present embodiment, the composition gradient layer Si _1-x C _x (in which the carbon concentration continuously changes between the diffusion block layer formed of the silicon carbide layer 4 and the P well 2p constituting the fin F. 0 <x <0.5) 4G is interposed. For this reason, the lattice misfit of Si / SiC can be reduced, and the fall of an electron mobility is not caused. Therefore, the performance degradation of the NMOS FinFET can be suppressed.

  Furthermore, the composition gradient layer 4G may be formed not only on the diffusion block layer 4 but also on the bottom.

In addition, the diffusion block layer itself may be formed of a composition gradient layer. In this case, a silicon carbide layer is formed inside the diffusion block layer, and the composition gradient layer Si _1-x C _{x in} which the carbon concentration x continuously decreases toward the upper layer side and the lower layer side is formed as the diffusion block layer. Can be used as

Although the composition gradient layer is used as the buffer layer in the second embodiment, the lattice constant is Si ₀ having a value between the lattice constant of the diffusion block layer and the lattice constant of the convex semiconductor layer (fin). A single buffer layer such as _.75 C _0.25 may be used. The single buffer layer preferably has a lattice constant that is an intermediate value between the lattice constant of the diffusion block layer and the lattice constant of the convex semiconductor layer, but may have a value close to either. Further, the buffer layer may be composed of a plurality of layers whose composition is not continuous. Also in this case, the lattice constant of the layer located on the diffusion block layer side is closer to the lattice constant of the diffusion block layer than the lattice constant of the layer located on the convex semiconductor layer side, and is located on the convex semiconductor layer side. The lattice constant of the layer to be formed is preferably closer to the lattice constant of the convex semiconductor layer than the lattice constant of the layer located on the diffusion block layer side.

  As another method, boron phosphide (BP) may be used as a buffer layer between Si / SiC.

  Furthermore, in the second embodiment, the N-channel FinFET has been described. However, it is needless to say that the present invention can also be applied to a P-channel FinFET, and can be applied to a CMOS FinFET as in the first embodiment. Also in this case, it is possible to obtain a FinFET having a high well breakdown voltage without causing a decrease in electron mobility in the channel for the N-channel FinFET.

  As described above, according to the semiconductor device of the present embodiment, the buffer layer is formed at the heterointerface between the diffusion block layer made of the wide band gap material formed at the bottom of the fin channel and the silicon layer above and below the diffusion block layer. Thus, it is possible to suppress the deterioration of the characteristics of the FinFET due to the strain in silicon due to the lattice mismatch between the diffusion block layer and the silicon layer and the occurrence of crystal defects.

  In addition, the semiconductor device of this embodiment can be applied to a FinFET having a CMOS structure like the semiconductor device of the first embodiment. In this case, distortion may occur in the fin channel due to the heterojunction between the fin channel and the diffusion block layer, and the carrier mobility in the channel may change, which may degrade the performance of either the N-channel FinFET or the P-channel FinFET. is there. On the other hand, when the composition gradient layer or the buffer layer is used, the lattice mismatch at the heterojunction can be relaxed, and the performance degradation of the FinFET due to the lattice mismatch can be avoided.

(Third embodiment)
Next, a third embodiment of the present invention will be described. FIG. 13 is a perspective view illustrating a schematic configuration of a FinFET which is a semiconductor device according to the third embodiment, and FIG. 14 is a cross-sectional view taken along line AA of FIG. In this embodiment, gallium nitride (GaN) is used in place of silicon carbide as the diffusion block layer 4N of the N-channel FinFET. This embodiment is also substantially the same as the N-channel FinFET of the first embodiment and the second embodiment, but in this embodiment, as shown in FIGS. 13 and 14, a diffusion block layer made of a gallium nitride layer. By forming the 4N film thickness as thin as 10 nm, it is possible to avoid the occurrence of defects due to the difference in lattice constant. Others are the same as those of the N-channel FinFET of the CMOS FinFET of the first embodiment, and the description is omitted here.

  GaN has a lattice constant of 3.19 Å. Since Si is 5.43 mm, Si / GaN heterojunction is likely to have crystal defects due to lattice mismatch. At this time, generation of defects can be avoided by reducing the film thickness of GaN. The film thickness is not limited to 10 nm and can be set appropriately between 5 nm and 100 nm.

  As described above, according to the semiconductor device of this embodiment, the upper and lower silicon layers are sufficiently thinned by sufficiently reducing the thickness of the diffusion block layer made of the wide band gap material formed at the bottom of the fin channel. It is possible to suppress deterioration in characteristics of the FinFET due to strain in silicon due to lattice mismatch or generation of crystal defects at the heterointerface with the.

  In addition, the semiconductor device of this embodiment can also be applied to a FinFET having a CMOS structure like the semiconductor device of the first embodiment. In this case, distortion may occur in the fin channel due to the heterojunction between the fin channel and the diffusion block layer, and the carrier mobility in the channel may change, which may degrade the performance of either the N-channel FinFET or the P-channel FinFET. is there. On the other hand, if thin GaN is used for the diffusion block layer as in this embodiment, lattice mismatch at the heterojunction can be mitigated, and performance degradation of the FinFET due to lattice mismatch can be avoided. It becomes possible.

(Fourth embodiment)
Next, a fourth embodiment of the present invention will be described. FIG. 15 is a perspective view illustrating a schematic configuration of a FinFET which is a semiconductor device according to the fourth embodiment, and FIG. 16 is a cross-sectional view taken along line AA of FIG. In this embodiment, GaN is used for the diffusion block layer, and the lattice mismatch due to the difference in lattice constant between GaN and Si is alleviated by sandwiching the buffer layer 4B, and the generation of strain due to the lattice mismatch is reduced. Like to do. That is, boron phosphide (BP) is sandwiched between the GaN as the diffusion block layer 4N and the silicon forming the fin as the buffer layer 4B. The Si / GaN heterojunction buffer layer 4B is not limited to boron phosphide, and other materials can also be used. Others are the same as those of the N-channel FinFET of the CMOS FinFET of the first embodiment, and the description is omitted here.

  As described above, according to the semiconductor device of the present embodiment, the buffer layer 4B is formed at the heterointerface between the diffusion block layer 4N made of the wide band gap material formed at the bottom of the fin channel and the silicon layer above and below the diffusion block layer 4N. doing. As a result, it is possible to suppress the deterioration of the characteristics of the FinFET due to strain into the silicon and crystal defects due to lattice mismatch between the diffusion block layer and the silicon layer.

  At the time of manufacture, a step of forming a second semiconductor layer to be the diffusion block layer 4N on a semiconductor substrate having at least a surface made of the first semiconductor layer, and a third region to be a channel region on the second semiconductor layer A step of forming the semiconductor layer and a step of performing etching to form the fin F as the convex semiconductor layer made of the first to third semiconductor layers are sequentially performed. Here, the band gap of the diffusion block layer 4N as the second semiconductor layer is larger than the band gap of the third semiconductor layer.

  In the present embodiment, prior to the step of forming the second semiconductor layer, the buffer layer 4B having a lattice constant intermediate between the lattice constants of the first semiconductor layer and the second semiconductor layer is replaced with the first semiconductor layer. Forming on the top. According to this configuration, it is possible to avoid generation of crystal defects due to lattice mismatch between the second semiconductor layer and the first semiconductor layer constituting the diffusion block layer 4N. This plays a role of enhancing the crystallinity of the third semiconductor layer constituting the channel region formed on the diffusion block layer 4N.

  Furthermore, in this embodiment, after the step of forming the second semiconductor layer, the buffer layer 4B having a lattice constant intermediate between the lattice constants of the second semiconductor layer and the third semiconductor layer is replaced with the second semiconductor layer. Forming on the layer. According to this configuration, it is possible to avoid the occurrence of crystal defects due to lattice mismatch between the second semiconductor layer constituting the diffusion block layer 4N and the third semiconductor layer constituting the channel region. Then, the crystallinity of the third semiconductor layer constituting the channel region can be further increased.

  The buffer layer 4B may have different compositions between the upper layer and the lower layer of the diffusion block layer, or may have the same composition. The buffer layer 4B may be formed on either the upper layer or the lower layer of the diffusion block layer 4N, or may be formed on both.

  In addition, the semiconductor device of this embodiment can also be applied to a FinFET having a CMOS structure like the semiconductor device of the first embodiment. In this case, distortion may occur in the fin channel due to the heterojunction between the fin channel and the diffusion block layer, and the carrier mobility in the channel may change, which may degrade the performance of either the N-channel FinFET or the P-channel FinFET. is there. On the other hand, by using boron phosphide (BP) in the buffer layer as in this embodiment, the lattice mismatch at the heterojunction can be alleviated, and the performance degradation of the FinFET due to the lattice mismatch is avoided. It becomes possible.

(Fifth embodiment)
Next, a fifth embodiment of the present invention will be described. FIG. 17 is a perspective view illustrating a schematic configuration of a FinFET which is a semiconductor device according to the fifth embodiment, and FIG. 18 is a cross-sectional view taken along line AA of FIG. In this embodiment, the fin channel is made of germanium (Ge) instead of silicon, and gallium arsenide (GaAs) is used as the diffusion block layer 4a of the N-channel FinFET. This embodiment is also substantially the same as the N-channel FinFET of the first to fourth embodiments, but in this embodiment, as shown in FIGS. 17 and 18, the fin F is made of germanium instead of silicon. The diffusion block layer 4a made of gallium arsenide is used. The rest is the same as the N-channel FinFET of the CMOS FinFET of the first embodiment, and a description thereof will be omitted here.

  Since gallium arsenide is a wide band gap material with a small lattice misfit with germanium, it is possible to obtain a FinFET with a high well breakdown voltage while avoiding the generation of crystal defects in the germanium channel due to lattice mismatch.

  In the first to fourth embodiments, the example in which the upper and lower semiconductor layers of the diffusion block layer are made of the same material has been described. However, different materials are used as in the fifth embodiment. It may be configured.

  In the first to fifth embodiments, an adhesion layer for enhancing adhesion between the diffusion block layer and the upper or lower semiconductor layer, a channel and the diffusion block layer, and May be interposed with other functional layers such as thin dielectric layers having different dielectric constants. The lattice constant of this functional layer may deviate from the intermediate value of the lattice constants of the diffusion block layer and the semiconductor layers above and below it.

  For example, even if some constituent elements are deleted from all the constituent elements shown in the first to fifth embodiments or the respective embodiments, the problems described in the column of problems to be solved by the invention can be solved. When the effects described in the column “Effects of the Invention” can be obtained, a configuration from which this component is deleted can be extracted as an invention. Furthermore, you may combine suitably the structural requirement covering the said 1st Embodiment to 5th Embodiment.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

A part of the summary of the configuration example of the semiconductor device and the manufacturing method thereof according to the present embodiment is shown below.
(1) The convex semiconductor layer is a silicon layer,
The diffusion block layer is a silicon carbide (SiC) layer,
The buffer layer is a composition gradient layer represented by a composition formula of Si _1-x C _x , and the carbon concentration in the composition gradient layer is low at the interface with the silicon layer,
The height increases as the silicon carbide layer is approached.

(2) The convex semiconductor layer is a silicon layer,
The diffusion block layer is a silicon carbide layer;
The buffer layer includes a boron phosphide (BP) layer.

(3) The convex semiconductor layer is a silicon layer,
The diffusion block layer is a gallium nitride (GaN) layer,
The buffer layer includes a boron phosphide (BP) layer.

(4) The convex semiconductor layer is a silicon layer,
The diffusion block layer includes a gallium phosphide (GaP) layer.

(5) At least a part of the diffusion block layer is covered with an insulating layer,
The insulating layer includes a layer formed up to the semiconductor substrate with a position in contact with the diffusion block layer as an upper surface.

(6) The convex semiconductor layer includes a source / drain region of an N-channel FinFET in which electrons are majority carriers.

(7) including a plurality of convex semiconductor layers on the semiconductor substrate;
The plurality of convex semiconductor layers include those constituting FinFETs having channels of different conductivity types.

(8) forming a second semiconductor layer serving as a diffusion block layer on a semiconductor substrate composed of the first semiconductor layer;
Forming a third semiconductor layer to be a channel region on the second semiconductor layer;
Etching to form a convex semiconductor layer comprising the first to third semiconductor layers;
Including
The band gap of the second semiconductor layer includes a band gap larger than that of the third semiconductor layer.

(9) After forming the first semiconductor layer, prior to the step of forming the second semiconductor layer,
Forming a buffer layer having a lattice constant intermediate between lattice constants of the first semiconductor layer and the second semiconductor layer.

(10) After forming the second semiconductor layer, prior to the step of forming the third semiconductor layer,
Forming a buffer layer having a lattice constant intermediate between lattice constants of the second semiconductor layer and the third semiconductor layer.

(11) The step of forming the buffer layer includes:
This includes a step of forming a composition gradient layer in which the composition is gradually changed so that the lattice constant gradually changes.

(12) The step of forming the convex semiconductor layer includes:
After forming a mask material on the third semiconductor layer, a part of the first semiconductor layer that is not covered with the mask material, the second semiconductor layer, and the entire third semiconductor layer are anisotropic. Is a process of etching by reactive etching,
The method includes a step of filling the region etched in the etching step with an insulating layer so as to surround the convex semiconductor layer.

  1 p-type silicon substrate, 2p P well, 2n N well, 3c channel region, 3e epitaxial layer, 3s source region, 3d drain region, 3M silicide layer, 4 silicon carbide layer, 4p, 4n, 4N, 4a diffusion block layer, 4G composition gradient layer, 4B buffer layer, 5 gate insulating film, 6 gate electrode, 7 element isolation insulating layer, 8 upper insulating film, 9 side wall insulating film, 10n first FinFET (N channel FET), 10p second FinFET (P channel FET), F fin (convex semiconductor layer)

Claims (7)

A plurality of convex semiconductor layers provided on a semiconductor substrate;
A source region and a drain region provided in the convex semiconductor layer;
A gate electrode provided on a side surface of the convex semiconductor layer corresponding to a channel region formed between the source region and the drain region via a gate insulating film, and giving a field effect to the channel region;
A material layer having a band gap larger than that of the convex semiconductor layer is formed inside the convex semiconductor layer, and prevents majority carriers from diffusing into the semiconductor substrate from the source region and the drain region. A diffusion block layer;
A buffer layer interposed between the diffusion block layer and the convex semiconductor layer, the lattice constant having a value between the lattice constant of the diffusion block layer and the lattice constant of the convex semiconductor layer;
Comprising
At least a part of the diffusion block layer is covered with an insulating layer;
The insulating layer is formed up to the semiconductor substrate with the position in contact with the diffusion block layer as an upper surface,
A semiconductor device in which the plurality of convex semiconductor layers have different conductivity type channels. A convex semiconductor layer provided on a semiconductor substrate;
A source region and a drain region provided in the convex semiconductor layer;
A gate electrode provided on a side surface of the convex semiconductor layer corresponding to a channel region formed between the source region and the drain region via a gate insulating film, and giving a field effect to the channel region;
A diffusion block layer for preventing majority carriers from diffusing into the semiconductor substrate from the source region and the drain region inside the convex semiconductor layer,
A semiconductor device in which the diffusion block layer is made of a material layer having a band gap larger than that of the convex semiconductor layer.   The semiconductor device according to claim 2, wherein the convex semiconductor layer is one of a silicon germanium (SiGe) layer and a germanium (Ge) layer.   The semiconductor device according to claim 2, wherein the convex semiconductor layer is a silicon (Si) layer.   The semiconductor device according to claim 2, wherein the diffusion block layer is a silicon carbide (SiC) layer. A buffer layer is provided between the diffusion block layer and the convex semiconductor layer,
The semiconductor device according to claim 2, wherein a lattice constant of the buffer layer has a value between a lattice constant of the diffusion block layer and a lattice constant of the convex semiconductor layer.   The buffer layer is composed of a plurality of layers, and the lattice constant of the layer located on the diffusion block layer side is set to be greater than the lattice constant of the layer located on the convex semiconductor layer side. The semiconductor device according to claim 6.