JP2013246668A - Communication device - Google Patents

Abstract

Provided is a communication device having a configuration suitable for high-speed communication between high-functional function packages.
A communication unit of all packages is provided with an oscillator having the same frequency and a counter for counting a reference clock signal oscillated by the oscillator. The counter counts a count value corresponding to the frequency division ratio of the generated clock signal to the reference clock signal. When the count value of the counter reaches a predetermined value, a counter reset signal is sent to all packages including its own package. The reset signal is Wired-ORed, and the reset of the counters of all packages is released at the timing when the last package is released from the reset state. As a result, the counters of all packages start counting up at the same timing, and the counters can be synchronized.
[Selection] Figure 3

Description

  The following embodiments relate to a communication device.

  Communication devices are often composed of a line package (hereinafter referred to as PKG) that accommodates communication lines and a control PKG that monitors / controls a plurality of line PKGs, and the number of accommodated lines increases by adding line PKGs. The structure to be taken is taken. Hereinafter, the line PKG and the control PKG may be collectively referred to as a function PKG.

FIG. 1 is a diagram illustrating a state in which function packages of communication apparatuses are arranged.
FIG. 1A is a diagram of the communication device viewed from the front, and FIG. 1B is a diagram of the communication device viewed from above.

  A plurality of lines PKG that accommodate communication lines are mounted on one shelf. One control PKG for monitoring and controlling the line PKG is mounted on one shelf.

  Communication signals between the control PKG and each line PKG are wired and transmitted / received via a back wiring board (hereinafter referred to as BWB).

  As communication methods, two types of communication, asynchronous communication and clock (hereinafter referred to as CLK) parallel communication, are mainly used.

  FIG. 2 is a diagram for explaining start-stop synchronization communication and CLK parallel communication.

<Asynchronous communication (FIG. 2 (a))>
In asynchronous communication, only data signals are transmitted between function packages. Asynchronous communication is used for low-speed communication on the order of kbps.

  In asynchronous communication, it is not necessary to run the CLK signal simultaneously, but the synchronization detection circuit 9 is required on the receiving side, and the circuit scale is not small. When asynchronous communication is used for communication between functional PKGs, one synchronization detection circuit 9 is mounted on the line PKG side, but as many synchronization detection circuits 9 as the number of line PKGs are required on the control PKG side.

<CLK parallel communication (Fig. 2 (b))>
In the CLK parallel communication, the DATA signal CLK signal line is run along with the DATA signal line. On the receiving side, DATA is captured in synchronization with the data capturing CLK signal. The CLK parallel communication is used for communication at a higher speed than the asynchronous communication.

  In the CLK parallel communication, the data capturing circuit on the receiving side is simple, but the number of signal lines is increased to run the CLK signal line in parallel.

  Further, since the level of the CLK signal is constantly changing, it causes noise and it is necessary to suppress radio wave radiation as a device.

  Further, in the CLK parallel communication, it is necessary to wire the number of CLK signal lines of the 2 × N (N is the number of sets of transmission / reception ends) packages to the BWB by transmission / reception CLK.

  Since current communication devices require high-function / high-speed processing, CLK parallel communication that enables high-speed communication is often used for inter-PKG communication. Communication between PKGs is mainly performed only between the control PKG and the line PKG.

  In the conventional technology, the clock signal and data signal are transmitted and received between multiple packages, and the clock signal is used to synchronize the data signal. In the technology, the clock signal is synchronized by transmitting the control signal from the master board to the slave board. There is technology to take.

JP-A-7-281785

  The conventional line PKG is a PKG specialized for the transmission of the main signal, which is the main function, and does not have a CPU (even if it has a low function). The monitoring / control of a plurality of lines PKG is designed with a configuration in which the functions are divided into the lines PKG and the control PKG as the control PKG does.

  However, recently, as the functionality of the device has increased, the load on the control PKG has increased, and a certain amount of monitoring / control is also performed on the line PKG, and a set of information is communicated on the control PKG-line PKG. It is coming. For this reason, it has become mainstream to install a high-performance CPU in the line PKG.

  Therefore, information is exchanged with the surrounding line PKG as a line PKG (an individual having a brain), not a relationship where there is a control PKG (parent) and there is a line PKG (child). Depending on how it is used, any line PKG can become a parent and control the surrounding lines PKG.

  Therefore, in the future, if further high-function processing is required for the communication device, it is necessary to perform communication between the line PKG and the line PKG. Then, it is necessary to wire the DATA signal lines between the PKGs in a mesh shape. Then, the CLK signal line running along with the DATA signal line also needs to be wired in the same manner. As the number of lines PKG increases, the number of CLK signal lines becomes enormous. In addition, the generation of noise increases.

  In the prior art, as a CLK signal line reduction measure, there is one that transmits a common communication CLK to all PKGs.

  According to this, communication data can be processed at the same timing, and there is no need to run a CLK signal line for each DATA signal line. By simply supplying a CLK signal from a PKG (for example, control PKG) as a master to a PKG (for example, a line PKG) as a slave among a plurality of PKGs, there is no need to wire CLK signal lines in a mesh shape between the PKGs.

However, this technique has the following problems.
1) Since the CLK master / slave relationship is fixed, there is a problem that CLK is not supplied to the slave PKG (for example, the line PKG) when the master PKG is failed / unmounted.
2) When a high-speed CLK signal is wired from the CLK master to the CLK slave, it is ideally necessary to connect transmission: reception = 1: 1 in consideration of the influence of waveform distortion due to reflection. As a matter of fact, as the number of CLK slaves (for example, the line PKG) increases, the output PIN from the CLK master (for example, the control PKG) increases, and BWB and cable wiring become difficult. It becomes impossible.
3) Furthermore, the increase in the number of CLK signal lines increases the current consumption and the radiation noise in the BWB / cable.
4) If the length of the CLK signal line is extended, the waveform rounding becomes severe. If the CLK phase difference between the near-end PKG and the far-end PKG increases, it cannot be said that the CLK is synchronized.

  In the following embodiments, a communication apparatus having a configuration suitable for high-speed communication between high-functional function packages is provided.

  The communication device according to one aspect of the following embodiment is a communication device in which a plurality of function packages that communicate with each other are mounted. Each function package receives a clock signal for data transmission / reception synchronized between all function packages. A data transmission / reception clock generation unit is provided.

  According to the following embodiments, it is possible to provide a communication device having a configuration suitable for high-speed communication between high-functional function packages.

It is a figure which shows a mode that the function package of a communication apparatus is arrange | positioned. It is a figure explaining asynchronous communication and CLK parallel communication. It is a figure which shows the structural example of this embodiment. It is a figure which shows the circuit example of Wired-OR. It is the figure which showed the example of a structure of the output part of the initialization setting request | requirement part. It is a figure explaining the structure for reset of a counter. It is a figure which shows the structural example of the initialization process part. It is a figure explaining the synchronization timing at the time of apparatus starting. It is a figure explaining the phase difference of the oscillator which each PKG has. It is a figure explaining the synchronization timing at the time of PKG insertion. It is FIG. (1) explaining reset of a regular counter. It is FIG. (2) explaining reset of a regular counter. It is FIG. (3) explaining reset of a regular counter. FIG. 6 is a diagram (part 1) illustrating a phase shift of CLK and a reset timing. FIG. 6 is a diagram (part 2) illustrating a phase shift of CLK and a reset timing.

  In the present embodiment, in an apparatus configured to perform data communication between PKGs in a plurality of packages, it is possible to transmit and receive data by realizing CLK synchronization without wiring only the data signal line and wiring the clock signal in parallel. To do.

  In this embodiment, the CLK master / slave relationship is eliminated, and all PKGs have an internally common CLK generation circuit. Further, by providing a mechanism for synchronizing this CLK with all PKGs, it is possible to synchronize CLK with all other PKGs, regardless of which PKG is faulty / unmounted. Then, it is possible to perform communication between PKGs by wiring only the DATA signal line without running the CLK signal line.

  By transmitting data signals between a plurality of PKGs and synchronizing the operations of the oscillators mounted on the plurality of PKGs, the data signals are synchronously communicated using the clocks of the oscillators. In particular, the newly mounted package can synchronize all PKG oscillators by sending a clock reset signal to other packages. Further, clock synchronization is maintained by periodically transmitting a clock reset signal from all packages to all other packages. All packages output a reset signal, and all packages release reset in accordance with the last released package to ensure synchronization of all packages.

  Since there is no CLK master / slave relationship, no matter which PKG is faulty / unimplemented, all other PKGs keep the internally generated CLK for communication (for data transmission / reception) in a synchronized state, and communication between PKGs Will not be lost.

  Further, since the communication CLK is generated in each PKG, it is not necessary to wire the CLK signal line to the BWB / cable.

  Since there is no increase in the number of CLK signal lines to be wired, there is no increase in current consumption, and there is no radiation noise in the BWB / cable.

Since the CLK signal line is not wired, waveform rounding and CLK phase difference due to wiring length do not occur.
FIG. 3 is a diagram illustrating a configuration example of the present embodiment.

  Each PKG (control PKG10, lines PKG11-1 and 11-2) includes a communication CLK generation unit 20 that generates a CLK for inter-PKG communication (hereinafter referred to as PKG communication CLK). The communication CLK generation unit 20 includes a (fixed) oscillator 21 and a counter 22. The fixed oscillator 21 is equipped with one that outputs the same frequency for each of the PKGs 10, 11-1, and 11-2.

  The counter 22 uses the output CLK from the fixed oscillator 21 as a reference CLK and counts the clock a specified number of times. The counter 22 maintains the same output value until the designated number is counted. When the designated number is counted, the counter 22 is “H” when the output value is “L”, and “L” when the output value is “H”. To "". The communication CLK generation unit 20 generates the PKG communication CLK obtained by dividing the reference CLK using the count result of the counter 22 (for example, by counting 100 using the 100 MHz oscillator as the reference CLK, 1 MHz of the PKG communication CLK is 1 MHz). CLK is generated).

  An initialization setting request unit 23 is provided inside each PKG 10, 11-1, and 11-2. The initialization setting request unit 23 outputs a reset pulse toward the BWB 12 after the activation of each of the PKGs 10, 11-1, and 11-2 is completed. Further, it has a function of using the count value of the counter 22 and periodically outputting a reset pulse.

  A counter initialization processing unit 24 is provided inside each PKG 10, 11-1, 11-2. The counter initialization processing unit 24 receives a reset pulse from another PKG via the BWB 12 and resets the counter 22 of the communication CLK generation unit 20. The counter 22 is reset to return the count value to 0 (zero).

  Each PKG 10, 11-1, and 11-2 has a reset signal input / output pin 25 of the communication CLK generation unit 20 as a BWB signal pin. The output buffer for this signal (the output part of the initialization setting request unit 23) employs an open collector, and a pull-up resistor is connected in each PKG. The reset pulse output is output with 'L' active, so that this signal can be wired-OR connected with the BWB 12 (when the reset is not output, it becomes 'H' level by a pull-up resistor).

  Therefore, in each PKG10, 11-1, 11-2, the reset pulse output to other PKG and the reset pulse input from other PKG are implemented simultaneously. In addition, when the own PKG outputs a reset pulse, the reset pulse is input to the own PKG at the same time. That is, the wiring for outputting the reset pulse is branched and input to the own PKG. Furthermore, the reset signal is wired-ORed, so all PKG resets are ORed (or even if 1PKG is 'L' output, it will be 'L'), and the reset will be released in accordance with the PKG that was finally released. Is done. Thereby, all PKGs can be reset synchronously.

  In this embodiment, when a certain PKG outputs a reset pulse, all PKGs receive the reset pulse at the same time, the counter 22 of the communication CLK generation unit 20 of each PKG is reset at the same timing, and all PKGs are counted simultaneously. Set the value to 0 (zero). Thereafter, the reset release is performed at the same time, and the counter counts up at the same timing, and the PKG communication CLK generated from this count value has the same rising timing and becomes a synchronous (same phase) signal.

  According to the present embodiment, since the PKG communication CLK is synchronized with all the PKGs when performing the inter-PKG communication, there is no need to wire a signal line for the PKG communication CLK to the BWB / cable. According to this, even if PKG increases, it is not necessary to additionally wire the PKG communication CLK signal line, and it is theoretically possible to increase PKG without limitation. Furthermore, there is no increase in current consumption and radio wave radiation noise due to the transmission of a high-speed CLK signal to the BWB / cable.

  According to the present embodiment, it is possible to continue the CLK synchronization only with the mounted PKG regardless of which PKG is failed / removed, so that the CLK is stopped / asynchronized and the communication function is stopped / abnormal. It will never be.

  Further, according to the present embodiment, even if a PKG is added later, it is not necessary for the control master (maintenance SOFT or the like) to instruct to reset all PKGs. This is because, after the additional PKG is activated, all the PKGs are autonomously reset and the synchronization process is performed. The additional PKG can start communication between PKGs without waiting for the reset processing time from the control master.

  The synchronization method according to the present embodiment can be used not only for communication between PKGs but also for synchronization of various internal CLKs of each PKG. For example, the LED blinking CLK (ex. 1 Hz) of each PKG can be synchronized.

  In order to synchronize the blinking cycle as a device, it is necessary to supply the common blinking CLK by BWB. However, when this embodiment is applied, there is no wiring of the common blinking CLK signal, and the blinking cycle of each PKG is synchronized. It is possible.

  The control PKG 10 / lines PKG 11-1 and 11-2 have a common circuit mounted as a communication unit 15 in each PKG. The communication unit 15 includes a communication CLK generation unit 20, an initialization setting request unit 23, a counter initialization processing unit 24, a data transmission unit 26, and a data reception unit 27.

  The communication CLK generation unit 20 includes a counter 22, and a PKG communication CLK 28 is generated using the timing at which the reference CLK from the oscillator 21 is counted a plurality of times (ex. 100 counts using a 100 MHz oscillator as a reference CLK). To generate 1 MHz of PKG communication CLK).

  The initialization setting request unit 23 outputs a 'L' active reset pulse to the CLK generation unit reset signal line 30 of the BWB 12 after the activation of the own PKG is completed.

  The other PKG counter initialization processing unit 24 receives the reset pulse from the BWB 12 and resets the counter 22 of the communication CLK generation unit 20. The counter 22 of the communication CLK generation unit 20 is reset to return the count value to 0 (zero).

  Since all PKGs start counting from 0 (zero) at the same time, the subsequent counter 22 counts up at the same timing, and the PKG communication CLK 28 generated from this count value has the same rising timing and is synchronized (in phase). Become.

  The data transmitting unit 26 of the control PKG 10 outputs data to the DATA signal line (1) 31 at the timing of the PKG communication CLK 28 synchronized with all the PKGs.

  The DATA signal output from the data transmission unit 26 of the line PKG11-1 is input to the control PKG 10 via the DATA signal line (2) 31. In the data receiving unit 27, the serial data is punched out by the PKG communication CLK 28 and is taken in internally. At this time, since the data transmission CLK / reception CLK is a synchronous CLK, the setup time / hold time specification at the time of data acquisition is satisfied, and high-speed data communication is possible.

  The CLK generation unit reset signal line (input / output) 30 is wired-OR connected to each PKG and within the BWB 12, and outputs a reset pulse from the initialization setting request unit 23, and simultaneously outputs to the counter initialization processing unit 24. Input a reset pulse. When reset pulses output from a plurality of PKGs overlap, all PKGs are released from reset at the timing when the final PKG is released from reset.

  The initialization setting request unit 23 outputs a reset pulse to the CLK generation reset signal line 30 after each PKG is activated. When CLK is synchronized after each PKG is activated, a phase shift occurs due to the accuracy of the oscillator 21 of each PKG. Therefore, the initialization setting request unit 23 outputs a reset pulse at a constant timing such that the phase shift becomes severe and asynchronous CLK does not occur.

FIG. 4 is a diagram illustrating an example of a wired-OR circuit.
As shown in FIG. 4A, a plurality of signal lines are connected through an open collector circuit, and a pull-up resistor is connected to the output of the connection. The open collector circuit has an output value of “L” or high impedance (Hi-z). When a plurality of these are connected, a negative logic OR is obtained. When all of the outputs of the open collector circuits A, B, and C in FIG. 4A are in a high impedance state, the connection output becomes “H” by a pull-up resistor.

  FIG. 4B is a logical value table of Wired-OR in FIG. When the outputs of all the open collector circuits are high impedance, the connection output is “1”, that is, “H”. In all other cases, the output of the connection is “0”, that is, “L”.

FIG. 5 is a diagram illustrating a configuration example of an output portion of the initialization setting request unit.
The configuration of the output part of the initialization setting request unit includes the above-described open collector circuit 40, a pull-up resistor 42, and a buffer 43 for inputting the output of the open collector circuit. In this configuration, the control PKG and the reset signal of the line PKG are set to input “H” to all the buffers only when all the open collector circuits 40 are high impedance. The buffer of the counter initialization setting unit 24 is configured to reset a counter (not shown in FIG. 5) when the reset signal is “L” when it is low active.

FIG. 6 is a diagram for explaining a configuration for resetting the counter.
6A, the initialization setting request unit 23 includes a reset output circuit (open collector circuit) 40 and a counter comparison circuit 41. A pull-up resistor 42 is provided at the output of the initialization setting request unit 23. The communication CLK generation unit 20 inputs a reference CLK from an oscillator (not shown) to the initialization setting request unit 23 and inputs the count value of the counter 22 to the counter comparison circuit 41. The initialization setting request unit 23 stores a counter comparison value. Here, it is assumed that the count value is 0 to 5 and the reset is performed when the count value is 5. In that case, 5 is set as the count comparison value. When the counter comparison circuit 41 detects that the count value has reached 5, a reset signal is output from the reset output circuit 40 at the next count value. Here, for convenience of explanation, the count value is set to 0-5. However, in practice, for example, when a 1 MHz PKG communication CLK is generated from a 100 MHz reference CLK, it is 0 to 99. In this case, the reset is performed when the count value is 99.

  The counter is also reset when the power supply voltage monitoring circuit 44 powers on the PKG. When the power supply of the PKG is activated, the power supply voltage monitoring circuit 44 releases the reset of the entire PKG. As a result, the counter value from the communication CLK generation unit 20 is input to the counter comparison circuit 41, and the initialization setting request unit 23 also starts to operate. As a result, the first reset output is generated. If the initial value of the counter of the communication CLK generation unit 20 is set to “4”, it is detected that a reset signal should be output when the counter value changes from “4” to “5” after reset release. When a 1 MHz PKG communication CLK is generated from a 100 MHz reference CLK, the initial value of the counter is set to “98”.

  In the signal diagram of FIG. 6B, the counter value is counted according to the reference CLK during operation. When the counter value becomes “5”, a reset output is obtained when the counter value is the next “0”. Immediately after the power is turned on, the entire PKG is reset to the reset release state. When the counter value changes from “4” to “5”, a reset output is obtained when the counter value is the next “0”.

FIG. 7 is a diagram illustrating a configuration example of the initialization processing unit.
The counter initialization processing unit 24 is simply a reception buffer that receives a reset signal. However, depending on the configuration of the circuit, a circuit that inverts the polarity of the reset signal or widens the width of the reset signal may be required. Therefore, each circuit is provided in the counter initialization processing unit 24 as necessary.

FIG. 8 is a diagram for explaining the synchronization timing when the apparatus is activated.
The control PKG, line PKG1, and line PKG2 start to start when the power is turned on.

  In this example, it is assumed that there is an individual difference in activation time in each line PKG, and activation is started in the order of control PKG → line PKG1 → line PKG2. The counter value is assumed to be a large value, but here, for convenience of explanation, it is assumed that “0” to “5” are counted.

  After start-up, the counter counts up to an initial value, for example, “4”, and counts up according to the reference CLK of the oscillator 21. The count repeats from “0” to “5”, and outputs a reset pulse when it is “5” (since the counter value is punched out by the oscillator CLK, the reset pulse is actually output at the timing of the count value “0”. ).

  Since the reset input of each PKG becomes the OR of the reset outputs of all PKGs, the reset release of the control PKG and the line PKG1 is waited until the reset release of the line PKG2.

  After reset release, all PKG counters start from the same value, and the PKG communication CLK is synchronized.

FIG. 9 is a diagram illustrating the phase difference of the PKG communication CLK used by each PKG.
There is a phase difference in the PKG communication CLK generated in each PKG. This occurs because the CLKs of the oscillators 21 of each PKG are asynchronous with each other, and a maximum phase difference of 1 CLK time of the oscillator CLK occurs. However, by generating the PKG communication CLK from the reference CLK of the oscillator 21 with a large division ratio (in the example of FIG. 9, dividing by 100, the CLK of the 100 MHz oscillator is divided by 100 to obtain the 1 MHz PKG communication CLK). The phase difference between the PKG communication CLKs can be regarded as a rising edge at almost the same timing on the scale of the PKG communication CLK1 cycle, and can be handled as a synchronous CLK.

  In FIG. 9, the oscillator CLK is shifted by a half cycle between the control PKG and the line PKG1. When the oscillator CLK is 100 MHz and is divided by 100 to generate a 1 MHz PKG communication CLK, the phase difference is about 10 ns at maximum with respect to one period 1000 ns (1 MHz) of the PKG communication CLK.

FIG. 10 is a diagram for explaining the synchronization timing when PKG is inserted.
In this example, the line PKG3 is mounted when the control PKG, the line PKG1, and the line PKG2 are in the CLK synchronization state. The line PKG3 outputs a reset pulse after activation.

  After reset release, all PKG counters start from the same value, and the PKG communication CLK is synchronized. At this time, the PKG communication CLK of the control PKG, the line PKG1, and the line PKG2 changes for a moment so that an error occurs during communication, but the problem can be avoided by performing the retransmission procedure.

FIG. 11 to FIG. 13 are diagrams for explaining periodic counter reset.
FIG. 11 shows the passage of time when there is no periodic reset.

  In this example, as shown in the table of FIG. 13, the accuracy of the 100 MHz oscillator used for the control PKG and the line PKG1 is assumed to be −100 ppm / + 100 ppm.

  In this example, since the control PKG has an accuracy of −100 ppm at 100 MHz, it becomes 99.99 MHz. Since the line PKG has an accuracy of +100 ppm at 100 MHz, it becomes 100.01 MHz.

  The difference in CLK is 20000 CLK in 1 second (100010000-99990000 = 20000). That is, if the reset is not performed for 1 second, it will be shifted 20000 counts.

  Although a constant phase difference is maintained at the beginning of reset, a phase shift gradually occurs due to the CLK accuracy, and a maximum of 20000 count shift occurs after 1 second. When this is converted into PKG communication CLK (1 MHz), it is shifted by 20 cycles. When it is shifted by more than a half cycle, it cannot be called synchronous CLK.

FIG. 12 shows the passage of time when there is a periodic reset.
If the counter 22 is reset at the full count period (100 counts), the 100 MHz clock phase shift within the reset interval becomes 0.02 CLK, and the phase can be corrected during a slight shift.

  Calculate how many counts it takes until the CLK of the oscillator deviates in half a cycle from the oscillation frequency and accuracy of the oscillator, and select an oscillator with an accuracy such that the maximum count value of the counter is smaller than the count taken until it deviates in half a cycle Try to use it. That is, if the counter is reset each time the count number counted when generating the CLK for PKG communication from the oscillator CLK by frequency division, the CLK of the oscillator is reset before the half cycle is shifted. Set to.

  14 and 15 are diagrams for explaining the phase shift of CLK and the reset timing.

  In the above description, the resetting may be performed while the phase shift of CLK is within the half cycle range. 14 and 15 explain the reason for the half cycle.

  As shown in FIG. 14, data is output at the falling edge of CLK and data is captured at the rising edge of CLK. However, as shown in FIG. 15, when the CLK phase of the control PKG and the line PKG shifts and the phase shift changes from less than half cycle to more than half cycle, before the rising edge of CLK arrives on the receiving side. Then, the fall of CLK occurs on the transmission side, and the next data may be output. When this happens, there are cases where data cannot be captured.

  Therefore, it is necessary to hold the phase difference of the PKG communication CLK within a half cycle. If the reset is performed while the phase difference of the CLK for PKG communication is within a half cycle, no problem occurs in data transmission and reception.

  Therefore, if the reset is performed every time the reference CLK count value of the oscillator 21 reaches 100, the maximum value of the count value determined by the counter before the phase difference of the PKG communication CLK reaches a half cycle. Use an oscillator with a precision as high as possible.

9 Synchronization detection circuit 10 Control PKG
11-1, 11-2 Line PKG
12 BWB
15 Communication Unit 20 Communication CLK Generation Unit 21 Oscillator 22 Counter 23 Initialization Setting Request Unit 24 Counter Initialization Processing Unit 25 Input / Output Signal Pin 26 Data Transmission Unit 27 Data Reception Unit 28 PKG Communication CLK
30 CLK generator reset signal line 31 DATA signal line 40 open collector circuit 41 counter comparison circuit 42 pull-up resistor 43 operational amplifier 44 power supply voltage monitoring circuit

Claims (7)

In a communication device with multiple function packages that communicate with each other,
Each function package
A data transmission / reception clock generation unit for generating a data transmission / reception clock signal synchronized in all function packages;
A communication apparatus comprising: The data transmission / reception clock generation unit includes:
A fixed oscillator,
A counter for counting the reference clock signal, generating a clock signal for data transmission / reception by dividing the reference clock signal output from the fixed oscillator;
When the count value of the counter reaches a predetermined value, the initialization setting request unit that resets the counter of the self-function package and outputs a reset signal that also resets the counter of the other function package,
The communication apparatus according to claim 1, further comprising:   3. The communication apparatus according to claim 2, wherein the reset signal output unit of the initialization setting request unit is connected to a common reset signal line in which reset signals from all function packages are wired-OR connected. The initialization setting request unit includes:
An open collector circuit;
A pull-up resistor,
With
The communication device according to claim 3, wherein the reset signal is low active.   3. The communication device according to claim 2, wherein each function package is mounted on the communication device, and the initialization setting request unit outputs a reset signal when the activation is completed.   The communication apparatus according to claim 2, wherein the counter repeatedly counts up, and the initialization setting request unit outputs a reset signal each time the counter value reaches a predetermined value.   The communication apparatus according to claim 6, wherein the reset signal is output before a phase shift of the data transmission / reception clock signal reaches a half cycle of the data transmission / reception clock signal.

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