JP2013183032A - Semiconductor light-emitting element - Google Patents

Abstract

A semiconductor light emitting device having high light output is provided.
In a semiconductor light emitting device, a semiconductor light emitting layer has a multiple quantum well structure in which well layers having a thickness of 6 nm or more and 10 nm or less and barrier layers are alternately stacked, and a main surface is polar. Surface. The semiconductor light emitting layer 15 is provided between the first conductive type first semiconductor layer 12 and the second conductive type second semiconductor layers 13 and 14. The first electrode 16 and the second electrode 18 are electrically connected to the first semiconductor layer 12 and the second semiconductor layer 14 so that a current flows in a direction substantially perpendicular to the main surface of the semiconductor light emitting layer 15.
[Selection] Figure 1

Description

  Embodiments described herein relate generally to a semiconductor light emitting device.

  Conventionally, a nitride semiconductor light-emitting device has a nitride semiconductor light-emitting layer having a multiple quantum well structure in which a main surface is a polar surface and well layers and barrier layers are alternately stacked, and the nitride semiconductor light-emitting device has a substantially perpendicular direction to the main surface. Some are configured to allow current to flow.

  In this semiconductor light emitting device, an InGaN well layer and an InGaN barrier layer having a smaller In composition than the GaN barrier layer or the InGaN well layer are used. Since InGaN has a larger lattice constant than GaN, compressive strain is applied to the InGaN well layer.

  A piezoelectric field is induced in the nitride semiconductor due to compressive strain. Due to the piezo electric field, holes and electrons injected into the InGaN well layer are spatially separated, preventing luminescence recombination.

  In order to suppress the reduction of light emission recombination due to the piezoelectric effect, an InGaN well layer having a thickness as thin as 3 nm or less is often used. When the InGaN well layer is thinned, holes and electrons come close to each other, so that a decrease in light-emitting recombination of holes and electrons is suppressed.

  However, when a semiconductor light emitting device having an InGaN well layer as thin as 3 nm or less is driven with a large current, the carrier density in the InGaN well layer may become too high. As a result, Auger recombination that increases with the third power of the carrier density is increased rather than light emission recombination that increases with the second power of the carrier density. Furthermore, the number of carriers overflowing from the InGaN well layer increases. Therefore, there is a problem that the internal light emission efficiency is lowered and a semiconductor light emitting device having a high light output cannot be obtained.

JP 2009-200137 A

  The present invention provides a semiconductor light emitting device having high light output.

  According to one embodiment, in a semiconductor light emitting device, the semiconductor light emitting layer has a multiple quantum well structure in which well layers and barrier layers having a thickness of 6 nm to 10 nm are alternately stacked, and the main surface is a polar surface. It is. The semiconductor light emitting layer is provided between a first conductive type first semiconductor layer and a second conductive type second semiconductor layer. The first electrode and the second electrode are electrically connected to the first and second semiconductor layers so that a current flows in a direction substantially perpendicular to the main surface of the semiconductor light emitting layer.

The figure which shows the semiconductor light-emitting device based on an Example. Sectional drawing which shows the principal part of the semiconductor light-emitting device based on an Example. The figure which shows the crystal structure of the semiconductor light-emitting device based on an Example. The figure which shows the characteristic of the semiconductor light-emitting device based on an Example. The figure which shows the characteristic of the semiconductor light-emitting device based on an Example. Sectional drawing which shows the manufacturing process of the semiconductor light-emitting device based on an Example in order. Sectional drawing which shows the manufacturing process of the semiconductor light-emitting device based on an Example in order. Sectional drawing which shows the manufacturing process of the semiconductor light-emitting device based on an Example in order. Sectional drawing which shows another semiconductor light-emitting device based on an Example. Sectional drawing which shows another semiconductor light-emitting device based on an Example. Sectional drawing which shows the principal part of another semiconductor light-emitting device based on an Example.

  Embodiments of the present invention will be described below with reference to the drawings.

  A semiconductor light emitting device according to this example will be described with reference to FIG. FIG. 1 is a diagram showing a semiconductor light emitting device of this example, FIG. 1 (a) is a plan view thereof, and FIG. 1 (b) is cut along the line AA in FIG. FIG. The semiconductor light emitting device of this example is a blue LED (Light Emitting Diode) using an InGaN-based nitride semiconductor.

  As shown in FIG. 1, in the semiconductor light emitting device 10 of this example, the semiconductor stacked body 11 includes an N-type GaN clad layer 12 that is a first semiconductor layer of a first conductivity type and a second semiconductor of a second conductivity type. P-type GaN cladding layer 13 and P-type GaN contact layer 14 which are layers, and a semiconductor light emitting layer 15 provided between N-type GaN cladding layer 12 and P-type GaN cladding layer 13 are included.

  As will be described later, the semiconductor stacked body 11 is epitaxially grown on a C-plane sapphire substrate via a buffer layer. The growth surface (main surface) of the semiconductor stacked body 11 is a C plane. The main surface 15a of the semiconductor light emitting layer 15 is also a C plane and a polar plane.

  The N-type GaN clad layer 12 has a concavo-convex portion 12 a on the upper surface opposite to the semiconductor light emitting layer 15. Light incident on the concavo-convex portion 12 a from the semiconductor light emitting layer 15 side is scattered or refracted by the concavo-convex portion 12 a and is extracted from the upper surface of the N-type GaN clad layer 12. The uneven portion 12 a improves the light extraction efficiency from the upper surface of the N-type GaN cladding layer 12.

  A transparent conductive film (first electrode) 16 that is transparent to the light emitted from the semiconductor light emitting layer 15 is provided on the concavo-convex portion 12 a of the N-type GaN cladding layer 12. The transparent conductive film 16 is provided on substantially the entire surface of the concavo-convex portion 12 a of the N-type GaN cladding layer 12.

  The transparent conductive film 16 has a concavo-convex portion reflecting the concavo-convex portion 12 a of the N-type GaN clad layer 12 on the upper surface opposite to the semiconductor light emitting layer 15.

  The transparent conductive film 16 is an ITO (Indium Tin Oxide) film having a thickness of 100 to 200 nm, for example. The current is spread to the periphery of the semiconductor stacked body 11 by the transparent conductive film 16. In order to spread the current, the ITO film should be thicker. On the other hand, the ITO film absorbs light although it is slight, so that it is preferable to be thin in order to extract more light. Hereinafter, the transparent conductive film is also referred to as an ITO film.

  Note that the P-type nitride semiconductor has a higher resistivity than a transparent conductive film such as an ITO film and has a high sheet resistance because it is difficult to grow thick. The current spreads almost through the transparent conductive film 16. The spread of current through the P-type GaN layers such as the P-type GaN cladding layer 13 and the P-type GaN contact layer 14 can be ignored.

  A pad electrode 17a for bonding wires is provided at the center of the transparent conductive film 16. Further, the transparent conductive film 16 has a thin frame line along the outer periphery and a thin line extending in the diagonal direction of the frame from the pad electrode 17a and connected to the corner of the thin frame line. An electrode 17b is provided. The thin wire electrode 17b is, for example, a gold (Au) film having a width of 2 μm.

  Since the sheet resistance of the transparent conductive film 16 is much higher than the sheet resistance of the thin wire electrode 17b, the spread of current to the peripheral portion becomes worse as the size of the semiconductor laminate 11 increases. The thin wire electrode 17b is provided to promote the spread of current by the transparent conductive film 16.

  A metal electrode (second electrode) 18 is provided on the P-type GaN contact layer 14 opposite to the semiconductor light emitting layer 15. The metal electrode 18 is provided on substantially the entire surface of the P-type GaN contact layer 14. The metal electrode 18 is, for example, a laminated film of silver (Ag) and gold (Au) capable of ohmic contact with P-type GaN. Since silver has a high reflectance of light, it efficiently reflects light incident from the semiconductor light emitting layer 15 side.

  The semiconductor laminate 11 is provided on the conductive support substrate 20 with the metal electrode 18 side sandwiching the bonding layer 19. The bonding layer 19 is, for example, a gold tin (AuSn) alloy layer. The support substrate 20 is a silicon substrate, for example.

  A substrate electrode 21 is provided on the support substrate 20 on the side opposite to the semiconductor laminate 11. The substrate electrode 21 is, for example, a gold film capable of ohmic contact with silicon.

As shown in FIG. 2, the semiconductor light emitting layer 15 includes an In _x1 Ga _(1-x1) N well layer 25 (hereinafter simply referred to as an InGaN well layer) and an In _x2 Ga _(1-x2) N barrier layer 26 (hereinafter, referred to as “In _x1 Ga”). This is a quantum well structure in which the InGaN barrier layers are simply stacked. The semiconductor light emitting layer 15 starts with an InGaN barrier layer and ends with an InGaN barrier layer.

  Here, x1 and x2 have a relationship of 0 ≦ x2 <x1 <1. The In composition x1 of the InGaN well layer 26 is set to, for example, about 0.15 so that light having a wavelength of 450 nm is emitted from the semiconductor light emitting device 10. The In composition x2 of the InGaN barrier layer 25 is set to, for example, 0.05 so that the band gap is wider than the band gap of the InGaN well layer 26.

  The thickness W1 of the InGaN well layer 26 is set to 6 nm or more and 10 nm or less. Desirably, it is set to 8 nm or more and 9 nm or less. The number of InGaN well layers 26 may be two or more. The thickness W2 of the InGaN barrier layer 26 is, for example, 5 nm to 20 nm.

For example, the N-type GaN cladding layer 12 has a thickness of 2 to 5 μm and an impurity concentration of 1E19 cm ⁻³ . The N-type GaN cladding layer 12 also serves as a base single crystal layer for epitaxial growth from the semiconductor light emitting layer 15 to the P-type GaN contact layer 14.

The P-type GaN cladding layer 14 has, for example, a thickness of 100 nm and an impurity concentration of 1E20 cm ⁻³ . For example, the P-type GaN contact layer 14 has a thickness of 10 nm and an impurity concentration of 1E21 cm ⁻³ .

  When a voltage is applied between the pad electrode 17a and the substrate electrode 21, a current flows through the semiconductor light emitting layer 15 in a direction substantially perpendicular to the main surface 15a. The carriers injected into the InGaN well layer 26 recombine with light and, for example, light having a peak wavelength of about 450 nm is emitted.

  In the semiconductor light emitting device 10 described above, the InGaN well layer 26 is thicker than a general thickness (about 3 nm) so that the carrier density in the InGaN well layer 26 does not become excessive when a large current flows. It is configured.

  FIG. 3 is a diagram showing a crystal structure of a nitride semiconductor. As shown in FIG. 3, the crystal structure of GaN is a hexagonal wurtzite type. The main surface 15a of the semiconductor light emitting layer 15 is a C plane (0001), which is a polar surface. Since InGaN stacked on GaN has a larger lattice spacing than GaN, it is distorted by compressive stress. A piezoelectric field is generated in the c-axis direction, which is the growth axis.

  4 and 5 are diagrams showing the results of simulating the light output characteristics of the semiconductor light emitting device 10. The simulation is performed in consideration of the piezoelectric field described above.

  4A is a diagram showing the relationship between the current and the optical output, using the thickness W1 of the InGaN well layer 26 as a parameter, and FIG. 4B is a diagram showing the relationship between the thickness W1 of the InGaN well layer 26 and the optical output. It is.

  As initial conditions, the thickness of the InGaN barrier layer 25 was 5 nm, and the number of InGaN well layers 26 was eight. The thickness W1 of the InGaN well layer 26 was changed from 2.5 nm to 10 nm. A semiconductor light emitting device having an InGaN well layer with a thickness of 2.5 nm was used as a comparative example. White circles show experimental results of the semiconductor light emitting device of the comparative example.

  As shown in FIG. 4A, when the thickness W1 of the InGaN well layer 26 is 2.5 nm to 10 nm, the light output increases monotonically while showing a saturation tendency as the current increases. When the thickness W1 of the InGaN well layer 26 is 2.5 nm, the light output substantially matches the experimental result of the semiconductor light emitting device of the comparative example. This shows the validity of the simulation.

  When the thickness W1 of the InGaN well layer 26 is 4 nm to 10 nm, a light output sufficiently higher than the experimental result (white circle) of the semiconductor light emitting device of the comparative example is obtained. The light output is about 1.5 times to about 2 times.

  As shown in FIG. 4B, the light output generally tends to increase according to the thickness W1 of the InGaN well layer 26. Specifically, the optical output increases, but the thickness W1 of the InGaN well layer 26 tends to saturate once from 6 nm to 7 nm.

  Further, when the thickness W1 of the InGaN well layer 26 is changed from 8 nm to 9 nm, the light output tends to increase again from the saturation tendency. Furthermore, when the thickness W1 of the InGaN well layer 26 is set to 10 nm, the light output is reversed and reduced.

  The relationship between the thickness W1 of the InGaN well layer 26 and the light output has a peak at a thickness of 9 nm. In particular, when the thickness W1 of the InGaN well layer 26 is 8 nm and 9 nm, an optical output approximately twice as high is obtained. Even if the thickness W1 of the InGaN well layer 26 is 6 nm, an optical output about 1.8 times higher is obtained.

  When the thickness W1 of the InGaN well layer 26 is 8 nm to 9 nm, the light output tends to be remarkably increased. This is considered to indicate a critical characteristic that is not expected from the fitting curve 40 obtained by simply curve fitting the light output when the thickness W1 of the InGaN well layer 26 is 2.5 nm to 6 nm. .

  On the other hand, when the thickness W1 of the InGaN well layer 26 exceeds 10 nm, the thickness W1 of the InGaN well layer 26 is not less than 6 nm and not more than 10 nm. Is suitable. Desirably, the thickness W1 of the InGaN well layer 26 is 8 nm or more and 9 nm or less.

  In general, in a nitride semiconductor light emitting device, when the InGaN well layer is thick, holes and electrons are spatially separated in the InGaN well layer due to the piezo effect, so that light emission recombination is suppressed and light output is reduced. It has been.

  When a current flows in a direction substantially perpendicular to the main surface of the semiconductor light emitting layer and the distance between the semiconductor light emitting layer and the electrode is short, a voltage is applied almost directly to the semiconductor light emitting layer. For this reason, electrons and holes increase in the InGaN well layer as compared with the case where there is a current component flowing obliquely through the semiconductor light emitting layer even with the same current.

  Holes are injected into the semiconductor light emitting layer 15 from the P-type GaN clad layer 13 side and electrons from the N-type GaN clad layer 12 side from the opposite sides. Holes remain on the P-type GaN cladding layer 13 side due to their large effective mass, and electrons reach the P-type GaN cladding layer 13 side because of their small effective mass.

  As a result, the ratio of recombination in the InGaN well layer 26 on the P-type GaN cladding layer 13 side increases. When holes and electrons are concentrated in one InGaN well layer 26, the carrier density becomes excessively high when the InGaN well layer 26 is thin.

  When the carrier density becomes excessively high, the optical output decreases due to the effects of Auger recombination and carrier overflow. Since Auger recombination increases with the third power of the carrier density, the Auger recombination becomes larger than the light emission recombination that increases with the second power of the carrier density.

  Therefore, when the thickness W1 of the InGaN well layer 26 is 6 nm or more, the carrier density is lowered, so that Auger recombination can be suppressed and the light output can be increased. Further, when the thickness W1 of the InGaN well layer 26 is 8 nm or more, it is considered that the carrier overflow is suppressed and the light output is further increased. When the thickness W1 of the InGaN well layer 26 exceeds 10 nm, it is considered that the quantum effect is reduced and the light output is also reduced.

  FIG. 5 is a diagram showing the relationship between current and light output, using the number of InGaN well layers 26 as a parameter. As initial conditions, the thickness W2 of the InGaN barrier layer 25 was 5 nm, and the thickness W1 of the InGaN well layer 26 was 8 nm. The number of InGaN well layers 26 was varied from 1 to 5.

  As shown in FIG. 5, the light output of the semiconductor light emitting device 10 increases according to the number of InGaN well layers 26. When the number of InGaN well layers 26 is 1 and when the number of InGaN well layers 26 is 2 to 5, there is a large difference in the light output of the semiconductor light emitting device 10.

  When the current is 600 mA, the light output of the semiconductor light emitting device 10 having 2 to 5 InGaN well layers 26 is increased by about 1.3 times the light output of the semiconductor light emitting device 10 having 1 InGaN well layer 26. .

  On the other hand, there is no significant difference in the light output of the semiconductor light emitting device 10 having 2 to 5 InGaN well layers 26. More specifically, when the current is 400 mA or less, the light output is substantially the same regardless of the number of InGaN well layers 26. When the current is 400 mA or more, the light output slightly increases according to the number of InGaN well layers 26.

  When the number of InGaN well layers 26 is 1, carriers are concentrated in one InGaN well layer 26, and the overflow of carriers is the main cause of a decrease in light output. When there are a plurality of InGaN well layers 26, carriers are dispersed in each InGaN well layer 26, so that carrier overflow is suppressed.

  Accordingly, the larger the number of InGaN well layers 26, the better. However, since the increase in light output is small, it is sufficient that the number of InGaN well layers 26 is two or more.

  Next, a method for manufacturing the semiconductor light emitting device 10 will be described with reference to FIGS. 6 to 9 are cross-sectional views sequentially showing the manufacturing process of the semiconductor light emitting device 10.

  As shown in FIG. 6A, an N-type GaN cladding layer 12, a semiconductor light emitting layer 15, a P-type GaN cladding layer 13, and a P-type GaN contact are formed on a C-plane sapphire substrate 51 by MOCVD (Metal Organic Chemical Vapor Deposition) method. The layer 14 is sequentially epitaxially grown to form the semiconductor stacked body 11.

A manufacturing process of the semiconductor stacked body 11 will be briefly described below. As a pretreatment, the sapphire substrate 51 is subjected to, for example, organic cleaning and acid cleaning, and then stored in a reaction chamber of the MOCVD apparatus. Next, the temperature of the sapphire substrate 51 is raised to, for example, 1100 ° C. by high-frequency heating in an atmospheric pressure mixed gas atmosphere of nitrogen (N ₂ ) gas and hydrogen (H ₂ ) gas, for example. Thereby, the surface of the sapphire substrate 51 is vapor-phase etched, and the natural oxide film formed on the surface is removed.

Next, a mixed gas of N ₂ gas and H ₂ gas is used as a carrier gas, and as a process gas, for example, ammonia (NH ₃ ) gas and trimethylgallium (TMG) are supplied, and as an N-type dopant, For example, silane (SiH ₄ ) gas is supplied to form the N-type GaN layer 12 having a thickness of 4 μm and a Si concentration of about 1E19 cm ⁻³ .

Next, the supply of the TMG gas and the SiH ₄ gas is stopped while the NH ₃ gas is continuously supplied, and the temperature of the sapphire substrate 51 is lowered to a temperature lower than 1100 ° C., for example, 800 ° C., and held at 800 ° C.

Next, N ₂ gas is used as a carrier gas, and as a process gas, for example, NH ₃ gas, TMG gas, and tri-methyl indium (TMI) gas are supplied, and the thickness is 5 nm and the In composition ratio is 0.05. By forming the InGaN barrier layer 25 and increasing the supply of TMI, the InGaN well layer 26 having a thickness of 8 nm and an In composition ratio of 0.15 is formed.

  Next, by increasing or decreasing the supply of TMI gas, the formation of the InGaN barrier layer 25 and the InGaN well layer 26 is repeated, for example, twice. Finally, the InGaN barrier layer 25 is formed. Thereby, the semiconductor light emitting layer 15 of MQW structure is obtained.

Next, the supply of TMI gas is stopped while continuously supplying TMG gas and NH ₃ gas, and an undoped GaN cap layer (not shown) having a thickness of 5 nm is formed.

Next, the supply of TMG gas is stopped while continuing to supply NH ₃ gas, and the temperature of the sapphire substrate 51 is raised to a temperature higher than 800 ° C., for example, 1030 ° C., and held at 1030 ° C. in an N ₂ gas atmosphere. To do.

Next, a mixed gas of N ₂ gas and H ₂ gas is used as a carrier gas, NH ₃ gas as a process gas, TMG gas, and biscyclopentadienyl magnesium (Cp 2 Mg) gas as a P-type dopant are supplied, and the thickness is 100 nm. Then, a P-type GaN cladding layer 13 having an Mg concentration of about 1E20 cm ⁻³ is formed.

Next, the supply of Cp2Mg gas is increased to form a P-type GaN contact layer 14 having a thickness of 10 nm and an Mg concentration of about 1E21 cm ⁻³ .

Next, the supply of the TMG gas is stopped while continuing to supply the NH ₃ gas, and only the carrier gas is continuously supplied, and the sapphire substrate 51 is naturally cooled. The supply of NH ₃ gas is continued until the temperature of the sapphire substrate 51 reaches 500 ° C. Thereby, the semiconductor stacked body 11 is formed on the sapphire substrate 51, and the P-type GaN contact layer 14 becomes the surface.

  Next, as shown in FIG. 6B, a silver film having a thickness of about 0.5 μm and a gold film having a thickness of 1 μm are stacked on the P-type GaN contact layer 14 by, for example, a sputtering method to form the metal electrode 18. Form.

  Next, as shown in FIG. 6C, a silicon substrate 52 is prepared, and gold films 53 and 54 having a thickness of 1 μm are formed on both surfaces of the silicon substrate 52 by, eg, sputtering. A gold tin alloy film 55 having a thickness of 2 μm is formed on the gold film 53 by, for example, a vacuum deposition method. The silicon substrate 52 is the support substrate 20, and the gold film 54 is the substrate electrode 21.

  Next, as shown in FIG. 7A, the sapphire substrate 51 is turned upside down so that the metal electrode 18 and the gold-tin alloy film 55 face each other, and the sapphire substrate 51 and the silicon substrate 52 are overlaid, and then the sapphire substrate. 51 and the silicon substrate 52 are heated by a heater 56 and pressurized.

  The gold-tin alloy film 55 is melted, and the bonding layer 19 fused with the gold film of the metal electrode 18 and the gold film 53 is formed. The sapphire substrate 51 and the silicon substrate 52 are bonded via the bonding layer 19.

  Next, as shown in FIG. 7B, the sapphire substrate 51 and the semiconductor stacked body 11 are separated by a laser lift-off method. The laser lift-off method is a method in which the inside of a substance is partially thermally decomposed by irradiating with a high-power laser beam, and the decomposed portion is separated as a boundary.

  Specifically, a laser beam that passes through the sapphire substrate 51 and is absorbed by the N-type GaN cladding layer 12 is irradiated to dissociate the N-type GaN cladding layer 12 to separate the sapphire substrate 51 and the N-type GaN cladding layer 12. .

  For example, the fourth harmonic (266 nm) of an Nd-YAG laser is irradiated from the sapphire substrate 51 side. Since sapphire is transparent to this light, the irradiated light passes through the sapphire substrate 51 and is effectively absorbed by the N-type GaN cladding layer 12.

Since there are many crystal defects in the N-type GaN cladding layer 12 in the vicinity of the interface with the sapphire substrate 51, almost all of the absorbed light is converted into heat, and a reaction of 2GaN = 2Ga + N ₂ (g) ↑ occurs. As a result, GaN dissociates into Ga and N ₂ gas.

  The laser may be continuous light (CW) or pulsed light (PW), but is preferably pulsed light with a high peak output. As a pulse laser having a high peak output, a Q-switched laser, a mode-locked laser, or the like that can output ultrashort pulsed light on the order of picoseconds to femtoseconds is suitable.

  After the dissociation, the Ga layer 57 is left on the exposed N-type GaN cladding layer 12. The Ga layer 57 is removed with warm water or an aqueous solution containing hydrochloric acid.

  Next, as shown in FIG. 8A, the uneven portion 12 a is formed in the exposed N-type GaN clad layer 12. Specifically, for example, the N-type GaN clad layer 12 is wet-etched with an aqueous KOH solution. For example, a KOH aqueous solution having a concentration of about 20% to 40% and a temperature of about 60 ° C. to 70 ° C. is appropriate. Since the N-polar GaN surface is anisotropically etched with a KOH aqueous solution, the concavo-convex portion 12 a is formed in the N-type GaN cladding layer 12.

  Next, as shown in FIG. 8B, an ITO film 58 having a thickness of about 200 nm is formed on the N-type GaN cladding layer 12 on which the concavo-convex portion 12a is formed by, for example, sputtering. In order to promote the crystallization of the ITO film 58 and increase the conductivity of the ITO film 58, the ITO film 58 is subjected to a heat treatment.

  For the heat treatment, for example, in a nitrogen atmosphere or a mixed atmosphere of nitrogen and oxygen, a temperature of about 400 to 750 ° C. and a time of about 1 to 20 minutes are appropriate. At this stage, the ITO film 58 becomes the transparent conductive film 16 shown in FIG.

  Next, a gold film is formed on the transparent conductive film 16 by sputtering, for example, and the gold film is patterned by photolithography to form the pad electrode 17a and the fine wire electrode 17b. Thereby, the semiconductor light emitting device 10 shown in FIG. 1 is obtained.

  Note that the thickness W2 of the InGaN barrier layer 25 and the thickness W1 of the InGaN well layer 26 can be obtained by cross-sectional TEM (Transmission Electron Microscope) observation or X-ray reflectivity method.

  According to the cross-sectional TEM observation, the thickness W2 of the InGaN barrier layer 25 and the thickness W1 of the InGaN well layer 26 can be directly obtained. The lattice constant of GaN is about 0.319 nm for the a axis and about 0.518 nm for the c axis. In the InGaN well layer 26 having a thickness W1 of 8 nm, about 16 InGaN lattices are stacked.

  According to the X-ray reflectivity method, the thickness W2 of the InGaN barrier layer 25 and the thickness W1 of the InGaN well layer 26 can be obtained indirectly. The X-ray reflectivity method is a method in which X-rays are incident on a sample surface at a very shallow angle, and the X-ray reflection intensity profile is analyzed to determine the film thickness, density, and the like of the sample.

  Specifically, when X-rays are incident on the thin film at an extremely shallow angle, the surface of the thin film, the thin film / substrate interface, and the X-rays reflected at each interface interfere with each other. The reflectance profile obtained by continuously changing the incident angle shows a specific vibration structure depending on the film thickness, density, and interface roughness of the material. This profile can be analyzed based on a theoretical formula, and physical properties such as film thickness, density, and roughness of the thin film can be evaluated.

  If a high-intensity parallel beam is used, it is possible to measure an extremely thin film (on the order of several nm). A high-intensity parallel beam is obtained by using, for example, a parabolic artificial multilayer film in an X-ray incident optical system.

  As described above, in the semiconductor light emitting device 10 of this example, the semiconductor light emitting layer 15 has a main surface of a polar surface and a thickness W1 of 8 nm, which is a commonly used thickness (about 3 nm). It has an MQW structure in which thicker InGaN well layers 26 and InGaN barrier layers 25 are alternately stacked. A transparent conductive film 16 and a metal electrode 18 are provided so that a current flows in a direction substantially perpendicular to the main surface of the semiconductor light emitting layer 15.

  As a result, even when driven with a large current, the carrier density in the InGaN well layer 26 is properly maintained, so Auger recombination can be suppressed and carrier overflow can be prevented. Therefore, a semiconductor light emitting device having a high light output can be obtained.

  The semiconductor light emitting device 10 can further be provided with an overflow prevention layer for preventing carrier overflow. A superlattice buffer layer for improving the crystallinity of the semiconductor stacked body 15 can be provided. FIG. 9 is a cross-sectional view showing a semiconductor light emitting device having an overflow prevention layer and a superlattice buffer layer.

  As shown in FIG. 9, in the semiconductor stacked body 61 of the semiconductor light emitting device 60, a P-type AlGaN overflow prevention layer 62 is provided between the semiconductor light-emitting layer 15 and the P-type GaN cladding layer 13.

The P-type AlGaN overflow prevention layer 62 has, for example, a thickness of 5 nm, an Mg concentration of 1E20 cm ⁻³ , and an Al composition ratio of 0.2. The band gap of the P-type AlGaN overflow prevention layer 62 is larger than the band gap of the P-type GaN cladding layer 13.

  A superlattice buffer layer 63 is provided between the semiconductor light emitting layer 15 and the N-type GaN cladding layer 12. In the superlattice buffer layer 63, for example, 30 pairs of first and second InGaN layers having different In compositions are alternately stacked.

  The first InGaN layer has a thickness of 1 nm, for example, and the second InGaN layer has a thickness of 3 nm, for example. The In composition of the first InGaN layer is larger than the In composition of the second InGaN layer.

  The P-type AlGaN overflow prevention layer 62 effectively suppresses the overflow of carriers in the InGaN well layer 26 to the P-type GaN cladding layer 13. The superlattice buffer layer 63 suppresses the propagation of crystal defects such as dislocations from the N-type GaN cladding layer 12 to the semiconductor light emitting layer 15. As a result, there is an advantage that the light output of the semiconductor light emitting device 60 can be further increased.

  Although the case where the support substrate 20 is a silicon substrate has been described here, other conductive substrates can be used. Examples of the conductive substrate include a metal substrate, a conductive ceramic substrate, and a germanium (Ge) substrate. The conductive ceramic substrate is, for example, a SiC ceramic substrate.

  Moreover, although the case where the board | substrate which makes the semiconductor laminated body 11 grow is the C surface sapphire board | substrate 51, the electroconductive board | substrate can be used. Examples of the conductive substrate include a GaN substrate, a SiC substrate, and a ZnO substrate whose main surface is a C plane.

  FIG. 10 is a cross-sectional view showing a semiconductor light-emitting element having a semiconductor stacked body provided on a conductive substrate. As shown in FIG. 10, in the semiconductor light emitting device 70, the semiconductor stacked body 11 is provided on a growth conductive substrate 71 whose main surface is a C-plane, for example, a C-plane GaN substrate.

  An N-type GaN clad layer 12, a semiconductor light emitting layer 15, a P-type GaN clad layer 13, and a P-type GaN contact layer 14 are sequentially provided on the conductive substrate 71. The transparent conductive film 16 is provided on the P-type GaN contact layer 14.

  A substrate electrode 72 is provided on the surface of the conductive substrate 71 opposite to the N-type GaN cladding layer 12 side. The substrate electrode 72 is, for example, a Ti / Pt / Au film capable of ohmic contact with N-type GaN.

  The conductive substrate 71 can serve as both a growth substrate and a support substrate. There is an advantage that the steps of bonding the support substrate and removing the growth substrate are unnecessary.

  Note that a current blocking layer corresponding to the pad electrode 17a and the thin wire electrode 17b may be formed between the P-type GaN contact layer 14 and the transparent conductive film 16.

  Further, the transparent conductive film 16 may have a concavo-convex portion for improving the light extraction efficiency. FIG. 11 is a cross-sectional view showing a main part of a semiconductor light emitting device provided with a transparent conductive film having an uneven portion.

  As shown in FIG. 11, the transparent conductive film 80 has a concavo-convex portion 81 including a convex portion 81a mainly made of crystalline ITO and a concave portion 81b mainly made of amorphous ITO.

  In general, it is known that when an ITO film is formed by sputtering or the like, an ITO film in which amorphous ITO and crystalline ITO are mixed can be obtained depending on the substrate temperature, plasma density, oxygen partial pressure, and the like at the time of film formation. .

  For example, in terms of the substrate temperature, the crystallization temperature of ITO is in the vicinity of 150 ° C. to 200 ° C. When the substrate temperature is near the crystallization temperature, an ITO film in which amorphous ITO and crystalline ITO are mixed is obtained.

  It has been confirmed from cross-sectional TEM observation and electron diffraction pattern that crystalline ITO is dispersed in the ITO film so as to be surrounded by amorphous ITO and exists in a pillar shape.

  The etching rate of crystalline ITO is slower than the etching rate of amorphous ITO. The etching rate of crystalline ITO is, for example, about 50 to 100 nm / min. The etching rate of amorphous ITO is, for example, about 100 to 500 nm / min. Therefore, the selective ratio between crystalline ITO and amorphous ITO is expected to be about 2 to 5.

  A transparent conductive film having a concavo-convex portion 81 by selectively removing amorphous ITO having a high etching rate by using the difference in etching rate between crystalline ITO and amorphous ITO, and leaving the crystalline ITO having a low etching rate. 80 is obtained.

  Note that the transparent conductive film 80 is preferably formed thick in advance in anticipation of etching loss.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

The present invention can be configured as described in the following supplementary notes.
(Supplementary note 1) The semiconductor light emitting element according to claim 1, wherein the first semiconductor layer includes an N-type GaN cladding layer, and the second semiconductor layer includes a P-type GaN cladding layer and a P-type GaN contact layer.

(Additional remark 2) The said 1st semiconductor layer is a semiconductor light-emitting device of Additional remark 1 which has a superlattice buffer layer provided between the said N-type GaN cladding layer and the said semiconductor light emitting layer.

(Additional remark 3) The said 2nd semiconductor layer is a semiconductor light-emitting device of Additional remark 1 which has a P-type AlGaN overflow prevention layer provided between the said P-type GaN clad layer and the said semiconductor light emitting layer.

(Supplementary Note 4) The transparent conductive film is an ITO film, a semiconductor light-emitting device according to claim 4 which is a ZnO film or Sn ₂ O film.

(Additional remark 5) The semiconductor light-emitting device of Claim 4 with which the fine wire electrode is provided on the said transparent conductive film.

(Additional remark 6) The semiconductor light emitting element of Claim 4 with which the said semiconductor light emitting layer is provided on the electroconductive support substrate on both sides of the said 2nd electrode.

(Appendix 7) a conductive support substrate;
A first semiconductor layer of a first conductivity type, a semiconductor light emitting layer having a multiple quantum well structure in which well layers and barrier layers having a thickness of 6 nm to 10 nm are alternately stacked, and the main surface is a polar surface; , A semiconductor stacked body in which second semiconductor layers of the second conductivity type are sequentially stacked;
A transparent conductive film provided on the first semiconductor layer and having a light-transmitting property with respect to light emitted from the semiconductor light emitting layer;
A fine wire electrode provided on the transparent conductive film;
A metal electrode that is provided between the conductive substrate and the second semiconductor layer and reflects light emitted from the semiconductor light emitting layer;
A semiconductor light emitting device comprising:

(Appendix 8)
The semiconductor light-emitting element according to appendix 6 or appendix 7, wherein the conductive support substrate is a silicon substrate, a metal substrate, a ceramic substrate, or a germanium substrate.

DESCRIPTION OF SYMBOLS 10, 60, 70 Semiconductor light emitting element 11, 61 Semiconductor laminated body 12 N-type GaN clad layer 12a, 81 Uneven part 13 P-type GaN clad layer 14 P-type GaN contact layer 15 Semiconductor light-emitting layer 15a Main surface 16, 80 Transparent conductive film 17 Pad electrode 17a Fine wire electrode 18 Metal electrode 19 Bonding layer 20 Support substrate 21, 72 Substrate electrode 25 InGaN barrier layer 26 InGaN well layer 51 Sapphire substrate 52 Silicon substrate 53, 54 Gold film 55 Gold-tin alloy film 56 Heater 57 Ga layer 58 ITO film 62 P-type AlGaN overflow prevention layer 63 Superlattice buffer layer 71 Conductive substrate

Claims (7)

A first semiconductor layer of a first conductivity type;
A second semiconductor layer of a second conductivity type;
A semiconductor which is provided between the first and second semiconductor layers and has a multiple quantum well structure in which well layers and barrier layers having a thickness of 6 nm to 10 nm are alternately stacked, and the main surface is a polar surface A light emitting layer;
A first electrode and a second electrode electrically connected to the first and second semiconductor layers so that a current flows in a direction substantially perpendicular to the main surface of the semiconductor light emitting layer;
A semiconductor light emitting element comprising: The semiconductor light emitting element according to claim 1, wherein the well layer has a thickness of 8 nm to 9 nm.   The semiconductor light emitting element according to claim 1, wherein the semiconductor light emitting layer has two or more well layers.   The first electrode is a transparent conductive film that is provided on the first semiconductor layer and is transparent to light emitted from the semiconductor light emitting layer, and the second electrode is formed on the second semiconductor layer. The semiconductor light emitting element according to claim 1, wherein the semiconductor light emitting element is a metal electrode that is provided and reflects light emitted from the semiconductor light emitting layer.   The semiconductor light emitting device according to claim 4, further comprising a thin wire electrode provided on the transparent conductive film.   The semiconductor light emitting element according to claim 1, wherein the first semiconductor layer has a concavo-convex portion on at least a part of a main surface. The well layer is In _x1 Ga _y1 Al _(1-x1-y1) N (0 <x1 <1, 0 <y1 ≦ 1), and the barrier layer is In _x2 Ga _y2 Al _(1-x2-y2) N 2. The semiconductor light emitting device according to claim 1, wherein (0 ≦ x2 <x1 <1, 0 <y1 <y2 ≦ 1).

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