JP2013214700A - Semiconductor light-emitting element - Google Patents

Abstract

A semiconductor light emitting device having high light output is provided.
In a semiconductor light emitting device, a semiconductor light emitting layer is provided between an N type semiconductor layer and P type semiconductor layers. The semiconductor light emitting layer 15 has a multiple quantum well structure in which well layers 26 and barrier layers 25 are alternately stacked. Of the barrier layers 25 sandwiched between the well layers 26, the band gap of the barrier layer 25b closest to the P-type semiconductor layer 13 is narrower than the band gaps of the remaining barrier layers 25c and 25d. The N-side electrodes 17a, 17b and the P-side electrode 18 are electrically connected to the N-type semiconductor layer 12 and the P-type semiconductor layer 14 so that current flows in a direction substantially perpendicular to the main surface 15a of the semiconductor light emitting layer 15. ing.
[Selection] Figure 1

Description

  Embodiments described herein relate generally to a semiconductor light emitting device.

  Conventionally, a nitride semiconductor light emitting device has a semiconductor light emitting layer having a multiple quantum well structure in which well layers and barrier layers are alternately stacked so that a current flows in a direction substantially perpendicular to the main surface of the semiconductor light emitting layer. Some are configured. The semiconductor light emitting layer is provided between the N-type semiconductor layer and the P-type semiconductor layer.

  In this semiconductor light emitting device, the band gaps of the plurality of barrier layers are set equal to each other. Holes are injected from the P-type semiconductor layer side into the multi-quantum well structure semiconductor light-emitting layer, and electrons are injected from the N-type semiconductor layer side into the multi-quantum well structure semiconductor light-emitting layer.

  Since the holes are heavy, they remain in the well layer on the P-type semiconductor layer side, while the electrons are light and reach the well layer on the P-type semiconductor layer side. As a result, the proportion of holes and electrons recombined in the well layer on the P-type semiconductor layer side increases.

  When holes and electrons are concentrated in one well layer and the well layer is thin, the carrier density may become excessively high. As a result, there is a problem that non-luminous Auger recombination according to the third power of the carrier density is larger than light emission recombination according to the second power of the carrier density, and the light output is reduced.

JP 2011-86910 A

  An object of the present invention is to provide a semiconductor light emitting device having high light output.

  According to one embodiment, in the semiconductor light emitting device, the semiconductor light emitting layer is provided between the N-type semiconductor layer and the P-type semiconductor layer. The semiconductor light emitting layer has a multiple quantum well structure in which well layers and barrier layers are alternately stacked. Of the barrier layers sandwiched between the well layers, the band gap of the barrier layer closest to the P-type semiconductor layer is narrower than the band gap of the remaining barrier layers. The N-side electrode and the P-side electrode are electrically connected to the N-type semiconductor layer and the P-type semiconductor layer so that a current flows in a direction substantially perpendicular to the main surface of the semiconductor light emitting layer.

1 is a diagram illustrating a semiconductor light emitting element according to Embodiment 1. FIG. FIG. 3 is a cross-sectional view illustrating a main part of the semiconductor light emitting element according to the first embodiment. The figure which shows the relationship between the composition of the principal part which concerns on Embodiment 1, and a band gap. FIG. 3 is a view showing a composition distribution of a main part of the semiconductor light emitting element according to Embodiment 1. FIG. 3 is a diagram illustrating the light output characteristics of the semiconductor light emitting device according to Embodiment 1 in comparison with the light output characteristics of a semiconductor light emitting device of a comparative example. FIG. 3 is a diagram showing a band structure of the semiconductor light emitting element according to Embodiment 1 in comparison with a band structure of a semiconductor light emitting element of a comparative example. Sectional drawing which shows the manufacturing process of the semiconductor light-emitting device concerning Embodiment 1 in order. Sectional drawing which shows the manufacturing process of the semiconductor light-emitting device concerning Embodiment 1 in order. Sectional drawing which shows the manufacturing process of the semiconductor light-emitting device concerning Embodiment 1 in order. FIG. 3 is a cross-sectional view showing another semiconductor light emitting element according to the first embodiment. FIG. 3 is a cross-sectional view showing another semiconductor light emitting element according to the first embodiment. FIG. 3 is a cross-sectional view showing another semiconductor light emitting element according to the first embodiment. FIG. 3 is a cross-sectional view showing a main part of another semiconductor light emitting element according to Embodiment 1. FIG. 4 is a cross-sectional view showing a main part of a semiconductor light emitting element according to a second embodiment. FIG. 6 is a view showing a composition distribution of a main part of a semiconductor light emitting element according to Embodiment 2. FIG. 6 is a diagram illustrating a semiconductor light emitting element according to a third embodiment. The figure which shows the optical output characteristic of the semiconductor light-emitting device concerning Embodiment 3 in contrast with the optical output property of the semiconductor light-emitting device of a comparative example. Sectional drawing which shows the principal part of the manufacturing process of the semiconductor light-emitting device concerning Embodiment 3 in order. Sectional drawing which shows the principal part of the manufacturing process of the semiconductor light-emitting device concerning Embodiment 3 in order. FIG. 6 is a diagram showing another semiconductor light emitting element according to the third embodiment. Sectional drawing which shows the principal part of the manufacturing process of another semiconductor light-emitting device concerning Embodiment 3 in order. Sectional drawing which shows the principal part of the manufacturing process of another semiconductor light-emitting device concerning Embodiment 3 in order. FIG. 6 is a view showing a main part of another semiconductor light emitting element according to Embodiment 3.

  Hereinafter, embodiments will be described with reference to the drawings.

(Embodiment 1)
The semiconductor light emitting device according to this embodiment will be described with reference to FIG. FIG. 1 is a diagram showing a semiconductor light emitting device of this embodiment, FIG. 1 (a) is a plan view thereof, and FIG. 1 (b) is cut along the line AA in FIG. FIG. The semiconductor light emitting device of this embodiment is a blue LED (Light Emitting Diode) using an InGaN-based nitride semiconductor.

  As shown in FIG. 1, in the semiconductor light emitting device 10 of the present embodiment, the semiconductor stacked body 11 includes an N-type GaN cladding layer 12 as an N-type semiconductor layer, a P-type GaN cladding layer 13 and a P-type as a P-type semiconductor layer. A GaN contact layer 14 and a semiconductor light emitting layer 15 provided between the N-type GaN cladding layer 12 and the P-type GaN cladding layer 13 are included.

  The N-type GaN clad layer 12 has a concavo-convex portion 12 a on the upper surface opposite to the semiconductor light emitting layer 15. Light incident on the concavo-convex portion 12 a from the semiconductor light emitting layer 15 side is scattered or refracted by the concavo-convex portion 12 a and is extracted from the upper surface of the N-type GaN clad layer 12. The uneven portion 12 a improves the light extraction efficiency from the upper surface of the N-type GaN cladding layer 12.

  A pad electrode 17a for bonding wires is provided at the center of the N-type GaN clad layer 12. Further, the N-type GaN clad layer 12 includes a frame-shaped fine line along the outer periphery and an X-shaped thin line extending from the pad electrode 17a in the diagonal direction of the frame and connected to the corner of the frame-shaped thin line. A thin wire electrode 17b (N-side electrode) is provided.

  The current is spread to the periphery of the semiconductor stacked body 11 by the thin wire electrode 17b. The thin wire electrode 17b is, for example, a gold (Au) film having a width of 2 μm. Since the thin wire electrode 17b blocks light from the semiconductor light emitting layer 15 side, the narrow wire electrode 17b is preferably narrow.

  A metal electrode (P-side electrode) 18 is provided on the P-type GaN contact layer 14 opposite to the semiconductor light emitting layer 15. The metal electrode 18 is provided on substantially the entire surface of the P-type GaN contact layer 14. The metal electrode 18 is, for example, a laminated film of silver (Ag) and gold (Au) capable of ohmic contact with P-type GaN. Since silver has a high reflectance of light, it efficiently reflects light incident from the semiconductor light emitting layer 15 side.

  The semiconductor laminate 11 is provided on the conductive support substrate 20 with the metal electrode 18 side sandwiching the bonding layer 19. The bonding layer 19 is, for example, a gold tin (AuSn) alloy layer. The support substrate 20 is a silicon substrate, for example.

  A substrate electrode 21 is provided on the support substrate 20 on the side opposite to the semiconductor laminate 11. The substrate electrode 21 is, for example, a gold film capable of ohmic contact with silicon.

As shown in FIG. 2, the semiconductor light emitting layer 15 includes In _x2 Ga _(1-x2) N barrier layers 25a, 25b, 25c, 25d, and 25e (hereinafter simply referred to as InGaN barrier layers) In _x1 Ga _(1-x1). This is a quantum well structure in which N well layers 26a, 26b, 26c, and 26d (hereinafter simply referred to as InGaN well layers) are alternately stacked. The semiconductor light emitting layer 15 starts with an InGaN barrier layer 25a and ends with an InGaN barrier layer 25e.

  The InGaN barrier layers 25a, 25b, 25c, 25d, and 25e are collectively referred to as InGaN barrier layers 25, and the InGaN well layers 26a, 26b, 26c, and 26d are collectively referred to as InGaN well layers 26.

  The thickness of the InGaN barrier layer 25 is, for example, 5 nm. The thickness of the InGaN well layer 26 is, for example, 5 nm. The number of InGaN well layers 26 is four, for example.

  The In composition x1 of the InGaN well layer 26 is set to, for example, about 0.15 so that light having a wavelength of 450 nm is emitted from the semiconductor light emitting device 10.

  The In composition x1 of the InGaN well layer 26 and the In composition x2 of the InGaN barrier layer 25 have a relationship of 0 ≦ x2 <x1 <1. The band gap of the InGaN barrier layer 25 is set to be wider than the band gap of the InGaN well layer 26.

  Further, of the InGaN barrier layers 25b, 25c, 25d sandwiched between the InGaN well layers 26, the band gap of the InGaN barrier layer 25b closest to the P-type GaN cladding layer 13 is the band gap of the remaining InGaN barrier layers 25c, 25d. It is set to be narrower.

  Except for the InGaN barrier layer 25b, the band gap of the InGaN barrier layer 25 on the N-type GaN cladding layer 12 side is equal to or wider than the band gap of the InGaN barrier layer 25 on the P-type GaN cladding layer 13 side. Is set.

  That is, when the band gap of the InGaN barrier layer 25 is expressed as Eg (25), the following relationship is established.

Eg (25b) <Eg (25c) ≦ Eg (25d) ≦ Eg (25a) = Eg (25e)
FIG. 3 is a diagram showing the relationship between the In composition x of the In _x Ga _(1-x) N layer and the band gap Eg. As shown in FIG. 3, the band gap Eg of the In _x Ga _(1-x) N layer varies from the band gap of GaN (about 3.45 eV) to the band gap of InN (about 0.7 eV) depending on the In composition x. Change to. However, it is not straight but bent downward due to band gap bowing. When x is 0.15, Eg is about 2.64 eV.

Here, the N-type GaN cladding layer 12 has a thickness of 2 to 5 μm and an impurity concentration of 1E19 cm ⁻³ , for example. The N-type GaN cladding layer 12 also serves as a base single crystal layer for epitaxial growth from the semiconductor light emitting layer 15 to the P-type GaN contact layer 14.

The P-type GaN cladding layer 13 has, for example, a thickness of 100 nm and an impurity concentration of 1E20 cm ⁻³ . For example, the P-type GaN contact layer 14 has a thickness of 10 nm and an impurity concentration of 1E21 cm ⁻³ .

  When a voltage is applied between the pad electrode 17a and the substrate electrode 21, a current flows through the semiconductor light emitting layer 15 in a direction substantially perpendicular to the main surface 15a. The carriers injected into the InGaN well layer 26 recombine with light and, for example, light having a peak wavelength of about 450 nm is emitted.

  In the semiconductor light emitting device 10 described above, the band gap of the InGaN barrier layer 25b is set to be narrower than the band gaps of the remaining InGaN barrier layers 25c and 25d, and when a large current flows, the carrier density in the InGaN well layer 26a. Is configured not to become excessive.

  Next, simulation results of the light output of the semiconductor light emitting element 10 and the light output of the semiconductor light emitting elements of the first to third comparative examples will be described with reference to FIGS. 4 and 5.

  FIG. 4 is a diagram showing the In composition distribution of the semiconductor light emitting layer 15 in the semiconductor light emitting device 10 and the semiconductor light emitting devices of the first to third comparative examples. Here, the In composition of the InGaN barrier layer 25a in contact with the P-type cladding layer 13 and the InGaN barrier layer 25e in contact with the N-type cladding layer 12 was set to zero. That is, the InGaN barrier layers 25a and 25e are simply GaN layers.

As shown in FIG. 4, in the semiconductor light emitting device 10 of the present embodiment, the In compositions x1 of the InGaN barrier layers 25b, 25c, and 25d are 0.05, 0.03, and 0, respectively. That is, the band gaps of the InGaN barrier layers 25b, 25c, and 25d increase in order from the P-type clad layer 13 side to the N-type clad layer 12, and are in the relationship of the following expression.
Eg (25b) <Eg (25c) <Eg (25d) = Eg (25a) = Eg (25e)
On the other hand, in the semiconductor light emitting device of the first comparative example, the In compositions x1 of the InGaN barrier layers 25b, 25c, and 25d are 0.03, 0.03, and 0.03, respectively. That is, the band gaps of the InGaN barrier layers 25b, 25c, and 25d are equal to each other and have the relationship of the following formula.
Eg (25b) = Eg (25c) = Eg (25d) <Eg (25a) = Eg (25e)
In the semiconductor light emitting device of the second comparative example, the In compositions x1 of the InGaN barrier layers 25b, 25c, and 25d are 0, 0.03, and 0.05, respectively. In other words, the band gaps of the InGaN barrier layers 25b, 25c, and 25d decrease in order from the P-type cladding layer 13 side to the N-type cladding layer 12, and have the relationship of the following formula.
Eg (25d) <Eg (25c) <Eg (25b) <Eg (25a) = Eg (25e)
In the semiconductor light emitting device of the third comparative example, the In compositions x1 of the InGaN barrier layers 25b, 25c, and 25d are 0, 0, and 0, respectively. That is, the band gaps of the InGaN barrier layers 25b, 25c, and 25d are equal to each other and have the relationship of the following formula. The third comparative example is a conventional In concentration distribution.
Eg (25b) = Eg (25c) = Eg (25d) = Eg (25a) = Eg (25e)
FIG. 5 is a diagram showing the result of simulating the relationship between current and light output in the semiconductor light emitting device 10 and the semiconductor light emitting devices of the first to third comparative examples. Here, the thickness of the InGaN barrier layer 25 and the InGaN well layer 26 was 5 nm, respectively.

  As shown in FIG. 5, the semiconductor light emitting device 10 of this embodiment has a higher light output than the semiconductor light emitting device of the third comparative example. On the other hand, in the semiconductor light emitting devices of the first and second comparative examples, the light output is only slightly increased compared to the semiconductor light emitting device of the third comparative example.

  6A and 6B are diagrams showing how carriers are injected into the InGaN well layer 26. FIG. 6A shows the case of this embodiment, and FIG. 6B shows the case of the third comparative example. is there. First, the third comparative example will be described.

  As shown in FIG. 6B, in the semiconductor light emitting device of the third comparative example, holes enter the semiconductor light emitting layer 15 having the MQW structure from the P-type GaN cladding layer 13 side and electrons from the N-type GaN cladding layer 12 side. Injected.

  The holes are heavy and stay on the P-type GaN cladding layer 13 side, and the electrons are light and reach the P-type GaN cladding layer 13 side. As a result, the proportion of recombination in the InGaN well layer 26a on the P-type GaN cladding layer 13 side increases.

  Since holes and electrons are concentrated in the InGaN well layer 26a and the InGaN well layer 26a is thin, the carrier density becomes excessively high, and it corresponds to the third power of the carrier density rather than the light emission recombination according to the second power of the carrier density. Non-luminous Auger recombination increases and high luminous efficiency cannot be obtained.

  On the other hand, as shown in FIG. 6A, in the semiconductor light emitting device 10 of the present embodiment, holes injected into the InGaN well layer 26a pass over the InGaN barrier layer 25b having a low barrier to the InGaN well layers 26b and 26c. And the carrier (hole) density of the InGaN well layer 26a is averaged.

  As a result, in the InGaN well layer 26a, Auger recombination, which is a non-light emitting process, decreases, and the ratio of light emission (spontaneous emission) recombination increases.

  In InGaN well layers 26b and 26c, the hole density was originally low and both Auger recombination and light emission (spontaneous emission) recombination were small. However, as the number of holes increased to some extent, light emission (spontaneous emission) recombination and light output increased. I think that.

  In the semiconductor light emitting devices of the first and second comparative examples, there is no particular tendency for holes to easily move from the InGaN well layer 26a to the InGaN well layers 26b and 26c. As a result, it can be seen that the semiconductor light emitting devices of the first and second comparative examples show substantially the same light output characteristics as the semiconductor light emitting device of the third comparative example.

  As described above, in order to increase the light output of the semiconductor light emitting device, it is important to make the band gap of the InGaN barrier layer 25b narrower than the remaining InGaN barrier layers 25c and 25d.

  Next, a method for manufacturing the semiconductor light emitting device 10 will be described with reference to FIGS. 7 to 9 are cross-sectional views sequentially showing the manufacturing process of the semiconductor light emitting device 10.

  As shown in FIG. 7A, an N-type GaN cladding layer 12, a semiconductor light emitting layer 15, a P-type GaN cladding layer 13, and a P-type GaN contact are formed on a C-plane sapphire substrate 41 by MOCVD (Metal Organic Chemical Vapor Deposition) method. The layer 14 is sequentially epitaxially grown to form the semiconductor stacked body 11.

A manufacturing process of the semiconductor stacked body 11 will be briefly described below. As a pretreatment, the sapphire substrate 41 is subjected to, for example, organic cleaning or acid cleaning, and then stored in a reaction chamber of the MOCVD apparatus. Next, for example, the temperature of the sapphire substrate 41 is raised to, for example, 1100 ° C. by high-frequency heating in an atmospheric pressure mixed gas atmosphere of nitrogen (N ₂ ) gas and hydrogen (H ₂ ) gas. Thereby, the surface of the sapphire substrate 41 is vapor-phase etched, and the natural oxide film formed on the surface is removed.

Next, a mixed gas of N ₂ gas and H ₂ gas is used as a carrier gas, and as a process gas, for example, ammonia (NH ₃ ) gas and trimethylgallium (TMG) are supplied, and as an N-type dopant, For example, silane (SiH ₄ ) gas is supplied to form the N-type GaN layer 12 having a thickness of 4 μm and a Si concentration of about 1E19 cm ⁻³ .

Next, the supply of the TMG gas and the SiH ₄ gas is stopped while the NH ₃ gas is continuously supplied, the temperature of the sapphire substrate 41 is lowered to a temperature lower than 1100 ° C., for example, 800 ° C., and held at 800 ° C.

Next, by continuously supplying (TMI: Tri-Methyl Indium) gas while continuously supplying NH ₃ gas and TMG gas as process gases, for example, N ₂ gas as a carrier gas, a thickness of 5 nm, In InGaN barrier layer 25e having a composition ratio of 0, thickness 5 nm, InGaN well layer 26d having an In composition ratio of 0.15, thickness 5 nm, InGaN barrier layer 25d having an In composition ratio of 0, thickness 5 nm, and In composition ratio A 0.15 InGaN well layer 26c is formed.

Next, by increasing or decreasing the supply of TMI gas while continuing to supply NH ₃ gas and TMG gas, an InGaN barrier layer 25c having a thickness of 5 nm and an In composition ratio of 0.03, a thickness of 5 nm and an In composition ratio of 0 .15 InGaN well layer 26b, InGaN barrier layer 25b having a thickness of 5 nm and In composition ratio of 0.05, and InGaN well layer 26a having a thickness of 5 nm and In composition ratio of 0.15 are formed.

  Finally, supply of only the TMI gas is stopped, and an InGaN barrier layer 25a having a thickness of 5 nm and an In composition ratio of 0 is formed. Thereby, the semiconductor light emitting layer 15 of MQW structure is obtained.

Next, a GaN cap layer (not shown) having a thickness of 5 nm is formed undoped while continuing to supply TMG gas and NH ₃ gas.

Next, the supply of TMG gas is stopped while continuing to supply NH ₃ gas, and the temperature of the sapphire substrate 41 is raised to a temperature higher than 800 ° C., for example, 1030 ° C., and held at 1030 ° C. in an N ₂ gas atmosphere. To do.

Next, a mixed gas of N ₂ gas and H ₂ gas is used as a carrier gas, NH ₃ gas as a process gas, TMG gas, and biscyclopentadienyl magnesium (Cp 2 Mg) as a P-type dopant are supplied. A P-type GaN cladding layer 13 having an Mg concentration of about 1E20 cm ⁻³ is formed.

Next, the supply of Cp2Mg gas is increased to form a P-type GaN contact layer 14 having a thickness of 10 nm and an Mg concentration of about 1E21 cm ⁻³ .

Next, the supply of the TMG gas is stopped while the NH ₃ gas is continuously supplied, and only the carrier gas is continuously supplied to naturally cool the sapphire substrate 41. The supply of NH ₃ gas is continued until the temperature of the sapphire substrate 41 reaches 500 ° C. Thereby, the semiconductor stacked body 11 is formed on the sapphire substrate 41, and the P-type GaN contact layer 14 becomes the surface.

  Next, as shown in FIG. 7B, a silver film having a thickness of about 0.5 μm and a gold film having a thickness of 1 μm are stacked on the P-type GaN contact layer 14 by, for example, sputtering, and the metal electrode 18 is formed. Form.

  Next, as shown in FIG. 7C, a silicon substrate 42 is prepared, and gold films 43 and 44 having a thickness of 1 μm are formed on both surfaces of the silicon substrate 42 by, eg, sputtering. A gold-tin alloy film 45 having a thickness of 2 μm is formed on the gold film 43 by, for example, a vacuum deposition method. The silicon substrate 42 is the support substrate 20, and the gold film 44 is the substrate electrode 21.

  Next, as shown in FIG. 8A, the sapphire substrate 41 is turned upside down so that the metal electrode 18 and the gold-tin alloy film 45 face each other, and the sapphire substrate 41 and the silicon substrate 42 are overlaid, and then the sapphire substrate. 41 and the silicon substrate 42 are heated by a heater 46 and pressurized.

  The gold-tin alloy film 45 is melted, and the gold film of the metal electrode 18 and the bonding layer 19 fused with the gold film 43 are formed. The sapphire substrate 41 and the silicon substrate 42 are bonded via the bonding layer 19.

  Next, as shown in FIG. 8B, the sapphire substrate 41 and the semiconductor stacked body 11 are separated by a laser lift-off method. The laser lift-off method is a method in which the inside of a substance is partially thermally decomposed by irradiating with a high-power laser beam, and the decomposed portion is separated as a boundary.

  Specifically, the laser beam 47 that passes through the sapphire substrate 41 and is absorbed by the N-type GaN cladding layer 12 is irradiated, the N-type GaN cladding layer 12 is dissociated, and the sapphire substrate 41 and the N-type GaN cladding layer 12 are separated. To separate.

  For example, the fourth harmonic (266 nm) of an Nd-YAG laser is irradiated from the sapphire substrate 41 side. Since sapphire is transparent with respect to the laser beam 47, the irradiated laser beam 47 passes through the sapphire substrate 41 and is effectively absorbed by the N-type GaN cladding layer 12.

Since there are many crystal defects in the N-type GaN cladding layer 12 in the vicinity of the interface with the sapphire substrate 41, almost all of the absorbed light is converted into heat, and a reaction of 2GaN = 2Ga + N ₂ (g) ↑ occurs. As a result, GaN dissociates into Ga and N ₂ gas.

  The laser light 47 may be continuous light (CW) or pulsed light (PW), but is preferably pulsed light with a high peak output. As the pulse laser that generates the laser beam 47 having a high peak output, a Q-switched laser, a mode-locked laser, or the like that can output an ultrashort pulsed light of picosecond to femtosecond order is suitable.

  After the dissociation, the Ga layer 48 is left on the exposed N-type GaN cladding layer 12. The Ga layer 48 is a Ga drop and is removed with warm water or an aqueous solution containing hydrochloric acid.

  Next, as shown in FIG. 9, an uneven portion 12 a is formed in the exposed N-type GaN cladding layer 12. Specifically, for example, the N-type GaN clad layer 12 is wet-etched with an aqueous KOH solution. For example, a KOH aqueous solution having a concentration of about 20% to 40% and a temperature of about 60 ° C. to 70 ° C. is appropriate. Since the N-polar GaN surface is anisotropically etched with a KOH aqueous solution, the concavo-convex portion 12 a is formed in the N-type GaN cladding layer 12.

  Next, a gold film is formed on the N-type GaN clad layer 12 on which the concavo-convex portion 12a is formed by, for example, a sputtering method, and the gold film is patterned by a photolithography method to form a pad electrode 17a and a fine wire electrode 17b. . Thereby, the semiconductor light emitting device 10 shown in FIG. 1 is obtained.

  The In composition x2 of the InGaN barrier layer 25 and the In composition x1 of the InGaN well layer 26 can be obtained by an X-ray diffraction method or the like.

  The lattice constant of the InGaN barrier layer 25 is obtained by the X-ray diffraction method, and the In composition x2 is obtained from the lattice constant. The relationship between the In composition of InGaN and the lattice constant follows the Bekaard rule. The lattice constant of GaN is about 0.319 nm for the a axis and about 0.518 nm for the c axis. The lattice constant of InGaN is about 0.355 nm for the a axis and about 0.576 nm for the c axis.

  As described above, in the semiconductor light emitting device 10 of this embodiment, the semiconductor light emitting layer 15 has a multiple quantum well structure in which the InGaN well layers 26 and the InGaN barrier layers 25 are alternately stacked. Among the sandwiched InGaN barrier layers 25, the band gap of the InGaN barrier layer 25b closest to the P-type GaN cladding layer 13 is set to be narrower than the band gaps of the remaining InGaN barrier layers 26c and 26d.

  A thin wire electrode 17 b and a metal electrode 18 are provided so that a current flows in a direction substantially perpendicular to the main surface of the semiconductor light emitting layer 15.

  As a result, the holes injected into the InGaN well layer 26a are also injected into the InGaN well layers 26b and 26c beyond the low barrier InGaN barrier layer 25b, and the carrier (hole) density of the InGaN well layer 26 is averaged. .

  Even when driven with a large current, the carrier density in the InGaN well layer 26a is properly maintained, so Auger recombination can be suppressed and carrier overflow can be prevented. Therefore, a semiconductor light emitting device having a high light output can be obtained.

  The semiconductor light emitting device 10 can be provided with a transparent conductive film in order to ensure current spreading. FIG. 10 is a cross-sectional view showing a semiconductor light emitting device in which a transparent conductive film is provided on the N-type GaN cladding layer 12.

  As shown in FIG. 10, in the semiconductor light emitting device 50, a transparent conductive film 51 that is transparent to the light emitted from the semiconductor light emitting layer 15 is provided on substantially the entire surface of the N-type GaN cladding layer 12 having the concavo-convex portion 12 a. Is provided. The transparent conductive film 51 is an ITO (Indium Tin Oxide) film having a thickness of 100 to 200 nm, for example.

  The pad electrode 17a and the fine wire electrode 17b are provided on the transparent conductive film 51. If it is attempted to spread the current to the periphery of the semiconductor stacked body 11 with only the fine wire electrode 17b, the area of the fine wire electrode 17b becomes considerably large. The light shielding by the thin wire electrode 17b cannot be ignored, resulting in a problem that the light output decreases.

  Therefore, by using the thin wire electrode 17b as a trunk and the transparent conductive film 51 as branches and leaves, it is possible to reliably spread the current to the periphery of the semiconductor stacked body 11, and to significantly reduce light shielding by the thin wire electrode 17b.

  Since the sheet resistance of the transparent conductive film 51 is much higher than the sheet resistance of the thin wire electrode 17b, the current first spreads along the thin wire electrode 17b and then spreads from the thin wire electrode 17b along the transparent conductive film 51.

  In order to spread the current, the ITO film should be thicker. On the other hand, the ITO film absorbs light although it is slight, so that it is preferable to be thin in order to extract more light. Hereinafter, the transparent conductive film is also referred to as an ITO film.

  The ITO film is formed by sputtering, for example. In order to promote the crystallization of the ITO film and increase the conductivity, the ITO film is subjected to a heat treatment. For the heat treatment, for example, in a nitrogen atmosphere or a mixed atmosphere of nitrogen and oxygen, a temperature of about 400 to 750 ° C. and a time of about 1 to 20 minutes are appropriate.

  The N-type GaN clad layer 12 can be grown thick, but has a resistivity higher than that of a transparent conductive film such as an ITO film, so that the sheet resistance is about one digit higher than that of the ITO film. The current spreads almost through the transparent conductive film 51, but a part spreads through the N-type GaN cladding layer 12.

  The semiconductor light emitting device 10 can further be provided with an overflow prevention layer for preventing carrier overflow. A superlattice buffer layer for improving the crystallinity of the semiconductor stacked body 15 can be provided. FIG. 11 is a cross-sectional view showing a semiconductor light emitting device having an overflow prevention layer and a superlattice buffer layer.

  As shown in FIG. 11, in the semiconductor stacked body 61 of the semiconductor light emitting device 60, a P-type AlGaN overflow prevention layer 62 is provided between the semiconductor light-emitting layer 15 and the P-type GaN cladding layer 13.

The P-type AlGaN overflow prevention layer 62 has, for example, a thickness of 5 nm, an Mg concentration of 1E20 cm ⁻³ , and an Al composition ratio of 0.2. The band gap of the P-type AlGaN overflow prevention layer 62 is larger than the band gap of the P-type GaN cladding layer 13.

  A superlattice buffer layer 63 is provided between the semiconductor light emitting layer 15 and the N-type GaN cladding layer 12. In the superlattice buffer layer 63, for example, 30 pairs of first and second InGaN layers having different In compositions are alternately stacked.

  The first InGaN layer has a thickness of 1 nm, for example, and the second InGaN layer has a thickness of 3 nm, for example. The In composition of the first InGaN layer is larger than the In composition of the second InGaN layer.

  The P-type AlGaN overflow prevention layer 62 effectively suppresses the overflow of carriers in the InGaN well layer 26 to the P-type GaN cladding layer 13. The superlattice buffer layer 63 suppresses the propagation of crystal defects such as dislocations from the N-type GaN cladding layer 12 to the semiconductor light emitting layer 15. As a result, there is an advantage that the light output of the semiconductor light emitting device 60 can be further increased.

  Although the case where the support substrate 20 is a silicon substrate has been described here, other conductive substrates can be used. Examples of the conductive substrate include a metal substrate, a conductive ceramic substrate, and a germanium (Ge) substrate. The conductive ceramic substrate is, for example, a SiC ceramic substrate.

  Moreover, although the case where the board | substrate which makes the semiconductor laminated body 11 grow is the C surface sapphire board | substrate 41, the electroconductive board | substrate can be used. Examples of the conductive substrate include a GaN substrate, a SiC substrate, and a ZnO substrate whose main surface is a C plane.

  FIG. 12 is a cross-sectional view showing a semiconductor light emitting element having a semiconductor stacked body provided on a conductive substrate. As shown in FIG. 12, in the semiconductor light emitting device 70, the semiconductor stacked body 11 is provided on a growth conductive substrate 71 whose main surface is a C-plane, for example, a C-plane GaN substrate.

  An N-type GaN clad layer 12, a semiconductor light emitting layer 15, a P-type GaN clad layer 13, and a P-type GaN contact layer 14 are sequentially provided on the conductive substrate 71. The transparent conductive film 51 is provided on the P-type GaN contact layer 14.

  A substrate electrode 72 is provided on the surface of the conductive substrate 71 opposite to the N-type GaN cladding layer 12 side. The substrate electrode 72 is, for example, a Ti / Pt / Au film capable of ohmic contact with N-type GaN.

  The conductive substrate 71 can serve as both a growth substrate and a support substrate. There is an advantage that the steps of bonding the support substrate and removing the growth substrate are unnecessary.

  Note that the P-type nitride semiconductor has a higher resistivity than a transparent conductive film such as an ITO film and has a high sheet resistance because it is difficult to grow thick. The current spreads almost through the transparent conductive film 51. The spread of current through the P-type GaN layers such as the P-type GaN cladding layer 13 and the P-type GaN contact layer 14 can be ignored.

  A current blocking layer corresponding to the pad electrode 17a and the thin wire electrode 17b may be formed between the P-type GaN contact layer 14 and the transparent conductive film 51.

  Furthermore, the transparent conductive film 51 may have an uneven portion for improving the light extraction efficiency. FIG. 13 is a cross-sectional view showing a main part of a semiconductor light emitting device provided with a transparent conductive film having an uneven portion.

  As shown in FIG. 13, the transparent conductive film 80 has a concavo-convex portion 81 including a convex portion 81a mainly made of crystalline ITO and a concave portion 81b mainly made of amorphous ITO.

  In general, it is known that when an ITO film is formed by sputtering or the like, an ITO film in which amorphous ITO and crystalline ITO are mixed can be obtained depending on the substrate temperature, plasma density, oxygen partial pressure, and the like at the time of film formation. .

  For example, in terms of the substrate temperature, the crystallization temperature of ITO is in the vicinity of 150 ° C. to 200 ° C. When the substrate temperature is near the crystallization temperature, an ITO film in which amorphous ITO and crystalline ITO are mixed is obtained.

  It has been confirmed from cross-sectional TEM observation and electron diffraction patterns that crystalline ITO is dispersed and mixed in a pillar shape so as to be surrounded by amorphous ITO in the ITO film.

  The etching rate of crystalline ITO is slower than the etching rate of amorphous ITO. The etching rate of crystalline ITO is, for example, about 50 to 100 nm / min. The etching rate of amorphous ITO is, for example, about 100 to 500 nm / min. Therefore, the selective ratio between crystalline ITO and amorphous ITO is expected to be about 2 to 5.

  A transparent conductive film having a concavo-convex portion 81 by selectively removing amorphous ITO having a high etching rate by using the difference in etching rate between crystalline ITO and amorphous ITO, and leaving the crystalline ITO having a low etching rate. 80 is obtained.

  Note that the transparent conductive film 80 is preferably formed thick in advance in anticipation of etching loss.

  Although the case where the In composition x of the InGaN barrier layers 25b, 25c, and 25d is 0.05, 0.03, and 0 has been described, respectively, the In composition x is not particularly limited as long as the In composition x decreases in this order.

  For example, the In composition x of the InGaN barrier layers 25b, 25c, and 25d may be 0.05, 0.02, 0.01, or 0.06, 0.02, and 0. It can be determined appropriately so as to obtain the desired light output.

  Although the case where the number of InGaN well layers 26 is four has been described, the number of InGaN well layers 26 is not particularly limited.

(Embodiment 2)
The semiconductor light emitting device according to this embodiment will be described with reference to FIGS. FIG. 14 is a cross-sectional view showing the main part of the semiconductor light emitting device of this embodiment. FIG. 15 is a diagram showing the composition distribution of the main part. In the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, description thereof will be omitted, and different portions will be described. The present embodiment is different from the first embodiment in that the semiconductor light emitting layer is an AlGaN layer.

That is, as shown in FIG. 14, in the semiconductor stacked body 91 of the semiconductor light emitting device 90 of this embodiment, the N-type Al _y3 Ga _(1-y3) N clad is in contact with the N-type GaN layer 12 that is the underlying single crystal layer. A layer 92 (hereinafter simply referred to as an N-type AlGaN cladding layer) is provided. A P-type Al _y3 Ga _(1-y3) N cladding layer 93 (hereinafter simply referred to as a P-type AlGaN cladding layer) is provided in contact with the P-type GaN contact layer 14.

The semiconductor light emitting layer 94 is provided between the N-type AlGaN clad layer 92 and the P-type AlGaN clad layer 93, and Al _y2 Ga _(1-y2) N barrier layers 95a, 95b, 95c, 95d, and 95e (hereinafter simply referred to as AlGaN). This is a quantum well structure in which Al _y1 Ga _(1-y1) N well layers 96a, 96b, 96c, and 96d (hereinafter simply referred to as AlGaN well layers) are alternately stacked.

  The semiconductor light emitting layer 94 starts with an AlGaN barrier layer 95 a in contact with the P-type AlGaN cladding layer 93 and ends with an AlGaN barrier layer 95 e in contact with the N-type AlGaN cladding layer 92.

  The AlGaN barrier layers 95a, 95b, 95c, 95d, and 95e are collectively referred to as an AlGaN barrier layer 95, and the AlGaN well layers 96a, 96b, 96c, and 96d are collectively referred to as an AlGaN well layer 96.

  The thickness of the AlGaN barrier layer 95 is, for example, 5 nm. The thickness of the AlGaN well layer 96 is, for example, 5 nm. The number of AlGaN well layers 96 is four, for example.

  The Al composition y1 of the AlGaN well layer 96 is set to, for example, about 0.06 so that light with a wavelength of 360 to 380 nm is emitted from the semiconductor light emitting device 90.

  The Al composition y1 of the AlGaN well layer 96 and the Al composition y2 of the AlGaN barrier layer 95 have a relationship of 0 <y1 <y2 ≦ 1. The band gap of the AlGaN barrier layer 95 is set to be wider than the band gap of the AlGaN well layer 96.

  Further, of the AlGaN barrier layers 95b, 95c, and 95d sandwiched between the AlGaN well layers 96, the band gap of the AlGaN barrier layer 95b closest to the P-type AlGaN cladding layer 93 is the band gap of the remaining AlGaN barrier layers 95c and 95d. It is set to be narrower.

  Except for the AlGaN barrier layer 95b, the band gap of the AlGaN barrier layer 95 on the N-type AlGaN cladding layer 92 side is equal to or wider than the band gap of the AlGaN barrier layer 95 on the P-type AlGaN cladding layer 93 side. Is set.

That is, when the band gap of the AlGaN barrier layer 95 is expressed as Eg (95), the following relationship is established.
Eg (95b) <Eg (95c) ≦ Eg (95d) ≦ Eg (95a) = Eg (95e)
The band gap Eg of the Al _y Ga _(1-y) N layer varies from the band gap of GaN (about 3.45 eV) to the band gap of AlN (about 6.2 eV) depending on the Al composition y. However, it is not straight and is bent downward by band gap bowing.

  FIG. 15 is a view showing the Al composition distribution of the semiconductor light emitting layer 94. Here, the Al composition y3 of the N-type AlGaN cladding layer 92 and the P-type AlGaN cladding layer 93 was set to 0.2. The Al composition y2 of the AlGaN well layer 95a in contact with the P-type AlGaN cladding layer 93 and the AlGaN well layer 95e in contact with the N-type AlGaN cladding layer 92 was 0.2.

As shown in FIG. 15, in the semiconductor light emitting device 90 of the present embodiment, the Al compositions y1 of the AlGaN barrier layers 95b, 95c, and 95d are 0.09, 0.12, and 0.15, respectively. That is, the band gaps of the AlGaN barrier layers 95b, 95c, and 95d increase in order from the P-type AlGaN clad layer 93 side to the N-type AlGaN clad layer 92, and have the following relationship.
Eg (95b) <Eg (95c) <Eg (95d) = Eg (95a) = Eg (95e)
When a voltage is applied between the pad electrode 17a and the substrate electrode 21, a current flows through the semiconductor light emitting layer 15 in a direction substantially perpendicular to the main surface 15a. The carriers injected into the InGaN well layer 96 recombine with light and, for example, near ultraviolet light having a peak wavelength of about 360 to 380 nm is emitted.

  In the semiconductor light emitting device 90 described above, the band gap of the AlGaN barrier layer 95b is set narrower than the band gaps of the remaining AlGaN barrier layers 95a, 95c, 95d, and 95e, and when a large current is passed, the AlGaN well layer 96a. It is configured so that the carrier density in the inside does not become excessive.

  The operation, manufacturing method, and the like of the semiconductor light emitting device 90 are the same as those of the semiconductor light emitting device 10 shown in FIG.

  As described above, in the semiconductor light emitting device 90 of the present embodiment, the carrier density in the AlGaN well layer 96a is properly maintained even when driven with a large current, so that Auger recombination is suppressed and carrier overflow occurs. Can be prevented. Therefore, a semiconductor light emitting device having a high light output in the near ultraviolet (wavelength 380-200 nm) region can be obtained.

  In the semiconductor light emitting device 90, a transparent conductive film 51 can be provided as shown in FIG. 10, and a P-type AlGaN overflow prevention layer 162 and a superlattice buffer layer 163 can be provided as shown in FIG. As shown in FIG. 12, the semiconductor stacked body 91 can be provided on a conductive substrate.

  The Al composition y of the AlGaN barrier layers 95b, 95c, and 95d is not particularly limited as long as it increases in this order. There is no particular limitation on the number of AlGaN well layers 96.

(Embodiment 3)
The semiconductor light emitting device according to this embodiment will be described with reference to FIG. FIG. 16 is a view showing the semiconductor light emitting device of this embodiment, FIG. 16 (a) is a plan view with its upper portion removed, and FIG. 16 (b) is along the line CC in FIG. 16 (a). It is sectional drawing which cut | disconnected and looked in the arrow direction.

  In the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, description thereof will be omitted, and different portions will be described. This embodiment is different from the first embodiment in that the current flowing in the semiconductor light emitting layer is extracted from the P-type semiconductor layer side.

  As shown in FIG. 16, in the semiconductor light emitting device 210 of the present embodiment, the P-side electrode 211 is provided on the P-type GaN contact layer 14 as in the semiconductor light emitting device 10 shown in FIG. 1.

  The difference is that the N-side electrode 212 has a plurality of portions a that are equidistant from the P-side electrode 211 in the direction perpendicular to the major surface 15a from the major surface 15a of the semiconductor light emitting layer 15, and the P-side electrode in the portion a 211 is arranged so as to surround the N-side electrode 212. The portion a can also be said to be a portion where the N-side electrode 212 intersects the plane including the P-side electrode 211.

  That is, the N-side electrode 212 has a plurality of columnar first N-side electrodes 212 a that contact the N-type GaN cladding layer 12 through the semiconductor light emitting layer 15 from the P-side electrode 211. The first N-side electrode 212a is disposed, for example, at each vertex and center point of the hexagon b shown by a one-dot chain line (honeycomb structure). The first N-side electrode 212a is, for example, a circle having a diameter of 2 to 20 μm. The distance between adjacent first N-side electrodes 212a is, for example, 10 to 100 μm.

  The first N-side electrode 212a protrudes from the interface between the semiconductor light emitting layer 15 and the N-type GaN cladding layer 12 into the N-type GaN cladding layer 12 by a height H1. The side surface of the first N-side electrode 212 a is covered with an insulating film 213 and is electrically separated from the P-side electrode 211 to the semiconductor light emitting layer 15.

  Further, the N-side electrode 212 includes a second N-side electrode 212b that is provided on the P-side electrode 211 via an insulating film 213 and has a plurality of first N-side electrodes 212a connected in common. The insulating film 213 is a silicon oxide film having a thickness of 100 to 300 nm formed by, for example, a CVD (Chemical Vapor Deposition) method.

  The first N-side electrode 212a is provided to draw the current flowing through the semiconductor light emitting layer 15 to the P-type semiconductor layer side. The second N-side electrode 212b is provided to collect the current drawn by each first N-side electrode 212a.

  In the semiconductor stacked body 11, the N-side electrode 212 side is provided on the conductive support substrate 20 with the conductive bonding layer 19 interposed therebetween. The second N-side electrode 212 b is in contact with the bonding layer 19. The semiconductor stacked body 11 is provided with a notch portion 11 a penetrating the semiconductor stacked body 11. A part of the P-side electrode 211 is exposed to the notch 11a and becomes the P-side electrode pad 211a.

  In the semiconductor light emitting device 210 of the present embodiment, holes injected from the P-side electrode 211 are made uniform by the semiconductor light-emitting layer 15 so that the hole density of the InGaN well layer 26 is uniform, and electrons injected from the N-side electrode 212 are planar. Are uniformly distributed.

  When the P-side electrode pad 211a is connected to the positive terminal of the power source and the substrate electrode 21 is connected to the negative terminal of the power source, current flows so as to concentrate from the P-side electrode 211 to the first N-side electrode 212a as shown by the arrow c. . A hexagon d indicated by a broken line is a virtual line indicating a region where current is collected from the P-side electrode 211 to the first N-side electrode 212a. Thereby, the current distribution in the plane of the semiconductor light emitting element 210 is made uniform.

  While the distance between adjacent first N-side electrodes 212a is 10 to 100 μm, the thickness from the P-type GaN contact layer 14 to the semiconductor light emitting layer 15 is 145 nm at most. The ratio of the distance in the direction parallel to the main surface 15a of the semiconductor light emitting layer 15 and the distance in the direction perpendicular to the main surface 15a of the semiconductor light emitting layer 15 is one digit to two digits or more.

  Therefore, the current mainly flows in the direction parallel to the main surface 15 a of the semiconductor light emitting layer 15, and the current flowing in the direction perpendicular to the main surface of the semiconductor light emitting layer 15 tends to follow.

  Therefore, in order to increase the current in the direction perpendicular to the main surface 15a of the semiconductor light emitting layer 15, the height H1 at which the first N-side electrode 212a protrudes into the N-type GaN cladding layer 12 needs to be as large as possible. When the thickness of the N-type GaN cladding layer 12 is 4 μm, the height H1 is desirably 2 μm or more, for example.

  Thereby, the ratio of the distance in the direction parallel to the main surface 15a of the semiconductor light emitting layer 15 and the distance in the direction perpendicular to the main surface 15a of the semiconductor light emitting layer 15 is reduced to an order of magnitude. The current in the direction perpendicular to the major surface 15a of the semiconductor light emitting layer 15 can be increased.

  Next, the result of simulating the light output of the semiconductor light emitting element 210 will be described with reference to FIG. In FIG. 17, the simulation conditions and the first to third comparative examples are the same as the simulation conditions and the first to third comparative examples shown in FIG.

  As shown in FIG. 17, in the semiconductor light emitting device 210 of this embodiment, a higher light output is obtained than the semiconductor light emitting devices of the first to third comparative examples. From this, it was confirmed that a current in a direction perpendicular to the main surface 15a of the semiconductor light emitting layer 15 was sufficiently secured.

  Next, a method for manufacturing the semiconductor light emitting device 210 will be described with reference to FIGS. 18 and 19 are cross-sectional views sequentially showing the main part of the manufacturing process of the semiconductor light emitting device 210.

  First, the semiconductor stacked body 11 is formed on the sapphire substrate 41 by MOCVD in the same manner as in FIGS. 7A and 7B. A P-side electrode 211 is formed on the P-type GaN contact layer 14 of the semiconductor stacked body 11.

  Next, as shown in FIG. 18A, a resist film 221 having an opening 221a corresponding to the first N-side electrode 212a is formed on the P-type GaN contact layer 14 by photolithography. Using the resist film 221 as a mask, the P-side electrode 211 is removed by wet etching using, for example, an iodine-based etchant, and the P-type GaN contact layer 14 is exposed.

  The semiconductor stacked body 11 is anisotropically etched by RIE (Reactive Ion Etching) using chlorine-based gas. The anisotropic etching is performed until the N-type GaN cladding layer 12 is dug down to a depth H1. Thereby, the via hole 222 is obtained.

  Next, after removing the resist film 221, as shown in FIG. 18B, a silicon oxide film 223 that conformally covers the P-type GaN contact layer 14 and the side and bottom surfaces of the via hole 222 is formed by CVD.

  Next, as shown in FIG. 18C, only the silicon oxide film 223 on the bottom surface of the via hole 222 is removed. As a result, an insulating film 213 that covers the side surface and the bottom surface of the via hole 222 on the P-type GaN contact layer 14 is obtained. The removal of the silicon oxide film 223 on the bottom surface of the via hole 222 is performed as follows, for example.

  A positive resist film is formed on the silicon oxide film 223. Only the resist film on the bottom surface of the via hole 222 is exposed and developed by photolithography to expose the silicon oxide film 223 on the bottom surface of the via hole 222. The exposed silicon oxide film 223 is wet-etched with an aqueous solution containing hydrofluoric acid, for example. The resist film is removed.

  Next, as shown in FIG. 19A, a Ti / Pt / Au laminated film is formed on the insulating film 213 by, eg, sputtering. As a result, the N-side electrode 212 having the first N-side electrode 212 a embedded in the via hole 222 and the second N-side electrode 212 b formed on the P-type GaN contact layer 14 is obtained via the insulating film 213.

  Next, in the same manner as in FIGS. 7C to 9, the sapphire substrate 41 and the silicon substrate 42 are bonded together, the sapphire substrate 41 is removed, and the uneven portion 12 a is formed in the exposed N-type GaN cladding layer 12.

  Next, as shown in FIG. 19B, a resist film 224 having an opening 224a corresponding to the notch 11a is formed on the N-type GaN cladding layer 12, and the semiconductor multilayer body 11 is anisotropically formed by RIE. Etching is performed to expose a part of the P-side electrode 211. The exposed P-side electrode 211 is a P-side electrode pad 211a. The resist film 224 is removed. Thereby, the semiconductor light emitting device 210 shown in FIG. 16 is obtained.

  As described above, in the semiconductor light emitting device 210 of this embodiment, the N-side electrode 212 is provided on the P-type semiconductor layer side. Since there is no electrode on the N-type GaN cladding layer 12 that is the light extraction surface, the light extracted from the surface of the N-type GaN cladding layer 12 is not blocked by the electrode. Therefore, there is an advantage that the light output of the semiconductor light emitting device 210 can be increased.

  Similar to the semiconductor light emitting device 60 shown in FIG. 11, a P-type AlGaN layer overflow prevention layer 62 may be provided between the semiconductor light-emitting layer 15 and the P-type GaN cladding layer 13. A superlattice buffer layer 63 may be provided between the N-type GaN cladding layer 12 and the semiconductor light emitting layer 15.

  Although the case where the N-side electrode 212 includes the second N-side electrode 212b has been described, there is no particular problem even if the second N-side electrode 212b is not provided. It is only necessary that the first N-side electrode 212a is in contact with the bonding layer 19 reliably.

  Although the case where the P-side electrode is disposed so as to surround the N-side electrode in the portion a has been described, the N-side electrode may be disposed so as to surround the P-side electrode.

  20A and 20B are diagrams showing a semiconductor light emitting device in which the N-side electrode is disposed so as to surround the P-side electrode. FIG. 20A is a plan view with the upper portion removed, and FIG. It is sectional drawing cut | disconnected along the DD line of 20 (a) and looked at the arrow direction.

  As shown in FIG. 20, in the semiconductor light emitting device 230, the P-side electrode 231 is provided on the P-type GaN contact layer 14. The N-side electrode 232 has a plurality of portions a that are equidistant from the main surface 15a of the semiconductor light emitting layer 15 in the direction perpendicular to the main surface 15a, and the N-side electrode 232 is P-side in the portion a. It arrange | positions so that the electrode 231 may be enclosed.

  That is, the N-side electrode 232 is a hexagonal lattice-shaped (honeycomb structure) thin wire electrode that penetrates the semiconductor light emitting layer 15 from the P-side electrode 231 and contacts the N-type GaN cladding layer 12. The N-side electrode 232 is a thin line having a width of 2 to 20 μm, for example. The length of one side of the hexagon is, for example, 6 to 60 μm.

  The N-side electrode 232 protrudes from the interface between the semiconductor light emitting layer 15 and the N-type GaN cladding layer 12 into the N-type GaN cladding layer 12 by a height H1. The N-side electrode 232 has a side surface and an end surface on the P-side electrode 231 side covered with an insulating film 233 and is electrically separated from the P-side electrode 231 to the semiconductor light emitting layer 15.

  The P-side electrode 231 is divided by a hexagonal lattice-shaped N-side electrode 232 and is surrounded by the N-side electrode 232.

  Further, the semiconductor stacked body 11 has a notch portion 11 b in which a part of the semiconductor light emitting layer 15 is removed from the P-type GaN contact layer 14 and the N-type GaN cladding layer 12 is exposed. A columnar N-side electrode bump 234 is provided on the N-type GaN cladding layer 12 exposed at the notch 11b. The N-side electrode bump 234 is in contact with the adjacent N-side electrode 232.

  In the semiconductor stacked body 11, the P-side electrode 231 side is provided on the conductive support substrate 20 with the bonding layer 19 interposed therebetween. Each hexagonal P-side electrode 231 is in contact with the bonding layer 19 and electrically connected to the bonding layer 19 in common.

  The support substrate 20 is provided with a recess (not shown) adjacent to the semiconductor stacked body 11, and an insulating film 235 is embedded in the recess by, for example, a CVD method. An N-side electrode pad 236 is provided on the insulating film 235. The N-side electrode pad 235 is in contact with the N-side electrode bump 234.

  When the substrate electrode 21 is connected to the positive terminal of the power supply and the N-side electrode pad 236 is connected to the negative terminal of the power supply, current flows from the P-side electrode 231 through the semiconductor light emitting layer 15 as shown by the arrow b. Flows into the N-side electrode 232 surrounding the.

  The current flowing into the N-side electrode 232 surrounding the P-side electrode 231 is collected and taken out from the N-side electrode 232 through the N-side electrode bump 234 and the N-side electrode pad 236 as indicated by an arrow c. Therefore, the current distribution in the plane of the semiconductor light emitting device 230 is made uniform.

  Next, a method for manufacturing the semiconductor light emitting device 230 will be described. 21 and 22 are cross-sectional views showing the main parts of the manufacturing process of the semiconductor light emitting device 230.

  First, the semiconductor stacked body 11 is formed on the sapphire substrate 41 in the same manner as in FIGS. 7A and 7B. A P-side electrode 231 is formed on the P-type GaN contact layer 14 of the semiconductor stacked body 11.

  Next, as shown in FIG. 21A, a resist having an opening 241a corresponding to the hexagonal latticed N-side electrode 232 and an opening 241b corresponding to the notch 11b on the P-side electrode 231 by photolithography. A film 241 is formed.

  Using the resist film 241 as a mask, the P-side electrode 231 is wet-etched using an iodine-based etchant to expose the P-type GaN contact layer 14. At this stage, the P-side electrode 231 is divided into hexagonal shapes.

  The semiconductor stacked body 11 is anisotropically etched by the RIE method using a chlorine-based gas. The anisotropic etching is performed until the N-type GaN cladding layer 12 is dug down to a depth H1. As a result, hexagonal lattice-like trenches 242 and notches 11b are obtained.

  Next, after removing the resist film 241, as shown in FIG. 21B, a silicon oxide film is conformally formed on the P-side electrode 231 and on the side and bottom surfaces of the trench 242 by the CVD method. At this time, a silicon oxide film is also formed on the side surface and the bottom surface of the notch 11b.

  Next, the silicon oxide film is anisotropically etched by the RIE method using a fluorine-based gas. On the P-side electrode 231, the silicon oxide film on the bottom surface of the trench 242 and the bottom surface of the notch portion 11b is removed, and the silicon oxide film on the side surface of the trench 242 and the side surface of the notch portion 11b is left. Thereby, an insulating film 233 is formed on the side surface of the trench 242.

  Next, as shown in FIG. 21C, the N-side electrode 232 is embedded in the trench 242, and the end face of the N-side electrode 232 is covered with an insulating film. This insulating film becomes a part of the insulating film 233. At the same time, the N-side electrode bump 234 is formed.

  Next, as shown in FIG. 22A, a recess corresponding to the notch 11b is formed in the silicon substrate 42, and a silicon oxide film is formed on the silicon substrate 20 by, for example, a CVD method. The silicon oxide film is removed by, for example, the CMP method until is exposed. As a result, an insulating film 235 embedded in the silicon substrate 42 is obtained.

  Next, the bonding layer 19 is formed on the silicon substrate 42, and the N-side electrode pad 236 is formed on the insulating film 234. The N-side electrode pad 236 is preferably the same as the bonding layer 19.

  Next, as shown in FIG. 22B, the sapphire substrate 41 is turned upside down, facing the silicon substrate 42, the P-side electrode 231 and the bonding layer 19 are overlaid, and the N-side electrode bump 234 and the N-side electrode pad are overlapped. 236 are overlapped and pressed to connect to the N-side electrode 232.

  Next, similarly to FIGS. 8 and 9, the sapphire substrate 41 and the silicon substrate 42 are bonded, the sapphire substrate 41 is removed, and the concavo-convex portion 12 a is formed in the exposed N-type GaN clad layer 12. Thereby, the semiconductor light emitting device 230 shown in FIG. 20 is obtained.

  As described above, in the semiconductor light emitting device 230 of this embodiment, the hexagonal lattice-shaped N-side electrode 232 is disposed so as to surround the P-side electrode 231 in the portion a.

  Also in this structure, since the N-side electrode 232 surrounds the P-side electrode 231, the distance from the center of the P-side electrode 231 to the N-side electrode 232 is uniform. Therefore, the same effect as the semiconductor light emitting device 210 shown in FIG. 16 can be obtained.

  Further, in this structure, since the periphery of the semiconductor light emitting layer 15 is also surrounded by the N-side electrode 232, light can be easily extracted from the upper side of the N clad layer 12. When the trench 242 is formed, an angle is provided on the side surface to form an inclined surface, whereby the light can be further directed upward.

  That is, as shown in FIG. 23A, in the hexagonal N-side electrode 232, by tilting at least one of the two opposite sides of the hexagon, light incident perpendicular to the side can be directed upward. it can. On the other hand, as shown in FIG. 23 (b), when the two side surfaces of the hexagon facing each other are parallel, the light incident perpendicularly to the side surfaces cannot be directed upward.

  Although some embodiments have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

Note that the configurations described in the following supplementary notes are conceivable.
(Supplementary note 1) The semiconductor light emitting element according to claim 1 or 4, wherein the N type semiconductor layer includes an N type GaN cladding layer, and the P type semiconductor layer includes a P type GaN cladding layer and a P type GaN contact layer. .

(Supplementary note 2) The semiconductor light-emitting element according to supplementary note 1, wherein the N-type semiconductor layer includes a superlattice buffer layer provided between the N-type GaN cladding layer and the semiconductor light-emitting layer.

(Supplementary note 3) The semiconductor light-emitting element according to supplementary note 1, wherein the P-type semiconductor layer includes a P-type AlGaN overflow prevention layer provided between the P-type GaN cladding layer and the semiconductor light-emitting layer.

(Supplementary Note 4) The transparent conductive film is an ITO film, a semiconductor light-emitting device according to claim 3 is a ZnO film or Sn ₂ O film.

(Additional remark 5) The said semiconductor light emitting layer is a semiconductor light-emitting device of Claim 1 or Claim 4 provided on the electroconductive support substrate on both sides of the said P side electrode.

(Appendix 6) a conductive support substrate;
The barrier layer having a multiple quantum well structure in which an N-type semiconductor layer, well layers and barrier layers are alternately stacked, and is closest to the P-type semiconductor layer among the barrier layers sandwiched between the well layers A semiconductor stacked body in which a semiconductor light emitting layer whose band gap is narrower than a band gap of the remaining barrier layer, and a P-type semiconductor layer are sequentially stacked;
A fine wire electrode provided on the N-type semiconductor layer of the semiconductor laminate;
A metal electrode provided between the conductive substrate and the P-type semiconductor layer for reflecting light emitted from the semiconductor light emitting layer;
A semiconductor light emitting device comprising:

(Appendix 7)
The semiconductor light-emitting element according to appendix 5 or appendix 6, wherein the conductive support substrate is a silicon substrate, a metal substrate, a ceramic substrate, or a germanium substrate.

10, 50, 60, 70, 90, 210, 230 Semiconductor light emitting device 11, 61, 91 Semiconductor laminate 12 N-type GaN cladding layer 12a, 81 Concavity and convexity 13 P-type GaN cladding layer 14 P-type GaN contact layers 15, 94 Semiconductor light emitting layer 15a Main surface 17 Pad electrode 17a Fine wire electrode 18 Metal electrode 19 Bonding layer 20 Support substrate 21, 72 Substrate electrode 25 InGaN barrier layer 26 InGaN well layer 41 Sapphire substrate 42 Silicon substrate 43, 44 Gold film 45 Gold-tin alloy film 46 heater 47 laser beam 48 Ga layer 51, 80 transparent conductive film 62 P-type AlGaN overflow prevention layer 63 superlattice buffer layer 71 conductive substrate 92 N-type AlGaN cladding layer 93 P-type AlGaN cladding layer 95 AlGaN barrier layer 96 AlGaN well layer 211, 231 P-side electrodes 212, 23 N-side electrodes 213,233,235 insulating film 221,224,241 resist film 222 via hole 223 silicon oxide film 234 N side electrode bumps 236 N-side electrode pad 242 trench

Claims (14)

An N-type semiconductor layer;
A P-type semiconductor layer;
The P-type semiconductor of the barrier layers provided between the N-type and P-type semiconductor layers, having a multiple quantum well structure in which well layers and barrier layers are alternately stacked. A semiconductor light emitting layer in which the band gap of the barrier layer closest to the layer is narrower than the band gap of the remaining barrier layers;
An N-side electrode and a P-side electrode electrically connected to the N-type semiconductor layer and the P-type semiconductor layer so that a current flows in a direction substantially perpendicular to the main surface of the semiconductor light emitting layer;
A semiconductor light emitting element comprising:   The P-side electrode is a metal electrode that is provided on the P-type semiconductor layer and reflects light emitted from the semiconductor light-emitting layer, and the N-side electrode is a thin wire electrode provided on the N-type semiconductor layer. The semiconductor light emitting device according to claim 1, wherein the semiconductor light emitting device is provided.   2. The semiconductor light emitting device according to claim 1, further comprising a transparent conductive film provided on the N-type semiconductor layer, wherein the thin wire electrode is provided on the transparent conductive film. An N-type semiconductor layer;
A P-type semiconductor layer;
The P-type semiconductor of the barrier layers provided between the N-type and P-type semiconductor layers, having a multiple quantum well structure in which well layers and barrier layers are alternately stacked. A semiconductor light emitting layer in which the band gap of the barrier layer closest to the layer is narrower than the band gap of the remaining barrier layers;
An N-side electrode and a P-side electrode electrically connected to the N-type semiconductor layer and the P-type semiconductor layer so as to include a current flowing in a direction perpendicular to the main surface of the semiconductor light emitting layer;
Comprising
The N-side electrode and the P-side electrode have a plurality of portions equidistant from the main surface of the semiconductor light emitting layer in a direction perpendicular to the main surface, and one of the portions surrounds the other. A semiconductor light emitting element characterized by comprising: The P-side electrode is a metal electrode that is provided on the P-type semiconductor layer and reflects light emitted from the semiconductor light emitting layer,
The N-side electrode penetrates the semiconductor light emitting layer from the P-side electrode, contacts the N-type semiconductor layer, and draws out the N-type semiconductor layer to the P-type semiconductor layer side. The semiconductor light-emitting device according to claim 4, wherein   The N-side electrode is provided on the P-side electrode through an insulating film, and further includes a second N-side electrode to which the plurality of first N-side electrodes are connected in common. Semiconductor light emitting device.   The semiconductor light emitting device according to claim 6, wherein the plurality of first N-side electrodes are arranged in a hexagonal shape.   The semiconductor light emitting device according to claim 5, wherein the plurality of first N-side electrodes protrude into the N-type semiconductor layer by a predetermined height. The P-side electrode is a metal electrode that is provided on the P-type semiconductor layer and reflects light emitted from the semiconductor light emitting layer,
5. The semiconductor light emitting element according to claim 4, wherein the N-side electrode is a mesh-like fine wire electrode that penetrates the semiconductor light-emitting layer from the P-side electrode and contacts the N-type semiconductor layer.   The semiconductor light emitting device according to claim 9, wherein the N-side electrode is arranged in a hexagonal lattice shape.   10. The semiconductor light emitting device according to claim 9, wherein the N-side electrode protrudes by a predetermined height into the N-type semiconductor layer.   Except for the barrier layer closest to the P-type semiconductor layer among the barrier layers sandwiched between the well layers, the band gap of the barrier layer on the N-type semiconductor layer side is the P-type semiconductor layer side. 5. The semiconductor light emitting device according to claim 1, wherein the semiconductor light emitting device is equal to or wider than a band gap of the barrier layer.   5. The semiconductor light emitting element according to claim 1, wherein the N-type semiconductor layer has an uneven portion on at least a part of a main surface. The well layer is In _x1 Ga _y1 Al _(1-x1-y1) N (0 <x1 <1, 0 <y1 ≦ 1), and the barrier layer is In _x2 Ga _y2 Al _(1-x2-y2) N 5. The semiconductor light emitting device according to claim 1, wherein (0 ≦ x2 <x1 <1, 0 <y1 <y2 ≦ 1).

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