JP2013169031A - Battery equalization device and method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve optimum equalization of battery cells depending on the use situation of battery cell equalization, in the equalization control of voltage of a battery pack constituted by connecting a plurality of battery cells.SOLUTION: A high efficiency control mode (S510, S512) for controlling a switch control unit so as to reduce power loss in circuit elements including the switching elements in a balance circuit, a protection control mode (S511) for controlling the switch control unit so as to reduce the internal resistance loss while calculating the internal resistance of battery cells to be equalized, and a time shortening control mode (S513) for controlling the balance circuit so as to quicken convergence of discharge or charge voltage change of battery cells to be equalized, are switched (S504-S509) while determining the use situation of a battery pack thus controlling equalization of battery cells.

Description

  The present invention relates to a battery equalization apparatus and method for controlling voltage equalization of an assembled battery configured by connecting a plurality of battery cells.

  A so-called hybrid car, plug-in hybrid car, hybrid vehicle, hybrid electric vehicle or the like, which is equipped with a motor (electric motor) as a power source in addition to an engine or a transport machine (hereinafter referred to as “vehicle etc.”) is practical It has become. Furthermore, an electric vehicle that does not include an engine and drives the vehicle only by a motor is being put into practical use. As a power source for driving these motors, a lithium ion battery having a small size and a large capacity has been frequently used. And in such a use, a some battery cell is connected in series, for example, a battery block is comprised, and also it may be supplied as an assembled battery connected combining this battery block. A high voltage necessary for driving the motor of the vehicle is obtained by the series connection of the battery cells, and a necessary current capacity and a further high voltage can be obtained by connecting the battery blocks in combination in series and parallel.

  In this case, the characteristics of the lithium ion battery or the like greatly change depending on the temperature, and the remaining capacity and charging efficiency of the battery greatly change depending on the temperature of the environment in which the battery is used. This is especially true in environments where automobiles are used.

  As a result, in the battery cells constituting the battery block, the remaining capacity and the output voltage of each cell vary. When the voltage generated by each cell varies, it becomes necessary to stop or suppress the entire power supply when the voltage of one cell falls below the driveable threshold, resulting in reduced power efficiency. Resulting in. For this reason, the battery equalization control which equalizes the voltage of each cell is required. Furthermore, it is necessary to equalize the voltage between the battery blocks.

  As a conventional technique for battery equalization control, a so-called active method in which discharge power from a battery cell or battery stack that requires discharge is charged to a battery cell that needs to be charged by a switching operation in a balance circuit using an inductor or a transformer. A battery equalization control technique is known (for example, Patent Document 1).

The purpose of this conventional technique is to equalize battery cells with a small power loss by using discharge power from one battery cell as charge power to another battery cell.
However, in this prior art, however, since control is simply performed based on the potential difference between the battery cells, there is a problem that control according to the utilization scene is not necessarily optimal control. For example, depending on the user, since the ignition has been turned on for a long time, it may be better to equalize the battery cells in a short time during the short ignition off period, giving priority to time rather than efficiency. On the other hand, for users whose ignition is off longer, it may take more time, so it is better to perform efficient battery cell equalization. On the other hand, it is difficult to equalize battery cells with high efficiency unless power loss due to deterioration of the battery cells or power loss in the balance circuit is taken into consideration. The prior art has a problem that it is not possible to equalize battery cells to meet such various requirements.

JP 2001-185229 A

  An object of this invention is to implement | achieve the equalization of the optimal battery cell according to the use condition of a battery cell equalization.

  An example of an aspect is a battery equalization device that equalizes voltages of a plurality of battery cells in an assembled battery to which a plurality of battery cells are connected, and performs one or more batteries while performing a switching operation by a switching element. A balance circuit that equalizes the voltage of the battery cell by performing an operation of discharging the charge from the cell and an operation of charging the discharged charge to one or more other battery cells, and supplying a pulse signal to the switching element High efficiency control mode for controlling the switch control unit so as to reduce the power loss in the switch control unit for executing the switching operation, the circuit element including the switching element in the balance circuit, and the internal resistance of the battery cell for performing equalization Is a protection control mode that controls the switch controller so that the internal resistance loss of the battery cell is reduced. And a time reduction control mode for controlling the balance circuit so as to accelerate the convergence of the voltage change of the discharge or charging of the battery cells for performing equalization, and switching and controlling the battery pack while judging the usage status of the assembled battery With.

  ADVANTAGE OF THE INVENTION According to this invention, it becomes possible to implement | achieve optimal equalization of the battery cell according to the use condition of battery cell equalization.

It is a block diagram of the converter balance circuit in this embodiment. It is a block diagram of the switch control part in this embodiment. It is a lineblock diagram of the vehicle system to which this embodiment is applied. It is a timing chart which shows the control operation of this embodiment. In this embodiment, it is a flowchart which shows the control operation for implementing equalization control by switching high efficiency control mode, protection control mode, or time reduction control mode. It is a flowchart which shows the control operation in high efficiency control mode. It is operation | movement explanatory drawing of time reduction control mode. It is a flowchart which shows the control action of time-shortening control mode. It is a figure which shows the structural example of other embodiment of a balance circuit.

Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings.
FIG. 1 is a configuration diagram of a converter balance circuit in the present embodiment.
A plurality of battery cells are connected to form an assembled battery. In the present embodiment, the assembled battery is configured as a set of stacks 101 including a predetermined number of battery cells 102 continuously connected in series. FIG. 1 shows a part of one stack 101.

  The converter balance circuit 100 performs an operation of discharging the charge from one or more battery cells 102 in the stack 101 and one or more other charges in the stack 101 while performing a switching operation by the switching elements SW1 and SW2. The operation of charging the battery cell 102 is executed.

  Specifically, the converter balance circuit 100 switches the switching element SW1 (# 1, # 2, # 3) from one or more of the battery cells 102 in the stack 101 with respect to the stack 101 constituting the assembled battery. The operation of discharging the charge is performed through the switching operation of Following this, the converter balance circuit 100 charges the discharged electric charge to one or more other battery cells 102 in the stack 101 via a switching operation by the switching element SW2 (# 1, # 2, # 3). Perform the action. Thereby, the converter balance circuit 100 equalizes the voltages of the battery cells 102 in the stack 101.

  More specifically, the converter balance circuit 100 includes a balance circuit 103, a switch control unit 104, a current measurement unit 107, and a CPU (Central Processing Unit) 105 that operates as a balance control unit and a memory 109 connected thereto. . Further, a battery cell monitoring unit 106 is connected to the converter balance circuit 100. The battery cell monitoring unit 106 monitors the voltage of each battery cell 102 in the stack 101 and detects it as a digital signal value. Further, the battery cell monitoring unit 106 monitors the temperature detected by the temperature sensor 108 installed in the vicinity of the representative battery cell 102 in the stack 101 and detects it as a digital signal value. For example, the temperature sensor 108 is installed for each of several battery cells 102 in each part.

  For example, the balance circuit 301 includes a plurality of inductors L and a plurality of sets of switching elements SW1 and SW2 (hereinafter simply referred to as “SW1” and “SW2”) for four battery cells 102 # 1 to # 4 constituting the stack 101. (Sometimes called). Specifically, the first terminal of the # 1 inductor L is connected to the common connection terminal of the # 1 and # 2 battery cells 102, and the # 2 inductor is connected to the common connection terminal of the # 2 and # 3 battery cells 102. The first terminal of L is connected to the common connection terminal of the battery cells 102 of # 3 and # 4, and the first terminal of the inductor L of # 3 is connected thereto. The second terminal of # 1 inductor L is connected to the common connection terminal of SW1 and SW2 of # 1, and the second terminal of inductor L of # 2 is connected to the common connection terminal of SW1 and SW2 of # 2. The second terminal of the inductor L is connected to the common connection terminal of SW3 and SW2 of # 3, respectively. Further, the output terminal side of the # 1 battery cell 102 is connected to the single connection terminal of the SW1 of # 1. The common connection terminal of the battery cells 102 of # 1 and # 2 is connected to SW1 of # 2. The common connection terminal of the battery cells 102 of # 2 and # 3 is connected to the common connection terminal of SW2 of # 1 and SW1 of # 3. The common connection terminal of the battery cells 102 of # 3 and # 4 is connected to SW2 of # 2. The output terminal side of the battery cell 102 of # 4 is connected to the single connection terminal of SW2 of # 3.

  The switch control unit 104 supplies a pulse signal to each of the switching elements SW1 and SW2 to execute a switching operation. Specifically, the switch control unit 104 is an oscillation circuit that oscillates a pulse signal having a predetermined frequency and duty ratio designated by the CPU 105. The switching elements SW1 of # 1, # 2, and # 3 and the switching elements SW2 of # 1, # 2, and # 3 are FETs (field effect transistors), for example. The switching elements SW1 of # 1, # 2, and # 3 perform a switching operation by the first pulse signal from the switch control unit 104. The switching elements SW2 of # 1, # 2, and # 3 perform a switching operation by the second pulse signal from the switch control unit 104.

The battery cell monitoring unit 106 detects the voltages at both ends of the battery cells 102 # 1 to # 4 constituting the stack 101 and outputs the detected voltage to the CPU 105 as a digital value.
In the configuration of the converter balance circuit 100 described above, the CPU 105 designates a predetermined frequency and duty ratio to the switch control unit 104 when determining that the balance control between the battery cells 102 of # 1 and # 2 is to be performed, for example. Then, it instructs to operate # 1 SW1 and SW2. For example, the CPU 105 determines that the voltage of the # 1 battery cell 102 is higher than the voltage of the # 2 battery cell 102 based on the voltage monitoring result of the battery cell monitoring unit 106. In this case, first, the power discharged from the # 1 battery cell 102 is accumulated in the # 1 inductor L by the on / off operation of the # 1 SW1. Subsequently, the # 2 battery cell 102 is charged with the electric power stored in the # 1 inductor L by the on / off operation of the # 1 SW2 delayed by the duty ratio. Conversely, for example, the CPU 105 determines that the voltage of the # 2 battery cell 102 is higher than the voltage of the # 1 battery cell 102 based on the voltage monitoring result of the battery cell monitoring unit 106. In this case, first, the power discharged from the # 2 battery cell 102 is accumulated in the # 1 inductor L by the ON / OFF operation of the # 1 SW2. Subsequently, the # 1 battery cell 102 is charged with the electric power stored in the # 1 inductor L by the on / off operation of the # 1 SW1 delayed by the duty ratio.

  Further, when the CPU 105 determines that the balance control between the battery cells 102 of # 2 and # 3 is to be performed, the CPU 105 designates a predetermined frequency and duty ratio to the switch control unit 104, and switches SW1 and SW2 of # 2. To operate. For example, the CPU 105 determines that the voltage of the # 2 battery cell 102 is higher than the voltage of the # 3 battery cell 102 based on the voltage monitoring result of the battery cell monitoring unit 106. In this case, first, the power discharged from the # 2 battery cell 102 is accumulated in the # 2 inductor L by the on / off operation of the # 2 SW1. Subsequently, the power stored in the # 2 inductor L is charged in the # 3 battery cell 102 by the ON / OFF operation of the # 2 SW2 delayed by the duty ratio. Conversely, for example, the CPU 105 determines that the voltage of the # 3 battery cell 102 is higher than the voltage of the # 2 battery cell 102 based on the voltage monitoring result of the battery cell monitoring unit 106. In this case, first, the power discharged from the # 3 battery cell 102 is accumulated in the # 2 inductor L by the on / off operation of the # 2 SW2. Subsequently, the power stored in the # 2 inductor L is charged in the # 2 battery cell 102 by the on / off operation of the # 2 SW1 delayed by the duty ratio.

  Further, when the CPU 105 determines that the balance control between the battery cells 102 of # 3 and # 4 is to be performed, the CPU 105 designates a predetermined frequency and duty ratio to the switch control unit 104, and switches the switching element SW1 of # 3. , SW2 is instructed to operate. For example, the CPU 105 determines that the voltage of the # 3 battery cell 102 is higher than the voltage of the # 4 battery cell 102 based on the voltage monitoring result of the battery cell monitoring unit 106. In this case, first, the electric power discharged from the # 3 battery cell 102 is accumulated in the # 3 inductor L by the on / off operation of the # 3 SW1. Subsequently, the # 4 battery cell 102 is charged with the electric power stored in the # 3 inductor L by the on / off operation of the SW3 # 3 delayed by the duty ratio. Conversely, for example, the CPU 105 determines that the voltage of the # 4 battery cell 102 is higher than the voltage of the # 3 battery cell 102 based on the voltage monitoring result of the battery cell monitoring unit 106. In this case, first, the power discharged from the battery cell 102 of # 4 is accumulated in the inductor L of # 3 by the ON / OFF operation of SW2 of # 3. Subsequently, the power stored in the # 3 inductor L is charged in the # 3 battery cell 102 by the on / off operation of the # 3 SW1 delayed by the duty ratio.

  As described above, in converter balance circuit 100, when it is determined that balance control is necessary as a result of voltage monitoring of each battery cell 102 in stack 101 by battery cell monitoring unit 106, # 1 to # 3 Inductors L and # 1 to # 3 switching elements SW1 and SW2 are sequentially and selectively operated. As a result, the balance control is sequentially performed between the battery cells 102 adjacent to each of the battery cells 102 of # 1 to # 4, and the operation is repeated, so that the # 1 to # 4 in the stack 101 are finally obtained. The voltage of the battery cell 102 becomes uniform.

FIG. 2 is a detailed circuit configuration diagram of the switch control unit 104 for controlling the pair of switching elements SW1 and SW2.
The driver 201 in the switch control unit 104 oscillates each pulse signal having a frequency and a duty ratio designated by the CPU 105 and supplies them to the switching elements SW1 and SW2, respectively.

  The multiplexer (MUX) 202 in the switch control unit 104 is connected in series to both ends (drain-source) voltage / current of the switching element SW1, both ends (drain-source) voltage / current of the switching element SW2, and the inductor L. Each current (inductor average current or peak current) flowing through the resistor R (not shown in FIG. 1) is detected as an analog signal. Each voltage / current detection signal is converted into a digital signal by an A / D (analog / digital) converter 203 and notified to the CPU 105.

  The differential amplifier 204 in the switch control unit 104 activates the current limiter output when the inductor average current or peak current exceeds a predetermined threshold. When the current limiter output becomes active, the driver 201 stops the output of each pulse signal and stops the switching operation of the switching elements SW1 and SW2. As a result, an accident that an excessive inductor average current or peak current flows due to a circuit failure or the like to destroy the battery cell 102, the switching elements SW1, SW2, the inductor L, or the like can be prevented.

  FIG. 3 is a configuration diagram of a vehicle system to which the present embodiment is applied. 3, the converter balance circuit 100, the stack 101, and the battery cell monitoring unit 106 are the same as those shown in the configuration of FIG. 1 or FIG.

A plurality of sets including the stack 101, the battery cell monitoring unit 106, and the converter balance circuit 100 are combined to form one battery pack 301.
The battery control unit 302 controls the overall state of the battery pack 301. The battery control unit 302 communicates with the battery cell monitoring unit 106 to acquire voltage information and temperature information of the battery cell 102 and the entire stack 101, and performs control for equalizing voltage between the stacks 101. The battery control unit 302 in the battery pack 301 is connected to a travel control unit 303 that controls the travel of the vehicle via a controller area network (CAN). The battery control unit 302 notifies the travel control unit 303 of information related to the battery pack 301 via the CAN.

  Information on ignition on / off of the vehicle (IG-ON / OFF signal) is notified to the battery cell monitoring unit 106, the battery control unit 302, the travel control unit 303, and the like in the battery pack 301. The battery cell monitoring unit 106 notifies the received IG-ON / OFF signal to the CPU 105 (see FIG. 1) in the converter balance circuit 100.

  The eco mode ON / OFF instruction unit 304 notifies the CPU 105 in the converter balance circuit 100 via the battery control unit 302 of the eco mode ON / OFF instruction information from the user.

The environmental temperature sensor 305 notifies the measured environmental temperature around the vehicle to the CPU 105 in the converter balance circuit 100 via the battery control unit 302 from the CAN.
Then, the navigation system 306 notifies the current position information of the vehicle from the CAN to the CPU 105 in the converter balance circuit 100 via the battery control unit 302.

  In the present embodiment, the CPU 105 operating as a balance control unit in the converter balance circuit 100 switches between three modes of the high efficiency control mode, the protection control mode, and the time reduction control mode in the control of equalization of the battery cells 102. be able to. In switching between these modes, an IG-ON / OFF signal, echo mode ON / OFF instruction information, and environmental temperature information are determined. Further, battery temperature information from the temperature sensor 108 installed in the vicinity of the representative battery cell 102 of FIG. 1 is determined. Further, the degree of deterioration of the battery cell 102 to be controlled for equalization calculated from the voltage information of the battery cell 102 notified from the voltage monitoring unit 106 in FIG. 1 is determined. Here, in the high-efficiency control mode, it takes time to equalize the battery cells 102 by suppressing the heat generation of the battery cells 102 that perform equalization by suppressing the regenerative current for equalization. In this mode, the battery cell 102 can be implemented with high efficiency and high accuracy. In the protection control mode, when equalization control is performed on the battery cell 102 that has deteriorated, the regenerative current for equalization is further suppressed to suppress the heat generation of the battery cell 102, thereby the battery cell 102. This mode extends the lifespan of the device. The time reduction control mode is a mode in which the heat generation of the battery cells 102 to be equalized is allowed and the regenerative current for equalization is allowed to flow to complete the equalization of the battery cells 102 as soon as possible. In this embodiment, by switching between these modes while determining the above-described various information regarding the usage status of the battery pack 301, the battery power and the battery life are optimally controlled according to the usage status of the vehicle by the user. Can be realized.

  As one embodiment, in the high efficiency control mode, the switch control unit 104 is controlled so that the power loss in the circuit elements including the switching elements SW1 and SW2 in the balance circuit 103 in FIGS. More specifically, the CPU 105 selects either the frequency or duty ratio of the pulse signal that the switch control unit 104 supplies to the switching elements SW1 and SW2, or any switching signal source (not shown) that supplies power to the switching elements SW1 and SW2. Control one or more. In order to simply suppress the current flowing through the balance circuit 103 to some extent, it is possible to obtain a certain effect even by reducing the duty ratio of the pulse signal.

  In the protection control mode, the switch controller 104 is controlled so that the internal resistance loss of the battery cell 102 is reduced while the internal resistance of the battery cell 102 to be equalized is calculated. More specifically, the CPU 105 selects either the frequency or duty ratio of the pulse signal that the switch control unit 104 supplies to the switching elements SW1 and SW2, or any switching signal source (not shown) that supplies power to the switching elements SW1 and SW2. Control one or more. In order to further suppress the current flowing through the balance circuit 103, there is a certain effect even if the duty ratio of the pulse signal is made sufficiently small.

  Further, in the time reduction control mode, the balance circuit 103 is controlled so as to accelerate the convergence of the voltage change of the discharging or charging of the battery cells to be equalized. More specifically, the CPU 105 calculates a correction voltage corresponding to the internal resistance of the battery cell 102 to be equalized based on the measurement of the voltage and current of the battery cell 102 in the battery cell monitoring unit 106. Next, the CPU 105 corrects the equalization control end voltage corresponding to the battery cell 102 with the correction voltage. Then, the CPU 105 monitors the voltage of the battery cell 102 via the battery cell monitoring unit 106, and uses the corrected end voltage as the target value for the control end, and the equalization control by the balance circuit 103 for the battery cell 102. Execute. In order to simply increase the current flowing through the balance circuit 103, there is a certain effect even if the duty ratio of the pulse signal is increased or the frequency is decreased.

  FIG. 4 is a timing chart of the control operation of this embodiment. After the vehicle is ignited off (IG-OFF) or started idling at time t1 shown in (a), after waiting for a certain time by an internal timer as shown in (b), (c ), The converter balance circuit 100 of the present embodiment starts the equalization operation at time t2. The converter balance circuit 100 stops the equalization control operation at time t3 when the equalization operation is completed for all the battery cells 102 in the stack 101. The equalization operation by the converter balance circuit 100 from the time t2 to the time t3 may be executed only once after the start of ignition off or idling, or may be repeatedly executed at regular time intervals.

  FIG. 5 is a flowchart showing a control operation for performing control for switching the high efficiency control mode, the protection control mode, or the time reduction control mode executed by the CPU 105 of FIG. 1 or FIG. This control operation is realized as a process in which the CPU 105 executes a control program stored in the memory 109. Note that the control for selecting a set of battery cells 102 and stacks 101 to be equalized is performed in a separate routine, and in this control operation, information on the battery cells 102 for which equalization control is performed from the other routine. Is operated, and the equalization control mode for the battery cell 102 is determined and the equalization control is performed.

  First, the CPU 105 acquires parameters such as an IG-ON / OFF signal, echo mode ON / OFF instruction information, environmental temperature information, and battery temperature information, and stores them in the memory 109 (step S501).

  Next, based on the IG-ON / OFF signal held in the memory 109, the CPU 105 acquires an average value of the time from when the ignition is turned off (IG-OFF) to when the ignition is turned on (ON). (Step S502).

The CPU 105 acquires the identification information of the battery cell 102 or the set of stacks 101 (discharge side and charge side) to be controlled for equalization from another routine (step S503).
The CPU 105 determines whether the eco mode has been turned on or off by the user operating the eco mode on / off instruction unit 304 of FIG. 3 (step S504).

  If it is determined in step S504 that the eco mode has been turned ON by the user, the high efficiency control mode is selected and executed (steps S504 → S510). This mode can be selected according to the user's intention to perform the optimal equalization control of the battery cells 102 because it is not so steep in time. Details of one embodiment of the high efficiency control mode will be described later.

  If it is determined in step S504 that the eco mode has been turned off by the user, the CPU 105 further determines whether or not the time average value from ignition off to on calculated in step S502 is greater than or equal to a predetermined threshold value. Is determined (step S505).

  If it is determined in step 505 that the time average value from ignition off to on is smaller than the predetermined threshold, the time reduction control mode (time reduction control mode) is selected and executed (steps S505 → S513). When the user frequently gets on the vehicle and the ignition is turned off for a short time, the time reduction control mode is set in order to complete the equalization control of the battery cells 102 as soon as possible in the short period. Selected. In this case, priority is given to shortening the time for equalization control at the expense of the fact that the battery cell 102 tends to generate heat and its life is shortened. Details of one embodiment of the time reduction control mode will be described later.

  If it is determined in step 505 that the time average value from ignition off to on is equal to or greater than a predetermined threshold and there is sufficient time, the CPU 105 further detects the environmental temperature sensor 305 in FIG. It is determined whether the environmental temperature is higher, within the range, or lower than the predetermined appropriate range (step S506).

  When it is determined in step S506 that the environmental temperature is higher than the predetermined appropriate range, the high efficiency control mode is selected and executed (steps S506 → S510). When the environmental temperature is considerably high, the heat generation of the battery cell 102 is also accelerated, so this mode is selected in order to suppress the heat generation when it is determined in step S505 that there is enough time.

  If it is determined in step S506 that the environmental temperature is lower than the predetermined appropriate range, the time reduction control mode is selected and executed (steps S506 → S513). When the environmental temperature is considerably low, heat generation of the battery cell 102 is slow, and it is difficult to achieve an appropriate operating state when the vehicle is started. Therefore, heat generation of the battery cell 102 is promoted in the time reduction control mode in preparation for start-up.

  If it is determined in step S506 that the environmental temperature is within the predetermined appropriate range, the CPU 105 further determines whether the battery temperature detected by the temperature sensor 108 in FIG. 1 is higher than the predetermined appropriate range. Whether it is within the range or low is determined (step S507).

  When it is determined in step S507 that the battery temperature is higher than the predetermined appropriate range, the protection control mode is selected and executed (steps S507 → S511). In this case, the battery cell 102 has already generated considerable heat. In this case, this mode is selected in order to suppress the regenerative current as much as possible during the equalization control to suppress the internal resistance loss and to suppress the heat generation of the battery cell 102 to extend the life of the battery cell 102.

  If it is determined in step S507 that the battery temperature is lower than the predetermined appropriate range, the time reduction control mode is selected and executed (steps S507 → S513). In this case, when the battery temperature is considerably low, the battery cell 102 generates heat slowly and is unlikely to be in an appropriate operating state when the vehicle is started. Therefore, in preparation for the start-up, the heat generation of the battery cell 102 is promoted in the time reduction control mode. The

  When it is determined in step S506 that the battery temperature is within the predetermined appropriate range, the CPU 105 further calculates the internal resistance of the battery cell 102 that performs equalization control acquired in step S503, and the battery cell 102 Is calculated (step S508). When the internal resistance is large, the battery cell 102 is often deteriorated. Therefore, the CPU 105 determines the degree of deterioration from the internal resistance value of the battery cell 102. Here, when the stack 101 of FIG. 1 or FIG. 2 is in the power supply state, the CPU 105 determines those based on the voltage, current, and / or temperature of the battery cell 102 monitored by the battery cell monitoring unit 106. With reference to first map data (for example, held on the memory 109) for determining the internal resistance from the parameters, the internal resistance corresponding to the battery cell 102 is calculated. When the stack 101 is not in the power supply state, the CPU 105 determines the internal resistance from the parameters based on the voltage and / or temperature of the battery cell 102 monitored by the battery cell monitoring unit 106. The internal resistance corresponding to the battery cell 102 is calculated with reference to the map data (for example, held on the memory 109).

Subsequently, the CPU 105 determines whether or not the degree of deterioration of the battery calculated in step S508 is greater than or equal to a predetermined threshold (step S509).
If it is determined in step S509 that the degree of deterioration of the battery is greater than or equal to a predetermined threshold, the CPU 105 selects and executes the protection control mode (step S509 → S511). For a battery cell 102 that has deteriorated, this mode is used to extend the life of the battery cell 102 by sufficiently suppressing the regenerative current for equalization and suppressing the heat generation of the battery cell 102. Selected.

  If it is determined in step S509 that the degree of deterioration of the battery is smaller than the predetermined threshold, the CPU 105 selects and executes the high efficiency control mode (steps S509 → S512). If it is determined that the battery cell 102 has not deteriorated within the appropriate range of the environmental temperature or the battery temperature and that there is sufficient time in step S505, the battery life is not shortened and the optimum and accurate This mode in which high equalization control can be performed is selected.

  According to the above control operation, in this embodiment, the battery power and the battery are changed according to the use state of the vehicle by the user by appropriately switching the three modes of the high efficiency control mode, the protection control mode, and the time reduction control mode. It is possible to realize equalization with optimally controlled lifetime.

  If the CPU 105 obtains the current position information of the vehicle from the navigation system 306 in FIG. 3 and determines that the vehicle has stopped when the ignition is turned off for only a short time, such as a convenience store, for example. The equalization control may be activated in the time reduction control mode.

Next, an embodiment of the high efficiency control mode that is selected and executed in step S510 or S512 of FIG. 5 will be described in detail.
In the high-efficiency control mode, in FIG. 2, the CPU 105 outputs each pulse signal output from the driver 201 in the switch control unit 104 so that power loss in the circuit elements including the switching elements SW1 and SW2 in the balance circuit 103 is reduced. The frequency, the duty ratio, or any one or more of switching signal sources that supply power to the switching elements SW1 and SW2 are controlled. In the configuration of FIG. 2, the switching signal source and the control for it are omitted, but these may be included.

  More specifically, when the switching elements SW1 and SW2 are FETs (field effect transistors), the CPU 105 operates as follows. First, for each of the switching elements SW1 and SW2, the CPU 105 turns on the turn-on transition time with respect to any one or more values of drain-source voltage when turned off, drain-source current and voltage when turned on, and temperature. And map data obtained by measuring each value of the turn-off transition time in advance. Next, the CPU 105 measures one or more values of the drain-source voltage when the switching elements SW1 and SW2 are off, the drain-source current and voltage when they are on, and the temperature. Then, the CPU 105 uses one or more values of the measured drain-source voltage when the switching elements SW1 and SW2 are turned off, the drain-source current and voltage when turned on, and the temperature, and the values thereof. A turn-on transition time and a turn-off transition time obtained by referring to the map data are calculated. The CPU 105 selects either one of the frequency of each pulse signal, the duty ratio, or a switching signal source that supplies power to the switching elements SW1 and SW2 so that the switching loss of the switching elements SW1 and SW2 is reduced based on the calculation result. Control one or more.

  In the embodiment shown in FIG. 2, the CPU 105, via the MUX 202 in the switch control unit 104 and the A / D converter 203, drain-source voltage when the switching elements SW1 and SW2 are turned off, drain-source when turned on. Measure current and voltage. Measurement of temperature is omitted. The CPU 105 calculates these measured values and the turn-on transition time and the turn-off transition time obtained by referring to the aforementioned map data using these values. Based on the calculation result, the CPU 105 controls the frequency and duty ratio of each pulse signal so that the switching loss of the switching elements SW1 and SW2 becomes small. In the configuration of FIG. 2, the switching signal source that supplies power to the switching elements SW1 and SW2 and the control for the switching signal source are omitted, but these may be included.

  In the configuration of FIG. 2, the frequency of each pulse signal, the duty ratio, and the switching signal that supplies power to the switching elements SW1 and SW2 so that the on-resistance loss of the switching elements SW1 and SW2 is further reduced based on the measurement result described above. Any one or more of the sources may be controlled.

  In the configuration of FIG. 2, the following control may be further performed. The CPU 105 further measures the inductor average current or peak current via the MUX 202 and the A / D converter 203 in the switch control unit 104. Then, the CPU 105 switches the frequency of each pulse signal, the duty ratio, or the switching signal that supplies power to the switching elements SW1 and SW2 so that the power loss in the inductor L is further reduced based on the measured inductor average current or peak current. Control any one or more of the sources.

  With the configuration of the above embodiment, it is possible to realize the optimal equalization of the battery cells 102 including the switching loss or the on-resistance loss of at least the switching elements SW1 and SW2 constituting the balance circuit 103 in the high efficiency control mode. It becomes. Further, it is possible to realize the optimum equalization of the battery cells 102 including the power loss such as the parasitic resistance loss or the core loss of the inductor L and the internal resistance loss of the battery cell 102 to be charged as necessary.

The detailed operation of the embodiment of the above high efficiency control mode will be described below.
When the switching elements SW1 and SW2 are constituted by FETs, the switching loss of the FETs can be expressed by the following formula when expressed by mathematical formulas.

As understood from this equation, the switching loss of the FET can be expressed by the product of the drain-source voltage and the drain-source current of the FETs constituting the switching elements SW1 and SW2. Here, in the equalization control in the configuration of FIG. 2, it is considered to reduce the switching loss of Equation (1).

In order to reduce the switching loss,
Condition 1. 1. Conditions for reducing the on-time drain-source current Id for battery balance 2. Conditions for lowering the switching frequency fs of the pulse signal 405 (FIGS. 5A and 5B) 3. Conditions for reducing transistor transition times t_sw (on) and t_sw (off) It can be seen that a method such as lowering the drain-source voltage Vd during off-time is effective.

  Of these, condition 1. As for, the on-time drain-source current Id can be lowered by lowering the duty ratio of the switching signal or increasing the inductor L in FIG.

  Condition 2. If the frequency fs is simply lowered, the current increases. Therefore, the current can be suppressed by lowering the duty ratio as well as lowering the frequency. Alternatively, the current can be suppressed by increasing the inductor L. This can be expressed as:

In this equation, E ₂ is a potential when the pulse signal 405 is at a high level, and E ₁ is a potential (generally zero volts) when the pulse signal 405 is at a low level. Further, t1 to t2 are periods in which the pulse signal 405 is at a high level, and t2 to t3 are periods in which the pulse signal 405 is at a low level. Therefore, t1 to t3 are equal to the period of the pulse signal 405. L is equal to the inductance L in FIG. I _L is a current flowing through the inductor L. From the above equation (2), when the frequency of the pulse signal 405 is lowered, the integration period from t1 to t3 becomes longer, so that the current _IL increases. Therefore, the equation (2), E ₁ is zero for example, shortening the period from t1 to the pulse signal 405 goes high to t2, namely by reducing the duty ratio, or by the inductor L is increased, the current I _L can be reduced. From the above consideration, the switching loss of Equation 1 can be reduced by reducing the frequency and decreasing the duty ratio or increasing the inductor L. Note that when the frequency fs is lowered, the on-resistance loss of the FET increases, so it is lowered so as not to exceed it.

  Condition 3. As for, due to the characteristics of the FET, the transition time varies depending on the magnitude of the current Id. Therefore, the relationship between the current Id of the FET to be used and the transition time is stored in advance in the memory 109 as a map in the CPU 105 in FIG. 1 or FIG. 2, and the duty ratio and frequency fs are set so that the optimum current value is obtained. Control. The transition time can also be shortened by increasing the driving power of the FET switching signal source. In that case, for example, the driving force can be increased by increasing the output by using two switching signal sources that normally use one output.

Condition 4. Cannot be controlled due to the characteristics of the battery cell 102 itself to be controlled.
FIG. 6 is a flowchart showing equalization control for reducing the switching loss executed in the high efficiency control mode based on the above consideration. This control operation is realized as an operation in which the CPU 105 in FIG. 1 or 2 executes a control program stored in the memory 109. Hereinafter, FIG. 2 will be referred to as needed. In the following description, for example, the case of controlling the switching element SW1 of FIG. 2 will be described as an example, but the same applies to the case of the switching element SW2.

First, the CPU 105 measures the temperature in the vicinity of the FET of the switching element SW1 with a temperature sensor (not shown) and acquires the value (step S601).
Next, the CPU 105 acquires the voltage Vd when the FET of the switching element SW1 is turned off via the MUX 202 and the A / D converter 203 (step S602).

The CPU 105 acquires the current Id and the voltage Vd ′ when the FET of the switching element SW1 is on via the MUX 202 and the A / D converter 203 (step S603).
The CPU 105 uses the FET characteristic map of the switching element SW1 held in the memory 109 to correspond to the temperature, the off-time voltage Vd, the on-time current Id, and the on-time voltage Vd ′ acquired in steps S601 to S603. The FET turn-on transition time tr and turn-off transition time tf are obtained (step S604).

  The CPU 105 calculates the switching loss according to the above equation 1 using each of the acquired values, and calculates the on-resistance loss according to the following equation (step S605).

The CPU 105 compares the magnitudes of the losses calculated in step S605 (step S606).

  As a result of the comparison in step S606, if the switching loss is larger than the on-resistance loss, the CPU 105 calculates and adjusts the current or duty ratio so that the transition times tr and tf are minimized. Further, the switching frequency fs of the pulse signal 405 is lowered. Alternatively, as described above, the output of the switching signal source is increased (steps S606 → S607).

  If the on-resistance loss is greater than the switching loss as a result of the comparison in step S606, the CPU 105 calculates and adjusts the current or duty ratio so that the transition times tr and tf are minimized. Further, the switching frequency fs of the pulse signal 405 is increased. Alternatively, as described above, the output of the switching signal source is increased (steps S606 → S608).

  By the control operation shown in the above flowchart, in the high efficiency control mode in the present embodiment, the equalization operation of the battery cells 102 is performed while reducing the switching loss and the on-resistance loss in the switching element SW1 and the switching element SW2. It becomes possible to do.

  In the above description, paying attention to the switching loss and on-resistance loss of the FETs constituting the switching elements SW1 and SW2, the equalization control in the high-efficiency control mode is performed so as to reduce those power losses. In addition to these, it is also possible to take into account parasitic resistance losses or core losses in the inductor L. These losses can be expressed as:

Therefore, in order to reduce the loss in the inductor L, the CPU 105 equalizes the high-efficiency control mode so that the inductor average current or peak current obtained via the MUX 202 and the A / D converter 203 in FIG. Implement control.

  The above-described embodiment is an embodiment related to the optimum high-efficiency control mode, but the present invention is not limited to this, and most simply, in order to suppress the current flowing through the balance circuit 103 to some extent, Even if the duty ratio of the pulse signal output from the switch control unit 104 to the switching elements SW1 and SW2 is reduced, there are some effects.

Next, an embodiment of the protection control mode selected and executed in step S511 of FIG. 5 will be described in detail.
In the protection control mode, the switch controller 104 is controlled so that the internal resistance of the battery cell 102 is reduced while the internal resistance of the battery cell 102 to be equalized is calculated. First, the CPU 105 calculates the internal resistance of the battery cells 102 to be equalized by the same method as in step S508 in FIG. In this case, the internal resistance loss of the battery cell 102 can be expressed by the following equation.

Therefore, in order to reduce the internal resistance loss in the battery cell 102, the CPU 105 performs the equalization control so that the average current, the internal resistance value, and the duty ratio flowing in the charging-side battery cell 102 in the equalization are reduced. . Specifically, the CPU 105 is one of the frequency and duty ratio of the pulse signal that the switch control unit 104 supplies to the switching elements SW1 and SW2, or a switching signal source (not shown) that supplies power to the switching elements SW1 and SW2. One or more may be controlled so that the internal resistance loss calculated by Equation 5 falls within the allowable range.

  The above-described embodiment is an embodiment related to the optimum protection control mode, but the present invention is not limited to this, and most simply, in order to sufficiently suppress the current flowing through the balance circuit 103, Even if the duty ratio of the pulse signal is made sufficiently small, there is a certain effect.

Next, an embodiment of the time reduction control mode that is selected and executed in step S513 in FIG. 5 will be described in detail.
FIG. 7 is a diagram for explaining the operation in the time reduction control mode.

As illustrated in the balance circuit of FIG. 7A, the voltages of the two battery cells 102 are equalized in a state where the potential of the battery cell 102 of # 1 is higher than the potential of the battery cell 102 of # 2. Think about the case. In this case, the ideal voltage of the # 1 battery cell 102 gradually decreases from the initial highest potential due to the discharge, as indicated by a broken line OCV1 in FIG. 7B. On the other hand, the ideal voltage of the # 2 battery cell 102 gradually increases from the initial lowest potential by charging, as indicated by a broken line OCV2 in FIG. 7B. The target voltage G for equalization control is, for example,
Target voltage G = (OCV1 + OCV2) / 2 (1)
It is. However, the observed voltage of the # 2 battery cell 102 actually observed by the battery cell monitoring unit 106 in FIG. 1 is predetermined from the start of equalization control, as indicated by the solid line of the observed voltage 1 in FIG. After a lapse of time (several seconds), a voltage value lower than the ideal voltage OCV1 by a potential difference ΔV1 is observed. On the other hand, the observed voltage of the # 2 battery cell 102 actually observed by the battery cell monitoring unit 106 in FIG. 1 is predetermined from the start of equalization control, as indicated by the solid line of the observed voltage 2 in FIG. After a lapse of time (several seconds), a voltage value higher than the ideal voltage OCV2 by a potential difference ΔV2 is observed. These potential differences ΔV1 and ΔV2 are potentials generated by internal resistances including polarization resistances of the # 1 battery cell 102 and the # 2 battery cell 102, respectively.

  Here, consider a case where equalization control is simply performed so that the observed voltage 1 and the observed voltage 2 coincide with the target voltage G within a predetermined allowable error range. In this case, at time t1 in FIG. 7B, the observed voltage 1 and the observed voltage 2 substantially coincide with each other and reach the target voltage G, and equalization control for the # 1 battery cell 102 and the # 2 battery cell 102 is performed. finish. The time t1 required for the equalization control varies depending on the characteristics of the battery pack 301 and the level of the equalization control, but is several hours, for example. However, in this case, the average current I flowing in the balance circuit of FIG. 7A stops due to the end of the equalization control, and as a result, the observation voltage 1 increases by the internal resistance of the # 1 battery cell 102 × the average current I. End up. Conversely, the observed voltage 2 drops by the amount of the internal resistance of the # 2 battery cell 102 × the average current I. Thus, in the simple control as described above, the voltage values indicated by the # 1 battery cell 102 and the # 2 battery cell 102 after the time point t1 when the equalization control ends are the target voltage G in FIG. 7B. And the voltage values of both are not uniform at the convergence time t2. As a result, further equalization control needs to be performed, and the equalization control may take a long time.

Therefore, in the time reduction control mode of the present embodiment, the potential differences ΔV1 and ΔV2 (which are positive values) caused by the internal resistances of the # 1 battery cell 102 and the # 2 battery cell 102 are calculated as correction voltages. . Then, the CPU 105 determines that the observation voltage 1 by the battery cell monitoring unit 106 in FIG.
End voltage 1 = target voltage G−correction voltage ΔV1 (2)
The target voltage G is corrected to the end voltage 1 so that the equalization control is ended when. On the other hand, the observation voltage 2 from the battery cell monitoring unit 106 in FIG.
End voltage 2 = target voltage G + correction voltage ΔV2 (3)
The target voltage G is corrected to the end voltage 2 so that the equalization control is ended when.

  As a result, in the time reduction control mode according to the present embodiment, the equalization control for the # 1 battery cell 102 and the # 2 battery cell 102 ends at time t1 ′ in FIG. 7B. At this time t1 ′, the # 1 battery cell 102 on the discharge side shows a voltage value lower than the target voltage G by the internal resistance of the # 1 battery cell 102 × the average current I flowing through the cell balance circuit. Further, the # 2 battery cell 102 on the charging side shows a voltage value higher than the target voltage G by an amount corresponding to the internal resistance of the # 2 battery cell 102 × the average current I flowing through the cell balance circuit. In the case of the present embodiment, as shown in FIG. 7B, the average current I flowing through the balance circuit of FIG. 7A is stopped by the end of the equalization control. After that, it rises by the amount of the internal resistance of the battery cell 102 of # 1 × the average current I, and almost coincides with the target voltage G. On the contrary, the observed voltage 2 decreases by the amount corresponding to the internal resistance of the battery cell 102 of # 2 and the average current I after the time point t1 ′, and also almost coincides with the target voltage G. In this way, in the time reduction control mode according to the present embodiment, the voltage values of both can be made equal at the convergence time t2 after the time t1 ′ when the equalization control is completed. As a result, the time required for equalization control can be made shorter than before.

  FIG. 8 is a flowchart illustrating a control operation example of the equalization control start process in the time reduction control mode. This control operation is realized as an operation in which the CPU 105 executes a control program stored in the memory 109, for example.

First, the CPU 105 determines whether or not current is flowing through the battery cell 102 from the current measurement unit 107 of FIG. 1 via the battery cell monitoring unit 106 (step S801).
When it is determined in step S801 that current is flowing in the battery cell 102, and the stack 101 in FIG. 1 is in a power supply state, the CPU 105 determines the battery cell 102 that equalizes the voltage acquired in step S503 in FIG. The voltage and current of the battery cell 102 monitored by the battery cell monitoring unit 106 are acquired. Then, the CPU 105 estimates the internal resistance by referring to the map data for determining the internal resistance from the voltage and current, using the acquired set of voltage and current (step S802). In this map data, when the map data is referred to using the voltage CCV (V: volt) and current (A: ampere) detected from the battery cell 102, the map data is stored in the storage position corresponding to the intersection of these combinations. The data of the internal resistance (mΩ: milliohm) being read is read out. As described above, the internal resistance can be provided as map data in advance as data corresponding to the set of voltage and current of the battery cell 102, and this map data is used in the time reduction control mode of the present embodiment. Thus, the internal resistance of the battery cell 102 when the stack 101 is in the power supply state can be estimated.

  Next, the CPU 105 uses the switching elements SW1 and SW2 in FIG. 2 based on the following equations (4) and (5) according to the potential difference between the two battery cells 102 selected for equalization control. The switching control pulse frequency and duty ratio (duty ratio) are calculated and set in the switch control unit 104 (step S803).

In the above formulas (4) and (5), E1 and E2 are the voltage values of the two battery cells 102 to be equalized. Here, it is assumed that E1> E2. It is calculated by the potential difference ΔV = E1−E2. Imax is an allowable current value that can be passed through the battery cell 102. α is an appropriate weighting factor. The current value I _L flowing through the inductor L to which the switching elements SW1 and SW2 in operation are connected is calculated by these parameters and the equation (4). The duty ratio D is calculated by substituting the current value I _L , the inductor value L, and the predetermined pulse frequency freq into the equation (5). Although α in the equation (4) is a simple proportional coefficient, a threshold value may be provided for the potential difference ΔV, and α may be changed with the threshold value as a boundary. For example, weighting is performed so that a constant current is obtained up to a certain potential difference, and the current is decreased when the potential difference is less than a certain potential difference. Further, in the calculation of equation (5), the duty ratio D may be arbitrarily determined, and the pulse frequency freq may be calculated.

Thereafter, the CPU 105 instructs the driver 201 (FIG. 2) of the switch control unit 104 to start the equalization control operation (step S804).
Thereafter, the CPU 105 calculates a correction voltage value by multiplying the value of the internal resistance estimated in step S802 by the value of the current detected through the current measurement unit 107 and the battery cell monitoring unit 106 in FIG. . Then, the CPU 105 corrects the end voltage value for the battery cell 102 that performs the equalization control based on the above-described equation (2) (in the case of discharging) or (3) (in the case of charging), and performs the equalization control. The start process is terminated (step S805).

  When it is determined in step S801 in FIG. 8 that no current is flowing in the battery cell 102 and the assembled battery 101 is not in the power supply state, the CPU 105 performs the following operation on the battery cell 102 that equalizes the voltage.

  First, the CPU 105 performs switching control in the switching elements SW1 and SW2 based on the above-described equations (4) and (5) according to the potential difference between the two battery cells 102 selected for equalization control. The pulse frequency and the duty ratio (Duty ratio) are calculated and set in the switch control unit 104 (step S806). This process is the same as the process of step S803.

Next, the CPU 105 instructs the driver 201 in the switch control unit 104 to start the equalization control operation (step S807).
Next, the CPU 105 acquires from the battery cell monitoring unit 106 the voltage value (corresponding to the OCV in FIG. 7) of the corresponding battery cell 102 at the start of the equalization control in step S807. Subsequently, the CPU 105 acquires from the battery cell monitoring unit 106 the voltage value of the corresponding battery cell 102 when a predetermined time has elapsed after the start instruction. Then, the CPU 105 calculates the absolute value of the difference between the acquired two voltage values, and calculates the value of the change voltage from the OCV until a predetermined time has elapsed as a correction voltage. Then, the CPU 105 corrects the end voltage value for the battery cell 102 that performs the equalization control based on the above-described equation (2) (in the case of discharging) or (3) (in the case of charging), and performs the equalization control. The start process is terminated (step S808).

  After finishing the equalization control start process in the time reduction control mode shown in the flowchart of FIG. 8 as described above, the CPU 105 starts the battery cell 102 in FIG. 1 from the battery cell monitoring unit 106 in FIG. It is determined whether or not the notified voltage value matches the corrected end voltage value obtained in step S805 or S808 in FIG. 8 within a predetermined allowable error range. The switch control unit 104 is instructed to stop the switching operation of the switching elements SW1 and SW2, and the equalization control process in the time reduction control mode is terminated.

  In the embodiment described above, the circuit configuration example that realizes the equalization control by the converter balance circuit 100 shown in FIG. 1 or FIG. 2 has been described, but this circuit portion is not limited to the circuit configuration example.

  Examples of the cell balance circuit (cell balance unit) 103 include a transformer and a rectifier diode, a transformer, a rectifier diode, a capacitor, an inductor, or a transformer as shown in FIGS. 9A, 9B, and 9C. Can be realized by a balance circuit 900 or the like that combines a battery cell for discharging and a battery cell for charging.

  Further, as a balance circuit, for example, a transformer type and a converter type using an inductor may be combined to realize a converter or transformer type balance circuit that combines a battery cell for discharging and a battery cell for charging.

DESCRIPTION OF SYMBOLS 100 Converter balance circuit 101 Stack 102 Battery cell 103 Balance circuit 104 Switch control part 105 CPU (central processing unit)
106 Voltage Monitoring Unit 107 Current Measuring Unit 108 Temperature Sensor 201 Driver 202 Multiplexer (MUX)
203 A / D (Analog / Digital) Converter 204 Differential Amplifier 301 Battery Pack 302 Battery Control Unit 303 Travel Control Unit 304 Eco Mode ON / OFF Instruction Unit 305 Environmental Temperature Sensor 306 Navigation System SW1, SW2 Switching Element L Inductor R Resistance

Claims (10)

A battery equalizing device for equalizing voltages of a plurality of battery cells in an assembled battery to which a plurality of battery cells are connected,
The battery cell by performing an operation of discharging power from one or more of the battery cells and an operation of charging the one or more other battery cells with the discharged power while performing a switching operation by a switching element. A balance circuit that equalizes the voltage of
A switch controller for supplying the pulse signal to the switching element to execute the switching operation;
The battery cell while calculating the internal resistance of the battery cell for performing the equalization and the high-efficiency control mode for controlling the switch controller so as to reduce the power loss in the circuit element including the switching element in the balance circuit A protection control mode for controlling the switch control unit so as to reduce the internal resistance loss of the battery, and a time reduction for controlling the balance circuit so as to accelerate the convergence of the voltage change of the discharge or charge of the battery cell for performing the equalization A balance control unit for switching and controlling the control mode while determining the usage status of the assembled battery;
A battery equalizing apparatus comprising: The balance control unit is turned on after the high-efficiency control mode, the protection control mode, and the time reduction control mode are designated by the user, and the ignition switch of the vehicle on which the assembled battery is mounted is turned off. One or more of a time average value, a temperature of the assembled battery, an environmental temperature around the assembled battery, a deterioration degree of the battery cell that performs the equalization, or location information obtained from the navigation system is determined. Switch
The battery equalizing apparatus according to claim 1. The balance control unit supplies power to the frequency, duty ratio, or the switching element of the pulse signal so that power loss in a circuit element including the switching element in the balance circuit is reduced in the high efficiency control mode. Control any one or more of the switching signal sources;
The battery equalizing apparatus according to claim 1, wherein the battery equalizing apparatus is provided. In the protection control mode, the balance control unit calculates the internal resistance of the battery cell that performs the equalization while calculating the internal resistance loss of the battery cell, so that the frequency of the pulse signal, the duty ratio, or Controlling any one or more of the switching signal sources that supply power to the switching element;
The battery equalizing apparatus according to claim 1, wherein the battery equalizing apparatus is provided. The balance control unit calculates a correction voltage corresponding to the internal resistance of the battery cell that performs the equalization based on the measurement of the voltage and current of the battery cell in the time reduction control mode, and uses the correction voltage. The balance circuit corrects the equalization control end voltage corresponding to the battery cell, and monitors the voltage of the battery cell while using the corrected end voltage as a target value for the control end. Execute control,
The battery equalizing apparatus according to claim 1, wherein the battery equalizing apparatus is provided. A battery equalization method for equalizing voltages of a plurality of battery cells in an assembled battery to which a plurality of battery cells are connected,
The battery cell by performing an operation of discharging power from one or more of the battery cells and an operation of charging the one or more other battery cells with the discharged power while performing a switching operation by a switching element. Equalize the voltage of
Supplying a pulse signal to the switching element to perform the switching operation;
While calculating the high-efficiency control mode for controlling the switching operation so as to reduce the power loss in the circuit element including the switching element in the circuit for performing the equalization, and calculating the internal resistance of the battery cell for performing the equalization A protection control mode for controlling the switching operation so as to reduce the internal resistance loss of the battery cell, and the equalization operation for speeding up convergence of a voltage change in discharging or charging of the battery cell for performing the equalization. Switching and controlling the time reduction control mode to be controlled while determining the usage status of the assembled battery,
The battery equalization method characterized by the above-mentioned. The high-efficiency control mode, the protection control mode, and the time reduction control mode are designated by a user, a time average value from when an ignition switch of a vehicle on which the assembled battery is mounted is turned on to when it is turned on next, Determining and switching any one or more of the temperature of the assembled battery, the ambient temperature around the assembled battery, the degree of deterioration of the battery cell performing the equalization, or the location information obtained from the navigation system;
The battery equalization method according to claim 6. In the high-efficiency control mode, either the frequency of the pulse signal, the duty ratio, or a switching signal source that supplies power to the switching element so that power loss in a circuit element including the switching element in the balance circuit is reduced Control one or more,
The battery equalization method according to claim 6, wherein the battery equalization method is performed. In the protection control mode, the frequency of the pulse signal, the duty ratio, or power to the switching element is reduced so as to reduce the internal resistance loss of the battery cell while calculating the internal resistance of the battery cell that performs the equalization. Control any one or more of the switching signal sources supplied;
The battery equalization method according to claim 6, wherein the battery equalization method is performed. In the time reduction control mode, a correction voltage corresponding to the internal resistance of the battery cell that performs the equalization is calculated based on the measurement of the voltage and current of the battery cell, and the correction cell corresponds to the battery cell by the correction voltage. The equalization control end voltage is corrected, and while the voltage of the battery cell is monitored, the corrected end voltage is set as a control end target value, and the equalization control by the balance circuit is performed on the battery cell.
The battery equalization method according to claim 6, wherein the battery equalization method is performed.