JP2013153099A - Method for manufacturing semiconductor device - Google Patents

Abstract

A method for manufacturing a semiconductor device is provided that can be manufactured without reducing reliability, throughput, or the like.
A step of forming a first conductive layer on one main surface of a semiconductor substrate; and a step of forming an oxide pattern by oxidizing a surface layer portion of the first conductive layer. And polishing the first conductive layer at a polishing rate faster than the polishing rate for the oxide pattern, thereby forming the conductive pattern 44a of the first conductive layer in the region where the oxide pattern was present. doing.
[Selection] Figure 12

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  Recently, a technique has been proposed in which vias that penetrate through a substrate (through vias) are formed and signals are transmitted and electric power is supplied through the through vias.

  The technique for forming a through via in a silicon substrate is called a TSV (Through Silicon Via) process.

  When semiconductor chips with through vias are bonded to each other, signal transmission / reception can be speeded up and power loss can be reduced as compared with the case where bonding wires are used. Moreover, space saving can be achieved and it can contribute to size reduction of an electronic device.

JP 2005-191034 A

  However, the proposed technique may cause a decrease in reliability, throughput, and the like.

  An object of the present invention is to provide a method of manufacturing a semiconductor device that can be manufactured without degrading reliability, throughput, or the like.

  According to one aspect of the embodiment, a step of forming a first conductive layer on one main surface of a semiconductor substrate, and an oxide pattern is formed by oxidizing a surface layer portion of the first conductive layer And polishing the first conductive layer at a polishing rate faster than the polishing rate for the oxide pattern, thereby forming a conductive pattern of the first conductive layer in a region where the oxide pattern was present There is provided a method of manufacturing a semiconductor device characterized by comprising the steps of:

  According to the disclosed method for manufacturing a semiconductor device, an oxide pattern having a slower polishing rate than the first conductive layer is formed by oxidizing the surface layer portion of the first conductive layer, and then the first conductive layer is formed. To polish. For this reason, the conductive pattern formed of the first conductive layer can be formed in the region where the oxide pattern has been formed. Then, the second conductive layer can be formed by electroplating on the first conductive layer in the opening using the conductive pattern thus formed as a seed layer. Therefore, the second conductive layer can be formed in the opening in a relatively short time by electroplating. Further, since the thick second conductive layer is not formed on the entire surface of the semiconductor substrate, it is possible to prevent a large stress from occurring. For this reason, it is possible to prevent peeling of the plating film, warpage of the semiconductor wafer, cracks, and the like, and a highly reliable semiconductor device can be provided. In addition, when the second conductive layer in the region other than the inside of the opening is polished, the thick second conductive layer formed on the entire surface is not polished, so the second conductive layer is polished with a relatively high throughput. can do. Therefore, it is possible to provide a semiconductor device at low cost without reducing reliability and throughput.

FIG. 1 is a process sectional view showing an outline of the TSV process. FIG. 2 is a plan view (part 1) showing an example of a layout of energization patterns formed on a semiconductor wafer. FIG. 3 is a plan view (part 2) showing an example of a layout of energization patterns formed on a semiconductor wafer. FIG. 4 is a plan view (No. 3) showing an example of a layout of energization patterns formed on the semiconductor wafer. FIG. 5 is a process cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 6 is a process cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 7 is a process cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 8 is a process cross-sectional view (part 4) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 9 is a process cross-sectional view (part 5) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 10 is a process cross-sectional view (No. 6) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 11 is a process cross-sectional view (No. 7) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 12 is a process cross-sectional view (No. 8) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 13 is a process cross-sectional view (No. 9) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 14 is a process cross-sectional view (No. 10) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 15 is a process cross-sectional view (No. 11) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 16 is a schematic view showing an electroplating apparatus. FIG. 17 is a diagram showing a part of the electroplating apparatus. FIG. 18 is a plan view showing a modified example of the layout of the energization pattern formed on the semiconductor wafer. FIG. 19 is a process sectional view showing the method for manufacturing the semiconductor device according to the second embodiment. FIG. 20 is a process sectional view showing the method for manufacturing the semiconductor device according to the third embodiment. FIG. 21 is a process sectional view showing the method for manufacturing the semiconductor device according to the fourth embodiment. FIG. 22 is a process sectional view showing the method for manufacturing the semiconductor device according to the fifth embodiment. FIG. 23 is a process sectional view showing the method for manufacturing the semiconductor device according to the sixth embodiment. FIG. 24 is a process cross-sectional view illustrating the semiconductor device manufacturing method according to the seventh embodiment. FIG. 25 is a process cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor device according to the reference example. FIG. 26 is a process cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the reference example; FIG. 27 is a process cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the reference example; FIG. 28 is a schematic view showing a process of forming a plating film by electroplating.

  A method for manufacturing a semiconductor device according to a reference example will be described with reference to FIGS. 25 to 27 are process cross-sectional views illustrating a method of manufacturing a semiconductor device according to a reference example. The left side of the paper in FIGS. 25 to 27 shows the region 202 where the transistor is formed, and the right side of the paper 202 of the region 202 where the transistor is formed shows the region 204 where the through via is formed. The right side of the region 204 where the through via is formed shows a region 208 at the peripheral edge of the silicon wafer.

  First, an element isolation region 212 that defines an element region is formed on a silicon substrate (silicon wafer) 210. Next, a transistor 218 having a gate electrode 214 and source / drain regions 216 is formed in the element region. Next, an interlayer insulating film 220 is formed on the entire surface. Next, contact holes 222 reaching the source / drain regions 216 are formed in the interlayer insulating film 220 by using a photolithography technique. Next, a conductor plug 224 is embedded in the contact hole 222. Next, a silicon carbide (SiC) film 226 is formed on the entire surface. Next, an interlayer insulating film 228 is formed on the entire surface (see FIG. 25A).

  Next, a photoresist film 230 is formed on the entire surface. Thereafter, an opening 232 for forming an opening 234 (see FIG. 25C) is formed in the photoresist film 230 at a position where the through via 264 (see FIG. 27A) is embedded (FIG. 25). (See (b)).

  Next, the interlayer insulating film 228 and the SiC film 226 are etched using the photoresist film 230. As a result, a SiC hard mask 226 is formed.

  Next, the interlayer insulating film 220 and the semiconductor substrate 210 are dry-etched using the photoresist film 230 and the hard mask 226 as a mask. As a result, an opening 234 for embedding the through via 264 is formed in the semiconductor substrate 210 (see FIG. 25C). The diameter of the opening 234 is, for example, about 5 μm. The depth of the opening 234 is, for example, about 50 μm.

  Next, an insulating film 236 is formed on the entire surface (see FIG. 26A).

  Next, a barrier metal film 238 is formed on the entire surface by PVD (Physical Vapor Deposition). Next, a Cu seed layer 240 is formed on the entire surface by PVD (see FIG. 26B).

  Next, a Cu plating film 242 is formed on the entire surface by electroplating (electrolytic plating) (see FIG. 26C).

  FIG. 28 is a schematic view showing a process of forming a plating film by electroplating.

  FIG. 28A shows a state in which the silicon wafer 210 is supported by a clamp (not shown) of an electroplating apparatus.

  FIG. 28B shows a state immersed in the plating solution 211.

  FIG. 28C shows a process in which the plating film 242 is grown on the surface of the seed layer 240.

  FIG. 28D shows a state where the inside of the opening 234 is filled with the plating film 242. In a region other than the opening 234, for example, a plated film 242 of 5 μm or more is formed.

  Next, by polishing the plating film 242, the seed layer 240, and the barrier metal film 238 by CMP (Chemical Mechanical Polishing), the through via 264 is embedded in the opening 234 (FIG. 27 ( a)).

  Next, a multilayer wiring structure 302 is formed (see FIG. 27B).

  Next, the upper surface side of the semiconductor substrate 210 on which the multilayer wiring structure 302 is formed is supported by a support (not shown), and the lower surface side (back surface side) of the semiconductor substrate 210 is ground. As a result, a via 264 penetrating the semiconductor substrate 210 is obtained.

  Thus, the semiconductor device according to the reference example is manufactured (see FIG. 27C).

  In the semiconductor device manufacturing method according to the reference example, since the plating film 242 is formed so as to fill the deep opening 234, it takes a very long time to form the plating film 242. Further, since the thick plating film 242 is formed on the entire surface of the silicon wafer 210, a large stress is generated, and the plating film 242 or the like may be peeled off or the silicon wafer 210 may be warped. Further, since the thick plating film 242 formed on the entire surface of the silicon wafer 210 is polished by the CMP method, a high throughput cannot be obtained, which leads to an increase in cost.

[First Embodiment]
The semiconductor device manufacturing method according to the first embodiment embeds a via penetrating the semiconductor substrate in the semiconductor substrate. As described above, a technique for forming a via penetrating a silicon substrate is called a TSV process. Prior to describing the semiconductor device manufacturing method according to the present embodiment, an outline of the TSV process will be described. FIG. 1 is a process sectional view showing an outline of the TSV process. Here, the main steps and the like of the TSV process will be described, and detailed description will be omitted.

  First, a silicon wafer (silicon substrate) 10 is prepared (see FIG. 1A).

  Next, the transistor 18 and the like are formed on the silicon substrate 10. Thereafter, an interlayer insulating film 20 is formed on the silicon substrate 10. Thereafter, a conductor plug 24 connected to the source / drain (not shown) of the transistor 18 is embedded in the interlayer insulating film 20 (see FIG. 1B).

  Next, an opening 34 for embedding the through via 64 is formed in the silicon substrate 10. Thereafter, a Cu via 64 is embedded in the opening 34 by electroplating (see FIG. 2C).

  Next, the multilayer wiring structure 102 is formed on the silicon substrate 10.

  Next, in a state where the upper surface side of the silicon substrate 10 on which the multilayer wiring structure 102 is formed is supported by the support body 104, the lower surface side (back surface side) of the silicon substrate 10 is ground to expose the lower end of the via 64. . As a result, vias (through vias, through electrodes) 64 penetrating the silicon substrate 10 are obtained.

  Next, the method for fabricating the semiconductor device according to the first embodiment will be explained with reference to FIGS.

  FIG. 2 is a plan view (part 1) showing an example of a layout of energization patterns formed on a semiconductor wafer. FIG. 2 shows an intermediate stage when the semiconductor device according to the present embodiment is manufactured, and specifically shows a stage where the energization pattern 44a is formed.

  As shown in FIG. 2, a plurality of chip regions (semiconductor chip regions) 11 are formed in a matrix on the semiconductor wafer 10.

  A region between the chip region 11 and the chip region 11 becomes a scribe line region 52 for performing dicing.

  FIG. 3 is a plan view (part 2) showing an example of a layout of energization patterns formed on a semiconductor wafer. FIG. 3 is an enlarged view of a portion surrounded by a broken line in FIG.

  FIG. 4 is a plan view (No. 3) showing an example of a layout of energization patterns formed on the semiconductor wafer. FIG. 4 is an enlarged view of a portion surrounded by a broken line in FIG.

  As shown in FIGS. 2 to 4, a conductive pattern (energization pattern) 44 a is formed in the peripheral portion of the semiconductor wafer 10, the scribe line region 52, and the chip region 11. The energization pattern 44a functions as a seed layer when the plating film (conductive layer) 62 is formed by electroplating. The conductive pattern 44a formed on the peripheral edge of the semiconductor wafer 10, the conductive pattern 44a formed in the scribe line region 52, and the conductive pattern 44a formed in the chip region 11 are integrally formed. In the chip region 11, the conductive pattern 44 a is formed so as to connect the patterns of the places 13 where the through vias are formed. Therefore, the conductive pattern 44a in the portion 13 where the through via is formed and the conductive pattern 44a in the peripheral portion of the semiconductor wafer 10 are in an electrically connected state.

  5 to 15 are process cross-sectional views illustrating the semiconductor device manufacturing method according to the present embodiment. The left side of the drawing in FIGS. 5 to 15 shows a region 2 where a transistor is formed, and corresponds to a cross section taken along line AA ′ in FIG. The right side of the region 2 where the transistor is formed shows the region 4 where the through via is formed, and corresponds to the cross section taken along the line BB 'in FIG. The right side of the region 4 where the through via is formed shows the region 6 where the energization pattern is formed, and corresponds to the section CC 'in FIG. The right side of the region 6 where the energization pattern is formed on the paper surface shows the region 8 at the peripheral edge of the semiconductor wafer, and corresponds to the cross section along the line DD 'in FIG.

  First, an element isolation region 12 that defines an element region is formed on a semiconductor substrate (semiconductor wafer) 10 by, for example, STI (Shallow Trench Isolation) (see FIG. 5A). For example, a silicon substrate is used as the semiconductor substrate 10. As a material of the element isolation region 12, for example, a silicon oxide film is used.

  Next, a transistor 18 having a gate electrode 14 and a source / drain region 16 is formed in the element region by a normal transistor formation method.

  Thus, the transistor 18 is formed in the region 2 where the transistor is formed.

  Next, a silicon oxide interlayer insulating film 20 having a thickness of, for example, about 230 nm is formed on the entire surface by, eg, CVD (Chemical Vapor Deposition).

  Next, contact holes 22 reaching the source / drain regions 16 are formed in the interlayer insulating film 20 by using a photolithography technique.

  Next, for example, a titanium (Ti) film having a thickness of about 7 nm and a titanium nitride film (TiN) film having a thickness of about 7 nm are sequentially formed on the entire surface by, for example, the PVD method. (Not shown).

  Next, a tungsten (W) film having a thickness of, for example, about 200 nm is formed on the entire surface by, eg, CVD.

  Next, the tungsten film and the barrier metal film are polished by CMP, for example, until the surface of the interlayer insulating film 20 is exposed. In this way, the tungsten conductor plug 24 is buried in the contact hole 22 (see FIG. 5B).

  Next, a silicon carbide (silicon carbide, SiC) film 26 having a thickness of, eg, about 100 nm is formed on the entire surface by, eg, CVD (see FIG. 6A). The SiC film 26 functions as a hard mask, a polishing stopper or the like in a later process.

  Next, an interlayer insulating film 28 of, eg, a silicon oxide film with a thickness of about 200 nm is formed on the entire surface by, eg, CVD (see FIG. 6B).

  Next, a photoresist film 30 of, eg, a thickness of about 3 μm is formed on the entire surface by, eg, spin coating.

  Next, the photoresist film 30 is patterned using a photolithography technique. As a result, the opening 32 for forming the opening 34 (see FIG. 7B) in the portion 13 (see FIGS. 3 and 4) in which the through via 64 (see FIG. 13B) is embedded is a photo. It is formed on the resist film 30 (see FIG. 7A).

  Next, the interlayer insulating film 28 and the SiC film 26 are etched using the photoresist film 30. Thereby, a SiC hard mask 26 is formed.

  Next, the interlayer insulating film 20 and the semiconductor substrate 10 are dry-etched using the photoresist film 30 and the hard mask 26 as a mask. Thereby, the opening 34 for embedding the via 64 is formed in the semiconductor substrate 10 (see FIG. 7B). The diameter of the opening 34 is, for example, about 1 μm to 20 μm. Here, the diameter of the opening 34 is, for example, about 5 μm. The depth of the opening 34 is, for example, about 50 to 200 μm. Here, the depth of the opening 34 is about 50 μm.

  Next, an insulating film 36 of, eg, a silicon oxide film with a film thickness of, eg, about 200 nm is formed on the entire surface by, eg, CVD (see FIG. 8A). The insulating film 36 is also formed inside the opening 34. The insulating film 36 is for ensuring insulation between the via 64 (see FIG. 13B) embedded in the opening 34 in a later step and the semiconductor substrate 10.

  Next, a barrier metal film 38 of, for example, a tantalum compound (Ta compound) having a film thickness of about 250 nm is formed on the entire surface by, eg, PVD. The barrier metal film 38 is also formed inside the opening 34 in which the insulating film 36 is formed (see FIG. 8B).

  The material of the barrier metal film 38 is not limited to tantalum compounds. For example, a Ti compound or the like may be used as the material of the barrier metal film 38.

Further, heat treatment may be performed in an atmosphere of a reducing gas before the barrier metal film 38 is formed in order to remove moisture, foreign matter, and the like. For example, H ₂ gas or NH ₃ gas is used as the reducing gas. The heat treatment temperature is, for example, about 150 to 350 ° C. The heat treatment time is, for example, about 1 to 5 minutes.

  Further, instead of performing the heat treatment, foreign matter or the like may be removed by etching using Ar ions or the like.

  Next, a Cu film (seed layer) 40 having a thickness of, for example, about 500 to 800 nm is formed on the entire surface by, eg, PVD (see FIG. 9A).

  Next, a Cu plating film 42 having a film thickness of 500 nm is formed on the entire surface by, eg, electroplating (electrolytic plating) (see FIG. 9B). Thus, the Cu conductive layer 44 having a thickness of about 1 μm to 1.3 μm is formed by the Cu film 40 formed by the PVD method and the Cu plating film 42 formed by the electroplating method.

  When forming the plating film 42 by the electroplating method, an electroplating apparatus as shown in FIGS. 16 and 17 is used. With reference to FIGS. 16 and 17, the step of forming the plating film 62 will be described. This will be described in detail.

  The conductive layer 44 becomes an energization pattern (conductive pattern) 44a. As will be described later, the conductive pattern 44a is formed by forming the oxide pattern 50 on the surface layer portion of the conductive layer 44, polishing the conductive layer 44 at a polishing rate faster than the polishing rate for the oxide pattern 50, It is formed by leaving the conductive layer 44 in the existing region. In order to form the energization pattern 44a in this manner, it is preferable to form the conductive layer 44 relatively thick. Therefore, in this embodiment, the conductive layer 44 is formed by further forming a Cu plating film 42 by an electroplating method on the Cu film 40 formed by the PVD method.

  Next, a photoresist film 46 is formed on the entire surface by, eg, spin coating (see FIG. 10A). The photoresist film 46 is also buried in the opening 34 in which the insulating film 36, the barrier metal film 38, and the Cu film 40 are formed.

  Next, the photoresist film 46 is patterned by using a photolithography technique (see FIG. 10B). As a result, an opening 48 for forming the oxide pattern 50 (see FIG. 11A) is formed in the photoresist film 46 in a later step. The pattern of the opening 48 is formed in the planar shape of the oxide pattern 50 (see FIGS. 2 to 4). Since the oxide pattern 50 is also formed around the opening 34, the pattern of the opening 48 is formed so as to expose the periphery of the opening 34.

  Note that it is preferable that the surface of the conductive layer 44 existing in the opening 34 is not oxidized when the conductive layer 44 is oxidized using the photoresist film 46 as a mask in a later step. This is because if the surface of the conductive layer 44 existing in the opening 34 is oxidized, it is difficult to grow the plating film 62 in the opening 34. Therefore, the pattern of the opening 48 is formed in the photoresist film 46 so that the photoresist film 46 is embedded in the opening 34.

  Next, using the photoresist film 46 as a mask, the surface layer portion (upper layer portion) of the conductive layer 44 is oxidized using an oxidizing agent 49 to form an oxide pattern (oxide layer) 50 (FIG. 11A). )reference). For example, dilute sulfuric acid is used as the oxidizing agent 49. Here, the surface layer portion of the oxide layer 50 is oxidized by applying dilute sulfuric acid 49. The concentration of sulfuric acid in the diluted sulfuric acid 49 is, for example, about 1% to 10%. More preferably, the concentration of sulfuric acid in dilute sulfuric acid 49 is about 1% to 5%. Here, the concentration of sulfuric acid in the dilute sulfuric acid 49 is, for example, about 2%.

  In addition, after applying the diluted sulfuric acid 49, the excess diluted sulfuric acid 49 may be removed from the conductive layer 44. For example, excess diluted sulfuric acid 49 is removed from the conductive layer 44 by shaking off the diluted sulfuric acid 49. FIG. 11A shows a state after excess diluted sulfuric acid 49 is removed from the conductive layer 44. Then, by leaving it for a predetermined time, moisture in the dilute sulfuric acid 49 remaining on the conductive layer 44 is vaporized, and the concentration of sulfuric acid in the dilute sulfuric acid 49 is improved. The leaving time can be about 30 seconds, for example. Thereby, the oxidizing power of the diluted sulfuric acid 49 remaining on the conductive layer 44 is improved, and the conductive layer 44 can be oxidized appropriately.

  Alternatively, excess dilute sulfuric acid 49 may be removed from the conductive layer 44 by shaking off the dilute sulfuric acid 49, and then baking (heat treatment) may be performed. Also in this case, the water in the dilute sulfuric acid 49 remaining on the conductive layer 44 is vaporized, the concentration of sulfuric acid in the dilute sulfuric acid 49 is improved, and the oxidizing power of the dilute sulfuric acid 49 is improved.

  Since Cu is used as the material of the conductive layer 44, the oxide pattern 50 is formed of copper oxide. The thickness of the oxide pattern 50 is, for example, about 100 to 200 nm.

  Thus, the oxide pattern 50 is formed on the surface layer portion of the conductive layer 44 by the treatment using the diluted sulfuric acid 49.

  After the oxide pattern 50 having a desired thickness is formed, washing with water is performed.

  In addition, when it grinds immediately after formation of the oxidation pattern 50, or when the surface is a dry state, you may make it abbreviate | omit water washing.

  In the present embodiment, the oxide pattern 50 is formed on the surface layer portion of the conductive layer 44 because the polishing rate for the oxide 50 is slower than the polishing rate for the conductive layer 44. Specifically, the polishing rate for Cu is, for example, about 7.5 nm / second, whereas the polishing rate for CuO is, for example, about 3.75 nm / second.

  Note that the polishing rate for CuO varies depending on the degree of oxidation, but it does not change that it is sufficiently slow with respect to the polishing rate for Cu.

  Since the polishing rate for the oxide 50 is slower than the polishing rate for the conductive layer 44, the polishing rate can be reduced in the region where the oxide pattern 50 is formed when the conductive layer 44 is polished in a subsequent step. Therefore, the conductive layer 44 can be selectively left in the region where the oxide pattern 50 has been formed, and the conductive pattern 44a formed by the conductive layer 44 is obtained. Therefore, the oxide pattern 50 is formed so as to obtain a desired conductive pattern 44a. Since the conductive pattern 44 a is also formed around the opening 34, the oxide pattern 50 is also formed on the conductive layer 44 around the opening 34.

  Thereafter, for example, the photoresist film 46 is removed using NMP (N-methyl-2-pyrrolidone) (see FIG. 11B).

  Next, the oxide pattern 50 and the conductive layer 44 are polished by CMP. As the abrasive, it is preferable to use an abrasive that does not contain abrasive grains. This is because when a polishing agent containing abrasive grains is used, it is difficult to make the polishing rate for the oxide pattern 50 sufficiently slower than the polishing rate for the conductive layer 44. As such an abrasive, for example, an abrasive made by Hitachi Chemical Co., Ltd. (“HS-C” series) or the like can be used.

  FIG. 12A shows a stage in the middle of polishing the conductive layer 44. Since the polishing rate for the oxide pattern 50 is sufficiently slower than the polishing rate for the conductive layer 44, the polishing of the conductive layer 44 proceeds relatively quickly in the region where the oxide pattern 50 does not exist. On the other hand, in the region where the oxide pattern 50 exists, the oxide pattern 50 is polished at a polishing rate slower than the polishing rate for the conductive layer 44.

  FIG. 12B shows a state where the conductive layer 44 is removed and the surface of the barrier metal film 38 is exposed in a region excluding the region where the oxide pattern 50 is formed and the inside of the opening 34. In the region where the oxide pattern 50 was formed, the polishing rate was relatively slow, so that the conductive layer 44 remains.

  In this manner, the conductive layer 44 is polished until the surface of the barrier metal film 38 is exposed in a region excluding the region where the oxide pattern 50 has been formed and the inside of the opening 34. As a result, the conductive layer 44 remains in the region where the oxide pattern 50 has been formed. Also, the conductive layer 44 remains in the opening 34. Since the oxide pattern 50 is also formed around the opening 34, the conductive layer 44 remaining around the opening 34 is kept connected to the conductive layer 44 in the opening 34. A conductive pattern (conductive pattern) 44a is formed by the conductive layer 44 remaining in this manner. The oxide pattern 50 is removed when the conductive layer 44 is polished. As described above, the energization pattern 44a functions as a seed layer when the plating film 62 is formed by electroplating. The thickness of the energization pattern 44a is, for example, about 800 nm. The width w (see FIG. 13A) of the energization pattern 44a located between the portions 13 where the through vias are formed is, for example, about 100 nm.

  If the oxide pattern 50 remains on the conductive layer 44, the oxide pattern 50 may be removed by etching.

  As described above with reference to FIGS. 2 to 4, the energization pattern 44 a is formed in the peripheral portion of the semiconductor wafer 10, the scribe line region 52, and the chip region 11.

  For this reason, the peripheral portion of the semiconductor wafer 10 and the portion 13 where the through via is formed are electrically connected by the energization pattern 44a.

  FIG. 16 is a schematic view showing an electroplating apparatus.

  As shown in FIG. 16, a clamp (wafer clamp) 56 that supports the semiconductor wafer 10 is provided below the power feeding / rotor unit 54 that rotates while feeding power.

  The semiconductor wafer 10 is supported by a clamp 56 face down. That is, when the semiconductor wafer 10 is supported by the clamp 56, the side of the semiconductor wafer 10 on which the conductive layer 44 is formed is set to the lower side.

  A plating tank 58 for storing a plating bath is disposed below the power feeding / rotor unit 54. In the plating tank 58, an electrode (not shown) connected to a positive terminal (not shown) of a power source for electroplating (not shown) is disposed.

  FIG. 17 is a diagram showing a part of the electroplating apparatus. FIG. 17 is an enlarged view of a portion surrounded by a circle in FIG.

  As shown in FIG. 17, a power supply pin (contact pin) 58 is provided inside the clamp 56. The contact pins 58 are for supplying power to the seed layer on the semiconductor wafer 10 side when the plating film 62 is formed by electroplating. The contact pin 58 is electrically connected to, for example, a negative terminal (not shown) of a power source (not shown) for electroplating.

  The contact pin 58 and the clamp 56 are insulated by an insulating member 60.

  The contact pins 58 are connected to a current-carrying pattern (conductive pattern, seed layer, conductive layer) 44 a at the peripheral edge of the semiconductor wafer 10. Since the peripheral portion of the semiconductor wafer 10 and the portion 13 where the through via is formed are electrically connected by the energization pattern 44a, the conductor pattern 44a and the contact pin 58 in the region 13 where the through via is formed. Can be energized.

  Next, the surface of the semiconductor wafer 10 on which the conductor pattern 44a is formed is immersed in a plating solution in the plating tank 58, and a voltage is applied to the energization pattern 44a of the semiconductor wafer 10 through the contact pins 58. While performing electroplating. A current flows through the energization pattern 44a functioning as a seed layer, Cu ions supplied from the plating solution are reduced in the conductive pattern 44a, and Cu is deposited on the conductive pattern 44a. As a result, a Cu plating film (conductive layer) 62 is formed on the conductive pattern 44a. The thickness of the plating film 62 is, for example, about 1 μm. Thus, the conductive layer 62 is embedded in the opening 34.

  Note that the plating film 62 is hardly formed on the barrier metal film 38 because the electric resistance of the barrier metal film 38 is sufficiently larger than the electric resistance of the energization pattern 44a.

  Thus, according to the present embodiment, the plating film 62 is formed on the energization pattern 44a, while the plating film 62 is hardly formed in the region where the conductive layer pattern 44a is not formed.

  According to the present embodiment, the plating film 62 is not formed on the entire surface of the semiconductor wafer 10, but the plating film 62 is selectively formed on the conductive pattern 44a, so that electroplating can be performed efficiently. The thick plating film 62 can be formed in a relatively short time.

  Further, according to the present embodiment, since the thick plating film 62 is not formed on the entire surface, it is possible to prevent a large stress from occurring. For this reason, it is possible to prevent the occurrence of cracks and the like, to prevent the warpage of the semiconductor wafer 10 and the like, and to improve the reliability.

  Next, the plating film 62, the conductive pattern 44a, and the barrier metal film 38 in a region excluding the inside of the opening 34 are polished and removed by, for example, CMP. At this time, the SiC film 26 is used as a polishing stopper.

  According to this embodiment, since the thick plating film 62 is not formed on the entire surface of the semiconductor wafer 10, the plating film 62 can be polished with a relatively high throughput.

  Thus, the via 64 formed by the conductive layer (conductive pattern) 44a and the plating film 62 is buried in the opening 34 (see FIG. 13B).

  Next, an interlayer insulating film 66 of, eg, a silicon oxide film is formed on the entire surface by, eg, CVD.

  Next, a trench 68 for embedding the relay wiring 70a and the wiring 70b is formed in the interlayer insulating film 66 by using a photolithography technique (see FIG. 14A). The relay wiring 70a is for connecting the through via 64 to the outside, and is formed in the region 4 where the through via is formed. For example, the wiring 70a is formed above the transistor in the region 2 where the transistor is formed.

  Next, a barrier metal film (not shown) is formed by sputtering, for example.

  Next, for example, a Cu film is formed by, for example, electroplating.

  Next, the Cu film and the barrier metal film are polished by CMP, for example, until the surface of the interlayer insulating film 66 is exposed. As a result, the Cu relay wiring 70 a and the Cu wiring 70 b are embedded in the groove 68.

  Next, an interlayer insulating film 72 is formed on the entire surface by, eg, CVD (see FIG. 13B).

  Next, an interlayer insulating film 74 is formed on the entire surface by, eg, CVD.

  Next, a contact hole 76 reaching the relay wiring 70 a is formed in the interlayer insulating film 72 using a photolithography technique, and a groove 78 connected to the contact hole 76 is formed in the interlayer insulating film 74.

  Next, a barrier metal film (not shown) is formed by sputtering, for example.

  Next, for example, a Cu film is formed by, for example, electroplating.

  Next, the Cu film and the barrier metal film are polished by CMP, for example, until the surface of the interlayer insulating film 74 is exposed. As a result, the Cu conductor plug 80 is embedded in the contact hole 76, and the Cu relay wiring 82 a is embedded in the groove 78.

  In the region 2 where the transistor is formed, a wiring 82b and a conductor plug (not shown) are similarly formed above the transistor 18.

  Next, an interlayer insulating film 84 is formed on the entire surface by, eg, CVD.

  Next, an interlayer insulating film 86 is formed on the entire surface by, eg, CVD.

  Next, a contact hole 88 reaching the relay wiring 82 a is formed in the interlayer insulating film 84 using a photolithography technique, and a groove 90 connected to the contact hole 88 is formed in the interlayer insulating film 86.

  Next, a barrier metal film (not shown) is formed by sputtering, for example.

  Next, for example, a Cu film is formed by, for example, electroplating.

  Next, the Cu film and the barrier metal film are polished by CMP, for example, until the surface of the interlayer insulating film 86 is exposed. As a result, the Cu conductor plug 92 is embedded in the contact hole 88 and the Cu relay wiring 94 a is embedded in the groove 90.

  In the region 2 where the transistor is formed, a wiring 94b and a conductor plug (not shown) are similarly formed above the transistor 18.

  Next, a SiOC protective film 96 having a thickness of, eg, about 180 nm is formed on the entire surface by, eg, CVD (see FIG. 15A).

  Next, an opening 98 reaching the relay wiring 94 a is formed in the protective film 96 using a photolithography technique.

  Next, for example, an aluminum (Al) conductive film is formed by sputtering, for example.

  Next, the conductive film is patterned using a photolithography technique. Thereby, the electrode pad 100 of the conductive film connected to the relay wiring 94a in the opening 98 is formed.

  Thus, the multilayer wiring structure 102 is formed above the semiconductor substrate 10.

  Next, the upper surface side of the semiconductor substrate 10 on which the multilayer wiring structure 102 is formed is supported by the support body 104 (see FIG. 1E), and the lower surface side (back surface side) of the semiconductor substrate 10 is ground. As a result, a via 64 penetrating the semiconductor substrate 10 is obtained (see FIG. 15B).

  Thereafter, dicing is performed along the scribe line region 52, and the separated semiconductor chip 11 is obtained.

  Thus, the semiconductor device according to the present embodiment is manufactured.

  Thus, according to this embodiment, the oxide pattern 50 whose polishing rate is slower than that of the conductive layer 44 is formed on the surface layer portion of the conductive layer 44, and then the conductive layer 44 is polished. Therefore, the conductive pattern 44a formed by the conductive layer 44 can be formed in the region where the oxide pattern 50 has been formed. Then, using the conductive pattern 44a formed in this way as a seed layer, the conductive layer 62 can be formed on the conductive layer 44 in the opening 34 by electroplating. Therefore, the conductive layer 62 can be formed in the opening 34 in a relatively short time by electroplating. Further, since the thick conductive layer 62 is not formed on the entire surface of the semiconductor substrate 10, it is possible to prevent a large stress from occurring. For this reason, peeling of the plating film or the like, warping of the semiconductor wafer 10, cracking, or the like can be prevented, and a highly reliable semiconductor device can be provided. In addition, when polishing the conductive layer 62 in a region other than the inside of the opening 34, the thick conductive layer formed on the entire surface is not polished, and thus the conductive layer 62 can be polished with a relatively high throughput. Therefore, it is possible to provide a semiconductor device at low cost without reducing reliability and throughput.

(Modification)
Next, a method for manufacturing a semiconductor device according to a modification of the present embodiment will be described with reference to FIGS.

  FIG. 18 is a plan view showing a modified example of the layout of the energization pattern formed on the semiconductor wafer.

  As shown in FIG. 18, in this modification, not only the energization patterns (conductive patterns) 44b of the chip regions 11 adjacent in the vertical direction of the paper are connected to each other, but also of the chip regions 11 adjacent in the horizontal direction of the paper. The energization patterns 44b are also connected to each other.

  In this way, the energization pattern 44a may be formed so as to extend in various directions.

[Second Embodiment]
A method for fabricating a semiconductor device according to the second embodiment will be described with reference to FIGS. FIG. 19 is a process sectional view showing the method for manufacturing the semiconductor device according to the present embodiment. The same components as those in the semiconductor device manufacturing method according to the first embodiment shown in FIGS. 1 to 18 are denoted by the same reference numerals, and description thereof is omitted or simplified.

  In the semiconductor device manufacturing method according to the present embodiment, the conductive layer 44 is formed only by the Cu film 40a formed by the PVD method.

  First, from the step of forming the transistor 18 on the semiconductor substrate 10 to the step of forming the barrier metal film 38, the semiconductor device according to the first embodiment described above with reference to FIGS. 5A to 8B is manufactured. Since it is the same as the method, the description is omitted (see FIG. 19A).

  Next, a Cu film (seed layer) 40a having a thickness of, for example, about 600 nm to 1 μm is formed on the entire surface by, eg, PVD (see FIG. 19B). Thus, the Cu conductive layer 44 having a thickness of about 600 nm to 1 μm is formed by the Cu film 40a.

  The subsequent method for manufacturing the semiconductor device is the same as the method for manufacturing the semiconductor device according to the first embodiment described above with reference to FIGS.

  Thus, the semiconductor device according to the present embodiment is manufactured (see FIG. 15B).

  Thus, the conductive layer 44 may be formed only by the Cu film 40a formed by the PVD method. Even when the conductive layer 44 is formed only by the Cu film 40 formed by the PVD method, it is possible to form the energization pattern 44a with a certain thickness.

  However, when the conductive layer 44 is formed only by the Cu film 40a formed by the PVD method, it is preferable to set the thickness of the Cu film 40a formed by the PVD method to be thick.

[Third Embodiment]
A semiconductor device manufacturing method according to the third embodiment will be described with reference to FIGS. FIG. 20 is a process cross-sectional view illustrating the semiconductor device manufacturing method according to the present embodiment. The same components as those of the semiconductor device manufacturing method according to the first or second embodiment shown in FIGS. 1 to 19 are denoted by the same reference numerals, and description thereof will be omitted or simplified.

  The manufacturing method of the semiconductor device according to the present embodiment oxidizes the surface layer portion of the conductive layer 44 by performing a process using dilute sulfuric acid vapor.

  First, from the step of forming the transistor 18 on the semiconductor substrate 10 to the step of patterning the photoresist film 46, the semiconductor device according to the first embodiment described above with reference to FIGS. 5A to 10B is used. Since it is the same as that of a manufacturing method, description is abbreviate | omitted.

  Next, an oxide layer (oxide pattern) 50 is formed by oxidizing the surface layer portion of the conductive layer 44 using the photoresist film 46 as a mask and dilute sulfuric acid vapor (see FIG. 20). That is, the oxide layer 50 is formed by treatment (vapor treatment) using dilute sulfuric acid vapor.

  FIG. 20 conceptually shows a state where the dilute sulfuric acid vapor 106 is supplied.

  The treatment using the diluted sulfuric acid vapor 106 can be performed, for example, as follows.

  That is, first, the semiconductor substrate 10 on which the photoresist film 46 is formed is placed in the chamber of the vapor processing apparatus. As the vapor processing apparatus, for example, a liquid vaporization & gas heating apparatus (trade name: JetII) manufactured by OMEGA SEMICON ELECTRONICS CO., LTD. Can be used.

  Next, the surface layer portion of the conductive layer 44 exposed from the photoresist film 46 is oxidized by supplying dilute sulfuric acid vapor 106 into the chamber of the vapor processing apparatus. The processing time is, for example, about 20 to 60 seconds. The thickness of the oxide layer 50 is, for example, about 100 to 200 nm.

  Thus, the oxide pattern 50 is formed in the surface layer portion of the conductive layer 44 by the treatment using the diluted sulfuric acid vapor 106.

  After the oxide layer 50 having a desired thickness is formed, washing with water is performed.

  In addition, when it grinds immediately after formation of the oxide layer 50, or when the surface is a dry state, you may make it abbreviate | omit water washing.

  The subsequent method for manufacturing the semiconductor device is the same as the method for manufacturing the semiconductor device according to the first embodiment described above with reference to FIGS.

  Thus, the semiconductor device according to the present embodiment is manufactured (see FIG. 15B).

  In this manner, the oxide layer 15 may be formed by a treatment using dilute sulfuric acid vapor.

[Fourth Embodiment]
A semiconductor device manufacturing method according to the fourth embodiment will be described with reference to FIGS. FIG. 21 is a process sectional view showing the method for manufacturing the semiconductor device according to the present embodiment. The same components as those of the semiconductor device manufacturing method according to the first to third embodiments shown in FIGS. 1 to 20 are denoted by the same reference numerals, and description thereof will be omitted or simplified.

  The semiconductor device manufacturing method according to the present embodiment oxidizes the surface layer portion of the conductive layer 44 by performing a treatment using hydrogen functional water.

  First, from the step of forming the transistor 18 on the semiconductor substrate 10 to the step of patterning the photoresist film 46, the semiconductor device according to the first embodiment described above with reference to FIGS. 5A to 10B is used. Since it is the same as that of a manufacturing method, description is abbreviate | omitted.

  Next, an oxide layer (oxide pattern) 50 is formed by oxidizing the surface layer portion of the conductive layer 44 using hydrogen functional water (oxidant) 108 using the photoresist film 46 as a mask (FIG. 21). reference). Specifically, the hydrogen functional water 108 is applied to the entire surface and left for a certain period of time to oxidize the surface layer portion of the conductive layer 44. The functional hydrogen water is a liquid formed by dissolving hydrogen gas in pure water at a high concentration, that is, water in which hydrogen gas is dissolved at a high concentration. In other words, the hydrogen functional water is a chemical solution in which hydrogen gas is dissolved. The hydrogen functional water is also referred to as functional hydrogen water. The concentration of hydrogen in the hydrogen functional water used in the present embodiment is, for example, about 1 to 1.5 ppm. The thickness of the oxide layer 50 is, for example, about 100 to 200 nm.

Instead of using hydrogen functional water alone, or in combination of alkaline liquid such as KOH or NH 4 _OH. Specifically, the oxide layer 50 may be formed using a chemical solution formed by mixing hydrogen functional water and an alkaline liquid.

  Alternatively, the oxide layer 50 may be formed on the surface layer portion of the conductive layer 44 by immersing in hydrogen functional water to which ultrasonic waves are applied.

  Thus, the oxide pattern 50 is formed in the surface layer portion of the conductive layer 44 by the treatment using the hydrogen functional water 108.

  After the oxide layer 50 having a desired thickness is formed, washing with water is performed.

  In addition, when it grinds immediately after formation of the oxide layer 50, or when the surface is a dry state, you may make it abbreviate | omit water washing.

  The subsequent method for manufacturing the semiconductor device is the same as the method for manufacturing the semiconductor device according to the first embodiment described above with reference to FIGS.

  Thus, the semiconductor device according to the present embodiment is manufactured (see FIG. 15B).

  As described above, the oxide layer 15 may be formed by treatment using hydrogen functional water.

[Fifth Embodiment]
A semiconductor device manufacturing method according to the fifth embodiment will be described with reference to FIGS. FIG. 22 is a process cross-sectional view illustrating the semiconductor device manufacturing method according to the present embodiment. The same components as those in the method of manufacturing the semiconductor device according to the first to fourth embodiments shown in FIGS. 1 to 21 are denoted by the same reference numerals, and description thereof will be omitted or simplified.

  The semiconductor device manufacturing method according to the present embodiment oxidizes the surface layer portion of the conductive layer 44 by performing a treatment using ozone gas.

  First, from the step of forming the transistor 18 on the semiconductor substrate 10 to the step of patterning the photoresist film 46, the semiconductor device according to the first embodiment described above with reference to FIGS. 5A to 10B is used. Since it is the same as that of a manufacturing method, description is abbreviate | omitted.

  Next, an oxide layer (oxide pattern) 50 is formed by oxidizing the surface layer portion of the conductive layer 44 using ozone gas (oxidant) using the photoresist film 46 as a mask (see FIG. 22). Specifically, first, the semiconductor substrate 10 is placed in the chamber. Next, the surface layer portion of the conductive layer 44 is oxidized by irradiating ultraviolet rays while supplying ozone gas into the chamber. The processing time is about 60 seconds, for example. The thickness of the oxide layer 50 is, for example, about 100 to 200 nm.

  Thus, the oxide pattern 50 is formed on the surface layer portion of the conductive layer 44 by the treatment using ozone gas.

  The subsequent method for manufacturing the semiconductor device is the same as the method for manufacturing the semiconductor device according to the first embodiment described above with reference to FIGS.

  Thus, the semiconductor device according to the present embodiment is manufactured (see FIG. 15B).

  As described above, the oxide layer 15 may be formed by a treatment using ozone gas.

[Sixth Embodiment]
A method for fabricating a semiconductor device according to the sixth embodiment will be described with reference to FIGS. FIG. 23 is a process cross-sectional view illustrating the semiconductor device manufacturing method according to the present embodiment. The same components as those of the semiconductor device manufacturing method according to the first to fifth embodiments shown in FIGS. 1 to 22 are denoted by the same reference numerals, and description thereof will be omitted or simplified.

  The semiconductor device manufacturing method according to the present embodiment oxidizes the surface layer portion of the conductive layer 44 by performing treatment using ozone water 110.

  First, from the step of forming the transistor 18 on the semiconductor substrate 10 to the step of patterning the photoresist film 46, the semiconductor device according to the first embodiment described above with reference to FIGS. 5A to 10B is used. Since it is the same as the manufacturing method, description is abbreviate | omitted.

  Next, using the photoresist film 46 as a mask, the surface layer of the conductive layer 44 is oxidized using ozone water (oxidant) 110 to form an oxide layer (oxide pattern) 50 (see FIG. 23). ). Specifically, the surface layer portion of the conductive layer 44 is oxidized by applying ozone water 110. Ozone water is formed by dissolving ozone gas in pure water. The concentration of ozone gas in the ozone water used in the present embodiment is, for example, about 5 to 20 mg / liter. The processing time is, for example, about 10 to 30 seconds. The thickness of the oxide layer 50 is, for example, about 100 to 200 nm.

  Note that dilute hydrofluoric acid may be used in combination instead of ozone water alone. Specifically, the oxide layer 50 may be formed using a chemical solution formed by mixing dilute hydrofluoric acid with ozone water.

  Thus, the oxide pattern 50 is formed in the surface layer portion of the conductive layer 44 by the treatment using ozone water.

  The subsequent method for manufacturing the semiconductor device is the same as the method for manufacturing the semiconductor device according to the first embodiment described above with reference to FIGS.

  Thus, the semiconductor device according to the present embodiment is manufactured (see FIG. 15B).

  Thus, the oxide layer 15 may be formed by treatment using ozone water.

[Seventh Embodiment]
A method for fabricating a semiconductor device according to the seventh embodiment will be described with reference to FIGS. FIG. 24 is a process cross-sectional view illustrating the semiconductor device manufacturing method according to the present embodiment. The same components as those of the semiconductor device manufacturing method according to the first to sixth embodiments shown in FIGS. 1 to 23 are denoted by the same reference numerals, and description thereof will be omitted or simplified.

  The semiconductor device manufacturing method according to the present embodiment oxidizes the surface layer portion of the conductive layer 44 by plasma treatment in an atmosphere containing oxygen.

  First, from the step of forming the transistor 18 on the semiconductor substrate 10 to the step of patterning the photoresist film 46, the semiconductor device according to the first embodiment described above with reference to FIGS. 5A to 10B is used. Since it is the same as that of a manufacturing method, description is abbreviate | omitted.

  Next, an oxide layer (oxide pattern) 50 is formed by oxidizing the surface layer portion of the conductive layer 44 by plasma treatment in an atmosphere containing oxygen using the photoresist film 46 as a mask (see FIG. 24). ). Specifically, first, the semiconductor substrate 10 is placed in a chamber. Next, oxygen gas is introduced into the chamber and plasma is irradiated to oxidize the surface layer portion of the conductive layer 44. The pressure in the chamber is, for example, about 100 mT. The applied high frequency power is, for example, about 500 W. The flow rate of oxygen gas is, for example, about 500 sccm. The substrate temperature is about 20 ° C., for example. The processing time is about 60 seconds, for example. The thickness of the oxide layer 50 to be formed is, for example, about 100 to 200 nm.

  Thus, the oxide pattern 50 is formed on the surface layer portion of the conductive layer 44 by plasma treatment in an atmosphere containing oxygen.

  The subsequent method for manufacturing the semiconductor device is the same as the method for manufacturing the semiconductor device according to the first embodiment described above with reference to FIGS.

  Thus, the semiconductor device according to the present embodiment is manufactured (see FIG. 15B).

  As described above, the oxide layer 15 may be formed by plasma treatment in an atmosphere containing oxygen.

[Modified Embodiment]
The present invention is not limited to the above embodiment, and various modifications are possible.

  For example, in the above-described embodiment, the case where the photoresist 46 in which the opening 48 is formed is used as a mask to perform the application of the oxidizing agent, but the present invention is not limited to this. For example, the oxidizing agent may be supplied to the region where the oxide pattern 50 is to be formed by spraying the oxidizing agent. For example, the oxidizing agent may be supplied to the region where the oxide pattern 50 is to be formed by spraying using a spray or the like. Moreover, you may make it supply an oxidizing agent to the area | region which should form the oxide pattern 50 by the printing method. For example, by using a mechanism similar to that of an ink jet printer, the oxidizing agent can be supplied by a printing method. In these cases, since the oxidizing agent can be selectively supplied to the region where the oxide pattern 50 is to be formed without using the mask of the photoresist film 46, the photoresist film 46 need not be formed.

  Moreover, the oxidizing agent for oxidizing the surface layer part of the conductive layer 44 is not limited to the above, and various oxidizing agents can be used as appropriate.

  In the above embodiment, the case where the Cu seed layer 40 is formed by the PVD method has been described as an example. However, the seed layer 40 is not limited to the Cu film. For example, a Cu alloy seed layer 40 may be formed.

  In the above embodiment, the case where the Cu plating film 42 is formed by electroplating has been described as an example. However, the present invention is not limited to this. For example, the Cu alloy plating film 42 may be formed by electroplating.

  In the above embodiment, the case where the Cu plating film 62 is formed by electroplating has been described as an example. However, the present invention is not limited to this. For example, the Cu alloy plating film 62 may be formed by electroplating.

  In the third to seventh embodiments, the conductive layer 44 is formed by the Cu film 40 formed by the PVD method and the plating film 42 formed by the electroplating method. However, the conductive layer 44 is conductive only by the Cu film 40a formed by the PVD method. Layer 44 may be formed. In this case, it is preferable to form a thick Cu film 40a formed by the PVD method.

  Moreover, in the said embodiment, although the material containing Cu was used as a material of the seed layer 40, the plating film 42, and the plating film 62, it is not limited to this. As the material of the seed layer 40, the plating film 42, and the plating film 62, for example, a material containing aluminum, a material containing tungsten, or a material containing silver may be used.

  Regarding the above embodiment, the following additional notes are disclosed.

(Appendix 1)
Forming a first conductive layer on one main surface of the semiconductor substrate;
Oxidizing the surface layer portion of the first conductive layer to form an oxide pattern;
Forming the conductive pattern of the first conductive layer in a region where the oxide pattern was present by polishing the first conductive layer at a polishing rate faster than the polishing rate for the oxide pattern. A method for manufacturing a semiconductor device, comprising:

(Appendix 2)
In the method for manufacturing a semiconductor device according to attachment 1,
Prior to the step of forming the first conductive layer, the method further includes a step of forming an opening on the one main surface side of the semiconductor substrate,
In the step of forming the first conductive layer, the first conductive layer is also formed in the opening,
In the step of forming the oxide pattern, the oxide pattern is also formed in the surface layer portion of the first conductive layer around the opening,
In the step of forming the conductive pattern, the conductive pattern is also formed around the opening,
After the step of forming the conductive pattern, a step of forming a second conductive layer on the first conductive layer in the opening by electroplating, and the second of the region excluding the inside of the opening. And further forming a via including the first conductive layer and the second conductive layer by polishing and removing the conductive layer and the first conductive layer. A method for manufacturing a semiconductor device, comprising: .

(Appendix 3)
In the method for manufacturing a semiconductor device according to attachment 2,
In the step of forming the oxide pattern, the oxide pattern reaching the peripheral edge of the semiconductor substrate is formed,
In the step of forming the conductive pattern, the conductive pattern reaching the peripheral edge of the semiconductor substrate is formed,
In the step of forming the second conductive layer, a contact pin electrically connected to a power source for electroplating is connected to the conductive pattern on the peripheral portion of the semiconductor substrate. Method.

(Appendix 4)
In the method for manufacturing a semiconductor device according to attachment 2 or 3,
After the step of forming the via, the method further comprises the step of exposing the lower end of the via by grinding the other main surface side of the semiconductor substrate.

(Appendix 5)
In the method for manufacturing a semiconductor device according to any one of appendices 2 to 4,
After the step of forming the opening, and before the step of forming the first conductive layer, further comprising a step of forming a barrier metal film on the semiconductor substrate and in the opening,
In the step of forming the conductive pattern, the first conductive layer is polished until the surface of the barrier metal film is exposed,
In the step of forming the via, the barrier film in a region excluding the inside of the opening is further polished and removed.

(Appendix 6)
In the method for manufacturing a semiconductor device according to attachment 5,
A method of manufacturing a semiconductor device, further comprising a step of forming an insulating film on the semiconductor substrate and in the opening after the step of forming the opening and before the step of forming the barrier metal film. .

(Appendix 7)
In the method for manufacturing a semiconductor device according to any one of appendices 1 to 6,
The method for manufacturing a semiconductor device, wherein the first conductive layer contains Cu.

(Appendix 8)
In the method for manufacturing a semiconductor device according to any one of appendices 2 to 6,
The method for manufacturing a semiconductor device, wherein the second conductive layer contains Cu.

(Appendix 9)
In the method for manufacturing a semiconductor device according to any one of appendices 1 to 8,
In the step of forming the oxide pattern, a treatment using dilute sulfuric acid, a treatment using dilute sulfuric acid vapor, a treatment using water in which hydrogen gas is dissolved, a treatment using ozone gas, and a treatment using ozone water. Alternatively, the surface layer portion of the first conductive layer is oxidized by plasma treatment in an atmosphere containing oxygen. A method for manufacturing a semiconductor device, comprising:

(Appendix 10)
In the method for manufacturing a semiconductor device according to any one of appendices 1 to 9,
The step of forming the oxide pattern includes a step of forming a photoresist film on the first conductive layer, a step of forming an opening exposing the first conductive layer in the photoresist film, A method of manufacturing a semiconductor device, comprising: a step of oxidizing the surface layer portion of the first conductive layer using a photoresist film as a mask; and a step of removing the photoresist film.

(Appendix 11)
In the method for manufacturing a semiconductor device according to any one of appendices 1 to 10,
The step of forming the first conductive layer includes a step of forming a first conductive film by physical vapor deposition and a step of forming a second conductive film by electroplating. A method for manufacturing a semiconductor device.

(Appendix 12)
In the method for manufacturing a semiconductor device according to any one of appendices 1 to 10,
In the step of forming the first conductive layer, the first conductive layer is formed by physical vapor deposition.

2 ... A region where a transistor is formed 4 ... A region where a through via is formed 6 ... A region where a conductive pattern is formed 8 ... A peripheral region 10 of a semiconductor wafer ... A semiconductor substrate, a semiconductor wafer 11 ... A semiconductor chip 12 ... Element isolation region 13 ... Location where via is formed 14 ... Gate electrode 16 ... Source / drain region 18 ... Transistor 20 ... Interlayer insulating film 22 ... Contact hole 24 ... Conductor plug 26 ... SiC film 28 ... Interlayer insulating film 30 ... Photoresist Film 32 ... Opening 34 ... Opening 36 ... Insulating film 38 ... Barrier metal film 40 ... Cu film, seed layer 42 ... Plating film, Cu film 44 ... Conductive layer 44a ... Conductive pattern 46 ... Photoresist film 48 ... Opening Portion 49 ... Oxidant, dilute sulfuric acid 50 ... Oxide, oxide layer, oxide pattern 52 ... Scribe line region 54 ... Power feeding / rotor unit 6 ... Clamp 58 ... Plating tank 60 ... Insulating member 62 ... Plating film, conductive layer 64 ... Via, through via, through electrode 66 ... Interlayer insulating film 68 ... Opening 70a ... Relay wiring 70b ... Wiring 72 ... Interlayer insulating film 74 ... Interlayer insulating film 76 ... contact hole 78 ... groove 80 ... conductor plug 82a ... relay wiring 82b ... wiring 84 ... interlayer insulating film 86 ... interlayer insulating film 88 ... contact hole 90 ... groove 92 ... conductor plug 94a ... relay wiring 94b ... wiring 96 ... Protective film 98 ... Opening part 100 ... Electrode pad 102 ... Multilayer wiring structure 104 ... Support 106 ... Dilute sulfuric acid vapor 108 ... Hydrogen functional water 110 ... Ozone water 202 ... Transistor formation region 204 ... Through via is formed Region 208 ... region 210 around the periphery of the semiconductor wafer ... silicon substrate, silicon wafer 211 ... plating solution 212 ... element isolation region 14 ... Gate electrode 216 ... Source / drain region 218 ... Transistor 220 ... Interlayer insulating film 222 ... Contact hole 224 ... Conductor plug 230 ... Photoresist film 232 ... Opening 234 ... Opening 236 ... Insulating film 238 ... Barrier metal film 240 ... Seed layer 242 ... plated film 264 ... via, through via 302 ... multilayer wiring structure

Claims (6)

Forming a first conductive layer on one main surface of the semiconductor substrate;
Oxidizing the surface layer portion of the first conductive layer to form an oxide pattern;
Forming the conductive pattern of the first conductive layer in a region where the oxide pattern was present by polishing the first conductive layer at a polishing rate faster than the polishing rate for the oxide pattern. A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 1,
Prior to the step of forming the first conductive layer, the method further includes a step of forming an opening on the one main surface side of the semiconductor substrate,
In the step of forming the first conductive layer, the first conductive layer is also formed in the opening,
In the step of forming the oxide pattern, the oxide pattern is also formed on a surface layer portion of the first conductive layer around the opening,
In the step of forming the conductive pattern, the conductive pattern is also formed around the opening,
After the step of forming the conductive pattern, a step of forming a second conductive layer on the first conductive layer in the opening by electroplating, and the second of the region excluding the inside of the opening. And further forming a via including the first conductive layer and the second conductive layer by polishing and removing the conductive layer and the first conductive layer. A method for manufacturing a semiconductor device, comprising: . The method of manufacturing a semiconductor device according to claim 2.
In the step of forming the oxide pattern, the oxide pattern reaching the peripheral edge of the semiconductor substrate is formed,
In the step of forming the conductive pattern, the conductive pattern reaching the peripheral edge of the semiconductor substrate is formed,
In the step of forming the second conductive layer, a contact pin electrically connected to a power source for electroplating is connected to the conductive pattern on the peripheral portion of the semiconductor substrate. Method. In the manufacturing method of the semiconductor device according to any one of claims 1 to 3,
The method for manufacturing a semiconductor device, wherein the first conductive layer contains Cu. In the manufacturing method of the semiconductor device of Claim 2 or 3,
The method for manufacturing a semiconductor device, wherein the second conductive layer contains Cu. In the manufacturing method of the semiconductor device according to any one of claims 1 to 5,
In the step of forming the oxide pattern, a treatment using dilute sulfuric acid, a treatment using dilute sulfuric acid vapor, a treatment using water in which hydrogen gas is dissolved, a treatment using ozone gas, and a treatment using ozone water. Alternatively, the surface layer portion of the first conductive layer is oxidized by plasma treatment in an atmosphere containing oxygen. A method for manufacturing a semiconductor device, comprising:

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