JP2013031082A - V-f conversion circuit and current detection device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid the situation where an integrating capacitor constituting an integration circuit is saturated to disable the integration circuit from functioning normally.SOLUTION: A third switch SW3 is connected between one terminal of an integrating capacitor C1 of an integration circuit 7 and a power line 6 fed with a ground potential. A first comparator CP1 compares a voltage Vo with a maximum specified voltage Vth2. A second comparator CP2 is configured to switch between a normal state to compare the voltage Vo with a minimum specified voltage Vth1 and a saturation detection state to compare the voltage Vo with a saturation detection voltage Vth3. Control logic 13 switches the second comparator CP2 to the normal state while the integration circuit 7 is in a discharged state and to the saturation detection state while it is in a charged state. The control logic 13 turns on the third switch SW3 to electrically discharge the integrating capacitor C1 if a comparison signal Sc2 indicates that the voltage Vo has reached the voltage Vth3.

Description

  The present invention relates to a VF conversion circuit that outputs an output signal having a frequency corresponding to an input voltage, and a current detection device including the VF conversion circuit.

  As a VF conversion circuit that performs voltage-frequency conversion (VF conversion) for converting an input voltage (input voltage) into a frequency, an integration circuit and a control circuit that controls the operation of the integration circuit are provided. There is a configuration. The integrating circuit includes an operational amplifier, an integrating capacitor connected between the inverting input terminal and the output terminal of the operational amplifier, and an integrating resistor that limits a current (charge / discharge current) flowing through the integrating capacitor.

  The integration circuit having the above configuration is an operation state in which the intermediate voltage of the input voltage is applied to the non-inverting input terminal of the operational amplifier, and the output voltage is lowered when the high potential side of the input voltage is applied to the inverting input terminal through the integrating resistor. (Discharge state). In addition, the integration circuit is an operating state (charged state) in which the output voltage rises when an intermediate potential is applied to the non-inverting input terminal of the operational amplifier and the low potential side of the input voltage is applied to the inverting input terminal through the integrating resistor. It becomes. The control circuit controls the operation state of the integration circuit so that a triangular wave voltage having a frequency corresponding to the input voltage is output from the output terminal of the operational amplifier. In such an integration circuit, when the integration capacitor is saturated, switching from the charged state to the discharged state cannot be performed. For this reason, the charge of the integrating capacitor is discharged (reset) when the circuit is not operating (see, for example, Patent Document 1).

JP 2006-184035 A

  However, in the above-described prior art, a case where the integrating capacitor is saturated during the operation of the circuit is not assumed. For this reason, in the VF conversion circuit having the above configuration, even when the charge of the integration capacitor is discharged when the circuit is not operating, if the integration capacitor is saturated again during the operation of the circuit, the integration circuit is normally operated. As a result, the operation as the VF conversion circuit (VF conversion operation) may not be performed normally.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to avoid a situation in which the integration circuit does not normally operate when the integration capacitor constituting the integration circuit is saturated. An object of the present invention is to provide an F conversion circuit and a current detection device including the VF conversion circuit.

  According to the first aspect of the present invention, an integration circuit and a control circuit for controlling the operation of the integration circuit are provided, and an output signal having a frequency corresponding to the input voltage is output (voltage-frequency conversion operation is performed). ) VF conversion circuit. The integrating circuit includes an operational amplifier, an integrating resistor, an integrating capacitor, charge discharging means, two input resistors, a first switch, and a second switch. The two input resistors are connected in series between two input terminals to which an input voltage is applied. The interconnection point of the two input resistors is connected to the non-inverting input terminal of the operational amplifier. That is, the non-inverting input terminal of the operational amplifier is given an intermediate potential obtained by dividing the input voltage by the two input resistors. Accordingly, the voltage at the non-inverting input terminal of the operational amplifier is lower than the high potential side potential of the input voltage and higher than the low potential side potential of the input voltage.

  One terminal of an integrating resistor is connected to the inverting input terminal of the operational amplifier. An integrating capacitor is connected between the inverting input terminal and the output terminal of the operational amplifier. The first switch is connected between the input terminal on the high potential side (given the high potential side potential of the input voltage) of the two input terminals and the other terminal of the integrating resistor. The second switch is connected between the input terminal on the low potential side (given the low potential side potential of the input voltage) of the two input terminals and the other terminal of the integrating resistor.

  In the integrating circuit, basically, a charging state in which the first switch is turned off and the second switch is turned on and a discharging state in which the first switch is turned on and the second switch is turned off are alternately repeated. When the integrating circuit is set to the charged state, the voltage at the other terminal of the integrating resistor becomes equal to the low potential side potential of the input voltage. When the operational amplifier is operating normally, the voltage at one terminal of the integrating resistor becomes equal to the intermediate potential due to an imaginary short. Therefore, when the integrating circuit is set to the charged state, a current (charging current) flows from the integrating capacitor side to the integrating resistor side. As a result, the voltage of the terminal connected to the output terminal side of the operational amplifier of the integrating capacitor, that is, the output voltage of the operational amplifier rises with a constant rate of change. The magnitude of the charging current is determined according to the voltage between the terminals of the integrating resistor (the difference voltage between the intermediate potential and the low potential of the input voltage). Therefore, the larger the input voltage, the larger the charging current and the greater the change rate of the output voltage. In addition, the smaller the input voltage, the smaller the charging current, and the smaller the rate of change of the output voltage.

  When the integration circuit is set to the discharge state, the voltage at the other terminal of the integration resistor becomes equal to the high potential side potential of the input voltage. Therefore, when the integration circuit is set to the discharge state, a current (discharge current) flows from the integration resistor side to the integration capacitor side. As a result, the output voltage of the operational amplifier decreases with a constant rate of change. The magnitude of the discharge current is determined according to the voltage between the terminals of the integrating resistor (the difference voltage between the high potential side potential and the intermediate potential of the input voltage). Therefore, as the input voltage increases, the discharge current increases and the rate of change of the output voltage also increases. Further, the smaller the input voltage, the smaller the discharge current, and the smaller the change rate of the output voltage. By alternately repeating such a charging state and a discharging state, a triangular wave voltage having a frequency corresponding to the magnitude of the input voltage is output from the output terminal of the operational amplifier.

  The control circuit includes comparison means, switch switching means, signal output means, and saturation release means. The comparison means compares the output voltage of the operational amplifier with the minimum value specified voltage, the maximum value specified voltage, or the saturation detection voltage. The minimum value regulation voltage is a voltage that regulates the minimum value (lower peak value) of the triangular wave. The maximum value regulation voltage is a voltage that regulates the maximum value (upper peak value) of the triangular wave. The saturation detection voltage is a voltage higher than the maximum specified voltage.

  The switch switching means controls the first switch and the second switch as follows according to the comparison result by the comparison means. That is, the switch control means turns off the first switch and turns on the second switch when the output voltage of the operational amplifier reaches the minimum prescribed voltage. As a result, the integrating circuit is set to the charged state. The switch control means turns on the first switch and turns off the second switch when the output voltage of the operational amplifier reaches the maximum value regulation voltage. As a result, the integrating circuit is set to a discharged state. By such control, the output voltage of the operational amplifier becomes a triangular wave voltage in which the upper peak value is the maximum value defining voltage and the lower peak value is the minimum value defining voltage. The signal output means outputs a signal corresponding to the triangular wave voltage output from the operational amplifier as an output signal. That is, the signal output means outputs an output signal having a frequency corresponding to the magnitude of the input voltage.

  Now, the present inventor generates an abnormality in which the integrating capacitor constituting the integrating circuit is saturated during the period in which the voltage-frequency conversion operation is performed with the above-described configuration, and the integrating circuit does not operate normally. Confirmed that there was a case. Specifically, the above abnormality occurs when the input offset voltage of the operational amplifier meets the following conditions. That is, the input offset voltage is larger than the voltage input to the operational amplifier (the difference voltage between the high potential side potential of the input voltage and the intermediate potential, or the difference voltage between the low potential side potential of the input voltage and the intermediate potential), and When the polarity of the input offset voltage is higher at the inverting input terminal voltage than at the non-inverting input terminal voltage, the above abnormality occurs.

  When an input offset voltage that meets the above conditions is generated, the voltage at the other terminal of the integrating resistor is turned on even if the first switch is turned on and the second switch is turned off in order to switch the integrating circuit to the discharge state. Is always smaller than the voltage at one terminal, which is higher due to the influence of the input offset voltage. Therefore, the integrating circuit is always in a charged state in which current flows from the integrating capacitor side to the integrating resistor side, and cannot be switched to the discharging state. By continuing the charging state in this way, the output voltage of the operational amplifier rises even if it exceeds the maximum specified voltage, and eventually the integrating capacitor is saturated, and the integrating circuit cannot operate normally.

  In this means, the occurrence of the abnormality is avoided as follows. That is, when the output voltage of the operational amplifier is higher than the maximum value specified voltage, there is a high possibility that the switching of the state of the integration circuit cannot be performed successfully due to the reasons described above. Therefore, when the output voltage reaches the saturation detection voltage set higher than the maximum value specified voltage, the saturation release means controls the charge discharge means to discharge the charge of the integrating capacitor. In this way, even when the integrating capacitor is about to be saturated or completely saturated, it is possible to return the integrating circuit to normal operation.

  According to the means described in claim 2, the comparison means includes a first comparator, a second comparator, and a comparison state switching means. The first comparator compares the output voltage of the operational amplifier and the maximum value defining voltage. The second comparator is configured to be switchable between a normal state in which the output voltage of the operational amplifier and the minimum value specified voltage are compared and a saturation detection state in which the output voltage of the operational amplifier and the saturation detection voltage are compared.

  During the period when the integration circuit is in a discharged state, the integration capacitor of the integration circuit does not saturate. Therefore, the comparison state switching means switches the second comparator to the normal state during the period in which the integration circuit is in the discharge state. On the other hand, there is a possibility that the integrating capacitor of the integrating circuit is saturated while the integrating circuit is in a charged state. Further, since the output voltage of the operational amplifier does not decrease during the same period, it is not necessary to compare the output voltage with the minimum value specified voltage. For this reason, the comparison state switching means switches the second comparator to the saturation detection state during a period in which the integration circuit is in the charged state. Thus, by switching the comparison target in the second comparator in accordance with the state of the integration circuit, the same operation and effect as the means of the first aspect can be obtained. Further, according to this means, since the comparison means is mainly composed of two comparators, the circuit scale can be kept relatively small.

  According to the means described in claim 3, the comparison means comprises a first comparator, a second comparator, and a third comparator. The first comparator compares the output voltage of the operational amplifier and the maximum value defining voltage. The second comparator compares the output voltage of the operational amplifier and the minimum value specified voltage. The third comparator compares the output voltage of the operational amplifier and the saturation detection voltage. According to such a configuration, the circuit scale is increased by the necessity of providing three comparators, but there is no need to switch the input of each comparator. As a result, the control contents of the control circuit can be simplified, and there can be obtained an effect that there is no possibility of errors in comparison results due to various delays at the time of switching the input.

  According to a fourth aspect of the present invention, the charge discharging means includes a charge connected between a terminal connected to the output terminal side of the operational amplifier among each terminal of the integrating capacitor and a ground terminal to which a ground potential is applied. It is a discharge switch. The saturation release unit discharges the charge of the integrating capacitor by turning on the charge discharge switch. According to such a configuration, the charge of the integrating capacitor can be reliably discharged (reset). For this reason, the output voltage of the operational amplifier is immediately reduced, so that an abnormality in which the integrating circuit becomes inoperable can be avoided more reliably.

  According to the means of Claim 5, it is a current detection apparatus provided with the VF converter circuit as described in any one of Claims 1-4, and shunt resistance. The shunt resistor is connected in series with the load between a pair of power supply lines for supplying a power supply voltage to the load. With such a configuration, a voltage corresponding to the current flowing through the load (load current) is generated between the terminals of the shunt resistor. The terminal voltage of the shunt resistor is input to the VF conversion circuit. Thereby, the VF conversion circuit outputs an output signal having a frequency corresponding to the load current. According to this means, the current flowing through the load is detected based on the frequency of the output signal.

  Now, when detecting the current flowing directly to the load from the value of the terminal voltage of the shunt resistor, a configuration is adopted in which the terminal voltage is A / D converted and the converted digital value is input to a microcomputer or the like. Often. In such a configuration, in order to be able to detect a relatively small current, it is necessary to increase the resolution of A / D conversion. However, increasing the resolution of A / D conversion leads to problems such as an increase in circuit scale and cost. On the other hand, according to this means, the terminal voltage of the shunt resistor is converted into the form of the frequency of the output signal by the operation of the VF conversion circuit. For example, it is relatively easy to detect the frequency of a signal by using a counter or the like. Therefore, according to the present means, it is possible to detect a relatively small value of current (for example, a microampere order minute current) such as a standby load current while suppressing an increase in circuit scale and cost. Can be realized.

The 1st Embodiment of this invention is shown, The schematic block diagram of a current detection apparatus Flow chart showing control contents of control logic Diagram showing each switch state and operational amplifier output voltage waveform A diagram showing a specific configuration example of the control logic It is a figure for demonstrating the conventional problem, and is a figure which shows the voltage waveform of each part, and the switching state of each switch FIG. 1 equivalent diagram showing a second embodiment of the present invention 4 equivalent diagram FIG. 1 equivalent view showing a third embodiment of the present invention 4 equivalent diagram

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS.
FIG. 1 shows a schematic configuration of the current detection device of the present embodiment. A current detection device 1 shown in FIG. 1 detects a consumption current (for example, a current in a range of 10 mA to 1100 mA) of a load 2 that operates by receiving power supply from a battery (not shown). The load 2 is, for example, a portable electronic device. An output signal So indicating the current consumption of the load 2 output from the current detection device 1 is given to an external control device (not shown). The external control device performs processing such as estimation of the remaining battery level using the output signal So.

  The current detection device 1 includes a shunt resistor 3 and a VF conversion circuit 4. The shunt resistor 3 is connected in series with the load 2 between a pair of power supply lines 5 and 6 for supplying a DC voltage VBAT (corresponding to a power supply voltage) from the battery to the load 2. The shunt resistor 3 has a very low resistance value (for example, 51 mΩ). The DC voltage VBAT has a voltage value of about + 4V to + 5V, for example. Each terminal of the shunt resistor 3 is connected to two input terminals P1 and P2 of the VF conversion circuit 4, respectively. A voltage proportional to the consumption current of the load 2 is generated between the terminals of the shunt resistor 3. That is, the input voltage Vi corresponding to the magnitude of the current consumption of the load 2 is applied between the input terminals P1 and P2 of the VF conversion circuit 4. The VF conversion circuit 4 outputs an output signal So having a frequency corresponding to the magnitude (level) of the input voltage Vi.

  The VF conversion circuit 4 includes an integration circuit 7 and a control circuit 8 that controls the operation of the integration circuit 7. The integrating circuit 7 outputs a triangular wave voltage Vo having a frequency corresponding to the magnitude of the input voltage Vi. The integrating circuit 7 includes an input switching unit 9 and an integrating amplifier 10. The input switching unit 9 includes input resistors R1 and R2, a first switch SW1, and a second switch SW2. The input resistors R1 and R2 are connected in series between the input terminals P1 and P2. The resistance values of the input resistors R1 and R2 are extremely higher than the resistance value of the shunt resistor 3, and are the same value (for example, 200 kΩ).

The voltage Vm at the interconnection point Nm between the input resistors R1 and R2 is applied to the integrating amplifier 10. The voltage Vm is obtained by dividing the input voltage Vi by the input resistors R1 and R2, and corresponds to an intermediate potential. In the present embodiment, the voltage Vm is expressed by the following equation (1), where Vih is the high potential side potential of the input voltage Vi and Vil is the low potential side potential.
Vm = Vih− (Vih−Vil) / 2 (1)
Thus, the voltage Vm is lower than the high potential side potential Vih of the input voltage Vi and is higher than the low potential side potential Vil of the input voltage Vi.

  One terminal of the first switch SW1 is connected to an input terminal P1 to which a high potential side potential Vih of the input voltage Vi is applied. One terminal of the second switch SW2 is connected to an input terminal P2 to which a low potential side potential Vil of the input voltage Vi is applied. The other terminal of the first switch SW1 and the other terminal of the second switch SW2 are commonly connected. The voltage Vn at the other commonly connected terminal is supplied to the integrating amplifier 10. On / off of the first switch SW1 and the second switch SW2 is switched by switching signals Ss1 and Ss2 given from the control circuit 8. Specifically, when the switching signals (Ss1, Ss2) are at the H level (the power supply voltage level of the control circuit 8, for example, +5 V), the corresponding switches (SW1, SW2) are turned on. When the switching signals (Ss1, Ss2) are at the L level (ground potential, for example, 0 V), the corresponding switches (SW1, SW2) are turned off.

  The integrating amplifier 10 includes an operational amplifier OP1, an integrating resistor R3, an integrating capacitor C1, and a third switch SW3. The operational amplifier OP1 operates by receiving the supply of the DC voltage VDD from the pair of power supply lines 11 and 6. The DC voltage VDD is generated by a power supply circuit (not shown) and is, for example, + 5V. The voltage Vm output from the input switching unit 9 is applied to the non-inverting input terminal of the operational amplifier OP1. The voltage Vn output from the input switching unit 9 is applied to the inverting input terminal of the operational amplifier OP1 through the integrating resistor R3. An integrating capacitor C1 is connected between the output terminal and the inverting input terminal of the operational amplifier OP1. A third switch SW3 is connected between the output terminal of the operational amplifier OP1 and the power supply line 6 (corresponding to a ground terminal). The third switch SW3 (corresponding to the charge discharging means and the charge discharging switch) is turned on / off by a switching signal Ss3 given from the control circuit 8. Specifically, the third switch SW3 is turned on when the switching signal Ss3 is at the H level, and is turned off when the switching signal Ss3 is at the L level.

  When one of the switching signals Ss1 and Ss2 is at H level, the other is at L level. Accordingly, when one of the first switch SW1 and the second switch SW2 is turned on, the other is turned off. The integrating amplifier 10 is charged when the first switch SW1 is turned off and the second switch SW2 is turned on. When the integrating amplifier 10 is set to the charged state, the voltage Vn at the terminal on the input switching unit 9 side of the integrating resistor R3 becomes equal to the low potential side potential Vil of the input voltage Vi. Further, the voltage at the terminal on the operational amplifier OP1 side of the integrating resistor R3 (= the voltage at the inverting input terminal of the operational amplifier OP1) becomes equal to the voltage Vm due to an imaginary short if the operational amplifier OP1 is operating normally.

  Therefore, when the integrating amplifier 10 is set to the charged state, a current (charging current) flows from the integrating capacitor C1 side toward the integrating resistor R3 side. As a result, the voltage at the terminal connected to the output terminal side of the operational amplifier OP1 of the integrating capacitor C1, that is, the output voltage Vo of the operational amplifier OP1 rises at a constant rate of change. The magnitude of the charging current is determined according to the voltage between the terminals of the integrating resistor R3 (= the difference voltage between the voltage Vm and the low potential side potential Vil) and the resistance value of the integrating resistor R3. Therefore, it can be said that the rate of change of the charging current and output voltage Vo and the input voltage Vi are in a proportional relationship.

  The integrating amplifier 10 enters a discharge state when the first switch SW1 is turned on and the second switch SW2 is turned off. When the integrating amplifier 10 is set to the discharging state, the voltage Vn at the terminal on the input switching unit 9 side of the integrating resistor R3 becomes equal to the high potential side potential Vih of the input voltage Vi. Note that the voltage at the terminal on the operational amplifier OP1 side of the integrating resistor R3 is equal to the voltage Vm as in the charged state. Therefore, when the integrating amplifier 10 is set to the discharging state, a current (discharge current) flows from the integrating resistor R3 side toward the integrating capacitor C1 side. As a result, the output voltage Vo of the operational amplifier OP1 decreases with a constant rate of change. The magnitude of the discharge current is determined according to the voltage between the terminals of the integrating resistor R3 (= the difference voltage between the high potential side potential Vih and the voltage Vm) and the resistance value of the integrating resistor R3. Therefore, it can be said that the rate of change of the discharge current and output voltage Vo is proportional to the input voltage Vi. In the integration circuit 7, the charging state and the discharging state are alternately repeated, so that a triangular wave output voltage Vo having a frequency corresponding to the magnitude of the input voltage Vi is output from the output terminal of the operational amplifier OP 1. .

  The control circuit 8 includes a comparison circuit 12 and a control logic 13. The comparison circuit 12 (corresponding to comparison means) includes voltage dividing resistors R4 to R7, a first comparator CP1, a second comparator CP2, and a fourth switch SW4. The voltage dividing resistors R 4 to R 7 are connected in series between the power supply lines 11 and 6. A voltage Vth1 obtained by dividing the DC voltage VDD by the series combined resistance of the voltage dividing resistors R4 to R6 and the voltage dividing resistor R7 is generated at the interconnection point N1 of the voltage dividing resistors R6 and R7. The interconnection point N1 is connected to the first switching terminal a of the fourth switch SW4. A voltage Vth2 obtained by dividing the DC voltage VDD by the series combined resistance of the voltage dividing resistors R4 and R5 and the series combined resistance of the voltage dividing resistors R6 and R7 is generated at the interconnection point N2 of the voltage dividing resistors R5 and R6. The interconnection point N2 is connected to the non-inverting input terminal of the first comparator CP1.

  A voltage Vth3 obtained by dividing the DC voltage VDD by the voltage dividing resistor R4 and the series combined resistance of the voltage dividing resistors R5 to R7 is generated at the interconnection point N3 of the voltage dividing resistors R4 and R5. The interconnection point N3 is connected to the second switching terminal b of the fourth switch SW4. The common terminal c of the fourth switch SW4 is connected to the inverting input terminal of the second comparator CP2. The inverting input terminal of the first comparator CP1 and the non-inverting input terminal of the second comparator CP2 are commonly connected. An output voltage Vo output from the operational amplifier OP1 of the integrating circuit 7 is applied to these commonly connected terminals. The first comparator CP1 and the second comparator CP2 operate by receiving the DC voltage VDD from the power supply lines 11 and 6.

The voltage Vth1 corresponds to a minimum value defining voltage that defines the minimum value (the peak value on the lower side of the triangular wave) of the triangular wave voltage Vo output from the integrating circuit 7. The voltage Vth2 corresponds to a maximum value defining voltage that defines the maximum value (peak value on the upper side of the triangular wave) of the triangular wave voltage Vo output from the integrating circuit 7. The voltage Vth3 corresponds to a saturation detection voltage for detecting an abnormality in which an integration capacitor C1 described later is saturated. The resistance values (voltage division ratios) of the voltage dividing resistors R4 to R7 are set so that the relationship between the voltage values of the voltages Vth1 to Vth3 satisfies the relationship represented by the following equation (2).
Vth1 <Vth2 <Vth3 <VDD (2)

  With the above configuration, the first comparator CP1 compares the output voltage Vo and the voltage Vth2 output from the integrating circuit 7, and outputs a comparison signal Sc1 indicating the comparison result to the control logic 13. On the other hand, the second comparator CP2 enters a normal state in which the output voltage Vo and the voltage Vth1 are compared in a state where the fourth switch SW4 is switched to the first switching terminal a side. The second comparator CP2 is in a saturation detection state in which the output voltage Vo and the voltage Vth3 are compared in a state where the fourth switch SW4 is switched to the second switching terminal b side.

  Switching of the fourth switch SW4 is controlled by a switching signal Ss4 output from the control logic 13. Specifically, the fourth switch SW4 is switched to the first switching terminal a side when the switching signal Ss4 is at the L level, and is switched to the second switching terminal b side when the switching signal Ss4 is at the H level. . As described above, the second comparator CP2 compares the output voltage Vo and the voltage Vth1, or compares the output voltage Vo and the voltage Vth3, and outputs the comparison signal Sc2 indicating the comparison result to the control logic 13.

  The control logic 13 controls the switches SW1 to SW4 based on the comparison signals Sc1 and Sc2 representing the comparison results of the first comparator CP1 and the second comparator CP2, and has a pulse having a frequency corresponding to the consumption current of the load 2. The output signal So is output. That is, in the present embodiment, the control logic 13 functions as a switch switching unit, a saturation release unit, a signal output unit, and a comparison state switching unit.

  FIG. 2 is a flowchart showing the contents of control by the control logic 13. FIG. 3 shows the switching state of the switches SW1 to SW4 and the waveform of the output voltage Vo of the operational amplifier OP1. Here, the state in which the switching signals Ss1 to Ss4 and the comparison signals Sc1, Sc2 are at the H level is indicated by “1”, and the state in which the switching signals Ss1 to Ss2 are at the L level is indicated by “0”. After being activated, the control logic 13 first sets the switching signal Ss3 = 1 (step A1). Then, after waiting for a predetermined time (“YES” in step A2), the switching signal Ss3 = 0 is set (step A3). As a result, the charge of the integrating capacitor C1 is discharged (reset).

  Subsequently, initial setting of the switches SW1, SW2, and SW4 is performed (step A4). Specifically, the switching signal Ss1 = 0, the switching signal Ss2 = 1, and the switching signal Ss4 = 0. As a result, the integrating amplifier 10 is set to the charged state, and the second comparator CP2 is set to the normal state (at time t0 in FIG. 3). In addition, regarding the initial setting of the switching signals Ss1 and Ss2 in step A4, the integration amplifier 10 may be changed to be set in a discharging state.

  In subsequent step A5, it is determined whether or not the switching signal Ss1 = 1 and the switching signal Ss2 = 0. When step A5 is executed for the first time after startup, the integrating amplifier 10 is set to the charged state. Therefore, “NO” is determined in the step A5, the process proceeds to the step A6, and is waited until the comparison signal Sc1 = 0. That is, the process waits until the output voltage Vo reaches the voltage Vth2. When the comparison signal Sc1 = 0 (“YES” in step A6), the process proceeds to step A7.

  In step A7, the switching signal Ss1 = 1, the switching signal Ss2 = 0, and the switching signal Ss4 = 1. As a result, the integrating amplifier 10 is set to the discharge state, and the second comparator CP2 is set to the saturation detection state (at time t1 or time t3 in FIG. 3). In subsequent step A8, it is determined whether or not the comparison signal Sc1 = 1. That is, it is determined whether or not the output voltage Vo is less than the voltage Vth2. As long as there is no abnormality (described later) due to the saturation of the integrating capacitor C1, the output voltage Vo decreases when the integrating amplifier 10 is set to the discharge state. Therefore, normally, the comparison signal Sc1 = 1 (“YES” in step A8), and the process proceeds to step S9.

  In step A9, the switching signal Ss4 = 0 is set, and the comparator CP2 is set to the normal state. After execution of step A9, the process returns to step A5. In this case, the integrating amplifier 10 is set to a discharge state. Therefore, “YES” is determined in the step A5, the process proceeds to the step A10, and is waited until the comparison signal Sc2 = 0. That is, the process waits until the output voltage Vo reaches the voltage Vth1. When the comparison signal Sc2 = 0 (“YES” in step A10), the process proceeds to step A11. In step A11, the switching signal Ss1 = 0 and the switching signal Ss2 = 1. As a result, the integrating amplifier 10 is set to the charged state (at time t2 in FIG. 3). After execution of step A11, the process returns to step A5.

  When the output voltage Vo of the operational amplifier OP1 reaches the voltage Vth1 under the control of the control logic 13, the integration amplifier 10 is set to the charged state. When the output voltage Vo of the operational amplifier OP1 reaches the voltage Vth2, the integral amplifier 10 is discharged. Is set. As a result of repeatedly executing such control, the output voltage Vo of the operational amplifier OP1 becomes a triangular wave voltage whose upper peak value is the voltage Vth2 and whose lower peak value is the voltage Vth1 (time in FIG. 3). (Refer to the period from t0 to t2.)

  In step A7, the control logic 13 sets the switching signals Ss1 and Ss2 so as to switch the integrating amplifier 10 from the charged state to the discharged state, and then the output voltage Vo does not fall below the voltage Vth2 (step A8). "NO"), the following control is executed. That is, if “NO” in the step A8, the process proceeds to a step A12. In step A12, it is determined whether or not the comparison signal Sc2 = 1. That is, it is determined whether or not the output voltage Vo exceeds the voltage Vth3. For example, when a slight delay occurs from when the switching signals Ss1 and Ss2 are changed to when the operating state of the integrating amplifier 10 is actually switched due to a transmission delay of various signals, the output voltage Vo Temporarily exceeds the voltage Vth2 (overshoot). When the output voltage Vo temporarily rises above the voltage Vth2 in this way, the output voltage Vo does not reach the voltage Vth3 (“NO” in step A12), and the output voltage Vo eventually falls below the voltage Vth2 ( “YES” in step A8). Thus, when there is no abnormality due to the saturation of the integrating capacitor C1, the normal control is returned.

  On the other hand, in the case of an abnormality due to the saturation of the integrating capacitor C1, the output voltage Vo continues to rise even if it exceeds the voltage Vth2, and eventually reaches the voltage Vth3 (time t4 in FIG. 3). Then, the comparison signal Sc2 = 1 (“YES” in step A12), and the process proceeds to step A13. In step A13, the switching signal Ss3 = 1. As a result, the terminal on the output terminal side of the operational amplifier OP1 of the integrating capacitor C1 becomes the ground potential, and the charge of the integrating capacitor C1 is discharged. This state continues until the comparison signal Sc1 = 0 (“YES” in step A14). That is, the integration capacitor C1 is discharged until the output voltage Vo decreases to reach the voltage Vth2 (period from time t4 to time t5 in FIG. 3). In subsequent step A15, the switching signal Ss3 = 0. That is, the discharging of the integrating capacitor C1 is stopped. After execution of step A15, the process proceeds to step A9, where the second comparator CP2 is set to the normal state (at time t5 in FIG. 3).

  FIG. 4 shows a specific configuration example of the control logic 13 that performs the above-described control. The control logic 13 shown in FIG. 4 includes an OR circuit 21, AND circuits 22 to 24, inverter circuits 25 and 26, RS flip-flops 27 and 28, and a switch circuit 29. The OR circuit 21 is a two-input type, and includes an inverting input terminal and a non-inverting input terminal. The AND circuits 22 and 23 are of a two-input type and have an inverting input terminal and a non-inverting input terminal. The AND circuit 24 is a two-input type and includes two non-inverting input terminals.

  The comparison signal Sc1 is input to the inverting input terminal of the OR circuit 21, the inverting input terminal of the AND circuit 22, the non-inverting input terminal of the AND circuit 23, the input terminal of the inverter circuit 26, and the reset terminal R of the flip-flop 27 through the input terminal 30. Is given. The comparison signal Sc2 is supplied to the common terminal c of the switch circuit 29 through the input terminal 31. The first switching terminal a of the switch circuit 29 is connected to the non-inverting input terminal of the OR circuit 21. The second switching terminal b of the switch circuit 29 is connected to one non-inverting input terminal of the AND circuit 24. The switch circuit 29 is switched by a switching signal Ss5 output from the inverter circuit 26. Specifically, the switch circuit 29 is switched to the first switching terminal a side when the switching signal Ss5 is L level, and is switched to the second switching terminal b side when the switching signal Ss4 is H level.

  The output terminal of the OR circuit 21 is connected to the non-inverting input terminal of the AND circuit 22 and the inverting input terminal of the AND circuit 23. The output terminal of the AND circuit 22 is connected to the set terminal S of the flip-flop 28, and the output terminal of the AND circuit 23 is connected to the reset terminal R of the flip-flop 28. The output terminal Q of the flip-flop 28 is connected to the output terminal 32 of the switching signal Ss1 and the output terminal 33 of the output signal So. That is, the pulsed output signal So having a frequency corresponding to the magnitude of the switching signal Ss1 and the input voltage Vi is the same signal. The output terminal Q of the flip-flop 28 is connected to the input terminal of the inverter circuit 25. The output terminal of the inverter circuit 25 is connected to the output terminal 34 of the switching signal Ss2. Thereby, the switching signals Ss1 and Ss2 are signals whose levels are inverted from each other.

  The output terminal of the AND circuit 24 is connected to the set terminal S of the flip-flop 27. The output terminal Q of the flip-flop 28 is connected to the output terminal 35 of the switching signal Ss3. The output terminal of the inverter circuit 26 is connected to the other non-inverting input terminal of the AND circuit 24 and the output terminal 36 of the switching signal Ss4. That is, the switching signal Ss4 and the switching signal Ss5 are the same signal.

  In the above configuration, the OR circuit 21 is provided so as not to make the inputs of the AND circuits 22 and 23 undefined when the switch circuit 29 is switched to the second switching terminal b side. The flip-flop 27 functions as a latch circuit for maintaining the switching signal Ss3 at the H level from the time when the output voltage Vo reaches the voltage Vth3 to the time when the output voltage Vo decreases and reaches the voltage Vth2. . Although a detailed description of the operation is omitted, the control contents shown in the flowchart of FIG. 2 can be realized by the logic circuit having such a configuration.

  In the current detecting device 1 having the above configuration, when steps A12 to A15 shown in FIG. 2 are omitted, that is, in the case of the configuration of the conventional technique, the integrating capacitor C1 is saturated during operation, and the integrating circuit 7 There is a possibility that an abnormality may occur that will not work properly. Specifically, when the input offset voltage Voft of the operational amplifier OP1 meets the following conditions, the above abnormality may occur. That is, the input offset voltage Voft is larger than the voltage input to the operational amplifier OP1 (the difference voltage between the voltage Vm and the voltage Vn), and the polarity of the inverting input terminal voltage is higher than that of the non-inverting input terminal voltage. In the case of polarity, the above abnormality occurs.

  FIG. 5 shows the voltage waveform of each part and the switching state of each switch. In FIG. 5, the period from time t0 to t5 shows the case where the input offset voltage Voft does not meet the above condition (for example, when Voft = 0V), and the input offset voltage Voft meets the above condition during the period after time t5. Shows the case. In the voltage waveform in the upper part of FIG. 5, the voltage Vn is indicated by a solid line, the voltage Vm is indicated by a broken line, and the voltage V + of the inverting input terminal of the operational amplifier OP1 is indicated by a one-dot chain line. The voltage Vm and the voltage V + have the same value during the period from time t0 to time t5.

  When the input offset voltage Voft is zero, when the first switch SW1 is turned on and the second switch SW2 is turned off in order to switch the integrating amplifier 10 to the discharging state, the integration resistor R3 on the input switching unit 9 side is turned on. The voltage Vn at the terminal becomes higher than the voltage V + at the terminal on the operational amplifier OP1 side. Therefore, the integrating amplifier 10 is switched to a discharging state in which a current flows from the integrating resistor R3 side to the integrating capacitor C1 side (time t1, time t3 in FIG. 5).

  On the other hand, when the input offset voltage Voft meets the above condition, the input switch of the integrating resistor R3 is switched even if the first switch SW1 is turned on and the second switch SW2 is turned off to switch the integrating amplifier 10 to the discharging state. The voltage Vn at the terminal on the unit 9 side is always smaller than the voltage at the terminal V + on the operational amplifier OP1 side, which is high due to the influence of the input offset voltage Voft. Therefore, the integrating amplifier 10 is always in a charged state in which a current flows from the integrating capacitor C1 side toward the integrating resistor R3 side, and cannot be switched to the discharging state. By continuing the charging state in this way, the output voltage Vo of the operational amplifier OP1 continues to rise even if it exceeds the voltage Vth2. Eventually, the output voltage Vo rises to the maximum voltage value that can be output from the operational amplifier OP1, and is fixed to that voltage value. In this way, the integrating amplifier 10 (= integrating capacitor C1) is saturated, and the integrating circuit 7 cannot operate normally.

  An operational amplifier is often provided with a function of self-adjusting the input offset voltage Voft at regular intervals. Therefore, it seems that the occurrence of the abnormality can be suppressed by using the operational amplifier OP1 having the adjustment function. However, before the adjustment is performed, the input offset voltage Voft increases due to, for example, a temperature change or a power supply voltage fluctuation, and the integration amplifier 10 is saturated when the above conditions are met.

  In the present embodiment, the occurrence of the abnormality is avoided as follows. That is, when the output voltage Vo of the operational amplifier OP1 is higher than the voltage Vth2, there is a high possibility that the state switching of the integrating amplifier 10 has not been successfully performed for the reason described above. Therefore, as described above, when the output voltage Vo reaches the voltage Vth3 set higher than the voltage Vth2, the control logic 13 turns on the third switch SW3 to discharge the charge of the integrating capacitor C1. In this way, when the input offset voltage Voft increases during operation and the integrating capacitor C1 is almost saturated or completely saturated, the charge of the integrating capacitor C1 is reset. Thereafter, the offset voltage adjusting function provided in the operational amplifier OP1 is activated, so that the input offset voltage Voft is reduced, and the integrating circuit 7 can be returned to normal operation.

  The second comparator CP2 of the comparison circuit 12 is configured to be switchable between a normal state in which the output voltage Vo and the voltage Vth1 are compared and a saturation detection state in which the output voltage Vo and the voltage Vth3 are compared. During the period in which the integrating amplifier 10 is in a discharged state, an abnormality in which the integrating capacitor C1 is saturated does not occur. On the other hand, there is a possibility that the integrating capacitor C1 is saturated while the integrating amplifier 10 is in a charged state. Further, since the output voltage Vo does not decrease during the same period, it is not necessary to compare the output voltage Vo and the voltage Vth1. Therefore, the second comparator CP2 is switched to the normal state during the period when the integrating amplifier 10 is in the discharging state, and is switched to the saturation detection state during the period when the integrating amplifier 10 is in the charging state. This makes it possible to compare the output voltage Vo with the voltages Vth1, Vth2, and Vth3 using the two comparators CP1 and CP2. Therefore, it is possible to obtain an effect that the circuit scale of the comparison circuit 12 and thus the circuit scale of the entire apparatus can be kept relatively small.

  The third switch SW3 is connected between the terminal on the output terminal side of the operational amplifier OP1 of the integrating capacitor C1 and the power supply line 6 to which the ground potential (0 V) is applied in the current detection device 1. According to such a configuration, when the third switch SW3 is turned on, one terminal of the integrating capacitor C1 becomes the ground potential, and the charge is surely discharged. For this reason, the output voltage Vo of the operational amplifier OP1 is immediately reduced, and the occurrence of an abnormality that makes the integrating circuit 7 inoperable can be avoided more reliably.

  The current detection device 1 includes a shunt resistor 3 connected in series with the load 2 between the power supply lines 5 and 6 for supplying the power supply voltage VBAT to the load 2, and a terminal voltage of the shunt resistor 3 input thereto and corresponding to the input voltage Vi. The VF conversion circuit 4 outputs an output signal So having a frequency. According to such a configuration, the current consumption of the load 2 can be detected based on the frequency of the output signal So.

  When the current consumption of the load 2 is detected directly from the value of the terminal voltage of the shunt resistor 3, in order to detect a relatively small current, the resistance value of the shunt resistor 3 is increased or decreased. It is necessary to use a voltage detection device that can accurately detect the voltage. However, in the former case, there arises a problem that power consumption in the shunt resistor 3 is increased. In the latter case, problems such as an increase in circuit scale and high cost occur. On the other hand, according to the current detection device 1 of the present embodiment, the operation of the VF conversion circuit 4 converts the terminal voltage of the shunt resistor 3 into the form of the frequency of the pulsed output signal So. The frequency of such a pulsed output signal So can be detected relatively easily by using, for example, a counter. Therefore, according to the present embodiment, while the power consumption in the shunt resistor 3 is kept small, problems such as an increase in circuit scale and high cost do not occur, and a relatively small value such as a current consumption during standby of the load 2 is obtained. A device capable of detecting a current (for example, a micro current on the order of microamperes) can be realized.

(Second Embodiment)
Hereinafter, a second embodiment of the present invention will be described with reference to FIGS. 6 and 7 mainly focusing on portions different from the above embodiment.
FIG. 6 is a diagram showing a schematic configuration of the current detection device of the present embodiment, and corresponds to FIG. 1 in the first embodiment. In the current detection device 41 shown in FIG. 6, the control circuit 43 of the VF conversion circuit 42 includes a comparison circuit 44 instead of the comparison circuit 12 with respect to the control circuit 8 shown in FIG. The difference is that a control logic 45 is provided instead of the logic 13.

  The comparison circuit 44 (corresponding to comparison means) is different from the comparison circuit 12 in that a third comparator CP3 is provided instead of the fourth switch SW4. In the third comparator CP3, the output voltage Vo of the operational amplifier OP1 is given to the non-inverting input terminal, and the voltage Vth3 of the interconnection point N3 is given to the inverting input terminal. With such a configuration, the third comparator CP3 compares the output voltage Vo and the voltage Vth3, and outputs a comparison signal Sc3 indicating the comparison result to the control logic 45.

  The control logic 45 controls the switches SW1 to SW3 based on the comparison signals Sc1 to Sc3 representing the comparison results of the three comparators CP1 to CP3 and has a pulse shape having a frequency corresponding to the current consumption of the load 2. Output signal So. That is, in the present embodiment, the control logic 45 functions as a switch switching unit, a saturation release unit, and a signal output unit.

  FIG. 7 is a diagram illustrating a specific configuration example of the control logic of the present embodiment, and corresponds to FIG. 4 in the first embodiment. The control logic 45 shown in FIG. 7 is different from the control logic 13 shown in FIG. 4 in that the OR circuit 21, the AND circuit 24, the inverter circuit 26, and the switch circuit 29 are omitted. In response to this, the comparison signal Sc <b> 2 is supplied to the non-inverting input terminal of the AND circuit 22 and the inverting input terminal of the AND circuit 23 through the input terminal 31. The set signal S of the flip-flop 27 is supplied with the comparison signal Sc3 through the input terminal 46.

  Although detailed description of the operation of the logic circuit is omitted, even in the present embodiment using the control logic 45 of the logic circuit having such a configuration, the same operations and effects as those of the first embodiment can be obtained. Further, the comparison circuit 44 uses three comparators CP1 to CP3 and compares the output voltage Vo with the voltages Vth1 to Vth3. According to such a configuration, although the circuit scale is increased by the necessity to provide the three comparators CP1 to CP3, it is not necessary to switch the inputs of the comparators CP1 to CP3. Therefore, it is possible to simplify the control contents of the control logic 45 and to obtain an effect that there is no possibility of errors in comparison results due to various delays at the time of switching the input.

(Third embodiment)
Hereinafter, a third embodiment of the present invention will be described with reference to FIGS. 8 and 9 mainly with respect to portions different from the above embodiment.
FIG. 8 is a diagram showing a schematic configuration of the current detection device of the present embodiment, and corresponds to FIG. 1 in the first embodiment. In the current detection device 51 shown in FIG. 8, the control circuit 53 of the VF conversion circuit 52 includes a comparison circuit 54 instead of the comparison circuit 12 with respect to the control circuit 8 shown in FIG. The difference is that a control logic 55 is provided instead of the logic 13. The comparison circuit 54 (corresponding to comparison means) is different from the comparison circuit 12 in that a latch circuit 56 is provided instead of the fourth switch SW4.

  The latch circuit 56 includes a third comparator CP3, an S-R flip-flop 57, and an inverter circuit 58. In the third comparator CP3 of the latch circuit 56, the output voltage Vo of the operational amplifier OP1 is applied to the non-inverting input terminal, and the voltage Vth3 of the interconnection point N3 is applied to the inverting input terminal. With such a configuration, the third comparator CP3 compares the output voltage Vo and the voltage Vth3, and outputs a comparison signal Sc3 indicating the comparison result to the set terminal S of the flip-flop 57. The inverter circuit 58 receives and inverts the comparison signal Sc2, and outputs the inverted signal to the reset terminal R of the flip-flop 57. The output signal of the flip-flop 57 becomes a switching signal Ss3 for switching on / off of the third switch SW3.

  The control logic 55 controls the switches SW1 and SW2 based on the comparison signals Sc1 and Sc2 representing the comparison results of the two comparators CP1 and CP2, and has a pulse shape having a frequency corresponding to the current consumption of the load 2. Output signal So is output. That is, in the present embodiment, the control logic 55 functions as a switch switching unit and a signal output unit. Further, the latch circuit 56 functions as a saturation canceling unit that turns on the third switch SW3 to discharge the charge of the integrating capacitor C1 when the output voltage Vo reaches the voltage Vth3.

  FIG. 9 is a diagram illustrating a specific configuration example of the control logic of the present embodiment, and corresponds to FIG. 4 in the first embodiment. The control logic 55 shown in FIG. 9 differs from the control logic 13 shown in FIG. 4 in that the OR circuit 21, the AND circuit 24, the inverter circuit 26, the flip-flop 27, and the switch circuit 29 are omitted. In response to this, the comparison signal Sc <b> 2 is supplied to the non-inverting input terminal of the AND circuit 22 and the inverting input terminal of the AND circuit 23 through the input terminal 31.

  Although detailed description of the operation of the logic circuit is omitted, even in the present embodiment using the control logic 55 of the logic circuit having such a configuration, the same operations and effects as those in the first embodiment can be obtained. However, according to the configuration of the present embodiment, the switching signal Ss3 is H from the time when the output voltage Vo reaches the voltage Vth3 until the time when the output voltage Vo decreases and reaches the voltage Vth1 by the operation of the latch circuit 56. Maintained at level. That is, in the configuration of the present embodiment, when the integrating capacitor C1 is saturated, the third switch SW3 is maintained in the ON state until the output voltage Vo of the operational amplifier OP1 drops to the voltage Vth1.

  Further, the comparison circuit 54 uses the third comparator CP3 included in the two comparators CP1 and CP2 and the latch circuit 56, and compares the output voltage Vo with the voltages Vth1 to Vth3. According to such a configuration, the same operations and effects as those of the second embodiment can be obtained.

(Other embodiments)
The present invention is not limited to the embodiments described above and illustrated in the drawings, and the following modifications or expansions are possible.
The specific configuration of the control logic 13, 45, 55 is not limited to that shown in FIGS. 4, 7, and 9, respectively.
The charge discharging means is not limited to the third switch SW3 connected between one terminal of the integrating capacitor C1 and the ground terminal to which the ground potential is applied, and the charge of the integrating capacitor C1 can be discharged. Anything can be adopted.

  In the configuration of the first embodiment and the second embodiment, the switching signal Ss3 is maintained at the H level from the time when the output voltage Vo reaches the voltage Vth3 to the time when the output voltage Vo decreases to reach the voltage Vth1. As described above, the configuration of the control logics 13 and 45 may be changed. In the configuration of the third embodiment, the switching signal Ss3 is maintained at the H level from the time when the output voltage Vo reaches the voltage Vth3 to the time when the output voltage Vo decreases to reach the voltage Vth2. The configuration of the latch circuit 56 may be changed. That is, when an abnormality occurs in which the integrating capacitor C1 is saturated, the charge of the integrating capacitor C1 may be discharged until the integrating circuit 7 can return to normal operation.

The VF conversion circuits 4, 42, and 52 may supply an external control device with a triangular wave output voltage Vo output from the operational amplifier OP 1 instead of the pulsed output signal So. In that case, the external control device may detect the current flowing through the load 2 based on the frequency of the output voltage Vo. As a method of detecting the frequency of the output voltage Vo, for example, there is a method of converting the output voltage Vo and a predetermined reference voltage into a pulse signal by comparing with a comparator and counting the frequency of the pulse signal with a counter or the like. Can be mentioned. In the case of such a configuration, it can be said that the VF conversion circuits 4, 42, and 52 are triangular wave generation circuits that generate a triangular wave signal.
The VF conversion circuit of the present invention can be applied not only to a current detection device that detects a current flowing through a load but also to various devices that require a function of converting a voltage into a frequency.

  In the drawing, 1, 41 and 51 are current detection devices, 2 is a load, 3 is a shunt resistor, 4, 42 and 52 are VF conversion circuits, 5 and 6 are power supply lines, 7 is an integration circuit, 8, 43, 53 is a control circuit, 12, 44 and 54 are comparison circuits (comparison means), 13 is control logic (switch switching means, signal output means, saturation release means, comparison state switching means), 45 is control logic (switch switching means, 55, control logic (switch switching means, signal output means), 56 a latch circuit (saturation release means), C1 an integrating capacitor, CP1 a first comparator, CP2 a second comparator CP3 is a third comparator, OP1 is an operational amplifier, P1 and P2 are input terminals, R1 and R2 are input resistors, R3 is an integration resistor, SW1 is a first switch, SW2 is a second switch, W3 denotes the third switch (charge discharging means, the charge discharging switch) a.

Claims (5)

An VF conversion circuit that includes an integration circuit and a control circuit that controls the operation of the integration circuit, and that outputs an output signal having a frequency corresponding to an input voltage;
The integration circuit includes:
An operational amplifier,
An integrating resistor with one terminal connected to the inverting input terminal of the operational amplifier;
An integrating capacitor connected between the inverting input terminal and the output terminal of the operational amplifier;
Charge discharging means capable of discharging the charge of the integrating capacitor;
Two input resistors connected in series with each other between two input terminals to which the input voltage is applied, and whose interconnection point is connected to a non-inverting input terminal of the operational amplifier;
A first switch connected between an input terminal on the high potential side of the two input terminals and the other terminal of the integrating resistor;
A second switch connected between the input terminal on the low potential side of the two input terminals and the other terminal of the integrating resistor;
With
The charging state in which the first switch is turned off and the second switch is turned on and the discharging state in which the first switch is turned on and the second switch is turned off are alternately repeated, whereby the output of the operational amplifier A triangular wave voltage is output from the terminal,
The control circuit includes:
Comparing means for comparing the output voltage of the operational amplifier with a minimum value specifying voltage that specifies the minimum value of the triangular wave, a maximum value specifying voltage that specifies the maximum value of the triangular wave, or a saturation detection voltage higher than the maximum value specifying voltage. ,
When the output voltage reaches the minimum prescribed voltage, the first switch is turned off and the second switch is turned on. When the output voltage reaches the maximum prescribed voltage, the first switch is turned on and the first switch is turned on. 2 switch switching means for turning off the switch;
Signal output means for outputting a signal corresponding to the output voltage as the output signal;
When the output voltage reaches the saturation detection voltage, saturation release means for controlling the charge discharging means to discharge the charge of the integrating capacitor;
A V-F conversion circuit comprising: The comparison means includes
A first comparator for comparing the output voltage of the operational amplifier and the maximum value defining voltage;
A second comparator configured to be switchable between a normal state in which the output voltage of the operational amplifier and the minimum value defining voltage are compared, and a saturation detection state in which the output voltage of the operational amplifier and the saturation detection voltage are compared;
Comparison state switching means for switching the second comparator to the normal state during a period in which the integration circuit is in a discharged state, and for switching the second comparator to the saturation detection state in a period in which the integration circuit is in a charged state;
The VF conversion circuit according to claim 1, comprising: The comparison means includes
A first comparator for comparing the output voltage of the operational amplifier and the maximum value defining voltage;
A second comparator for comparing the output voltage of the operational amplifier and the minimum prescribed voltage;
A third comparator for comparing the output voltage of the operational amplifier and the saturation detection voltage;
The VF conversion circuit according to claim 1, comprising: The charge discharge means is a charge discharge switch connected between a terminal of the integrating capacitor connected to the output terminal side of the operational amplifier and a ground terminal to which a ground potential is applied;
The VF conversion circuit according to claim 1, wherein the saturation release unit discharges the charge of the integrating capacitor by turning on the charge discharge switch. A VF conversion circuit according to any one of claims 1 to 4, and a shunt resistor connected in series with the load between a pair of power supply lines for supplying a power supply voltage to the load,
The terminal voltage of the shunt resistor is input to the VF conversion circuit,
A current detection device that detects a current flowing through the load based on a frequency of an output signal of the VF conversion circuit.

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