CN116819264A - Voltage arc detection circuit and control method - Google Patents

Abstract

This application relates to a voltage arc detection circuit and its control method. The circuit includes: a rectifier circuit, an integrating circuit, an average filter circuit, a NAND gate logic circuit, a NOR gate logic circuit and a comparator; the first signal output end of the NAND gate logic circuit is connected to a power output device; the power output device is connected to a power output device. The rectifier circuit is connected; the rectifier circuit is connected to the integrating circuit and the average filter circuit respectively; the second signal output end of the integrating circuit and the third signal output end of the average filter circuit are connected to the comparator; the NOR gate logic circuit includes a fourth signal output end , the first timing signal input terminal and the second timing signal input terminal, the fifth signal output terminal and the first timing signal input terminal of the comparator are connected to the NAND gate logic circuit; the fourth signal output terminal is connected to the integrating circuit for Control the working status of the integrating circuit. The solution provided by this application can detect and suppress voltage arcs in time, significantly reducing the probability of arc occurrence.

Description

Voltage arc detection circuit and control method

Technical field

The present application relates to the field of circuit technology, and in particular to voltage arc detection circuits and control methods thereof.

Background technique

In the plasma coating system, arcing phenomenon may occasionally occur due to occasional unstable conditions of load characteristics, which can easily cause damage to the coated product and even cause damage to the plasma coating system. The arcing phenomenon is generally divided into current arcing phenomenon and voltage arcing phenomenon. Among them, generally when a current arc occurs, it has a greater impact on the load. However, the current arc phenomenon can be detected using overcurrent detection, while the voltage arc phenomenon is difficult to detect. Therefore, it is necessary to design a voltage arc detection circuit for voltage arc detection, which can improve the arc suppression capability of the plasma coating system.

In the existing technology, the patent (Arc Fault Detection Method) with the publication number CN102621377B proposes to analyze whether the current waveform has zero breaks and asymmetry between positive and negative half cycles by collecting current data per cycle based on the universal characteristics of arcs. , periodicity is not obvious, and whether it contains rich high-frequency harmonics, these characteristics can be used to determine whether an arc fault has occurred, which can improve the accuracy and precision of arc fault judgment.

The above-mentioned prior art has the following shortcomings:

The detection method of fault arc based on the universal characteristics of arc has low detection efficiency and poor timely feedback. It cannot suppress the voltage arc in time and cannot reduce the probability of arc occurrence.

Contents of the invention

In order to overcome the problems existing in related technologies, this application provides a voltage arc detection circuit. The voltage arc detection circuit can detect and suppress voltage arcs in a timely manner and significantly reduce the probability of arc occurrence.

The first aspect of this application provides a voltage arc detection circuit, including:

Rectifier circuit, integrating circuit, average filter circuit, NAND gate logic circuit, NOR gate logic circuit and comparator;

The first signal output end of the NAND gate logic circuit is connected to the power output device and is used to control the start and stop of the power output device;

The power output device is connected to the rectifier circuit;

The rectifier circuit is connected to the integrating circuit and the average filter circuit respectively;

The second signal output terminal of the integrating circuit and the third signal output terminal of the average filter circuit are connected to the comparator;

The NOR gate logic circuit includes a fourth signal output terminal, a first timing signal input terminal and a second timing signal input terminal, and the fifth signal output terminal and the first timing signal input terminal of the comparator are connected to the NAND gate logic circuit;

The fourth signal output terminal is connected to the integrating circuit and is used to control the working state of the integrating circuit. The working state includes the integrating state and the clearing state.

In one implementation, the integrating circuit includes a first operational amplifier U1, a resistor R1, a capacitor C1 and a MOS transistor Q1;

One end of the resistor R1 is connected to the rectifier circuit, and the other end of the resistor R1 is connected to the first inverting input end of the first operational amplifier U1;

The capacitor C1 is connected between the first inverting input terminal and the second signal output terminal, the second signal output terminal is the first signal output terminal of the first operational amplifier U1, and the first signal output terminal and the first input terminal of the comparator connect;

MOS tube Q1 is connected in parallel with capacitor C1, and the fourth signal output terminal is connected with the gate of MOS tube Q1.

In one implementation, the average filter circuit includes a second operational amplifier U3, a resistor R3, a resistor R4, a resistor R5, a capacitor C2 and a capacitor C3;

One end of the resistor R4 is connected to the rectifier circuit, and the other end of the resistor R4 is connected to the second inverting input end of the second operational amplifier U3;

The capacitor C2 is connected between the second inverting input terminal and the second signal output terminal of the second operational amplifier U3;

One end of the resistor R5 is connected to the second signal output end, and the other end of the resistor R5 is connected to the second input end of the comparator;

One end of the capacitor C3 is connected to the second input terminal, and the other end of the capacitor C3 is connected to the ground; the node where the resistor R5 and the capacitor C3 intersect is the third signal output terminal;

Resistor R3 is connected in parallel with capacitor C2.

In one implementation, a parasitic diode is provided between the source and drain of MOS transistor Q1.

In one implementation, the first signal output end is connected to a device control circuit, and the device control circuit is used to control starting and stopping of the power output device.

A second aspect of this application provides a control method for a voltage arc detection circuit, including:

Collect the output voltage of the power output device, and input the rectified voltage obtained after rectifying the output voltage into the integrating circuit and the average filter circuit;

Input the first timing signal to the first timing signal input terminal of the NOR gate logic circuit, input the second timing signal value to the second timing signal input terminal of the NOR gate logic circuit, and output the fourth signal output terminal of the NOR gate logic circuit. first level signal;

The working state of the integrating circuit is controlled according to the first level signal. When the working state is the clear state, the output of the second signal output terminal of the integrating circuit is zero;

When the working state is the integration state and the first timing signal is high level, the first voltage signal output by the second signal output terminal is compared with the second voltage signal output by the third signal output terminal of the average filter circuit through the comparator. , determine the second level signal output by the first signal output terminal of the NAND gate logic circuit based on the comparison result;

Control starting and stopping of the power output device according to the second level signal.

In one implementation, controlling the working state of the integrating circuit according to the first level signal includes:

If the first level signal is a high level signal, the MOS transistor Q1 of the integrating circuit is controlled to be turned on.

In one implementation, determining the second level signal output by the first signal output terminal of the NAND gate logic circuit based on the comparison result includes:

If the first voltage signal is greater than the second voltage signal, the comparator outputs a low level, and the second level signal is a high level signal;

If the first voltage signal is less than or equal to the second voltage signal, the comparator outputs a high level, and the second level signal is a low level signal.

In one implementation, controlling the start and stop of the power output device according to the second level signal includes:

If the second level signal is a low level signal, the power output device is controlled to shut down through the device control circuit;

If the second level signal is a high level signal, the startup state of the power output device is maintained.

In one implementation, the first voltage signal is calculated through a first formula, and the first formula is:

V＝(U1+U2+U3+....+Un-1+Un)/n

Among them, V is the first voltage signal, U1, U2, U3...Un-1 and Un are the rectified voltages corresponding to each collected output voltage, and n is the number of output voltages collected in one collection cycle;

The second voltage signal is calculated through the second formula, and the second formula is:

P＝(V1+V2+V3+....+Vm-1+Vm)/m

Among them, P is the second voltage signal, V1, V2, V3...Vm-1 and Vm are the first voltage signals corresponding to each collection cycle, and m is the number of cycles of the collection cycle.

The technical solution provided by this application can include the following beneficial effects:

The voltage arc detection circuit of this application is provided with a rectifier circuit, an integrating circuit, an average filter circuit, a NAND gate logic circuit, a NOR gate logic circuit and a comparator. By connecting the power output device to the rectifier circuit, the output of the power output device is The voltage is rectified, and the rectifier circuit is connected to the integrating circuit and the average filter circuit respectively. The rectified voltage signal can be input to the integrating circuit and the average filter circuit; in addition, the NOR gate logic circuit includes a fourth signal output terminal, a first The timing signal input terminal and the second timing signal input terminal, so that the output signal of the fourth signal output terminal can be controlled based on the signals input by the first timing signal input terminal and the second timing signal input terminal, the fourth signal output terminal and the integrating circuit Connection is used to control the working state of the integrating circuit. The working state includes the integrating state and the clearing state to prevent the integrating circuit from reaching over saturation and affecting the detection of voltage arc; connect the second signal output end of the integrating circuit and the average filter circuit The third signal output terminal is connected to the comparator, and the fifth signal output terminal and the first timing signal input terminal of the comparator are connected to the NAND gate logic circuit, so that the voltage signal output by the integrating circuit and the average filter circuit output can be compared. The voltage signal is used to determine the signal output by the fifth signal output terminal, so that the signal output by the fifth signal output terminal and the timing signal input by the first timing signal input terminal jointly determine the first signal output terminal of the NAND gate logic circuit The output signal can be avoided by formulating the timing signal input to the first timing signal input terminal. When the voltage signal output by the integrating circuit ends in the clearing state, the voltage signal output by the integrating circuit may be smaller than the voltage signal output by the average filter circuit. This leads to misjudgments in voltage arc detection and improves the accuracy of voltage arc detection; the first signal output end of the NAND gate logic circuit is connected to the power output device and is used to control the start and stop of the power output device, which can perform timely monitoring of the voltage arc. Detect and implement protective measures in a timely manner to significantly reduce the probability of arc occurrence, avoid damage to power output equipment and even production products due to voltage arcs, and improve production efficiency and production quality.

It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and do not limit the present application.

Description of the drawings

The above and other objects, features and advantages of the present application will become more apparent through a more detailed description of the exemplary embodiments of the present application in conjunction with the accompanying drawings, in which the same reference numerals generally represent Same parts.

Figure 1 is a schematic circuit structure diagram of a voltage arc detection circuit according to an embodiment of the present application;

Figure 2 is a schematic flowchart of a control method of a voltage arc detection circuit according to an embodiment of the present application;

Figure 3 is a schematic diagram of the signal when the voltage arc detection circuit detects the occurrence of arc according to the embodiment of the present application;

Figure 4 is a schematic diagram of the signal when the voltage arc detection circuit does not detect the occurrence of arc according to the embodiment of the present application;

FIG. 5 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

Detailed ways

Preferred embodiments of the present application will be described in more detail below with reference to the accompanying drawings. Although preferred embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a," "the" and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will also be understood that the term "and/or" as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

It should be understood that although the terms "first", "second", "third", etc. may be used in this application to describe various information, the information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of the present application, the first information may also be called second information, and similarly, the second information may also be called first information. Therefore, features defined as "first" and "second" may explicitly or implicitly include one or more of these features. In the description of this application, "plurality" means two or more than two, unless otherwise explicitly and specifically limited.

Embodiment 1

In the plasma coating system, arcing phenomenon may occasionally occur due to occasional unstable conditions of load characteristics, which can easily cause damage to the coated product and even cause damage to the plasma coating system. The arcing phenomenon is generally divided into current arcing phenomenon and voltage arcing phenomenon. Among them, generally when a current arc occurs, it has a greater impact on the load. However, the current arc phenomenon can be detected using overcurrent detection, while the voltage arc phenomenon is difficult to detect. The existing technology is based on the universal characteristics of arcs as a detection method for fault arcs. The detection efficiency is low, the timely feedback is poor, and the voltage arc cannot be suppressed in a timely manner, and the probability of arc occurrence cannot be reduced.

In response to the above problems, embodiments of the present application provide a voltage arc detection circuit that can detect voltage arcs in a timely manner and significantly reduce the probability of arc occurrence.

The technical solutions of the embodiments of the present application are described in detail below with reference to the accompanying drawings.

Please refer to Figure 1. Embodiment 1 of the voltage arc detection circuit shown in the embodiment of this application includes:

Rectifier circuit, integrating circuit, average filter circuit, NAND gate logic circuit, NOR gate logic circuit and comparator. The NAND gate logic circuit is U5 in Figure 1, and the NOR gate logic circuit is U4 in Figure 1. Compare The device is U2 in Figure 1. Specifically, the power output device is connected to the rectifier circuit, so that the output voltage of the power output device, that is, Uac in Figure 1, can be collected and input into the rectifier circuit. The rectifier circuit is connected to the integrating circuit and the average filter circuit respectively, so that the rectifier The rectified voltage, namely Urec in Figure 1, can be input to the integrating circuit and the average filtering circuit for processing respectively. In the embodiment of the present application, the integrating circuit is used to average the voltage collected in each collection cycle. The average filter circuit is used to average the voltage collected in each historical collection period. The collection period can be set to the half-sinusoidal alternating current period corresponding to the output voltage of the power output device, or can be set to other forms. There is no unique limit here. In the embodiment of the present application, a rectifier circuit is required to rectify the output voltage into a DC pulse signal and then perform averaging processing.

In addition, the NOR gate logic circuit includes a fourth signal output terminal, a first timing signal input terminal and a second timing signal input terminal. The fourth signal output terminal is point C in Figure 1 and the first timing signal input terminal is Figure 1 Point A in , the second timing signal input terminal is point B in Figure 1, so that the output signal of the fourth signal output terminal can be controlled based on the signals input by the first timing signal input terminal and the second timing signal input terminal. The four signal output terminals are connected to the integrating circuit and are used to control the working state of the integrating circuit. The working state includes the integrating state and the clearing state. In the embodiment of this application, half the cycle of the sinusoidal alternating current will be used as the acquisition cycle. It can be understood that if it is not cleared, the integrating circuit will continue to integrate, so that the second signal output end of the integrating circuit, That is, at point E in Figure 1, the output voltage signal is oversaturated, which affects the voltage arc detection judgment of the next acquisition cycle and cannot reflect the waveform changes corresponding to each half-sinusoidal alternating current cycle. Therefore, it is necessary to change the working status of the integrating circuit. Switch to clear state appropriately.

Further, the second signal output terminal of the integrating circuit and the third signal output terminal of the average filter circuit, that is, point F in Figure 1, are connected to the comparator. Specifically, the second signal output terminal is connected to the inverting input of the comparator. terminal is connected, the third signal output terminal is connected to the non-inverting input terminal of the comparator, without limitation, the fifth signal output terminal of the comparator, which is point G in Figure 1, and the first timing signal input terminal AND NAND gate logic Circuit connection, the first signal output end of the NAND gate logic circuit, that is, point D in Figure 1, is connected to the power output device and is used to control the start and stop of the power output device.

It can be understood that the signal output by the fifth signal output terminal is determined through the comparison result of the voltage signal at the second signal output terminal and the voltage signal at the third signal output terminal, so that the timing signal input by the first timing signal input terminal and The signal output by the fifth signal output terminal jointly determines the output signal of the first signal output terminal of the NAND gate logic circuit, thereby controlling the start and stop of the power output device according to the signal. It is necessary to add the timing signal input to the first timing signal input terminal for judgment because the voltage signal at the third signal output terminal is a voltage signal obtained by averaging the voltages collected in each historical acquisition cycle. It is a relatively stable voltage signal. It can be regarded as a constant value, and the voltage signal at the second signal output terminal will be cleared after each acquisition cycle, and then the integration task of the next acquisition cycle will be re-executed. When the clearing state ends, it will even be reset for a certain period in the future. Within a period of time, the voltage signal at the second signal output terminal is likely to be smaller than the voltage signal at the third signal output terminal. At this time, there may be no voltage arc generated, which may easily lead to voltage arc detection errors. In order to avoid this situation, It is necessary to add the timing signal input to the first timing signal input terminal for judgment, and to formulate the timing signal input to the first timing signal input terminal. For example, when the timing signal input to the first timing signal input terminal is high level, Only the signal output by the fifth signal output terminal is valid. When the timing signal input by the first timing signal input terminal is low level, the signal output by the fifth signal output terminal has no impact on the output signal of the first signal output terminal. Therefore, it will not affect the start and stop of the control power output device. It can be understood that the formulation of the timing signal input by the first timing signal input terminal needs to be determined according to the actual application situation, and is not limited here.

The following beneficial effects can be seen from the above-mentioned Embodiment 1:

The voltage arc detection circuit of this application is provided with a rectifier circuit, an integrating circuit, an average filter circuit, a NAND gate logic circuit, a NOR gate logic circuit and a comparator. By connecting the power output device to the rectifier circuit, the output of the power output device is The voltage is rectified, and the rectifier circuit is connected to the integrating circuit and the average filter circuit respectively. The rectified voltage signal after rectification can be input into the integrating circuit and the average filter circuit; in addition, the NOR gate logic circuit includes a fourth signal output terminal, a third A timing signal input terminal and a second timing signal input terminal, so that the output signal of the fourth signal output terminal can be controlled based on the signals input by the first timing signal input terminal and the second timing signal input terminal, and the fourth signal output terminal is connected to the integral Circuit connection is used to control the working state of the integrating circuit. The working state includes the integrating state and the clearing state to prevent the integrating circuit from reaching over saturation and affecting the detection of voltage arc; connect the second signal output end of the integrating circuit and the average filter The third signal output terminal of the circuit is connected to the comparator, and the fifth signal output terminal and the first timing signal input terminal of the comparator are connected to the NAND gate logic circuit, so that the voltage signal output by the integrating circuit and the average filter circuit output can be compared. The voltage signal is used to determine the signal output by the fifth signal output terminal, so that the signal output by the fifth signal output terminal and the timing signal input by the first timing signal input terminal jointly determine the first signal output of the NAND gate logic circuit Therefore, it is possible to avoid the voltage signal output by the integrating circuit by formulating the timing signal input by the first timing signal input terminal. When the clearing state ends, the voltage signal output by the integrating circuit must be smaller than the voltage signal output by the average filter circuit. This leads to misjudgments in voltage arc detection and improves the accuracy of voltage arc detection; the first signal output end of the NAND gate logic circuit is connected to the power output device and is used to control the start and stop of the power output device, which can control the voltage arc. Timely detection and timely implementation of protective measures can significantly reduce the probability of arc occurrence, avoid damage to power output equipment and even production products due to voltage arcs, and improve production efficiency and production quality.

Embodiment 2

For ease of understanding, an embodiment of a voltage arc detection circuit is provided below for illustration. In practical applications, the integrating circuit and the average filter circuit will be further designed.

Please refer to Figure 1, Figure 3 and Figure 4. The second embodiment of the voltage arc detection circuit shown in the embodiment of the present application includes:

The integrating circuit includes a first operational amplifier U1, a resistor R1, a capacitor C1 and a MOS tube Q1. One end of the resistor R1 is connected to the rectifier circuit, the other end of the resistor R1 is connected to the first inverting input end of the first operational amplifier U1, and the capacitor C1 is connected between the first inverting input terminal and the second signal output terminal, the second signal output terminal is the first signal output terminal of the first operational amplifier U1, and the first signal output terminal is connected to the first input terminal of the comparator, MOS tube Q1 is connected in parallel with capacitor C1, the fourth signal output terminal is connected with the gate of MOS tube Q1, the first non-inverting input terminal of first operational amplifier U1 is connected to ground, and there is a connection between the source and drain of MOS tube Q1. Parasitic diodes.

It can be understood that the output signal of the fourth signal output terminal can control the on or off of the MOS transistor Q1. For example, as shown in Figure 3 and Figure 4, if the first timing signal input terminal and the second timing signal input terminals input a low-level signal at the same time, causing the output signal of the fourth signal output terminal to be a high-level signal, then the MOS tube Q1 is turned on. At this time, the voltage at point E in Figure 1, that is, the voltage signal at the second signal output terminal is 0V; If the first timing signal input terminal and the second timing signal input terminal input different level signals, causing the output signal of the fourth signal output terminal to be a low-level signal, the MOS transistor Q1 is disconnected, and the working state of the integrating circuit is at this time. Points status.

The average filter circuit includes a second operational amplifier U3, a resistor R3, a resistor R4, a resistor R5, a capacitor C2 and a capacitor C3. One end of the resistor R4 is connected to the rectifier circuit, and the other end of the resistor R4 is connected to the second inverter of the second operational amplifier U3. The input terminal is connected, the capacitor C2 is connected between the second inverting input terminal and the second signal output terminal of the second operational amplifier U3, one end of the resistor R5 is connected to the second signal output terminal, and the other end of the resistor R5 is connected to the comparator. The second input end is connected, one end of the capacitor C3 is connected to the second input end, and the other end of the capacitor C3 is connected to the ground; the node where the resistor R5 and the capacitor C3 intersect is the third signal output end, the resistor R3 and the capacitor C2 are connected in parallel, and the second The second non-inverting input terminal of op amp U3 is connected to ground. It can be understood that the average filter circuit can be represented by a low-pass filter circuit constructed in the above manner. In fact, the average voltage corresponding to multiple acquisition periods is accumulated and then averaged, which is equivalent to averaging the rectified voltage signal Urec. , obtain the voltage signal at the third signal output terminal.

In the embodiment of the present application, a device control circuit is also provided, and the first signal output terminal is connected to the device control circuit to guide the device control circuit to control the starting and stopping of the power output device.

Embodiment 3

Corresponding to the foregoing embodiments of the voltage arc detection circuit, this application also provides a control method for the voltage arc detection circuit and corresponding embodiments.

FIG. 2 is a schematic flowchart of a control method of a voltage arc detection circuit according to an embodiment of the present application.

Please refer to Figure 2. The control method of the voltage arc detection circuit shown in the embodiment of the present application includes:

301. Collect the output voltage of the power output device, and input the rectified voltage obtained after rectifying the output voltage into the integrating circuit and the average filter circuit;

Since the power output device is connected to the rectifier circuit, it is connected to the integrating circuit and the average filter circuit respectively. Therefore, the output voltage of the power output device can be collected and rectified into a DC pulse signal. The corresponding rectification of the DC pulse signal The voltage is input to the integrating circuit and the average filter circuit for processing.

302. Input the first timing signal to the first timing signal input terminal of the NOR gate logic circuit, input the second timing signal value to the second timing signal input terminal of the NOR gate logic circuit, and input the fourth signal output of the NOR gate logic circuit. The terminal outputs the first level signal;

In the embodiment of the present application, the first timing signal and the second timing signal are specific timing signals, which may be signals with twice the frequency of Uac and the same frequency as Urec, and are not uniquely limited. Within a collection cycle, that is, the half-sinusoidal alternating current cycle corresponding to the output voltage of the power output device, the first timing signal first maintains a low-level signal, then changes to a high-level signal, and finally falls back to a low-level signal. Among them, the reason for maintaining the low-level signal first is to consider the first voltage signal output by the second signal output terminal of the integrating circuit and the second voltage output by the third signal output terminal of the average filter circuit within a preset time. Comparison results between signals, because the first voltage signal is still in the stage of continuous integration improvement at this time, it is very likely that the first voltage signal is smaller than the second voltage signal, resulting in misjudgment, so the first timing signal needs to be first Keep the low-level signal so that the second-level signal output by the NAND gate logic circuit remains high-level, and shield or ignore the comparison result between the first voltage signal and the second voltage signal so that the comparison result will not affect Proper operation of power output devices. When the first timing signal changes to a high-level signal, as shown in Figure 3 and Figure 4, the second-level signal is determined by the comparison result between the first voltage signal and the second voltage signal. At this time, The time during which the first timing signal maintains a high level signal can be regarded as the arc detection time T1. When the first timing signal falls back to a low level signal, and at this time the second timing signal changes from the originally maintained high level signal to a low level signal, the fourth signal output end of the NOR gate logic circuit outputs the first level signal. The flat signal is a high-level signal, and the MOS tube Q1 that controls the integrating circuit is turned on. The MOS tube Q1 is turned on, which results in the voltage at point E in Figure 1, that is, the voltage signal at the second signal output terminal is 0V. Therefore, during acquisition Before the end of the cycle, the time when the first timing signal falls back to the low-level signal can be regarded as the E signal clearing time T2. As each acquisition cycle continues, the following can be deduced in this way.

303. Control the working state of the integrating circuit according to the first level signal. When the working state is the clear state, the output of the second signal output terminal of the integrating circuit is zero;

If it is not cleared, the integrating circuit will continue to integrate, causing the voltage signal output by the second signal output terminal of the integrating circuit, that is, point E in Figure 1, to be oversaturated, affecting the voltage arc of the next acquisition cycle. Detection and judgment cannot reflect the waveform changes corresponding to each half cycle of sinusoidal alternating current, so it is necessary to appropriately switch the working state of the integrating circuit to the clear state.

304. Control the working state of the integrating circuit according to the first level signal. When the working state is the integrating state and the first timing signal is high level, use the comparator to combine the first voltage signal output by the second signal output terminal with the average filter. Compare the second voltage signal output by the third signal output terminal of the circuit, and determine the second level signal output by the first signal output terminal of the NAND gate logic circuit based on the comparison result;

In the embodiment of this application, it is specified that when the first voltage signal is greater than the second voltage signal, the comparator outputs a low-level signal. It is considered that no voltage arc will occur at this time. Since the first timing signal is high-level, then the AND is not The second level signal output by the first signal output terminal of the gate logic circuit is high level, and there is no need to implement protective measures. When the first voltage signal is less than or equal to the second voltage signal, as shown in Figure 3, the first voltage The reason why the signal is less than or equal to the second voltage signal is that the generation of the voltage arc causes the waveform of Urec to drop, causing the signal amplitude of the E signal to decrease when the arc occurs. Therefore, it is believed that there is a risk of generating a voltage arc or that voltage has already been generated. arc, the comparator outputs a high-level signal. Since the first timing signal is high-level, the second-level signal output by the first signal output terminal of the NAND gate logic circuit is low-level, and protection measures need to be implemented. It can be understood that whether the level signal that triggers the execution of protective measures is high level or low level can be determined according to the actual application situation, and the level signal output by the comparator can be matched accordingly. There is no unique limitation here.

Specifically, the first voltage signal is equivalently calculated through the first formula, and the first formula is:

V＝(U1+U2+U3+....+Un-1+Un)/n

Among them, V is the first voltage signal, U1, U2, U3...Un-1 and Un are the rectified voltages corresponding to each collected output voltage, and n is the number of output voltages collected in one collection cycle;

The second voltage signal is equivalently calculated through the second formula, and the second formula is:

P＝(V1+V2+V3+....+Vm-1+Vm)/m

Among them, P is the second voltage signal, V1, V2, V3...Vm-1 and Vm are the first voltage signals corresponding to each collection cycle, and m is the number of cycles of the collection cycle.

It can be understood that the above equivalent calculation method for the first voltage signal and the second voltage signal is only for a better understanding of the technical solution. In practical applications, the first voltage signal and the second voltage signal are determined in various ways. , the voltage signal at the corresponding output end of the integrating circuit and the average filter circuit can be directly obtained. The method of determining the first voltage signal and the second voltage signal needs to be determined according to the actual application situation, and is not uniquely limited here.

It can also be understood that in practical applications, the second voltage signal can also be multiplied by a preset coefficient and then compared with the first voltage signal. For example, the preset coefficient can be 20%, 40%, 50 %, 60%, 80% or 100%, etc. The determination of the preset coefficient can be determined according to the actual application situation, and is not uniquely limited here.

It can also be understood that there is no strict execution sequence between step 303 and step 304, and execution of step 303 or step 304 needs to be determined based on actual judgment, and is not uniquely limited here.

305. Control the starting and stopping of the power output device according to the second level signal.

In the embodiment of the present application, if the second level signal is a low level signal, the power output device is controlled to be shut down through the device control circuit; if the second level signal is a high level signal, the startup of the power output device is maintained. state.

Embodiment 4

FIG. 5 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

Referring to FIG. 5 , electronic device 1000 includes memory 1010 and processor 1020 .

The processor 1020 can be a central processing unit (CPU), other general-purpose processor, digital signal processor (Digital Signal Processor, DSP), application specific integrated circuit (Application Specific Integrated Circuit, ASIC), or field-processable processor. Field-Programmable Gate Array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc.

Memory 1010 may include various types of storage units, such as system memory, read-only memory (ROM), and persistent storage. Among them, ROM can store static data or instructions required by the processor 1020 or other modules of the computer. Persistent storage may be readable and writable storage. Persistent storage may be a non-volatile storage device that does not lose stored instructions and data even when the computer is powered off. In some embodiments, the permanent storage device uses a large-capacity storage device (eg, magnetic or optical disk, flash memory) as the permanent storage device. In other embodiments, the permanent storage device may be a removable storage device (eg, floppy disk, optical drive). System memory can be a read-write storage device or a volatile read-write storage device, such as dynamic random access memory. System memory can store some or all of the instructions and data the processor needs to run. In addition, the memory 1010 may include any combination of computer-readable storage media, including various types of semiconductor memory chips (DRAM, SRAM, SDRAM, flash memory, programmable read-only memory), magnetic disks and/or optical disks may also be used. In some embodiments, memory 1010 may include a readable and/or writable removable storage device, such as a compact disc (CD), a read-only digital versatile disc (eg, DVD-ROM, dual-layer DVD-ROM), Read-only Blu-ray discs, ultra-density discs, flash memory cards (such as SD cards, min SD cards, Micro-SD cards, etc.), magnetic floppy disks, etc. Computer-readable storage media do not contain carrier waves and transient electronic signals that are transmitted wirelessly or wired.

The memory 1010 stores executable code. When the executable code is processed by the processor 1020, the processor 1020 can be caused to execute part or all of the above-mentioned methods.

The solution of the present application has been described in detail above with reference to the accompanying drawings. In the above embodiments, each embodiment is described with its own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. Those skilled in the art should also know that the actions and modules involved in the description are not necessarily necessary for this application. In addition, it can be understood that the steps in the methods of the embodiments of the present application can be sequentially adjusted, merged, and deleted according to actual needs, and the modules in the devices of the embodiments of the present application can be merged, divided, and deleted according to actual needs.

In addition, the method according to the present application can also be implemented as a computer program or computer program product, which computer program or computer program product includes computer program code instructions for executing part or all of the steps in the above method of the present application.

Alternatively, the present application can also be implemented as a non-transitory machine-readable storage medium (or computer-readable storage medium, or machine-readable storage medium) with executable code (or computer program, or computer instruction code) stored thereon. ), when the executable code (or computer program, or computer instruction code) is executed by the processor of the electronic device (or electronic device, server, etc.), causing the processor to execute each step of the above method according to the present application part or all of.

Those of skill will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the application herein may be implemented as electronic hardware, computer software, or combinations of both.

The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operations of possible implementations of systems and methods according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code that contains one or more components for implementing the specified logical function(s). Executable instructions. It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two consecutive blocks may actually execute substantially in parallel, or they may sometimes execute in the reverse order, depending on the functionality involved. It will also be noted that each block of the block diagram and/or flowchart illustration, and combinations of blocks in the block diagram and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or operations. , or can be implemented using a combination of specialized hardware and computer instructions.

The embodiments of the present application have been described above. The above description is illustrative, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims (10)

1. A voltage arc detection circuit, characterized by comprising: Rectifier circuit, integrating circuit, average filter circuit, NAND gate logic circuit, NOR gate logic circuit and comparator; The first signal output end of the NAND gate logic circuit is connected to the power output device and is used to control the start and stop of the power output device; The power output device is connected to the rectifier circuit; The rectifier circuit is connected to the integrating circuit and the average filter circuit respectively; The second signal output terminal of the integrating circuit and the third signal output terminal of the average filter circuit are connected to the comparator; The NOR gate logic circuit includes a fourth signal output terminal, a first timing signal input terminal and a second timing signal input terminal. The fifth signal output terminal of the comparator and the first timing signal input terminal are connected to the NAND gate logic circuit connection; The fourth signal output terminal is connected to the integrating circuit and is used to control the working state of the integrating circuit. The working state includes an integrating state and a clearing state. 2. The voltage arc detection circuit according to claim 1, characterized in that, The integrating circuit includes a first operational amplifier U1, a resistor R1, a capacitor C1 and a MOS transistor Q1; One end of the resistor R1 is connected to the rectifier circuit, and the other end of the resistor R1 is connected to the first inverting input end of the first operational amplifier U1; The capacitor C1 is connected between the first inverting input terminal and the second signal output terminal. The second signal output terminal is the first signal output terminal of the first operational amplifier U1. A signal output terminal is connected to the first input terminal of the comparator; The MOS transistor Q1 is connected in parallel with the capacitor C1, and the fourth signal output terminal is connected with the gate of the MOS transistor Q1. 3. The voltage arc detection circuit according to claim 1, characterized in that, The average filter circuit includes a second operational amplifier U3, a resistor R3, a resistor R4, a resistor R5, a capacitor C2 and a capacitor C3; One end of the resistor R4 is connected to the rectifier circuit, and the other end of the resistor R4 is connected to the second inverting input end of the second operational amplifier U3; The capacitor C2 is connected between the second inverting input terminal and the second signal output terminal of the second operational amplifier U3; One end of the resistor R5 is connected to the second signal output end, and the other end of the resistor R5 is connected to the second input end of the comparator; One end of the capacitor C3 is connected to the second input end, and the other end of the capacitor C3 is connected to ground; the node where the resistor R5 and the capacitor C3 intersect is the third signal output end; The resistor R3 is connected in parallel with the capacitor C2. 4. The voltage arc detection circuit according to claim 2, characterized in that, A parasitic diode is provided between the source and drain of the MOS transistor Q1. 5. The voltage arc detection circuit according to claim 1, characterized in that, The first signal output terminal is connected to a device control circuit, and the device control circuit is used to control starting and stopping of the power output device. 6. A control method for a voltage arc detection circuit, characterized in that it is used to control the voltage arc detection circuit according to any one of claims 1 to 5 to perform voltage arc detection, including: Collect the output voltage of the power output device, and input the rectified voltage obtained after rectifying the output voltage into the integrating circuit and the average filter circuit; The first timing signal is input to the first timing signal input terminal of the NOR gate logic circuit, the second timing signal value is input to the second timing signal input terminal of the NOR gate logic circuit, and the fourth timing signal input terminal of the NOR gate logic circuit is input. The signal output terminal outputs a first level signal; The working state of the integrating circuit is controlled according to the first level signal, and when the working state is a clear state, the second signal output terminal of the integrating circuit outputs zero; When the working state is an integration state and the first timing signal is high level, the first voltage signal output by the second signal output terminal and the third signal output terminal of the average filter circuit are compared through the comparator. Compare the output second voltage signal, and determine the second level signal output by the first signal output terminal of the NAND gate logic circuit based on the comparison result; Control starting and stopping of the power output device according to the second level signal. 7. The control method of the voltage arc detection circuit according to claim 6, characterized in that, Controlling the working state of the integrating circuit according to the first level signal includes: If the first level signal is a high level signal, the MOS transistor Q1 of the integrating circuit is controlled to be turned on. 8. The control method of the voltage arc detection circuit according to claim 6, characterized in that, Determining the second level signal output by the first signal output terminal of the NAND gate logic circuit based on the comparison result includes: If the first voltage signal is greater than the second voltage signal, the comparator outputs a low level, and the second level signal is a high level signal; If the first voltage signal is less than or equal to the second voltage signal, the comparator outputs a high level, and the second level signal is a low level signal. 9. The control method of the voltage arc detection circuit according to claim 6, characterized in that, Controlling the start and stop of the power output device according to the second level signal includes: If the second level signal is a low level signal, the power output device is controlled to shut down through the device control circuit; If the second level signal is a high level signal, the startup state of the power output device is maintained. 10. The control method of the voltage arc detection circuit according to claim 6, characterized in that: The first voltage signal is calculated through a first formula, and the first formula is: V＝(U1+U2+U3+....+Un-1+Un)/n Among them, V is the first voltage signal, U1, U2, U3...Un-1 and Un are the rectified voltages corresponding to each collected output voltage, and n is the value of the output voltage collected in one collection cycle. quantity; The second voltage signal is calculated through a second formula, and the second formula is: P＝(V1+V2+V3+....+Vm-1+Vm)/m Wherein, P is the second voltage signal, V1, V2, V3...Vm-1 and Vm are the first voltage signals corresponding to each collection cycle, and m is the number of cycles of the collection cycle.