JP2013030524A - Method of manufacturing light-emitting chip, light-emitting chip, and element group formation substrate - Google Patents

Abstract

When a light emitting chip is manufactured by dividing a plurality of semiconductor light emitting elements formed on a growth substrate, the productivity of the light emitting chip is improved.
A bonding step (S13) for bonding an element group forming substrate having a growth substrate and a plurality of semiconductor light emitting elements and a base at a bonding portion, and a growth substrate separation for separating the growth substrate from these laminates A step (S14), a supporting substrate bonding step (S15) for bonding a plurality of semiconductor light emitting elements, a bonded portion and a bonded portion of the base portion to the base material with a wax layer, and a base portion and a bonded portion for the bonded body External electrode forming step (S17 to S22) for forming an external electrode penetrating, a supporting substrate separating step for separating the wax layer and the base material from the adhesive body on which the external electrode is formed, and the external electrode formed on the base material And a dividing step of dividing the base portion and the joint portion with respect to the joined body separated.
[Selection] Figure 3

Description

  The present invention relates to a light emitting chip manufacturing method, a light emitting chip, and an element group forming substrate.

As a prior art, providing a semiconductor structure including a light emitting layer disposed between an n-type region and a p-type region and grown on a growth substrate; attaching the semiconductor structure to a carrier by at least one interconnect; An isolation method comprising introducing into the cavity between the semiconductor structure and the carrier an underfill that forms a rigid support for the semiconductor structure and removing the growth substrate. Exists (see Patent Document 1).
That is, in Patent Document 1, (1) a plurality of flip chip (FC) light emitting elements are formed on GaN grown on a growth substrate (sapphire substrate) made of sapphire, and (2) a plurality of FC light emission. The device is divided into individual sapphire substrates, and (3) a plurality of FC light emitting devices with sapphire substrates (hereinafter referred to as chips) are mounted on a submount, and (4) a plurality of FC mounted on a submount. Each chip is filled with underfill. (5) The sapphire substrate is removed from each chip by a laser lift-off process (LLO) to leave a plurality of FC light emitting elements on the submount. (6) Each submount is separated. A method of separating and mounting on a package is disclosed.

International Publication No. 2006/131844

However, as described in Patent Document 1, a group III nitride semiconductor layer grown on a growth substrate such as sapphire is processed to form a plurality of semiconductor light emitting devices, and then a plurality of semiconductors are formed for each growth substrate. When the method of dividing into light emitting elements is adopted, it is necessary to subsequently remove the sapphire substrate for each semiconductor light emitting element, leading to a decrease in productivity and cost increase of the light emitting chip.
An object of the present invention is to improve the productivity of a light-emitting chip when a light-emitting chip is manufactured by dividing a plurality of semiconductor light-emitting elements formed on a growth substrate.

According to the present invention, the inventions according to the following [1] to [14] are provided.
[1] A surface on which a semiconductor light emitting element is formed in an element group forming substrate, in which a plurality of semiconductor light emitting elements having a group III nitride semiconductor layer are formed on the surface of the first substrate, and a second substrate different from the first substrate A bonding step of bonding the first surface of the first surface via a bonding portion;
A first substrate separating step for separating the first substrate from the stacked body in which the element group forming substrate, the bonding portion, and the second substrate are stacked;
An exposed surface in which the plurality of semiconductor light emitting elements are exposed in a joined body in which the plurality of semiconductor light emitting elements and the second substrate are joined via the joint, and one of the third substrate different from the first substrate and the second substrate A bonding step of bonding the surface via the bonding portion;
With respect to the bonded body in which the bonded body and the third substrate are bonded via the bonded portion, the second substrate and the bonded portion are penetrated from the second surface side which is the back side of the first surface of the second substrate. And an external electrode forming step of forming an external electrode having one end connected to the semiconductor light emitting element and the other end exposed on the second surface side of the second substrate;
A third substrate separating step for separating the third substrate together with the bonding portion from the adhesive body on which the external electrode is formed;
A method for manufacturing a light-emitting chip, comprising: a dividing step of dividing a second substrate and a bonding portion with respect to a bonded body in which external electrodes are formed and a third substrate is separated.

[2] The junction is made of an insulating material containing a siloxane structure,
Before the bonding step, a precursor of an insulating material is applied to the first surface of the second substrate,
In the bonding step, the surface on which the semiconductor light emitting element is formed on the element group formation substrate and the surface on which the precursor is applied on the second substrate face each other, and heating is performed while applying pressure to the element group formation substrate and the second substrate. The method for producing a light-emitting chip as described in [1].
[3] The method for manufacturing a light-emitting chip according to [1] or [2], wherein in the element group forming substrate, the first substrate is made of a sapphire single crystal.
[4] The element group forming substrate is provided with a positive internal electrode and a negative internal electrode for each of the plurality of semiconductor light emitting elements,
In the external electrode forming step, a positive external electrode that passes through the second substrate and the junction and is connected to a positive internal electrode provided in the semiconductor light emitting element, and passes through the second substrate and the junction and passes through the semiconductor light emitting element. The method for manufacturing a light-emitting chip according to any one of [1] to [3], wherein a negative external electrode connected to a negative internal electrode provided on the substrate is formed.
[5] The external electrode forming step
With respect to the bonded body in which the bonded body and the third substrate are bonded via the bonded portion, the second substrate and the bonded portion are penetrated from the second surface side which is the back side of the first surface of the second substrate. A through hole forming step of forming a through hole;
An insulating portion forming step of forming an insulating portion on the inner wall surface of the through hole formed through the second substrate and the joint portion;
[1] to [4], further comprising a filling step of filling a through hole formed through the second substrate and the bonding portion and having an insulating portion formed on the inner wall surface with a conductive material. The manufacturing method of the light emitting chip in any one.
[6] The method for manufacturing a light-emitting chip according to any one of [1] to [5], wherein the second substrate is made of a silicon single crystal.

[7] A surface on which the semiconductor light emitting element is formed in the element group forming substrate, in which a plurality of semiconductor light emitting elements having a group III nitride semiconductor layer are formed on the surface of the first substrate, and a second substrate different from the first substrate A bonding step of bonding the first surface of the first surface via a bonding portion;
From the second surface side, which is the back side of the first surface of the second substrate, to the stacked body in which the element group forming substrate, the bonding portion, and the second substrate are stacked, the second substrate and the bonding portion are penetrated. And an external electrode forming step of forming an external electrode having one end connected to the semiconductor light emitting element and the other end exposed on the second surface side of the second substrate;
A first substrate separation step of separating the first substrate from the laminate in which the external electrode is formed;
A dividing step of dividing the second substrate and the bonding portion with respect to the bonded body in which the plurality of semiconductor light emitting elements and the second substrate are bonded via the bonding portion, in which the external electrode is formed and the first substrate is separated; A method for manufacturing a light-emitting chip including:

[8] A first semiconductor layer made of a group III nitride semiconductor having a first conductivity type, a light emitting layer made of a group III nitride semiconductor, provided in contact with the first semiconductor layer and emitting light when energized; A semiconductor light emitting device comprising a group III nitride semiconductor having a second conductivity type opposite to the first conductivity type, and a second semiconductor layer provided in contact with the light emitting layer;
A base provided opposite to the second semiconductor layer provided in the semiconductor light emitting device;
A junction provided between the semiconductor light emitting element and the base, and joining the semiconductor light emitting element and the base;
A first electrode provided through the base and the joint, one end of which is electrically connected to the first semiconductor layer in the semiconductor light emitting element, and the other end is exposed to the outside from the base;
A light-emitting chip that includes a second electrode that is provided through the base and the joint, has one end electrically connected to the second semiconductor layer of the semiconductor light-emitting element, and the other end exposed to the outside from the base.

[9] The light-emitting chip according to [8], further including an insulating portion that is provided in the base portion and the joint portion and electrically insulates the first electrode and the second electrode.
[10] The light-emitting chip according to [8] or [9], wherein the base is made of silicon single crystal, and the junction includes silicon oxide.
[11] The light-emitting chip according to any one of [8] to [10], wherein the semiconductor light-emitting element has an uneven surface on the end surface on the first semiconductor layer side as viewed from the light-emitting layer.

[12] a base having a plate-like structure;
A plurality of semiconductor light emitting devices each having a group III nitride semiconductor layer;
A bonding portion for bonding a plurality of semiconductor light emitting elements in a state of being aligned to one surface of the base portion,
An element group forming substrate having a plurality of external electrodes formed through the base and the junction corresponding to each of the plurality of semiconductor light emitting elements and supplying power to each of the plurality of semiconductor light emitting elements.

[13] Used in the growth process of a group III nitride semiconductor layer for forming a plurality of semiconductor light emitting elements, and the plurality of semiconductor light emitting elements are attached via the group III nitride semiconductor layer, and the plurality of semiconductor light emitting elements The element group forming substrate according to claim 12, further comprising a growth substrate disposed to face the base portion via the bonding portion.
[14] The plurality of semiconductor light emitting elements are formed of a first semiconductor layer made of a group III nitride semiconductor having a first conductivity type, a group III nitride semiconductor, and provided in contact with the first semiconductor layer. A light-emitting layer that emits light when energized, and a second semiconductor layer that is formed of a group III nitride semiconductor having a second conductivity type opposite to the first conductivity type and is provided in contact with the light-emitting layer,
The external electrode is provided through the base and the joint, and has one end electrically connected to the first semiconductor layer in the semiconductor light emitting device and the other end exposed to the outside from the base, the base and the joint. [12] or [13], wherein one end side is electrically connected to the second semiconductor layer in the semiconductor light emitting device, and the other end side is exposed to the outside from the base. ] The element group formation board | substrate of description.

  According to the present invention, when a light emitting chip is manufactured by dividing a plurality of semiconductor light emitting elements formed on a growth substrate, the productivity of the light emitting chip can be improved.

It is a perspective view of an example of the light emitting chip to which this embodiment was applied. It is sectional drawing of the light emitting chip shown in FIG. 4 is a flowchart illustrating an example of a method for manufacturing a light-emitting chip in the first embodiment. It is a flowchart which shows an example of the manufacturing method of an element group formation board | substrate. It is a figure which shows an example of the whole structure of an element group formation board | substrate. It is an enlarged view of one semiconductor light emitting element in an element group formation substrate. It is VII-VII sectional drawing in FIG. It is a figure which shows an example of the cross-sectional structure around the p side internal electrode in a semiconductor light-emitting device. It is a figure which shows an example of the cross-sectional structure of the n side internal electrode periphery in a semiconductor light-emitting device. FIG. 11 is a diagram for explaining an example of an element group forming substrate manufacturing process in step 11 and an example of a mounting board manufacturing process in step 12; It is a figure for demonstrating an example of the joining process of step 13. FIG. FIG. 10 is a diagram for explaining an example of a growth substrate separating step in Step 14; It is a figure for demonstrating an example of the support board | substrate adhesion process of step 15. FIG. It is a figure for demonstrating an example of the mounting board | substrate grinding | polishing process of step 16. FIG. FIG. 10 is a diagram for explaining an example of a via hole forming step in Step 17; It is a figure for demonstrating an example of the insulation part formation process of step 18. FIG. It is a figure for demonstrating an example of the barrier / seed layer formation process of step 19. FIG. FIG. 10 is a diagram for explaining an example of a plug portion forming process in step 20. It is a figure for demonstrating an example of the electrode formation surface grinding | polishing process of step 21. FIG. FIG. 11 is a diagram for explaining an example of an external pad forming process in step 22. It is a figure for demonstrating an example of the support substrate separation process of step 23. FIG. It is a figure for demonstrating an example of the light extraction surface processing process of step 24. FIG. It is a figure for demonstrating an example of the individualization process of step 25. FIG. It is a figure which shows an example of a structure of the light-emitting device carrying a light-emitting chip. It is a figure which shows an example of the mounting state of the light emitting chip in a light-emitting device. 6 is a flowchart illustrating an example of a method for manufacturing a light-emitting chip in a second embodiment. It is a figure for demonstrating an example of the mounting board | substrate grinding | polishing process of step 54. FIG. It is a figure for demonstrating an example of the via hole formation process of step 55. FIG. It is a figure for demonstrating an example of the insulation part formation process of step 56. FIG. FIG. 10 is a diagram for explaining an example of a barrier / seed layer forming step of Step 57; It is a figure for demonstrating an example of the plug part formation process of step 58. FIG. It is a figure for demonstrating an example of the electrode formation surface grinding | polishing process of step 59. FIG. FIG. 10 is a diagram for explaining an example of an external pad forming step in Step 60. It is a figure for demonstrating an example of the board | substrate separation process for growth of step 61. FIG.

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.
Embodiment 1
FIG. 1 is a perspective view of an example of a light-emitting chip 1 to which the exemplary embodiment is applied, and FIG. 2 is a cross-sectional view of the light-emitting chip 1 shown in FIG.
The light emitting chip 1 includes a semiconductor light emitting element 10 that emits light by power feeding, a mounting substrate 50 on which the semiconductor light emitting element 10 is mounted, and an insulating portion 60 that insulates the mounting substrate 50 and a power feeding system for the semiconductor light emitting element 10. And a p-side external electrode 70 constituting a positive feeding system for the semiconductor light emitting element 10 and an n-side external electrode 80 constituting a negative feeding system for the semiconductor light emitting element 10.

  In the light-emitting chip 1, the semiconductor light-emitting element 10 includes a base layer 13, an n-type semiconductor layer 14 stacked on the base layer 13, a light-emitting layer 15 stacked on the n-type semiconductor layer 14, and a light-emitting layer. 15 and a p-type semiconductor layer 16 stacked on the substrate 15. Further, in this semiconductor light emitting device 10, the stacked p type semiconductor layer 16, light emitting layer 15 and n type semiconductor layer 14 are integrated so that the upper surface of the n type semiconductor layer 14 is exposed upward in the drawing. In the region of the part, it is cut out in the thickness direction. And the lower surface in the figure exposed to the exterior in the light emitting chip 1 among the base layers 13 is a concavo-convex processed surface 13a subjected to concavo-convex processing.

Further, the semiconductor light emitting element 10 has a transparent conductive layer 17 that is transparent and conductive with respect to the light output from the light emitting layer 15 and is laminated on the p-type semiconductor layer 16.
Furthermore, the semiconductor light emitting element 10 has transparency and insulation with respect to the light output from the light emitting layer 15, and from the upper surface of the transparent conductive layer 17, the p-type semiconductor layer 16, the light emitting layer 15, and the n-type semiconductor layer. A transparent insulating layer 18 that is integrally laminated is provided so as to reach the upper surface of the n-type semiconductor layer 14 through the side surfaces of the 14. The transparent insulating layer 18 also has a function as a protective film for protecting the light emitting layer 15 and the like, and a material that is chemically stable and excellent in moisture resistance is suitable. The transparent insulating layer 18 has a function of increasing the reflection of light from the light emitting layer 15 under the following conditions in combination with a metal reflective film such as Ag or Al as a transparent low refractive index dielectric.

  Here, when the refractive index of the transparent conductive layer 17 at the emission wavelength λ (nm) of the light emitting layer 15 is the first refractive index n1, and the refractive index of the transparent insulating layer 18 is the second refractive index n2, both are n1. > N2 relationship. Then, reflection at the interface between the transparent conductive layer 17 and the transparent insulating layer 18 increases due to the difference in refractive index between the two (n1−n2), and the light extraction efficiency from the semiconductor light emitting element 10 is improved. The difference in refractive index is desirably 0.4 or more.

  Further, the transparent insulating layer 18 is provided with a plurality of through holes penetrating in the thickness direction of the transparent insulating layer 18. In the present embodiment, a plurality of through-holes are disposed, for example, above the transparent conductive layer 17 (16 in this example: see FIGS. 6 and 7 described later) and, for example, the n-type semiconductor layer 14 A plurality of (four in this example: see FIGS. 6 and 7 described later) are also arranged above the upper surface of the. Thereby, for example, in a state where the transparent insulating layer 18 is laminated on the transparent conductive layer 17, a part of the transparent conductive layer 17 is exposed through the plurality of through holes. For example, the n-type semiconductor layer 14 is exposed. In a state where the transparent insulating layer 18 is laminated on the upper surface of the n-type semiconductor layer, a part of the n-type semiconductor layer 14 is exposed through the plurality of through holes. Here, each of the plurality of through-holes provided in the transparent insulating layer 18 has a circular shape when viewed from above (see FIG. 6 described later), and the diameter of the through-holes approaches the transparent conductive layer 17. 2 has a so-called tapered cross section (see FIG. 2). The shape of the through hole formed in the transparent insulating layer 18 is optimally a circular shape without stress concentration, but may be a polygonal shape or an elliptical shape having a large radius of curvature at the corners. In the example shown in FIG. 2, the through hole reaches the boundary between the transparent insulating layer 18 and the transparent conductive layer 17. If the through hole does not penetrate the transparent conductive layer 17, a part of the through hole is transparent. It does not matter if it enters the conductive layer 17.

  Further, the semiconductor light emitting element 10 is further laminated on the transparent conductive layer 17 and the transparent insulating layer 18 laminated on the p-type semiconductor layer 16, and one electrode (positive electrode) is emitted when the light emitting layer 15 emits light. P-side internal electrode 20 functioning as Here, the p-side internal electrode 20 passes through a plurality of through holes provided in the transparent insulating layer 18, and a plurality (16 in this example) of p are provided so that one end thereof is in contact with the transparent conductive layer 17. The p-side internal formed on the side connection conductor 21 and the transparent insulating layer 18 and connected to the other ends of the plurality of p-side connection conductors 21 and used for electrical connection with the p-side external electrode 70 Pad 22. The plurality of p-side connection conductors 21 electrically improve the light emission efficiency and the light extraction efficiency of the entire light emitting layer 15 by causing a current to flow through the light emitting layer 15 at a uniform current density. Moreover, although it is desirable to arrange many fine through holes in the transparent insulating layer 18, the size of the through holes is preferably 1 to 20 μm because of variations in formation of the through holes and difficulty in the fine processing technique. It is a range. In the present embodiment, the p-side internal electrode 20 has a structure in which a plurality of p-side connection conductors 21 and the p-side internal pad 22 are integrated. This will be described later.

  Furthermore, the semiconductor light emitting element 10 is further laminated on the transparent insulating layer 18 laminated on the upper surface of the n-type semiconductor layer 14 and functions as the other electrode (negative electrode) when the light emitting layer 15 emits light. An n-side internal electrode 30 is provided. In the n-side internal electrode 30, the transparent insulating layer 18 formed on the upper surface of the n-type semiconductor layer 14 may or may not be present. Hereinafter, the case where the transparent insulating layer 18 is formed on the upper surface of the n-type semiconductor layer 14 will be described. Here, the n-side internal electrode 30 passes through a plurality of through holes provided in the transparent insulating layer 18, and a plurality of (in this example, four) are provided so that one end thereof is in contact with the upper surface of the n-type semiconductor layer 14. ) And the other end of each of the plurality of n-side connection conductors 31 and is used for electrical connection with the n-side external electrode 80. and an n-side internal pad 32. In the present embodiment, similar to the p-side internal electrode 20 described above, the n-side internal electrode 30 has a structure in which a plurality of n-side connection conductors 31 and n-side internal pads 32 are integrated. However, this will be described later.

  The semiconductor light emitting device 10 includes a p-side internal electrode 20, a peripheral edge of the p-side internal electrode 20, side surfaces of the p-type semiconductor layer 16, the light-emitting layer 15 and the n-type semiconductor layer 14, an n-side internal electrode 30 and an n-side internal. The protective layer 19 that protects the p-side internal electrode 20 and the n-side internal electrode 30 is provided by being integrally laminated over the periphery of the electrode 30. However, the protective layer 19 is a substantially central portion of a plurality of regions (9 regions each having a circular shape in this example) on the upper surface of the p-side internal electrode 20 and an upper surface of the n-side internal electrode 30. It is not provided in the part (in this example, one area configured in a circular shape). Thereby, in this semiconductor light emitting device 10, a part of the upper surface of the p-side internal electrode 20 is exposed to the outside, and a part of the upper surface of the n-side internal electrode 30 is exposed to the outside. When the light emitting chip 1 is viewed as a whole, the p-side external electrode 70 is connected to the exposed portion of the p-side internal electrode 20, and the n-side external electrode 80 is connected to the exposed portion of the n-side internal electrode 30. .

  As described above, the semiconductor light emitting element 10 provided in the light emitting chip 1 has the p-side internal electrode 20 and the n-side on one surface side opposite to the base layer 13 (more specifically, the uneven surface 13a). The internal electrode 30 is formed. In this semiconductor light emitting device 10, the p-side internal electrode 20 is a positive electrode and the n-side internal electrode 30 is a negative electrode, and a current is passed through the p-type semiconductor layer 16, the light-emitting layer 15, and the n-type semiconductor layer 14 via both. As a result, the light emitting layer 15 emits light.

The mounting substrate 50 constituting the light emitting chip 1 has a plate-like shape, and is a base portion disposed on the side facing the p-side internal electrode 20 and the n-side internal electrode 30 provided in the semiconductor light emitting element 10. 51 and a base 52 and a semiconductor light emitting element 10 are provided so as to be in contact with both, and a base 52 and a semiconductor light emitting element 10 are joined to each other. The joint portion 52 is provided so as to fill the unevenness existing on the electrode formation surface side of the semiconductor light emitting element 10. If this bonding is insufficient and a gap exists between the semiconductor light emitting element 10 and the mounting substrate 50, a growth substrate separation step using LLO described later (see step 14 shown in FIG. 3). ), The generation of nitrogen gas may cause cracks at the locations where voids exist (2GaN → 2Ga + N ₂ ↑).

  In addition, in the upper part of the p-side internal electrode 20 in the figure, a plurality of through holes (vias described later) penetrating the mounting substrate 50 (base 51, joint 52) and the protective layer 19 of the semiconductor light emitting element 10 are formed. Hall VH) is provided. In addition, a single through hole (via hole VH described later) that penetrates the mounting substrate 50 and the protective layer 19 of the semiconductor light emitting element 10 is provided in the upper portion of the n-side internal electrode 30 in the drawing. .

  Furthermore, the insulating portion 60 constituting the light emitting chip 1 is provided corresponding to the p-side external electrode 70 and the p-side internal electrode 20 in the semiconductor light emitting element 10, and is a positive electrode extending from the p-side external electrode 70 to the p-side internal electrode 20. Corresponding to the p-side insulating layer 61 that restricts the leakage of current to the mounting substrate 50 (base 51 and junction 52), the n-side external electrode 80, and the n-side internal electrode 30 in the semiconductor light emitting device 10 in the power supply path. An n-side insulating layer 62 that regulates current leakage to the mounting substrate 50 in the negative power supply path from the n-side internal electrode 30 to the n-side external electrode 80, and the outer side of the base 51 in the mounting substrate 50. And a p-n insulating layer 63 that restricts current leakage between the p-side external electrode 70 and the n-side external electrode 80. As is clear from FIG. 1, the pn insulating layer 63 is exposed on the upper surface of the light emitting chip 1.

  Among these, the p-side insulating layer 61 has a plurality of through-holes (vias to be described later) penetrating the mounting substrate 50 (base 51 and joint 52) above the p-side internal electrode 20 in the drawing of the semiconductor light emitting device 10. -It is provided so that each inner wall surface of hole VH) may be covered. One end side of each p-side insulating layer 61 is connected to the protective layer 19 formed on the upper surface of the p-side internal electrode 20 in the semiconductor light emitting element 10, and the other end side of each p-side insulating layer 61 is between pn It is connected to the insulating layer 63.

  Further, the n-side insulating layer 62 is a single through-hole (via hole / hole to be described later) penetrating the mounting substrate 50 (base 51 and joint 52) above the n-side internal electrode 30 in the drawing of the semiconductor light emitting device 10. VH) is provided so as to cover the inner wall surface. One end side of the n-side insulating layer 62 is connected to the protective layer 19 formed on the upper surface of the n-side internal electrode 30 in the semiconductor light emitting element 10, and the other end side of the n-side insulating layer 62 is connected to the inter-pn insulating layer 63. It is connected.

  Further, the p-side external electrode 70 as an example of the positive external electrode or the second electrode constituting the light-emitting chip 1 is a plurality of through holes provided above the p-side internal electrode 20 in the semiconductor light emitting element 10 in the figure. The p-side barrier / seed layer 71 provided so as to be in contact with the upper surface of the p-side internal electrode 20 and the p-side insulating layer 61, and the plurality of through holes are in contact with the p-side barrier / seed layer 71 and The p-side plug portion 72 provided so as to fill the through-hole and the upper portion of the mounting substrate 50 in the figure are provided so as to be in contact with the plurality of p-side plug portions 72 and the inter-pn insulating layer 63 and are electrically connected to the outside. And a p-side external pad 73 used for simple connection.

  On the other hand, the negative external electrode or the n-side external electrode 80 as an example of the first electrode constituting the light-emitting chip 1 is a single penetration provided above the n-side internal electrode 30 in the semiconductor light emitting element 10 in the figure. An n-side barrier / seed layer 81 provided so as to be in contact with the upper surface of the n-side internal electrode 30 and the n-side insulating layer 62 in the hole, and the n-side barrier / seed layer 81 in contact with the single through-hole; The n-side plug portion 82 provided so as to fill the through-hole, and the single n-side plug portion 82 and the pn insulating layer 63 are provided in the upper part of the mounting substrate 50 in the drawing, and are electrically connected to the outside. And an n-side external pad 83 used for general connection.

  When the light-emitting chip 1 is used in a flip-chip connection as shown in FIG. 25 or the like described later, the p-side external pad 73 in the p-side external electrode 70 and the n-side external electrode in the n-side external electrode 80 shown in FIG. Solder bumps may be formed on the pads 83 in advance. The solder bump is preferably a eutectic metal having a low melting point (less than 400 ° C.) such as AuSn. The solder bump used for such a purpose is desirably a thick film having a thickness of 1 μm or more. For example, it is desirable to form by a plating method from the viewpoint of productivity.

FIG. 3 is a flowchart showing an example of a method for manufacturing the light-emitting chip 1 according to the first embodiment.
In the present embodiment, first, an element group forming substrate 40 (see FIG. 5 described later) formed by forming a plurality of semiconductor light emitting elements 10 on one surface of a wafer-like growth substrate 11 (see FIG. 7) described later. ) Is manufactured (step 11).
Separately from the element group forming substrate 40, a mounting substrate manufacturing process for manufacturing a mounting substrate 50 in which the bonding portion 52 is laminated on one surface of the wafer-like base 51 is executed (step 12).
Next, the formation surface of each semiconductor light emitting element 10 in the element group formation substrate 40 obtained in step 11 and the formation surface of the bonding portion 52 in the mounting substrate 50 obtained in step 12 are opposed to each other. Then, a bonding process for bonding the element group forming substrate 40 and the mounting substrate 50 is performed (step 13).

After step 13, a growth substrate separation step as an example of a first substrate separation step is performed to separate the growth substrate 11 from the stacked body of the element group formation substrate 40 and the mounting substrate 50 (step 14).
After step 14, the bonded body of the element group formation substrate 40 and the mounting substrate 50 from which the growth substrate 11 has been separated is used for supporting in place of the growth substrate 11 in a portion where the growth substrate 11 is attached. A supporting substrate bonding process as an example of a bonding process for bonding the substrate 90 is performed (step 15).

After step 15, the base 51 provided on the mounting substrate 50 is polished to be thinned with respect to the bonded body of the element group forming substrate 40 and the mounting substrate 50 and the supporting substrate. A substrate polishing process is executed (step 16).
After step 16, via holes VH are formed in the adhesive body whose base 51 is polished to expose the p-side internal electrode 20 and the n-side internal electrode 30 of each semiconductor light emitting element 10 from the mounting substrate 50 side. A via hole forming process as an example of the through hole forming process is executed (step 17).
After step 17, an insulating portion forming step for forming the insulating portion 60 (p-side insulating layer 61, n-side insulating layer 62, and inter-pn insulating layer 63) is performed on the adhesive formed up to the via hole VH. (Step 18).

After step 18, a barrier / seed layer forming step for forming the p-side barrier / seed layer 71 and the n-side barrier / seed layer 81 is performed on the adhesive body on which the insulating portion 60 is formed (step 19).
As an example of the filling step, after step 19, the p-side plug portion 72 and the n-side plug portion 82 are formed on the adhesive body in which the p-side barrier / seed layer 71 and the n-side barrier / seed layer 81 are formed. The plug portion forming step is executed (step 20).
After the step 20, the electrode forming surface polishing for polishing the base 51 side of the mounting substrate 50 to expose the inter-pn insulating layer 63 is performed on the adhesive formed with the p-side plug portion 72 and the n-side plug portion 82. The process is executed (step 21).
External pads for forming the p-side external pad 73 and the n-side external pad 83 on the inter-pn insulating layer 63 for the adhesive that has been subjected to polishing for exposing the inter-pn insulating layer 63 after step 21. A formation process is executed (step 22).
In the present embodiment, the process from the via hole forming process in step 17 to the external pad forming process in step 22 corresponds to the external electrode forming process.

After step 22, a supporting substrate separating step as an example of a third substrate separating step is performed, in which the supporting substrate 90 is separated from the adhesive formed with the p-side external pad 73 and the n-side external pad 83. (Step 23).
After step 23, the light extraction surface processing is performed by performing uneven processing on the surface of the base layer 13 to form the uneven processing surface 13 a for the joined body of the element group forming substrate 40 and the mounting substrate 50 from which the supporting substrate 90 is separated. The process is executed (step 24).
After the step 24, the element group forming substrate 40 and the mounting substrate 50 on which the uneven surface 13a is formed are cut to form a single element group forming substrate 40 as a plurality of semiconductors. An individualization step as an example of a division step for dividing the light emitting element 10 into individual pieces is executed (step 25).

Subsequently, the element group forming substrate manufacturing process of step 11 described above will be described more specifically.
FIG. 4 is a flowchart showing an example of a method for manufacturing the element group forming substrate 40.
In this example, first, on one surface of a wafer-like growth substrate 11 (see FIG. 7 described later), an intermediate layer 12 (see FIG. 7 described later), a base layer 13, an n-type semiconductor layer 14, and a light emitting layer 15. Then, a semiconductor layer stacking step for sequentially stacking the p-type semiconductor layer 16 is executed (step 111).
After step 111, a transparent conductive layer forming step for further forming transparent conductive layer 17 on p-type semiconductor layer 16 is executed (step 112).
After step 112, a partial region (in this example, from above) of the region where each semiconductor light emitting element 10 is to be formed is applied to the laminated transparent conductive layer 17, p type semiconductor layer 16, light emitting layer 15 and n type semiconductor layer 14. A digging process for exposing the upper surface of the n-type semiconductor layer 14 is performed by digging up one region of the four corners when viewed (step 113).
After step 113, a transparent insulating layer forming step for forming the transparent insulating layer 18 provided with a plurality of through holes corresponding to the formation planned regions of the respective semiconductor light emitting elements 10 is executed (step 114).
After step 114, the p-side internal electrode 20 is formed on the transparent insulating layer 18 on the transparent conductive layer 17 corresponding to the formation region of each semiconductor light emitting element 10, and the formation region of each semiconductor light emitting element 10 is formed. An internal electrode forming step is performed for forming the n-side internal electrode 30 on the transparent insulating layer 18 on the n-type semiconductor layer 14 corresponding to (step 115).
After step 115, a protective layer forming step for forming protective layer 19 is performed so as to cover the upper surface of each semiconductor light emitting element 10 including p-side internal electrode 20 and n-side internal electrode 30 (step 116).
After step 116, a groove forming process for forming a plurality of grooves T (see FIG. 5B described later) along the vertical direction and the horizontal direction so as to partition the formation planned regions of the respective semiconductor light emitting elements 10. This is executed (step 117), and the element group forming substrate 40 is obtained.
In the element group forming substrate manufacturing process, the through hole is not formed in the protective layer 19 provided on the p-side internal electrode 20, and the protective layer 19 provided on the n-side internal electrode 30 is not formed. No through holes are formed.

Now, the configuration of the element group formation substrate 40 obtained by the above-described procedure will be described in more detail.
FIG. 5 is a diagram showing an example of the entire configuration of the element group formation substrate 40, and here, a top view of the element group formation substrate 40 as viewed from the formation surface side of each semiconductor light emitting element 10 is shown. Here, FIG. 5A shows the element group forming substrate 40 before the protective layer forming process of step 116 is executed and the groove forming process of step 117 is executed, and FIG. The element group formation board | substrate 40 after performing this groove part formation process is shown.
6 is an enlarged view of one semiconductor light emitting element 10 in the element group forming substrate 40 shown in FIG. 5B, and FIG. 7 is a sectional view taken along line VII-VII in FIG.

  The element group forming substrate 40 includes a wafer-like growth substrate 11, an intermediate layer 12 stacked on one surface of the growth substrate 11, and a plurality of semiconductor light emitting elements 10 formed on the intermediate layer 12. Prepare. In this example, the base layer 13 provided in each semiconductor light emitting element 10 is stacked on the intermediate layer 12, so that one growth substrate 11 and a plurality of semiconductor light emitting elements 10 are intermediate. An element group forming substrate 40 integrated through the layer 12 is configured.

  Each groove T formed in the element group formation substrate 40 is provided on the formation surface side of each semiconductor light emitting element 10. Each trench T is dug up to the intermediate layer 12 between the semiconductor light emitting elements 10, and the growth substrate 11 is exposed at the bottom of each trench T. Each groove T is preferably formed so as not to enter the growth substrate 11.

  Further, in each semiconductor light emitting element 10 constituting the element group forming substrate 40, the p-side internal electrode 20 has a plurality of (4 × 4 = 16 in this example) p-side connection on the back side of the p-side internal pad 22. A conductor 21 is arranged, and in the n-side internal electrode 20, a plurality (2 × 2 = 4 in this example) of n-side connection conductors 31 are arranged on the back side of the n-side internal pad 32.

Hereinafter, the configuration of the element group formation substrate 40 and the configuration of the semiconductor light emitting element 10 in the present embodiment will be described. In this specification, AlGaN and GaInN may be described in a form in which the composition ratio of each element is omitted.
<Growth substrate>
The growth substrate 11 as an example of the first substrate is not particularly limited as long as a group III nitride semiconductor crystal is epitaxially grown on the surface, and various substrate materials can be used. Examples of the growth substrate 11 include sapphire, SiC, silicon, zinc oxide, magnesium oxide, manganese oxide, zirconium oxide, manganese zinc iron, magnesium aluminum oxide, zirconium boride, gallium oxide, indium oxide, lithium gallium oxide, A substrate formed of lithium aluminum oxide, neodymium gallium oxide, lanthanum strontium aluminum tantalum oxide, strontium titanium oxide, titanium oxide, hafnium oxide, tungsten oxide, molybdenum oxide, or the like can be used. In the present embodiment, sapphire whose principal surface is the C plane is used as the growth substrate 11. When sapphire is used as the growth substrate 11, an intermediate layer 120 (buffer layer) is preferably formed on the C surface of sapphire.

<Intermediate layer>
Intermediate layer 12 is preferably made of polycrystalline _{Al x Ga 1-x N (} 0 ≦ x ≦ 1) , more preferably a single-crystal _{Al x Ga 1-x N (} 0 ≦ x ≦ 1) For example, the thickness may be 10 to 500 nm made of polycrystalline Al _x Ga _1-x N (0 ≦ x ≦ 1). The intermediate layer 12 relaxes the difference in lattice constant between the growth substrate 11 and the underlayer 13, and forms a c-axis oriented single crystal layer on the (0001) plane (C plane) of the growth substrate 11. There is work to make it easier. Therefore, when the single crystal underlayer 13 is laminated on the intermediate layer 12, the underlayer 13 with better crystallinity can be laminated. In this example, the intermediate layer 12 is made of AlN.

<Underlayer>
As the underlayer 13, Al _x Ga _y In _z N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z = 1) can be used, but Al _x Ga _1-x N When (0 ≦ x <1) is used, it becomes easy to form the base layer 13 with good crystallinity. The thickness of the underlayer 13 is preferably 0.1 μm or more, and an Al _x Ga _1-x N layer with good crystallinity is more easily obtained when the thickness is greater than this thickness. Further, the film thickness of the underlayer 13 is preferably 10 μm or less. In this example, the underlayer 13 is made of undoped GaN.

<N-type semiconductor layer>
The n-type semiconductor layer 14 as an example of the first semiconductor layer having the first conductivity type (n-type in this example) includes an n-contact layer stacked on the growth substrate 11 side (in this example, the base layer 13). The n-cladding layer laminated on the n-contact layer is preferable. The n contact layer can also serve as the n clad layer. Further, the base layer 13 described above may be included in the n-type semiconductor layer 14.

The n contact layer is a layer for providing the n-side internal electrode 30. Therefore, the n contact layer is preferably exposed on the upper surface of the n-type semiconductor layer 14. As the n contact layer, an Al _x Ga _1-x N layer (0 ≦ x <1, preferably 0 ≦ x ≦ 0.5, more preferably 0 ≦ x ≦ 0.1) may be used.

  The n-cladding layer is a layer for injecting carriers into the light emitting layer 15 and confining carriers. The n-clad layer can be formed of AlGaN, GaN, GaInN, or the like. Alternatively, a heterojunction of these structures or a superlattice structure in which a plurality of layers are stacked may be used. When the n-cladding layer is formed of GaInN, it is desirable to make it larger than the band gap of GaInN of the light emitting layer 15.

When the n-cladding layer is a layer including a superlattice structure, the composition differs between the n-side first layer made of a group III nitride semiconductor having a thickness of 10 nm or less and the n-side first layer. In addition, it may include a structure in which an n-side second layer made of a group III nitride semiconductor having a film thickness of 10 nm or less is stacked.
The n-clad layer may include a structure in which n-side first layers and n-side second layers are alternately and repeatedly stacked. In this case, an alternate structure of GaInN and GaN or It is preferable to have an alternating structure of GaInN having different compositions.

<Light emitting layer>
As the light emitting layer 15, a single quantum well structure or a multiple quantum well structure can be employed.
As a well layer having a quantum well structure, a group III nitride semiconductor layer made of Ga _1-y In _y N (0 <y <0.4) is usually used. The film thickness of the well layer can be a film thickness that provides a quantum effect, for example, 1 to 10 nm, and preferably 2 to 6 nm, from the viewpoint of light emission output.
Further, in the case of the light emitting layer 15 having a multiple quantum well structure, the Ga _{1 -y} In _y N is used as a well layer, and Al _z Ga _{1 -z} N (0 ≦ z <0.3) having a band gap energy larger than that of the well layer. ) As a barrier layer. The well layer and the barrier layer may or may not be doped with impurities.

<P-type semiconductor layer>
The p-type semiconductor layer 16 as an example of the second semiconductor layer having the second conductivity type (p-type in this example) includes a p-clad layer laminated on the light emitting layer 15 and a p-contact laminated on the p-clad layer. It is preferable to comprise with a layer. However, the p-contact layer can also serve as the p-cladding layer.

The p-cladding layer is a layer that performs confinement of carriers in the light emitting layer 15 and injection of carriers. The p-cladding layer is not particularly limited as long as it has a composition larger than the band gap energy of the light-emitting layer 15 and can confine carriers in the light-emitting layer 15. For example, Al _x Ga _1-x N (0 < x ≦ 0.4) can be used.
When the p-cladding layer is made of such AlGaN, it is preferable in terms of confining carriers in the light emitting layer 15. The thickness of the p-clad layer is not particularly limited, but is preferably 1 to 400 nm, more preferably 5 to 100 nm.
Further, the p-cladding layer may have a superlattice structure in which a plurality of layers are stacked. In this case, it is preferable to have an alternating structure of AlGaN and AlGaN or an alternating structure of AlGaN and GaN.

The p contact layer is a layer for providing the p-side internal electrode 20 via the transparent conductive layer 17. The p contact layer is preferably Al _x Ga _1-x N (0 ≦ x ≦ 0.4). It is preferable that the Al composition in the p contact layer is in the above range in that good crystallinity and good ohmic contact with the transparent conductive layer 17 can be maintained.
Although the film thickness of a p contact layer is not specifically limited, 10-500 nm is preferable, More preferably, it is 50-200 nm. When the thickness of the p-contact layer is within this range, it is preferable in that the forward voltage Vf can be reduced.

<Transparent conductive layer>
The transparent conductive layer 17 is formed so as to cover almost the entire surface excluding the peripheral portion of the upper surface of the p-type semiconductor layer 16.
As the transparent conductive layer 17, it is preferable to use a material having an ohmic contact with the p-type semiconductor layer 16 and having a low contact resistance with the p-type semiconductor layer 16. Moreover, in this semiconductor light emitting element 10, since the light from the light emitting layer 15 is taken out to the base layer 13 side through the transparent conductive layer 17 and the transparent insulating layer 18 etc., the transparent conductive layer 17 was excellent in light transmittance. It is preferable to use one. Furthermore, in order to uniformly diffuse the current over the entire surface of the p-type semiconductor layer 16, it is preferable to use the transparent conductive layer 17 having excellent conductivity and having a small resistance distribution.

  The thickness of the transparent conductive layer 17 can be selected from the range of 2 nm to 500 nm. Here, if the thickness of the transparent conductive layer 17 is less than 2 nm, ohmic contact with the p-type semiconductor layer 16 may be difficult, and if the thickness of the transparent conductive layer 17 is greater than 500 nm, the light emitting layer is formed. In some cases, it is not preferable in terms of light transmittance with respect to the light output from 15 and the reflected light from the transparent insulating layer 18 and the like.

As the transparent conductive layer 17, for example, an oxide conductive material having good light transmittance with respect to light having a wavelength emitted from the light emitting layer 15 can be used. The transmittance for light having a wavelength output from the light emitting layer 15 is 90% or more, preferably 95% or more. In particular, a part of the oxide containing In is preferable in that both light transmittance and conductivity are superior to other transparent conductive films. As the conductive oxide containing In, for example, IZO (indium zinc oxide (In ₂ O ₃ —ZnO)), ITO (indium tin oxide (In ₂ O ₃ —SnO ₂ )), IGO (indium gallium oxide (In ₂ O ₃ —Ga ₂ O ₃ )), ICO (indium cerium oxide (In ₂ O ₃ —CeO ₂ )) and the like. In addition, for example, a dopant such as fluorine may be added. For example, an oxide containing no In, for example, a conductive material such as SnO ₂ , ZnO ₂ , or TiO ₂ doped with carriers may be used.
The transparent conductive layer 17 can be formed by providing these materials by conventional means well known in this technical field. Then, after forming the transparent conductive layer 17, heat treatment is performed to promote crystallization, thereby increasing the light transmittance of the transparent conductive layer 17, increasing the work function, and decreasing the sheet resistance, thereby reducing the p-type semiconductor layer. It is easy to make ohmic contact with 16 (p-GaN).

In the present embodiment, the transparent conductive layer 17 may have a crystallized structure, and in particular, a translucent material (for example, IZO) containing In ₂ O ₃ crystal having a hexagonal crystal structure or a bixbite structure. Or ITO) can be preferably used.
Moreover, as a film | membrane used for the transparent conductive layer 17, it is preferable to use the composition from which a specific resistance becomes low. For example, the ZnO concentration in IZO is preferably 1 to 20% by mass, more preferably 5 to 15% by mass, and particularly preferably 10% by mass.
Further, the transparent conductive layer 17 is preferably formed by, for example, a sputtering method from the viewpoint of improving the adhesion of the obtained film.

<Transparent insulation layer>
For example, as shown in FIG. 7, the transparent insulating layer 18 includes a transparent conductive layer 17, a p-type semiconductor layer 16 in which the transparent conductive layer 17 is not stacked, and an n-type semiconductor layer 14 in which the light emitting layer 15 is not stacked. It is laminated so as to cover it. Further, the transparent insulating layer 18 not only covers the surface of each layer, but also the side surfaces of the light emitting layer 15 and the p-type semiconductor layer 16, that is, the stepped wall formed by the p-type semiconductor layer 16 and the n-type semiconductor layer 14. The portion corresponding to this is covered, and the side surface of the transparent conductive layer 17 is also covered.

As described above, the transparent insulating layer 18 is transparent to the light output from the light emitting layer 15, and has a refractive index (second refractive index n2) lower than the refractive index (first refractive index n1) of the transparent conductive layer 17. ), And an insulating material. As a material constituting the transparent insulating layer 18, for example, SiO ₂ (silicon oxide), MgF ₂ (magnesium fluoride), CaF ₂ (calcium fluoride), Si ₃ N ₄ (silicon nitride), Al ₂ O ₃ (oxidation) Aluminum) can be used. In this example, the transparent insulating layer 18 is made of SiO ₂ (silicon dioxide) which is an optimum material having high insulation, low refractive index (1.4 to 1.5), and excellent moisture resistance. It was.

  Further, in the present embodiment, the thickness of the transparent insulating layer 18 is H, and the emission wavelength λ (nm) of the light emitting layer 15 is divided by four times the second refractive index n2 that is the refractive index of the transparent insulating layer 18. When Q is Q, the film thickness H is set by the relationship of the following formula (1). However, A is an integer.

    H = AQ (1)

  The film thickness H of the transparent insulating layer 18 is set based on the following formula (2), that is, the film thickness H is in the range of 3λ / 4n2 or more (the film thickness H is 3Q or more. More preferably, it is 3Q or more and an odd multiple of Q). Here, the film thickness H (= AQ) is a film thickness range of (A−0.5) × Q ≦ H (= AQ) ≦ (A + 0.5) × Q centering on the AQ. . Furthermore, it is preferably 5Q or more for improving the light emission output. However, the film thickness H is preferably 20Q or less, more preferably 10Q or less, because production costs are limited and cracks that are the subject of the present invention are easily generated with an increase in film thickness. When the film thickness H of the transparent insulating layer 18 is selected from this range, the optical reflectance with respect to the light output from the light emitting layer 15 increases, and as a result, a high light emission output is obtained. In this example, the film thickness H of the transparent insulating layer 18 is H = 375 nm when, for example, A = 5, λ = 460 nm, and n2 = 1.5.

  3λ / 4n2 ≧ H (2)

<P-side internal electrode>
FIG. 8 is a diagram showing an example of a cross-sectional configuration around the p-side internal electrode 20 in the semiconductor light emitting device 10 of the present embodiment. Here, FIG. 8 is an enlarged view of the section around the p-side internal electrode 20 in FIG.

  The p-side internal electrode 20 as an example of the positive internal electrode is a p-adhesion layer laminated so as to be in contact with the transparent conductive layer 17 and the transparent insulating layer 18 on the side closest to the transparent conductive layer 17 and the transparent insulating layer 18. 201, p metal reflection layer 202 laminated on p adhesion layer 201, p diffusion prevention layer 203 laminated on p metal reflection layer 202, p bonding layer 204 laminated on p diffusion prevention layer 203, p A p-protective adhesion layer 205 is laminated on the bonding layer 204 and a protective layer 19 is further laminated thereon. In this embodiment, a plurality of p-side connection conductors 21 and p-side internal pads 22 are formed by the p adhesion layer 201, the p metal reflection layer 202, the p diffusion prevention layer 203, the p bonding layer 204, and the p protective adhesion layer 205. Constitutes the p-side internal electrode 20.

Hereinafter, each configuration of the p-side internal electrode 20 in the present embodiment will be described.
[P adhesion layer]
As shown in FIG. 8, the p-adhesion layer 201 is laminated on the transparent insulating layer 18 and the transparent conductive layer 17 exposed through each through-hole provided in the transparent insulating layer 18, and on the transparent conductive layer 17 P metal reflective layer 202 is laminated. This p adhesion layer 201 is provided in order to improve the physical adhesion of the materials constituting these three layers. However, when the adhesion between the transparent insulating layer 18 and the p metal reflection layer 202 is good, the p adhesion layer 201 can be omitted.

  Further, in the semiconductor light emitting device 10 of the present embodiment, among the light output from the light emitting layer 15, the light incident on the p-side internal electrode 20 side is converted into the transparent conductive layer 17, the transparent insulating layer 18 and the p metal reflection. Since it reflects to the base layer 13 side through the layer 202 etc., it is preferable to use the material excellent in the light transmittance as the p adhesion layer 201. Furthermore, since the current is uniformly diffused over the entire surface of the p-type semiconductor layer 16 from the p-side internal electrode 20, the p-adhesion layer 201 has excellent conductivity, has a small resistance distribution in the surface direction, and is transparent. It is preferable to use a material whose contact resistance with the layer 17 is kept low.

From these points, it is preferable to use a transparent conductive layer as the p adhesion layer 201. In this example, as the p-adhesion layer 201, a metal oxide having conductivity and having good light transmittance with respect to light having a wavelength emitted from the light emitting layer 15 is used. In particular, a metal oxide containing In is preferable in that both light transmittance and conductivity are superior to other transparent conductive films. As the conductive metal oxide containing In, for example, ITO (indium tin oxide (In ₂ O ₃ —SnO ₂ )), IZO (indium zinc oxide (In ₂ O ₃ —ZnO)), IGO (indium gallium oxide ( In ₂ O ₃ —Ga ₂ O ₃ )), ICO (indium cerium oxide (In ₂ O ₃ —CeO ₂ )) and the like. Particularly preferred is IZO (indium zinc oxide (In ₂ O ₃ —ZnO)).

  The thickness of the p adhesion layer 201 is preferably selected from the range of 1 nm to 50 nm for the above-described reason. When the film thickness of the p adhesion layer 201 is less than 1 nm, the adhesion with the transparent conductive layer 17 is lowered, and the contact resistance may be increased. On the other hand, when the film thickness of the p-adhesion layer 201 exceeds 50 nm, the light transmittance is lowered, and the light emission output in the obtained semiconductor light emitting device 10 is lowered. In this example, the thickness of the p adhesion layer 201 is desirably 1 to 5 nm, for example.

[P metal reflection layer]
As shown in FIG. 8, the p metal reflection layer 202 is laminated on the p adhesion layer 201, and the p diffusion preventing layer 203 is laminated thereon. The p metal reflection layer 202 is provided to reflect the light emitted from the light emitting layer 15 and passing through the transparent conductive layer 17 and the transparent insulating layer 18 toward the base layer 13 side. Here, in the present embodiment, by disposing the transparent insulating layer 18 and the p metal reflective layer 202 via the p adhesion layer 201, the transparent insulating layer 18 and the p metal reflective layer 202 are not in direct contact with each other. It has a structure. Further, since the p metal reflection layer 202 is one of the constituent elements of the p-side internal electrode 20, it is preferable to use a layer having a low resistance and a low contact resistance with the p-adhesion layer 201. .

  The p metal reflective layer 202 of the present embodiment is made of a metal such as silver, palladium, copper, aluminum, nickel, gold, platinum, and an alloy including at least one of them. In particular, the use of silver or a silver alloy as the p metal reflection layer 202 is preferable in that it has high light reflectivity with respect to light of all wavelengths in the visible light region output from the light emitting layer 15. Here, when silver is used for the p metal reflection layer 202, silver alloy is preferably used because heat resistance and high temperature and high humidity resistance (so-called migration suppression) may not be sufficient depending on the use environment. In particular, it is desirable to use a silver alloy containing palladium and copper.

  When silver or a silver alloy is used for the p metal reflection layer 202, it is preferable to use an oxide containing In, for example, a transparent conductive material such as IZO or ITO, as the material of the p adhesion layer 201. Here, when the p metal reflective layer 202 is directly laminated on the transparent insulating layer 18 without providing the p adhesion layer 201, the adhesion is remarkably reduced as compared with the case where the p adhesion layer 201 is provided.

  The thickness of the p metal reflective layer 202 is preferably selected from the range of 80 nm to 200 nm. When the film thickness of the p metal reflection layer 202 is less than 80 nm, the light reflectance by the p metal reflection layer 202 is lowered. Moreover, when the film thickness of the p metal reflective layer 202 exceeds 200 nm, the cost for manufacturing the semiconductor light emitting device 10 increases. In this example, the thickness of the p metal reflection layer 202 is 100 nm.

[P diffusion prevention layer]
As shown in FIG. 8, the p diffusion preventing layer 203 is laminated on the p metal reflective layer 202, and a p bonding layer 204 is laminated thereon. The p diffusion preventing layer 203 includes a metal (in this example, a silver alloy) that constitutes the p metal reflective layer 202 in a contact state, and a metal (in this example, gold (in detail, a silver alloy) in the contact state. (This will be described later). Here, in the present embodiment, the p metal reflection layer 202 and the p bonding layer 204 are disposed via the p diffusion preventing layer 203 so that the p metal reflection layer 202 and the p bonding layer 204 are in direct contact with each other. It has a structure that does not. Since the p-diffusion prevention layer 203 is one of the components of the p-side internal electrode 20, its own resistance is low and the contact resistance with the p-metal reflective layer 202 and the p-bonding layer 204 is kept low. It is preferable to use those that can be used. Note that the p-diffusion prevention layer 203 basically does not require the function of transmitting light from the light-emitting layer 15, and therefore does not need to have light transmission, unlike the p-adhesion layer 201 described above. For the p-diffusion prevention layer 203, it is desirable to use a refractory metal that is stable at a high temperature, such as titanium, tantalum, tungsten, molybdenum, chromium, platinum, palladium, or nickel. The p-diffusion prevention layer 203 may have a single-layer structure, but there is no suitable material that provides good adhesion to both the p-metal reflective layer 202 and the p-bonding layer 204 and does not alloy with them. In some cases, it is desirable to use a multilayer structure as described below.

  The p diffusion prevention layer 203 in the present embodiment includes a p first diffusion prevention layer 203a laminated on the p metal reflection layer 202, a p second diffusion prevention layer 203b laminated on the p first diffusion prevention layer 203a, A p third diffusion prevention layer 203c is formed on the p second diffusion prevention layer 203b, and a p bonding layer 204 is further laminated thereon.

  In the present embodiment, for example, tantalum is used as the p first diffusion prevention layer 203a, titanium is used as the p second diffusion prevention layer 203b, and platinum is used as the p third diffusion prevention layer 203c. Note that nickel may be used in place of titanium as the p second diffusion preventing layer 203b.

  Here, the p first diffusion prevention layer 203a and the p second diffusion prevention layer 203b not only suppress the diffusion of the metal (silver alloy in this example) constituting the p metal reflection layer 202 described above, but also the p third. It also has a function of suppressing the diffusion of the metal (platinum in this example) constituting the diffusion preventing layer 203c. The p third diffusion prevention layer 203c not only suppresses the diffusion of the metal (gold in this example) constituting the p bonding layer 204 described above, but also the metal (this example) constituting the p second diffusion prevention layer 203b. Has a function of suppressing diffusion of titanium).

  The thickness of the p first diffusion prevention layer 203a is preferably selected from the range of 20 nm to 200 nm. When the thickness of the p first diffusion prevention layer 203a is less than 20 nm, the barrier property between the p metal reflection layer 202 (in this example, a silver alloy) and the p third diffusion prevention layer 203c (in this example, platinum) is not good. In this example, silver and platinum may react. In addition, when the thickness of the p first diffusion prevention layer 203a exceeds 200 nm, the cost for manufacturing the semiconductor light emitting device 10 increases. In this example, the thickness of the p first diffusion prevention layer 203a is 50 nm to 100 nm.

  The thickness of the p second diffusion preventing layer 203b is preferably selected from 20 nm to 500 nm. When the thickness of the p second diffusion prevention layer 203b is less than 20 nm, there is a concern that the adhesion between the p second diffusion prevention layer 203b and the p third diffusion prevention layer 203c may be reduced. Furthermore, the barrier property between the p metal reflection layer 202 (in this example, a silver alloy) and the p third diffusion prevention layer 203c (in this example, platinum) becomes insufficient, and in this example, silver and platinum may react. Further, when the thickness of the p second diffusion preventing layer 203b exceeds 500 nm, the cost for manufacturing the semiconductor light emitting device 10 increases. In this example, the thickness of the p second diffusion preventing layer 203b is 300 nm.

  Furthermore, the film thickness of the p third diffusion preventing layer 203c is preferably selected from the range of 50 nm to 200 nm. If the thickness of the p third diffusion prevention layer 203c is less than 50 nm, the p second diffusion prevention layer 203b (titanium in this example) and the p bonding layer 204 (gold in this example) may react. Further, when the thickness of the p third diffusion preventing layer 203c exceeds 200 nm, the cost for manufacturing the semiconductor light emitting device 10 increases. In this example, the thickness of the p third diffusion prevention layer 203c is 100 nm.

[P bonding layer]
As shown in FIG. 8, the p bonding layer 204 is laminated on the p diffusion preventing layer 203, and the p protective adhesion layer 205 is laminated thereon. The p bonding layer 204 is provided to supply power to the p-side internal electrode 20 by being electrically connected to the p-side external electrode 70. Here, in the present embodiment, the p metal reflection layer 202 and the p bonding layer 204 are disposed via the p diffusion preventing layer 203 so that the p metal reflection layer 202 and the p bonding layer 204 are in direct contact with each other. It has a structure that does not. Moreover, since the p bonding layer 204 is one of the components of the p-side internal electrode 20, it is preferable to use a layer that has a low resistance and a low contact resistance with the p diffusion preventing layer 203. . Since the p bonding layer 204 basically does not require the function of transmitting the light from the light emitting layer 15 like the p diffusion preventing layer 203, the p bonding layer 204 does not have to be light transmissive.

  The p-bonding layer 204 in this embodiment may have a metal multi-layer structure or a gold single-layer structure as long as the uppermost layer, that is, the outermost surface layer exposed to the outside, is gold. May be. In the present embodiment, a gold single layer film is employed as the p bonding layer 204.

  The thickness of the p bonding layer 204 is preferably selected from the range of 100 nm to 2 μm. When the thickness of the p-bonding layer 204 is less than 100 nm, the shock absorption at the time of bonding decreases. Further, when the film thickness of the p bonding layer 204 exceeds 2 μm, the cost for manufacturing the semiconductor light emitting element 10 increases. In this example, the thickness of the p bonding layer 204 is 550 nm.

[P protective adhesive layer]
As shown in FIG. 8, the p protective adhesion layer 205 is laminated on the p bonding layer 204, and the protective layer 19 is laminated thereon. This p protective adhesion layer 205 is provided in order to enhance the physical adhesion of the materials constituting these two layers.

  The p protective adhesion layer 205 of the present embodiment is made of titanium. Note that tantalum may be used in place of titanium as the p protective adhesion layer 205.

  The thickness of the p protective adhesion layer 205 is preferably selected from the range of 5 nm to 50 nm. When the thickness of the p protective adhesion layer 205 is less than 5 nm, the adhesion between the p bonding layer 204 and the protective layer 19 is lowered. Further, when the thickness of the p protective adhesion layer 205 exceeds 20 nm, the working time in the etching process becomes long, and the cost for manufacturing the semiconductor light emitting device 10 increases. In this example, the thickness of the p protective adhesion layer 205 is 15 nm.

<N-side internal electrode>
FIG. 9 is a diagram illustrating an example of a cross-sectional configuration around the n-side internal electrode 30 in the semiconductor light emitting device 10 of the present embodiment. Here, FIG. 9 is an enlarged view of the section around the n-side internal electrode 30 in FIG.

  The n-side internal electrode 30 as an example of the negative internal electrode is an n layer that is laminated so as to be in contact with the n-type semiconductor layer 14 and the transparent insulating layer 18 on the side closest to the n-type semiconductor layer 14 and the transparent insulating layer 18. An adhesion layer 301, an n metal reflection layer 302 laminated on the n adhesion layer 301, an n diffusion prevention layer 303 laminated on the n metal reflection layer 302, and an n bonding layer 304 laminated on the n diffusion prevention layer 303 , And an n-protective adhesion layer 305 on which the protective layer 19 is further laminated. In this embodiment, a plurality of n-side connection conductors 31 and n-side internal pads 32 are formed by the n adhesion layer 301, the n metal reflection layer 302, the n diffusion prevention layer 303, the n bonding layer 304, and the n protective adhesion layer 305. Constitutes the n-side internal electrode 30.

Hereinafter, each configuration of the n-side internal electrode 30 in the present embodiment will be described.
[N adhesion layer]
As shown in FIG. 9, the n adhesion layer 301 is laminated on the n-type semiconductor layer 14 exposed through the transparent insulating layer 18 and each through hole provided in the transparent insulating layer 18. The n metal reflective layer 302 is laminated on the substrate. The n adhesion layer 301 is provided in order to improve the physical adhesion of the materials constituting these three layers and obtain ohmic contact with the n-type semiconductor layer 14 having a low contact resistance.

  Further, in the semiconductor light emitting device 10 of the present embodiment, among the light output from the light emitting layer 15, the light incident on the n-side internal electrode 30 side is passed through the transparent insulating layer 18, the n metal reflective layer 302, and the like. Therefore, it is preferable to use a material having excellent light transmittance for the n-adhesion layer 301 or a material having low light absorption and high light reflectivity. Furthermore, in order to diffuse the current from the n-side internal electrode 30 to the n-type semiconductor layer 14, the n-adhesion layer 301 has excellent conductivity, a small resistance distribution in the surface direction, and contact with the n-type semiconductor layer 14. It is preferable to use a material whose resistance is kept low.

  From these points, it is preferable to use a transparent conductive layer as the n adhesion layer 301. For example, as the n adhesion layer 301, a light-transmitting metal thin film made of a metal having conductivity and a low work function is formed. In the present embodiment, the n adhesion layer 301 is made of titanium. Moreover, you may use the transparent conductive layer which consists of metal oxides similarly to the p adhesion layer 201 mentioned above. Further, when the n metal reflective layer 302 is made of a material that performs the same function as the n adhesion layer 301, the n adhesion layer 301 can be omitted.

  The film thickness of the n adhesion layer 301 is preferably selected from the range of 1 nm to 50 nm for the reasons described above. When the film thickness of the n adhesion layer 301 is less than 1 nm, the adhesion with the n-type semiconductor layer 14 is lowered and the contact resistance may be increased. On the other hand, when the film thickness of the n-adhesion layer 301 exceeds 50 nm, the light transmittance is lowered and the resistance in the thickness direction (series resistance) is increased. Therefore, the forward voltage Vf in the obtained semiconductor light emitting device 10 is increased. Increase. In this example, the film thickness of the n adhesion layer 301 is 2 nm, for example.

[N metal reflective layer]
As shown in FIG. 9, the n metal reflection layer 302 is laminated on the n adhesion layer 301, and the n diffusion preventing layer 303 is laminated thereon. The n metal reflective layer 302 is provided to reflect the light emitted from the light emitting layer 15 and passing through the n-type semiconductor layer 14 and the transparent insulating layer 18 due to internal reflection or the like toward the base layer 13 side. ing. Here, in the present embodiment, by disposing the transparent insulating layer 18 and the n metal reflective layer 302 via the n adhesion layer 301, the transparent insulating layer 18 and the n metal reflective layer 302 are not in direct contact with each other. It has a structure. In addition, since the n metal reflective layer 302 is one of the components of the n-side internal electrode 30, it is preferable to use a material having a low resistance and a low contact resistance with the n adhesion layer 301. .

  The n metal reflective layer 302 of the present embodiment is made of a metal such as aluminum, palladium, copper, nickel, silver, neodymium, gold, platinum, or an alloy containing at least one of them. In particular, it is preferable to use an aluminum alloy having a low work function as the n metal reflection layer 302 in that the contact resistance with the n-type semiconductor layer 14 via the n adhesion layer 301 can be suppressed low.

  When aluminum or an aluminum alloy is used for the n metal reflective layer 302, the material of the n adhesion layer 301 is a light-transmitting metal thin film material such as titanium having a low contact resistance with the n-type semiconductor layer 14 and a low work function. It is preferable. Here, when the n metal reflective layer 302 is directly laminated on the transparent insulating layer 18 without providing the n adhesive layer 301, the adhesiveness is lowered as compared with the case where the n adhesive layer 301 is provided.

  The thickness of the n metal reflective layer 302 is preferably selected from the range of 80 nm to 200 nm. When the film thickness of the n metal reflective layer 302 is less than 80 nm, the light reflectance by the n metal reflective layer 302 is lowered. Moreover, when the film thickness of the n metal reflective layer 302 exceeds 200 nm, the cost for manufacturing the semiconductor light emitting element 10 increases. In this example, the thickness of the n metal reflective layer 302 is 100 nm.

[N diffusion prevention layer]
As shown in FIG. 9, the n diffusion preventing layer 303 is laminated on the n metal reflective layer 302, and the n bonding layer 304 is laminated thereon. The n diffusion prevention layer 303 includes a metal (in this example, an aluminum alloy) constituting the n metal reflective layer 302 in a contact state, and a metal (in this example, gold (details in detail) that constitute the n bonding layer 304 in a contact state. (This will be described later). Here, in the present embodiment, the n metal reflection layer 302 and the n bonding layer 304 are arranged via the n diffusion preventing layer 303 so that the n metal reflection layer 302 and the n bonding layer 304 are in direct contact with each other. It has a structure that does not. Further, since the n-diffusion prevention layer 303 is one of the components of the n-side internal electrode 30, its own resistance is low and the contact resistance with the n metal reflective layer 302 and the n bonding layer 304 is kept low. It is preferable to use those that can be used. Note that the n-diffusion prevention layer 303 basically does not need a function of transmitting light from the light-emitting layer 15, and therefore does not need to have light-transmitting properties, unlike the n-adhesion layer 301 described above. For the n-diffusion prevention layer 303, it is desirable to use a refractory metal that is stable at a high temperature, such as titanium, tantalum, tungsten, molybdenum, chromium, platinum, palladium, or nickel. The n-diffusion prevention layer 303 may have a single-layer structure, but there is no suitable material that can provide good adhesion to both the n-metal reflective layer 302 and the n-bonding layer 304 and does not alloy with them. In some cases, it is desirable to use a multilayer structure as described below.

  The n diffusion prevention layer 303 in the present embodiment includes an n first diffusion prevention layer 303a laminated on the n metal reflection layer 302, an n second diffusion prevention layer 303b laminated on the n first diffusion prevention layer 303a, An n third diffusion barrier layer 303c is stacked on the n second diffusion barrier layer 303b, and an n bonding layer 304 is further stacked thereon.

  Here, the n first diffusion prevention layer 303a and the n second diffusion prevention layer 303b not only suppress the diffusion of the metal (the aluminum alloy in this example) constituting the n metal reflection layer 302 described above, It also has a function of suppressing the diffusion of the metal (platinum in this example) constituting the diffusion prevention layer 303c. Further, the n third diffusion prevention layer 303c not only suppresses the diffusion of the metal (gold in this example) constituting the n bonding layer 304 described above, but also the metal (this example) constituting the n second diffusion prevention layer 303b. Has a function of suppressing diffusion of titanium).

  In this embodiment, the n first diffusion prevention layer 303a and the p first diffusion prevention layer 203a, the n second diffusion prevention layer 303b and the p second diffusion prevention layer 203b, and the n third diffusion prevention layer 303c and p. The third diffusion preventing layers 203c are made of the same material and the same thickness.

[N bonding layer]
As shown in FIG. 9, the n bonding layer 304 is laminated on the n diffusion preventing layer 303, and the n protective adhesion layer 305 is laminated thereon. The n bonding layer 304 is provided to supply power to the n-side internal electrode 30 by being electrically connected to the outside. Here, in the present embodiment, the n metal reflection layer 302 and the n bonding layer 304 are arranged via the n diffusion preventing layer 303 so that the n metal reflection layer 302 and the n bonding layer 304 are in direct contact with each other. It has a structure that does not. In addition, since the n bonding layer 304 is one of the components of the n-side internal electrode 30, it is preferable to use a layer having a low resistance and a low contact resistance with the n diffusion preventing layer 303. . Since the n bonding layer 304 basically does not require the function of transmitting the light from the light emitting layer 15 like the n diffusion preventing layer 303, the n bonding layer 304 does not need to be light transmissive.

  In this embodiment, the n bonding layer 304 and the p bonding layer 204 are made of the same material and the same thickness.

[N protective adhesion layer]
As shown in FIG. 9, the n protective adhesion layer 305 is laminated on the n bonding layer 304, and the protective layer 19 is laminated thereon. This n protective adhesion layer 305 is provided in order to improve the physical adhesion of the materials constituting these two layers.

  In this embodiment, the n protective adhesive layer 305 and the p protective adhesive layer 205 are made of the same material and the same thickness.

  In the present embodiment, the n third diffusion prevention is performed so as to cover the periphery (including side surfaces) of the n adhesion layer 301, the n metal reflection layer 302, the n first diffusion prevention layer 303a, and the n second diffusion prevention layer 303b. The layer 303c is stacked, and an n bonding layer 304 is stacked so as to cover the periphery (including side surfaces) of the n third diffusion prevention layer 303c. Further, the periphery of the n bonding layer 304 is excluded except for the part of the region. An n protective adhesion layer 305 is laminated so as to cover (including side surfaces). A protective layer 19 is laminated so as to cover the periphery of the n-side internal electrode 30 with respect to the n-type semiconductor layer 14 and the transparent insulating layer 18 except for the partial region.

  In this embodiment, the p-diffusion prevention layer 203 and the n-diffusion prevention layer 303 each have a three-layer configuration. However, the number of these constituent layers may be appropriately changed.

<Protective layer>
In the present embodiment, the p third diffusion prevention layer 203c covers the periphery (including side surfaces) of the p adhesion layer 201, the p metal reflection layer 202, the p first diffusion prevention layer 203a, and the p second diffusion prevention layer 203b. And a p-bonding layer 204 is laminated so as to cover the periphery (including side surfaces) of the p third diffusion prevention layer 203c, and the periphery (side surface) of the p-bonding layer 204 except for the part of the region. P protective adhesion layer 205 is laminated so as to cover the same. And the protective layer 19 is laminated | stacked so that the circumference | surroundings of the p side internal electrode 20 may be covered with respect to the transparent conductive layer 17 and the transparent insulating layer 18 except the said one part area | region.

The protective layer 19 is made of a material having insulating properties and excellent moisture resistance. As a material constituting the protective layer 19, for example, SiO ₂ (silicon oxide), Si ₃ N ₄ (silicon nitride), Al ₂ O ₃ (aluminum oxide) can be used. In this example, as the protective layer 19, SiO ₂ (silicon dioxide), which is an optimum material having high insulation and excellent moisture resistance, was used. In particular, an oxide such as SiO ₂ or Al ₂ O ₃ is preferable because it can form a firm bond with a precursor of an insulating material including a siloxane structure.

Then, the manufacturing method of the light emitting chip 1 shown in FIG. 3 is demonstrated in detail.
<< Element group forming board manufacturing process and mounting board manufacturing process >>
FIG. 10 is a diagram for explaining an example of the element group forming substrate manufacturing process in step 11 and an example of the mounting board manufacturing process in step 12. More specifically, FIG. 10A is a diagram showing an example of a cross-sectional configuration of the element group formation substrate 40 obtained by executing the element group formation substrate manufacturing process, and FIG. It is a figure which shows an example of the cross-sectional structure of the mounting board | substrate 50 obtained by performing the mounting board | substrate manufacturing process.

The element group forming substrate 40 shown in FIG. 10A has the same configuration as that described with reference to FIGS. That is, in the element group forming substrate 40, a plurality of semiconductor light emitting elements 10 separated by a plurality of grooves T are formed on one surface of one growth substrate 11 formed in a wafer shape via the intermediate layer 12. It is in the attached state. Here, a substrate having a diameter of 100 mm is used as the growth substrate 11.
On the other hand, the mounting substrate 50 shown in FIG. 10B has a configuration in which a bonding portion 52 is formed on one surface of one base portion 51 formed in a wafer shape.

  Here, the base 51 as an example of the second substrate is not particularly limited, and various substrate materials can be used. Examples of the base 51 include silicon, sapphire, SiC, zinc oxide, magnesium oxide, manganese oxide, zirconium oxide, manganese zinc iron, magnesium aluminum oxide, zirconium boride, gallium oxide, indium oxide, lithium gallium oxide, and lithium oxide. A substrate formed of aluminum, neodymium gallium oxide, lanthanum strontium aluminum tantalum oxide, strontium titanium oxide, titanium oxide, hafnium oxide, tungsten oxide, molybdenum oxide, or the like can be used. Further, as the base 51, a substrate made of glass can be used. Among these, silicon and glass have high heat dissipation and are preferable as the base 51. Furthermore, it is desirable that the size of one surface of the base portion 51 be equal to or greater than the size of the formation surface of each semiconductor light emitting element 10 in the growth substrate 11 of the element group formation substrate 40. In the present embodiment, undoped silicon having the (100) plane as the main surface is used as the base 51. In this example, the diameter of the base 51 made of silicon is 100 mm, and the thickness thereof is 525 μm. As the base 51, silicon doped with p-type impurities or silicon doped with n-type impurities may be used.

On the other hand, the bonding portion 52 constituting the mounting substrate 50 has good adhesion to the base 51 in the mounting substrate manufacturing process, and is to be bonded in the bonding process (in this example, provided on the element group forming substrate 40). In addition, the material is not particularly limited as long as the bonding property with the protective layer 19) made of SiO ₂ (silicon dioxide) is good, and various materials can be used. However, the bonding portion 52 has insulation, weather resistance, and chemical resistance, and is bonded to the element group formation substrate 40 at a temperature of 200 ° C. or lower, preferably 100 ° C. to 200 ° C., in a bonding step described later. It is desirable that the material be capable of. As the bonding portion 52, for example, an underfill adhesive used for mounting in a semiconductor process, SOG (Spin On Glass), SOD (Spin On Dielectric), or the like used for forming an insulating film in a semiconductor process may be used. it can. In the present embodiment, a material including a siloxane structure is used as the bonding portion 52. For example, as a precursor for forming the joint portion 52, a siloxane structure containing a hydrocarbon group having 1 to 10 carbon atoms or an aromatic substituent having 6 to 10 carbon atoms is used, and a crosslinking reaction such as an acrylic group or an epoxy group is further performed. Inorganic / organic hybrid materials including possible substituents are preferably used. The forming material (precursor) of the joint portion 52 including a siloxane structure has a liquid property before heat curing, and thus can be easily applied to one surface of the base portion 51, and by heat curing treatment. A non-liquid joint 52 is formed. In addition, depending on the material system to be used, the bonding portion 52 may be softened with heat due to the effect of a substituent of the material and have fluidity even after heat curing. As a precursor material containing a siloxane structure, for example, OCRT-11 manufactured by Tokyo Ohka Co., Ltd. can be used.

  In the mounting substrate manufacturing process, the base 51 made of silicon, the surface of which has been cleaned with hydrofluoric acid or ammonium fluoride, is set on a known spin coater, and the SOG solution is placed at the center of one surface of the base 51. By dripping and rotating the base 51, a joint 52 made of an SOG coating film is formed on one surface of the base 51. Thereafter, the bonding portion 52 formed on one surface of the base portion 51 is thermally cured to obtain the mounting substrate 50. In addition, in the joining process mentioned later, the adhesiveness of the base 51 and the junction part 52 can be improved by forming the junction part 52 after previously wash | cleaning the base part 51 with the fluorine-type solution mentioned above. . However, the present invention is not limited to this, and when a configuration is adopted in which an oxide film, that is, a layer made of silicon dioxide is formed on one surface of the base portion 51 made of silicon, and a bonding portion 52 is formed on this layer. In addition, it is possible to improve the adhesion between the base portion 51 and the joint portion 52 in the joining step described later.

<< Joining process >>
FIG. 11 is a diagram for explaining an example of the joining process in step 13. More specifically, FIG. 11 is a diagram showing an example of a cross-sectional configuration of a joined body of the element group forming substrate 40 and the mounting substrate 50 obtained by executing a joining step.

  In the bonding step, the formation surface of each semiconductor light emitting element 10 in the element group forming substrate 40 shown in FIG. 10A and the bonding portion 52 in the mounting substrate 50 shown in FIG. In the state they are heated, for example to 200 ° C. Then, depending on the material system to be used, the bonding portion 52 provided on the mounting substrate 50 is softened with heating so as to have fluidity, so that the concavities and convexities of the opposing element group forming substrate 40 are filled. Deform. At this time, it is desirable that the bonding portion 52 is not embedded in the groove portion T provided in the element group formation substrate 40. Then, after a predetermined time has elapsed, heating is stopped and cooling is performed, so that the element group forming substrate 40 and the base portion 51 of the mounting substrate 50 are bonded via the bonding portion 52.

<< Growth substrate separation process >>
FIG. 12 is a diagram for explaining an example of the growth substrate separating step in step 14. More specifically, FIG. 12 shows a joined body of the element group formation substrate 40 and the mounting substrate 50 (excluding the growth substrate 11 and the intermediate layer 12) obtained by executing the growth substrate separation step. FIG. 3 is a diagram showing an example of a cross-sectional configuration of a growth substrate 11 and an intermediate layer 12 separated from the joined body.

  In the growth substrate separating step, a so-called laser lift off (LLO) technique is used to separate the growth substrate 11 from the bonded body. More specifically, in the growth substrate separation step, first, the outer side of the growth substrate 11 (the growth substrate 11 in FIG. 11) is bonded to the joined body of the element group formation substrate 40 and the mounting substrate 50 shown in FIG. The laser beam is irradiated from the upper side) toward the inside of the element group formation substrate 40. This laser light irradiation is performed over almost the entire surface of one side of the growth substrate 11.

Here, in this embodiment, a KrF excimer laser is used as the laser light used in the LLO. The oscillation wavelength of the KrF excimer laser is 248 nm. This oscillation wavelength is a transmission region in the growth substrate 11 made of sapphire and the intermediate layer 12 made of AlN, but is absorbed in the base layer 13 made of undoped GaN. It becomes an area. For this reason, the laser light applied to the bonded body from the growth substrate 11 side is transmitted through the growth substrate 11 and the intermediate layer 12 and then absorbed by the underlayer 13 at the boundary between the intermediate layer 12 and the underlayer 13. The Then, a region of the underlayer 13 that becomes a boundary portion with the intermediate layer 12 is thermally decomposed into gallium and nitrogen (2GaN → 2Ga + N ₂ ↑) with the absorption of the laser light, and the intermediate layer 12 and the underlayer 13 The degree of bonding with the remarkably decreases. As a result, as shown in FIG. 12, the growth substrate 11 on which the intermediate layer 12 is laminated is separated from the joined body of the element group formation substrate 40 and the mounting substrate 50. Accordingly, in the joined body of the element group forming substrate 40 and the mounting substrate 50 from which the growth substrate 11 and the intermediate layer 12 are separated, the base layer 13 provided in each semiconductor light emitting element 10 is exposed to the outside. It will be in the state.

  By the way, when the lattice constant does not match between the growth substrate 11 and each semiconductor layer formed on the growth substrate 11 as in the element group formation substrate 40 of the present embodiment, the element group formation substrate 40. As a result, a large stress is applied to the growth substrate 11 that constitutes the structure, and as a result, the element group formation substrate 40 may be warped due to the growth substrate 11. Here, in the LLO, the coupling between the intermediate layer 12 and the base layer 13 is released with the irradiation of the laser beam, but at this time, the stress applied to the growth substrate 11 is eliminated. Accordingly, there is a concern that each semiconductor light emitting element 10 may be damaged by applying a force to each semiconductor light emitting element 10. Therefore, in the present embodiment, by providing the element group forming substrate 40 with grooves T that individually partition the semiconductor light emitting elements 10 in advance, for example, in the semiconductor light emitting elements 10 with laser light irradiation. Even when a force is applied, it is difficult to transmit the force to other semiconductor light emitting elements 10 adjacent to the semiconductor light emitting element 10 via each semiconductor layer, thereby preventing each semiconductor light emitting element from being damaged. doing.

In the growth substrate separation step, the growth substrate 11 and the intermediate layer 12 separated from the joined body of the element group formation substrate 40 and the mounting substrate 50 are separated from the growth substrate 11 by, for example, chemical treatment. By removing 12, it can be used again for manufacturing the element group formation substrate 40. In particular, in the present embodiment, it is not necessary to break the growth substrate 11 in both the element group forming substrate manufacturing process and the bonding process, and therefore there is a step of polishing and thinning the growth substrate 11. For this reason, the growth substrate 11 can be reused a plurality of times, for example.
In the present embodiment, the substrate in which the growth substrate 11 and the intermediate layer 12 are separated from the element group formation substrate 40 is also referred to as the element group formation substrate 40.

<< Support substrate bonding process >>
FIG. 13 is a diagram for explaining an example of the supporting substrate bonding step in step 15. More specifically, FIG. 13 is a cross-sectional configuration of the bonded body of the bonded assembly of the element group forming substrate 40 and the mounting substrate 50 and the supporting substrate 90 obtained by executing the supporting substrate bonding step. It is a figure which shows an example.

The support substrate 90 used in the support substrate bonding step includes a single base material 91 formed in a wafer shape and a wax layer 92 provided on one surface of the base material 91.
Here, the substrate 91 as an example of the third substrate is not particularly limited, and various substrate materials can be used. Examples of the base material 91 include silicon, sapphire, SiC, zinc oxide, magnesium oxide, manganese oxide, zirconium oxide, manganese zinc iron, magnesium aluminum oxide, zirconium boride, gallium oxide, indium oxide, lithium gallium oxide, and oxide. A substrate formed of lithium aluminum, neodymium gallium oxide, lanthanum strontium aluminum tantalum, strontium titanium oxide, titanium oxide, hafnium oxide, tungsten oxide, molybdenum oxide, or the like can be used. A substrate made of glass can also be used as the base material 91. For example, an inexpensive borosilicate glass substrate such as Pyrex (a trademark of Corning) or Tempax (a trademark of Schott) can be used as the base material 91. Furthermore, the size of one surface of the base material 91 is desirably equal to or greater than the size of one surface of the base 51 of the mounting substrate 50. In the present embodiment, silica glass is used as the base material 91. The diameter of the substrate 91 made of silica glass is 100 mm and the thickness is 500 μm.

  On the other hand, as the wax layer 92 as an example of the bonding portion, a known adhesive used for temporary fixing at the time of cutting or polishing the electronic component material can be used. Here, it is desirable that the adhesive has a thermal expansion coefficient close to that of the material (silicon or the like) used as the base 51 in consideration of heat applied at the time of bonding. It is desirable that the material be transparent in the visible region in order to facilitate the execution of general alignment.

  In the supporting substrate bonding step, the exposed surface of the base layer 13 and one surface of the base material 91 in the joined body of the element group forming substrate 40 and the mounting substrate 50 are opposed to each other, and the wax layer 92 is interposed therebetween. Heat while applying pressure in the state of placing. Then, the wax layer 92 has fluidity by being softened with heating, and comes into contact with both the base layer 13 and the base material 91 in the joined body. Then, after a predetermined time has elapsed, heating is stopped and cooling is performed, so that the joined body of the element group forming substrate 40 and the mounting substrate 50 and the base material 91 of the supporting substrate 90 become wax. It is bonded through the layer 92 to form an integrated body. In the support substrate bonding step, it is desirable to bond the base 51 of the mounting substrate 50 and the base material 91 of the support substrate 90 so that they are in a parallel positional relationship.

<< Mounting substrate polishing process >>
FIG. 14 is a diagram for explaining an example of the mounting substrate polishing process in step 16. More specifically, FIG. 14 shows a cross-sectional configuration of the bonded body of the bonded assembly of the element group forming substrate 40 and the mounting substrate 50 and the supporting substrate 90 obtained by executing the mounting substrate polishing step. It is a figure which shows an example.

  In the mounting substrate polishing step, the base 51 in the mounting substrate 50 constituting the adhesive body is polished using a known technique called lapping and polishing. More specifically, in the mounting substrate polishing step, the base part constituting the mounting substrate 50 in the bonded body of the element group forming substrate 40 and the mounting substrate shown in FIG. Polishing to reduce the thickness of 51 is performed. In the present embodiment, in the mounting substrate polishing step, the thickness of the base 51 is reduced from 525 μm at the time of bonding to about 100 μm.

  For example, when the mounting substrate 50 having a thin base 51 is used or when it is desired to obtain the light-emitting chip 1 having a large thickness, the mounting substrate polishing step of step 16 can be omitted. .

<< Via hole formation process >>
FIG. 15 is a diagram for explaining an example of the via hole forming process in step 17. More specifically, FIG. 15 shows a cross-sectional configuration of the bonded body of the element group forming substrate 40 and the mounting substrate 50 and the supporting substrate 90 obtained by executing the via hole forming step. It is a figure which shows an example.

  In the via hole forming step, a known technique called reactive ion etching (RIE), in particular, a technique called deep RIE is used to form an assembly of the element group forming substrate 40 and the mounting substrate 50 in an adhesive body. A plurality of via holes VH are formed. More specifically, in the via hole forming step, the base portion of the mounting substrate 50 with respect to the bonded body of the element group forming substrate 40 and the mounting substrate 50 shown in FIG. A plurality of (3 × 3 = 9 in this example) via holes VH are formed from the 51 side toward the p-side internal electrode 20 of each semiconductor light emitting element 10, and from the base 51 side of the mounting substrate 50. A single (one) via hole VH is formed toward the n-side internal electrode 30 of each semiconductor light emitting element 10.

In the present embodiment, in order to form a via hole VH extending from the base 51 to the p-side internal electrode 20 and a via hole VH extending from the base 51 to the n-side internal electrode 30, the deep hole RIE is made of silicon. Further, it is required to cut the base portion 51, the joint portion 52 made of SOG containing silicon dioxide, and the protective layer 19 made of silicon dioxide. Therefore, in the present embodiment, in the deep digging RIE, a reactive gas used for digging the base 51 and a reactive gas used for digging the joint 52 and the protective layer 19 are processed in one batch. It is changed on the way. As each reaction gas used in the deep digging RIE, a mixed gas of fluorine-containing gas and O ₂ can be preferably used.

<< Insulator formation process >>
FIG. 16 is a diagram for explaining an example of the insulating portion forming step of Step 18. More specifically, FIG. 16 shows a cross-sectional configuration of an adhesive body between the bonded assembly of the element group forming substrate 40 and the mounting substrate 50 and the support substrate 90 obtained by executing the insulating portion forming step. It is a figure which shows an example.

  In the insulating portion forming step, each via formed in the bonded body of the element group forming substrate 40 and the mounting substrate 50 in the adhesive body using a known chemical vapor deposition (CVD) and a known RIE. The p-side insulating layer 61 and the n-side insulating layer 62 are formed on the inner wall of the hole VH, and the pn insulating layer 63 is formed on the exposed surface of the base 51 of the mounting substrate 50 in the joined body.

  More specifically, in the insulating part forming step, first, the mounting substrate 50 is bonded to the bonding body of the element group forming substrate 40 and the mounting substrate 50 shown in FIG. An insulating film made of, for example, silicon dioxide is formed by CVD from the base 51 side. At this time, in the joined body of the element group forming substrate 40 and the mounting substrate 50, it corresponds to the inner wall surface and the bottom surface of each via hole VH provided corresponding to each p-side internal electrode 20 and each n-side internal electrode 30. An insulating film made of silicon dioxide is formed on the inner wall surface and bottom surface of each via hole VH and the exposed surface of the base 51. At this time, the thickness of the insulating film formed on the inner wall surface of each via hole VH is larger than the thickness of the insulating film formed on the bottom surface of each via hole VH, and on the exposed surface of the base 51. It becomes smaller than the thickness of the insulating film to be formed.

  In the insulating portion forming step, the so-called entire surface RIE is then performed from the base 51 side of the mounting substrate 50 to the bonded body of the element group forming substrate 40 and the mounting substrate 50 and the support substrate 90. Etch back by. At this time, in the joined body of the element group forming substrate 40 and the mounting substrate 50, it corresponds to the inner wall surface and the bottom surface of each via hole VH provided corresponding to each p-side internal electrode 20 and each n-side internal electrode 30. Insulating films formed on the inner wall surface and the bottom surface of each via hole VH and the exposed surface of the base 51 are respectively cut away. However, the insulating layer formed on the inner wall surface of each via hole VH is scraped more than the insulating layer formed on the bottom surface of each via hole VH and the exposed surface of the base 51 due to the anisotropy peculiar to RIE. The rate is lowered. Here, in the present embodiment, as described above, the thickness of the insulating layer formed on the bottom surface of each via hole VH is smaller than the thickness of the insulating layer formed on the exposed surface of the base 51. By completing the entire surface RIE at the timing when the insulating layer formed on the bottom surface of each via hole VH is removed, the insulating layer formed on the exposed surface of the base 51 remains on the exposed surface, and each The p-side insulating layer 61 and the n-side insulating layer 62 formed on the inner wall surface of the via hole VH also remain.

  Therefore, by executing such a procedure, the inner wall surfaces of the plurality of via holes VH provided corresponding to the p-side internal electrodes 20 in the joined body of the element group formation substrate 40 and the mounting substrate 50 are formed on the inner wall surfaces of the via holes VH. The p-side insulating layer 61 is formed, and the inner wall surface of the single via hole VH provided corresponding to each n-side internal electrode 30 in the joined body of the element group forming substrate 40 and the mounting substrate 50 is n A side insulating layer 62 is formed, and an inter-pn insulating layer 63 is formed on the exposed surface of the base 51 in the joined body of the element group forming substrate 40 and the mounting substrate 50. Further, one end side of the p-side insulating layer 61 is on the protective layer 19 formed on the upper surface of the p-side internal electrode 20 in the semiconductor light emitting element 10, and one end side of the n-side insulating layer 62 is on the n-side inside in the semiconductor light emitting element 10. Each is connected to the protective layer 19 formed on the upper surface of the electrode 30. Furthermore, the other end sides of the p-side insulating layer 61 and the n-side insulating layer 62 are connected to the pn insulating layer 63, respectively.

  In addition, when both the base 51 and the joining part 52 which comprise the mounting board | substrate 50 are comprised with the material which has high insulation, the insulating part formation process of step 18 can be skipped.

<< Barrier / seed layer formation process >>
FIG. 17 is a diagram for explaining an example of the barrier / seed layer forming step of Step 19. More specifically, FIG. 17 is a cross-sectional view of the bonded body obtained by executing the barrier / seed layer forming step and the bonded body of the element group forming substrate 40 and the mounting substrate 50 and the supporting substrate 90. It is a figure which shows an example of a structure.

  In the barrier / seed layer forming step, the insulating portion 60 (p-side insulating layer 61, n-side insulating layer 62, and inter-pn insulating layer 63) formed on the bonded body of the element group forming substrate 40 and the mounting substrate 50 in the adhesive. First, a barrier layer is formed on each upper surface of each of the p-side internal electrode 20 and the n-side internal electrode 30 exposed on the bottom surface of each via hole VH, and a seed layer is formed on the barrier layer. A barrier / seed layer in which the layer and the seed layer are laminated is obtained. Here, the seed layer serves as a seed for copper plating in the plug portion forming process described later, and is composed of copper in the present embodiment. On the other hand, the barrier layer suppresses diffusion of copper forming the seed layer into the base 51 made of silicon through the insulating portion 60, and is made of titanium in the present embodiment. For the barrier layer, in addition to titanium, tantalum, titanium / tungsten, or the like can be used, and titanium nitride or tantalum nitride can also be used.

  In the barrier / seed layer forming step, the barrier layer can be formed by CVD or sputtering, and the seed layer can be formed by sputtering. And by executing such a procedure, in the inner wall surface of the plurality of via holes VH provided corresponding to each p-side internal electrode 20 in the joined body of the element group forming substrate 40 and the mounting substrate 50, A p-side barrier / seed layer 71 is formed on the p-side insulating layer 61, and a single via provided corresponding to each n-side internal electrode 30 in the joined body of the element group forming substrate 40 and the mounting substrate 50. On the inner wall surface of the hole VH, an n-side barrier / seed layer 81 is formed on the n-side insulating layer 62. Further, on the exposed surface side of the base 51 in the joined body of the element group formation substrate 40 and the mounting substrate 50, the same as the p-side barrier / seed layer 71 and the n-side barrier / seed layer 81 on the inter-pn insulating layer 63. A film having a layer structure and integrated therewith is formed.

<< Plug part formation process >>
FIG. 18 is a diagram for explaining an example of the plug portion forming process in step 20. More specifically, FIG. 18 shows an example of a cross-sectional configuration of an adhesive body between the bonded body of the element group forming substrate 40 and the mounting substrate 50 and the supporting substrate 90 obtained by executing the plug portion forming step. FIG.

  In the plug portion forming step, the barrier / seed layer (p-side barrier / seed layer 71, n-side barrier / seed layer 81, and pn insulation) formed on the bonded body of the element group forming substrate 40 and the mounting substrate 50 in the adhesive. Copper plating is performed using the barrier / seed layer formed on the layer 63 as a seed. As a result, a plurality of via holes VH provided corresponding to each p-side internal electrode 20 in the joined body of the element group forming substrate 40 and the mounting substrate 50 are formed by filling the p-side plug portion 72. The single via hole VH provided corresponding to each n-side internal electrode 30 in the joined body of the element group forming substrate 40 and the mounting substrate 50 is formed by filling the n-side plug portion 82. Also, on the exposed surface side of the base 51 in the joined body of the element group forming substrate 40 and the mounting substrate 50, a plating layer integrated with the p-side plug portion 72 and the n-side plug portion 82 is formed on the barrier / seed layer. It is formed.

<< Electrode forming surface polishing process >>
FIG. 19 is a diagram for explaining an example of the electrode forming surface polishing step in step 21. More specifically, FIG. 19 shows a cross-sectional configuration of an adhesive body between the element group forming substrate 40 and the mounting substrate 50 and the supporting substrate 90 obtained by executing the electrode forming surface polishing step. It is a figure which shows an example.

  In the electrode forming surface polishing step, a known so-called chemical mechanical polishing (CMP) method is used, and the assembly of the element group forming substrate 40 and the mounting substrate 50 shown in FIG. Polishing for removing the copper plating layer and the barrier / seed layer formed on the exposed surface of the base 51 in the mounting substrate 50 is performed on the adhesive body. Thereby, on the exposed surface side of the base 51 in the mounting substrate 50, the inter-pn insulating layer 63 is exposed to the outside by removing the laminated copper plating layer and barrier / seed layer. In addition, the p-side plug portions 72 and the n-side plug portions 82 are also exposed to the outside together with the pn insulating layer 63.

  In this example, in the electrode formation surface polishing step, the copper plating layer and the barrier / seed layer are removed by CMP while the pn insulating layer 63 is left, but this is not restrictive. For example, in the electrode forming surface polishing step, in addition to the copper plating layer and the barrier / seed layer, the inter-pn insulating layer 63 may also be removed to expose the base 51. In this case, after the electrode forming surface polishing step, the inter-pn insulating layer 63 may be formed again by CVD or the like before executing the next external pad forming step.

<< External pad formation process >>
FIG. 20 is a diagram for explaining an example of the external pad forming process in step 22. More specifically, FIG. 20 shows a cross-sectional configuration of an adhesive body between the element group forming substrate 40 and the mounting substrate 50 and the supporting substrate 90 obtained by executing the external pad forming step. It is a figure which shows an example.

  In the external pad forming step, a known sputter is used, and a bonding body of the element group forming substrate 40 and the mounting substrate 50 in the adhesive is provided corresponding to each semiconductor light emitting element 10 from the base 51 side of the mounting substrate 50. A p-side external pad 73 is formed so as to cover the plurality of p-side plug portions 72 formed, and an n-side external pad is provided so as to cover a single n-side plug portion 82 provided corresponding to each semiconductor light emitting element 10. 83 is formed. The p-side external pad 73 and the n-side external pad 83 are both made of gold.

  As described above, through the procedure from the barrier / seed layer forming process in step 19 to the external pad forming process in step 22, the plurality of semiconductor light emitting elements 10 constituting the element group forming substrate 40 have the p-side barrier / A p-side external electrode 70 having a seed layer 71, a p-side plug portion 72 and a p-side external pad 73, and an n-side external electrode 80 having an n-side barrier / seed layer 81, an n-side plug portion 82 and an n-side external pad 83. Will be provided.

<< Support substrate separation process >>
FIG. 21 is a diagram for explaining an example of the supporting substrate separating step in step 23. More specifically, FIG. 21 shows a joined body of the element group forming substrate 40 and the mounting substrate 50 obtained by executing a supporting substrate separating step, and a supporting substrate separated from the joined body. It is a figure which shows an example of the cross-sectional structure of 90 (base material 91 and the wax layer 92).

  In the supporting substrate separation step, the wax layer 92 is softened by heating the bonded body of the element group forming substrate 40 and the mounting substrate 50 and the supporting substrate 90, and then the element group forming substrate 40 and the mounting substrate. The supporting substrate 90 is separated from the bonded body of the working substrate 50. After the separation, the residue of the wax layer 92 adhering to the exposed surface of the base layer 13 in the joined body of the element group formation substrate 40 and the mounting substrate 50 is removed using a known method.

<< Light extraction surface processing process >>
FIG. 22 is a diagram for explaining an example of the light extraction surface processing step in step 24. More specifically, FIG. 22 is a diagram illustrating an example of a cross-sectional configuration of a joined body of the element group formation substrate 40 and the mounting substrate 50 obtained by executing the light extraction surface processing step.

  In the light extraction surface processing step, the base layer 13 in the joined body of the element group forming substrate 40 and the mounting substrate 50 is immersed in, for example, TMAH (tetramethylammonium hydroxide) (for a specific method, see, for example, JP 2010-2010 A No. 016055). Thereby, the underlayer 13 is gradually etched from the exposed surface side. Here, TMAH has a function of easily eroding the nitrogen side out of gallium and nitrogen constituting the base layer 13. For this reason, the exposed surface of the underlayer 13 is selectively cut away from the nitrogen-containing region, and as a result, the exposed surface of the underlayer 13 becomes a concavo-convex processed surface 13a on which the concavo-convex is formed. The uneven processed surface 13 a functions as a light extraction surface for extracting light output from the light emitting layer 15 to the outside in each semiconductor light emitting element 10.

<< Individualization process >>
FIG. 23 is a diagram for explaining an example of the singulation process in step 25. More specifically, FIG. 23 shows an example of a cross-sectional configuration of a plurality of light emitting chips 1 obtained by executing the singulation process.

In the singulation step, the mounting substrate 50 (base 51 and bonding portion) are respectively formed along the plurality of grooves T formed in the element group formation substrate 40 with respect to the joined body of the element group formation substrate 40 and the mounting substrate 50. 52) is diced into light-emitting chips 1 each having the semiconductor light-emitting element 10. Here, as a dicing method, cutting using a known blade, cutting by a known laser irradiation, or the like can be used.
Further, in the bonding process of step 13, if the orientation of each groove T formed in the element group formation substrate 40 and the orientation of the crystal orientation in the base 51 of the mounting substrate 50 are previously matched, the base 51 Therefore, it is possible to easily divide the silicon light-emitting chip 1 from each other, and the light-emitting chip 1 that has been singulated is not particularly required to be polished. The end surface (cut surface) of the base portion 1 can be flattened.

  FIG. 24 is a diagram illustrating an example of the configuration of the light emitting device 100 on which the above-described light emitting chip 1 is mounted. Here, FIG. 24A shows a top view of the light emitting device 100, and FIG. 24B is a sectional view taken along line XXIVB-XXIVB of FIG. 6A. Note that the light emitting device 100 illustrated in FIG. 24 may be referred to as a “lamp”.

  The light emitting device 100 is attached to a housing 101 having a recess 101a formed on one side, a p-lead portion 102 and an n-lead portion 103 made of a lead frame formed in the housing 101, and a bottom surface of the recess 101a. The light emitting chip 1 and the sealing portion 104 provided so as to cover the light emitting chip 1 and the recess 101a are provided. In FIG. 24A, the sealing portion 104 is not shown.

  The casing 101 is formed by injection-molding a white thermoplastic resin in a metal lead portion including the p lead portion 102 and the n lead portion 103.

  The p lead portion 102 and the n lead portion 103 are metal plates having a thickness of about 0.1 to 0.5 mm, and are based on, for example, an iron / copper alloy as a metal excellent in workability and thermal conductivity. Further, nickel, titanium, gold, silver or the like is laminated as a plating layer by several μm. In this embodiment, part of the p lead portion 102 and the n lead portion 103 is exposed on the bottom surface of the recess 101a. Further, one end side of the p lead portion 102 and the n lead portion 103 is exposed to the outside of the housing 101 and is bent from the outer wall surface of the housing 101 to the back surface side.

  The semiconductor chip 1 is attached to the recess 101 a across the p lead portion 102 and the n lead portion 103. The details of the method of attaching the light emitting chip 1 to the p lead portion 102 and the n lead portion 103 will be described later.

  And the sealing part 104 is comprised with transparent resin with a high light transmittance in the wavelength of a visible region. For example, an epoxy resin or a silicon resin can be used as the resin that satisfies the characteristics of high heat resistance, weather resistance, and mechanical strength constituting the sealing portion 104. In this embodiment, the transparent resin constituting the sealing portion 104 contains a phosphor that converts part of the light emitted from the light emitting chip 1 into green light and red light. Instead of such a phosphor, a phosphor that converts part of blue light into yellow light or a phosphor that converts part of blue light into yellow light and red light may be included. Good.

  Note that electronic devices such as a backlight, a mobile phone, a display, various panels, a computer, a game machine, and a lighting incorporating the light emitting device 100 of this embodiment, and a mechanical device such as an automobile incorporating such an electronic device are used. The semiconductor light emitting device 1 having excellent light emission characteristics is provided. In particular, in an electronic device driven by a battery such as a backlight, a mobile phone, a display, a game machine, and an illumination, an excellent product including the semiconductor light emitting element 1 having excellent light emission characteristics can be provided, which is preferable. In addition, the configuration of the light emitting device 100 including the semiconductor light emitting element 1 is not limited to that shown in FIG. 24, and for example, a package configuration called a shell type may be adopted.

  25 is a diagram illustrating an example of a mounting state of the light-emitting chip 1 in the light-emitting device 100 illustrated in FIG. However, in FIG. 25, the description of the housing 101 and the sealing portion 104 provided in the light emitting device 100 is omitted.

  In the present embodiment, the light emitting chip 1 shown in FIG. 2 is turned upside down so that the p-side external pad 73 in the p-side external electrode 70 provided on the light-emitting chip 1 faces the p lead portion 102, and The n-side external pad 83 in the n-side external electrode 80 provided on the light emitting chip 1 is opposed to the n lead portion 103. The p-lead portion 102 and the p-side external pad 73 in the p-side external electrode 70 are connected by the solder 105, and the n-lead portion 103 and the n-side external pad 83 in the n-side external electrode 80 are connected to the solder 105. Connected. Thereby, the light emitting chip 1 is electrically connected to the p lead portion 102 and the n lead portion 103 and mechanically connected to the housing 101 (see FIG. 24) via the p lead portion 102 and the n lead portion 103. It is fixed to. Such a connection method of the light emitting chip 1 is generally called flip chip connection. In the flip chip connection, the base layer 13 (uneven surface 13a) side of the semiconductor light emitting element 1 provided on the light emitting chip 1 is disposed on the side farther from the lead portion than the light emitting layer 15.

Now, the light emission operation of the light emitting device 100 shown in FIG. 24 will be described with reference to FIGS. 24 and 25.
When a current flowing from the p lead portion 102 to the n lead portion 103 is passed through the light emitting chip 1 via the p lead portion 102 and the n lead portion 103 provided in the light emitting device 100, the p-side external electrode 70 in the light emitting chip 1. Current flows from the p-side internal electrode 20, the transparent conductive layer 17, the p-type semiconductor layer 16, the light emitting layer 15, the n-type semiconductor layer 14, and the n-side internal electrode 30 to the n-side external electrode 80. As a result, the light emitting layer 15 outputs, for example, blue light. At this time, the light output from the light emitting layer 15 is mainly directed to the base layer 13 side and the p-side internal electrode 20 side.

  Here, in the present embodiment, the transparent insulating layer 18 is provided in the semiconductor light emitting element 10 constituting the light emitting chip 1, but the inside of the p side is formed through a plurality of through holes provided in the transparent insulating layer 18. The electrode 20 (more specifically, the plurality of p-side connection conductors 21) and the transparent conductive layer 17 are electrically connected, and the n-side internal electrode 30 (more specifically, the plurality of n-side connection conductors 31) is connected to the n-type. When the semiconductor layer 14 is electrically connected, power is supplied to the light emitting layer 15.

Next, the behavior of light output from the light emitting layer 15 in the semiconductor light emitting element 10 provided in the light emitting chip 1 will be described.
Most of the light emitted from the light emitting layer 15 toward the base layer 13 side passes through the n-type semiconductor layer 14 and the base layer 13, and the semiconductor light emitting element from the uneven surface 13 a provided in the base layer 13. 10 (light emitting chip 1) is emitted to the outside (upper side in FIG. 25). However, part of the light traveling toward the base layer 13 is reflected by, for example, the difference in refractive index between the base layer 13 and the n-type semiconductor layer 14 and returns to the light emitting layer 15 side.

  In addition, a part of the light emitted from the light emitting layer 15 toward the side opposite to the base layer 13 and the light returned from the base layer 13 side is transmitted through the p-type semiconductor layer 16 and the transparent conductive layer 17. , And reaches the boundary with the transparent insulating layer 18 on the side where the p-side internal electrode 20 is provided (the portion of the transparent insulating layer 18 where no through hole is formed). A part of the light reaching the boundary is reflected by the difference in refractive index between the transparent conductive layer 17 and the transparent insulating layer 18 and travels toward the p-type semiconductor layer 16 through the transparent conductive layer 17. The light that has passed through the boundary between the transparent conductive layer 17 and the transparent insulating layer 18 reaches the boundary with the p-side internal electrode 20 through the transparent insulating layer 18. Then, the light that reaches this boundary is reflected by the p metal reflection layer 202 provided on the p-side internal electrode 20, and travels toward the p-type semiconductor layer 16 through the transparent insulating layer 18 and the transparent conductive layer 17. .

  On the other hand, of the light emitted from the light emitting layer 15, part of the light traveling toward the side opposite to the base layer 13 and the light returning from the base layer 13 side passes through the p-type semiconductor layer 16 and the transparent conductive layer 17. , And reaches the boundary with the p-side internal electrode 20 (the portion where the through hole is formed in the transparent insulating layer 18). Then, the light that reaches this boundary portion is reflected by the p metal reflection layer 202 provided on the p-side internal electrode 20 and travels toward the p-type semiconductor layer 16 through the transparent conductive layer 17.

  Thus, the light reflected on the p-side internal electrode 20 side further passes through the light emitting layer 15, the n-type semiconductor layer 14, and the base layer 13, and enters the semiconductor light emitting device 10 from the uneven surface 13 a provided on the base layer 13. The light is emitted to the outside (upper side in FIG. 25) of (light emitting chip 1).

  On the other hand, part of the light returned from the base layer 13 side passes through the n-type semiconductor layer 14 and has a boundary portion (transparent insulation) with the transparent insulating layer 18 on the side where the n-side internal electrode 30 is provided. It reaches the portion of the layer 18 where no through-hole is formed. A part of the light reaching the boundary is reflected by the difference in refractive index between the n-type semiconductor layer 14 and the transparent insulating layer 18, and travels toward the base layer 13 through the n-type semiconductor layer 14. Further, light that has passed through the boundary between the n-type semiconductor layer 14 and the transparent insulating layer 18 reaches the boundary with the n-side internal electrode 30 through the transparent insulating layer 18. Then, the light reaching this boundary portion is reflected by the n metal reflection layer 302 provided on the n-side internal electrode 30 and travels toward the base layer 13 through the transparent insulating layer 18 and the n-type semiconductor layer 14.

  On the other hand, a part of the light returning from the base layer 13 side passes through the n-type semiconductor layer 14 to the boundary part (the part where the through hole is formed in the transparent insulating layer 18) with the n-side internal electrode 30. To reach. The light that reaches this boundary is reflected by the n metal reflection layer 302 provided on the n-side internal electrode 30 and travels toward the base layer 13 through the n-type semiconductor layer 14.

  The light reflected on the n-side internal electrode 30 side in this way is emitted from the uneven surface 13a provided on the underlayer 13 to the outside of the semiconductor light emitting element 10 (light emitting chip 1) (upward in FIG. 25). .

  Thereafter, the light (blue light) output from the light emitting chip 1 travels in the sealing portion 104, that is, in the recess 101a, and is reflected directly or on the inner wall (bottom surface or wall surface) of the recess 101a. The light is emitted to the outside from an emission surface provided on the upper side. However, part of the light traveling toward the exit surface is reflected by the exit surface and travels through the sealing portion 104 again. During this time, a part of the blue light is converted into green light and red light by the phosphor in the sealing portion 104, and the converted green light and red light are reflected directly or after being reflected on the bottom surface or the wall surface and then together with the blue light. The light is emitted from the emission surface to the outside. Therefore, white light including blue light, green light, and red light is emitted from the light emitting device 100.

  Here, in the light emitting device 100 of the present embodiment, the growth substrate 11 is not attached to the light extraction surface of the light emitting chip 1 (the growth substrate 11 is removed from the light emitting chip 1). Accordingly, the amount of light output from the light emitting device 100 is improved by the amount of light absorption and light loss caused by 11. And in this Embodiment, the uneven | corrugated processed surface 13a used as the light extraction surface of the light emitting chip 1 has an unevenness | corrugation, Therefore The light which injects into the uneven | corrugated processed surface 13a at various angles is emitted from the light emitting chip 1. As a result, the amount of light output from the light emitting device 100 can be improved accordingly.

Embodiment 2
Although the present embodiment is substantially the same as the first embodiment, the manufacturing method of the light-emitting chip 1 shown in FIGS. 1 and 2 is different from the first embodiment. More specifically, in the first embodiment, the growth substrate 11 provided on the element group formation substrate 40 is used to perform various processes on the joined body of the element group formation substrate 40 and the mounting substrate 50. Removal and replacement on the supporting substrate 90 were performed. On the other hand, in the present embodiment, various processes are performed without removing the growth substrate 11 from the joined body of the element group forming substrate 40 and the mounting substrate 50, and the element group forming substrate 40 and the mounting substrate 50 are joined. Before the body is separated into individual light emitting chips 1, the growth substrate 11 is removed from the joined body. In the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

FIG. 26 is a flowchart illustrating an example of a method for manufacturing the light-emitting chip 1 according to the second embodiment.
In the present embodiment, first, an element group forming substrate manufacturing process is performed to manufacture an element group forming substrate 40 formed by forming a plurality of semiconductor light emitting elements 10 on one surface of a wafer-like growth substrate 11 ( Step 51).
Separately from the element group forming substrate 40, a mounting substrate manufacturing process for manufacturing a mounting substrate 50 in which the bonding portion 52 is laminated on one surface of the wafer-like base 51 is executed (step 52).
Next, the formation surface of each semiconductor light emitting element 10 in the element group formation substrate 40 obtained in step 51 and the formation surface of the bonding portion 52 in the mounting substrate 50 obtained in step 52 are opposed to each other, and the bonding portion 52 is formed. Then, a bonding process for bonding the element group forming substrate 40 and the mounting substrate 50 is performed (step 53).

After step 53, a mounting substrate polishing step is performed on the stacked body of the element group forming substrate 40 and the mounting substrate 50 to polish the base 51 provided on the mounting substrate 50 in order to reduce the thickness (step). 54).
After step 54, via holes VH for exposing the p-side internal electrode 20 and the n-side internal electrode 30 of each semiconductor light emitting element 10 from the mounting substrate 50 side are formed in the stacked body whose base 51 is polished. A via hole forming step is executed (step 55).
After step 55, an insulating portion forming step for forming the insulating portion 60 (the p-side insulating layer 61, the n-side insulating layer 62, and the pn insulating layer 63) is performed on the stacked body formed up to the via hole VH. (Step 56).

After step 56, a barrier / seed layer forming step for forming the p-side barrier / seed layer 71 and the n-side barrier / seed layer 81 is performed on the stacked body including the insulating portion 60 (step 57).
After step 57, a plug portion forming step for forming the p-side plug portion 72 and the n-side plug portion 82 is performed on the stacked body in which the p-side barrier / seed layer 71 and the n-side barrier / seed layer 81 are formed. (Step 58).
After step 58, the electrode-forming surface polishing for polishing the base 51 side of the mounting substrate 50 to expose the inter-pn insulating layer 63 is performed on the stacked body in which the p-side plug portion 72 and the n-side plug portion 82 are formed. The process is executed (step 59).
External pads for forming the p-side external pad 73 and the n-side external pad 83 on the inter-pn insulating layer 63 with respect to the stacked body that has been subjected to polishing for exposing the inter-pn insulating layer 63 after step 59. A formation process is executed (step 60).
In the present embodiment, the process from the via hole forming process in step 55 to the external pad forming process in step 60 corresponds to the external electrode forming process.

After step 60, a growth substrate separation step is performed as an example of a first substrate separation step, in which the growth substrate 11 is separated from the laminate in which the p-side external pad 73 and the n-side external pad 83 are formed ( Step 61).
After step 61, the light extraction surface processing is performed by subjecting the joined body of the element group forming substrate 40 and the mounting substrate 50 from which the growth substrate 11 has been separated to the surface of the base layer 13 to provide the uneven surface 13 a. The process is executed (step 62).
After step 62, the element group forming substrate 40 and the mounting substrate 50 on which the concave and convex processed surface 13a is formed are subjected to a cutting process, whereby one element group forming substrate 40 is converted into a plurality of semiconductors. An individualization step as an example of a division step for dividing the light emitting element 10 into individual pieces is executed (step 63).

  Then, the manufacturing method of the light emitting chip 1 shown in FIG. 26 is demonstrated in detail. However, step 51 to step 53 in the second embodiment are the same as step 11 to step 13 in the first embodiment, respectively, and step 62 and step 63 in the second embodiment are the same as those in the first embodiment. Steps 24 and 25 in FIG. 4 are the same as each other, so detailed description thereof will be omitted here.

<< Mounting substrate polishing process >>
FIG. 27 is a diagram for explaining an example of the mounting substrate polishing process in step 54. More specifically, FIG. 27 is a diagram showing an example of a cross-sectional configuration of a joined body of the element group forming substrate 40 and the mounting substrate 50 obtained by executing the mounting substrate polishing step.
In the mounting substrate polishing step of the present embodiment, the base 51 in the mounting substrate 50 constituting the joined body is polished using the same procedure as described in Step 16 of the first embodiment.
For example, in the case where a thin base 51 is used as the mounting substrate 50 or when it is desired to obtain the light emitting chip 1 having a large thickness, the mounting substrate in step 54 is the same as in the first embodiment. The polishing step can be omitted.

<< Via hole formation process >>
FIG. 28 is a diagram for explaining an example of the via hole forming step in step 55. More specifically, FIG. 28 is a diagram illustrating an example of a cross-sectional configuration of a joined body of the element group formation substrate 40 and the mounting substrate 50.
In the via hole forming process of the present embodiment, a plurality of vias are formed on the bonded assembly of the element group forming substrate 40 and the mounting substrate 50 using the same procedure as that described in Step 17 of the first embodiment. -Hole VH is formed.

<< Insulator formation process >>
FIG. 29 is a diagram for explaining an example of the insulating portion forming process in step 56. More specifically, FIG. 29 is a diagram showing an example of a cross-sectional configuration of a joined body of the element group forming substrate 40 and the mounting substrate 50 obtained by executing the insulating portion forming step.
In the insulating portion forming process of the present embodiment, the insulating portion (p) is formed on the bonded assembly of the element group forming substrate 40 and the mounting substrate 50 using the same procedure as described in Step 18 of the first embodiment. The side insulating layer 61, the n-side insulating layer, and the pn insulating layer 63) are formed.
When both the base 51 and the joint 52 constituting the mounting substrate 50 are made of a highly insulating material, the insulating portion forming step in step 56 is omitted as in the first embodiment. be able to.

<< Barrier / seed layer formation process >>
FIG. 30 is a diagram for explaining an example of the barrier / seed layer forming step of step 57. More specifically, FIG. 30 is a diagram showing an example of a cross-sectional configuration of a joined body of the element group forming substrate 40 and the mounting substrate 50 obtained by executing the barrier / seed layer forming step.
In the barrier / seed layer forming step of the present embodiment, the same procedure as that described in step 19 of the first embodiment is used, and the p-side of the bonded assembly of the element group forming substrate 40 and the mounting substrate 50 is used. A barrier / seed layer 71, an n-side barrier / seed layer 82, and the like are formed.

<< Plug part formation process >>
FIG. 31 is a diagram for explaining an example of the plug part forming step of step 58. More specifically, FIG. 31 is a diagram showing an example of a cross-sectional configuration of a joined body of the element group forming substrate 40 and the mounting substrate 50 obtained by executing the plug portion forming step.
In the plug portion forming process of the present embodiment, the p-side plug portion is bonded to the bonded assembly of the element group forming substrate 40 and the mounting substrate 50 using the same procedure as that described in Step 20 of the first embodiment. 72, the n-side plug portion 82, and the like are formed.

<< Electrode forming surface polishing process >>
FIG. 32 is a diagram for explaining an example of the electrode forming surface polishing step in step 59. More specifically, FIG. 32 is a diagram showing an example of a cross-sectional configuration of a joined body of the element group forming substrate 40 and the mounting substrate 50 obtained by executing the electrode forming surface polishing step.
In the electrode forming surface polishing step of the present embodiment, the same procedure as described in Step 21 of Embodiment 1 is used to polish the base 51 side of the mounting substrate 50 constituting the joined body (excess copper (Removal of plating layer and barrier / seed layer).

<< External pad formation process >>
FIG. 33 is a diagram for explaining an example of the external pad forming process in step 60. More specifically, FIG. 33 is a diagram showing an example of a cross-sectional configuration of a joined body of the element group forming substrate 40 and the mounting substrate 50 obtained by executing the external pad forming step.
In the external pad forming process of the present embodiment, a p-side external pad is formed on the bonded assembly of the element group forming substrate 40 and the mounting substrate 50 using the same procedure as described in step 22 of the first embodiment. 73 and an n-side external pad 83 are formed.

<< Growth substrate separation process >>
FIG. 34 is a diagram for explaining an example of the growth substrate separating step in step 61. More specifically, FIG. 34 shows a joined body (excluding the growth substrate 11 and the intermediate layer 12) of the element group formation substrate 40 and the mounting substrate 50 obtained by executing the growth substrate separation step. FIG. 3 is a diagram showing an example of a cross-sectional configuration of a growth substrate 11 and an intermediate layer 12 separated from the joined body.
In the growth substrate separation step of the present embodiment, the intermediate layer 12 is laminated from the joined body of the element group formation substrate 40 and the mounting substrate 50 using the same procedure as described in Step 14 of the first embodiment. The grown substrate 11 is separated.

Through the above-described procedure, the joined body of the element group formation substrate 40 and the mounting substrate 50 (the growth substrate 11 and the intermediate layer 12 has the same structure as that at the end of the supporting substrate separation step in the first embodiment. Except) is obtained.
Then, the light extraction chip 1 shown in FIGS. 1 and 2 can be obtained by executing the light extraction surface processing step in step 62 and the individualizing step in step 63.

  As described in the method for manufacturing the light-emitting chip 1 according to the first embodiment and the second embodiment, in the present invention, a plurality of semiconductor light-emitting elements having a group III nitride semiconductor layer are formed on the surface of the first substrate. A bonding step of bonding the formation surface of the semiconductor light emitting element in the element group formation substrate and the first surface of the second substrate different from the first substrate via the bonding portion, the element group formation substrate, and the bonding portion A plurality of semiconductors in a first substrate separation step of separating the first substrate from the laminate in which the second substrate is laminated, and a joined body in which the plurality of semiconductor light emitting elements and the second substrate are joined via the joint. A bonding step of bonding an exposed surface from which the light-emitting element is exposed and one surface of a third substrate different from the first substrate and the second substrate through the bonding portion; and the bonded body and the third through the bonding portion. The second substrate is bonded to the bonded body that is bonded to the substrate. From the second surface side which is the back side of the first surface, the second substrate and the joint are penetrated, and one end is connected to the semiconductor light emitting element and the other end is the second surface of the second substrate. An external electrode forming step for forming an external electrode exposed to the side, a third substrate separating step for separating the third substrate together with the bonding portion from the adhesive body on which the external electrode is formed, and the third substrate on which the external electrode is formed and formed The productivity of the light-emitting chip 1 can be improved by performing the dividing step of dividing the second substrate and the bonding portion on the bonded body from which the light is separated.

In particular, in the present invention, the bonding portion is made of an insulating material containing a siloxane structure, and before the bonding step, a precursor of the insulating material is applied to the first surface of the second substrate, and the bonding step. Then, the formation surface of the semiconductor light-emitting element in the element group formation substrate and the formation surface of the junction part in the second substrate in which the precursor of the junction part is formed on the first surface face each other, and the element group formation substrate and the second By heating the substrate, firm adhesiveness (bonding) can be formed at both interfaces.
The bonding method used in the present invention is an extremely simple method as compared with a room temperature bonding method (surface activated bonding) or an atomic diffusion bonding method applied to a known metal / metal interface, and is required for the room temperature bonding method. There is an advantage that a surface treatment or the like in a vacuum is not required.

In addition, since the bonding process used in the present invention can be bonded at a low temperature of 200 ° C. or lower, it is necessary to select in consideration of the thermal expansion coefficient of a material to be bonded (for example, a second substrate or a protective film on the element). Therefore, an inexpensive oxide-based bonded material can be used.
In particular, in the present invention, the formation surface of the semiconductor light emitting element in the element group formation substrate is formed of a protective layer, and the first surface of the second substrate different from the first substrate is bonded via the bonding portion. It is preferable to include a joining step.

DESCRIPTION OF SYMBOLS 1 ... Light emitting chip, 10 ... Semiconductor light emitting element, 11 ... Substrate for growth, 12 ... Intermediate layer, 13 ... Underlayer, 13a ... Uneven processed surface, 14 ... N type semiconductor layer, 15 ... Light emitting layer, 16 ... P type semiconductor Layer, 17 ... transparent conductive layer, 18 ... transparent insulating layer, 19 ... protective layer, 20 ... p-side internal electrode, 21 ... p-side connection conductor, 22 ... p-side internal pad, 30 ... n-side internal electrode, 31 ... n Side connection conductor, 32 ... n-side internal pad, 40 ... element group forming substrate, 50 ... mounting substrate, 51 ... base, 52 ... joining portion, 60 ... insulating portion, 61 ... p-side insulating layer, 62 ... n-side insulation Layer, 63 ... pn insulating layer, 70 ... p-side external electrode, 71 ... p-side barrier / seed layer, 72 ... p-side plug, 73 ... p-side external pad, 80 ... n-side external electrode, 81 ... n-side Barrier / seed layer, 82 ... n-side plug portion, 83 ... n-side external pad, 90 ... supporting substrate, 1 ... substrate, 92 ... wax layer, 100 ... light-emitting device, 101 ... housing, 101a ... recess, 102 ... p lead portion, 103 ... n leads, 104 ... sealing portion 105 ... solder

Claims (14)

A plurality of semiconductor light emitting elements having a group III nitride semiconductor layer are formed on the surface of the first substrate, and a formation surface of the semiconductor light emitting element in the element group forming substrate and a second substrate different from the first substrate A bonding step of bonding the first surface via the bonding portion;
A first substrate separation step of separating the first substrate from a stacked body in which the element group forming substrate, the bonding portion, and the second substrate are stacked;
In the joined body in which a plurality of the semiconductor light emitting elements and the second substrate are joined via the joint, an exposed surface from which the plurality of semiconductor light emitting elements are exposed is different from the first substrate and the second substrate. An adhering step of adhering one surface of the third substrate through an adhering portion;
The second substrate from the second surface side which is the back side of the first surface of the second substrate with respect to the bonded body in which the bonded body and the third substrate are bonded via the bonding portion. And an external electrode forming step of forming an external electrode penetrating the joint and having one end connected to the semiconductor light emitting element and the other end exposed on the second surface side of the second substrate;
A third substrate separating step for separating the third substrate together with the adhesive portion from the adhesive body on which the external electrode is formed;
A method of manufacturing a light-emitting chip, comprising: a dividing step of dividing the second substrate and the bonding portion with respect to the bonded body in which the external electrode is formed and the third substrate is separated. The joint is made of an insulating material containing a siloxane structure,
Before the bonding step, a precursor of the insulating material is applied to the first surface of the second substrate,
In the bonding step, the surface on which the semiconductor light emitting element is formed on the element group formation substrate and the surface on which the precursor is applied on the second substrate face each other, and the element group formation substrate and the second substrate The method for manufacturing a light-emitting chip according to claim 1, wherein heating is performed while applying pressure.   3. The method for manufacturing a light-emitting chip according to claim 1, wherein in the element group forming substrate, the first substrate is made of a sapphire single crystal. The element group forming substrate is provided with a positive internal electrode and a negative internal electrode for each of the plurality of semiconductor light emitting elements,
In the external electrode forming step, a positive external electrode penetrating the second substrate and the joint and connected to the positive internal electrode provided in the semiconductor light emitting element, the second substrate and the joint 4. The light-emitting chip manufacturing method according to claim 1, wherein a negative external electrode that penetrates through the substrate and is connected to the negative internal electrode provided in the semiconductor light-emitting element is formed. 5. Method. The external electrode forming step includes
The second substrate from the second surface side which is the back side of the first surface of the second substrate with respect to the bonded body in which the bonded body and the third substrate are bonded via the bonding portion. And a through-hole forming step for forming a through-hole penetrating the joint portion;
An insulating part forming step of forming an insulating part on an inner wall surface of the through hole formed through the second substrate and the joining part;
2. A filling step of filling a conductive material into the through hole formed through the second substrate and the joining portion and having the insulating portion formed on the inner wall surface. The method for manufacturing a light-emitting chip according to any one of claims 1 to 4.   The method of manufacturing a light emitting chip according to claim 1, wherein the second substrate is made of a silicon single crystal. A plurality of semiconductor light emitting elements having a group III nitride semiconductor layer are formed on the surface of the first substrate, and a formation surface of the semiconductor light emitting element in the element group forming substrate and a second substrate different from the first substrate A bonding step of bonding the first surface via the bonding portion;
From the second surface side, which is the back side of the first surface of the second substrate, with respect to the stacked body in which the element group forming substrate, the bonding portion, and the second substrate are stacked, the second substrate and An external electrode forming step of forming an external electrode penetrating the joint and having one end connected to the semiconductor light emitting element and the other end exposed on the second surface side of the second substrate;
A first substrate separation step of separating the first substrate from the laminate in which the external electrode is formed;
With respect to a joined body in which the external electrodes are formed and the first substrate is separated and a plurality of the semiconductor light emitting elements and the second substrate are joined via the joining portion, the second substrate and the joined The manufacturing method of the light emitting chip including the division | segmentation process which divides | segments a part. A first semiconductor layer composed of a group III nitride semiconductor having a first conductivity type; a light emitting layer composed of a group III nitride semiconductor, provided in contact with the first semiconductor layer and emitting light when energized; A semiconductor light emitting device comprising a group III nitride semiconductor having a second conductivity type opposite to the first conductivity type, and a second semiconductor layer provided in contact with the light emitting layer;
A base provided opposite to the second semiconductor layer provided in the semiconductor light emitting device;
A junction provided between the semiconductor light emitting element and the base, and joining the semiconductor light emitting element and the base;
A first electrode provided through the base and the joint, one end of which is electrically connected to the first semiconductor layer in the semiconductor light emitting element, and the other end is exposed to the outside from the base;
A light emitting chip including a second electrode that is provided through the base and the joint, one end of which is electrically connected to the second semiconductor layer of the semiconductor light emitting element, and the other end is exposed to the outside from the base. .   The light emitting chip according to claim 8, further comprising an insulating portion provided in the base portion and the joint portion and electrically insulating the first electrode and the second electrode.   The light emitting chip according to claim 8 or 9, wherein the base portion is made of a silicon single crystal, and the bonding portion contains silicon oxide.   11. The light emitting chip according to claim 8, wherein the semiconductor light emitting element has a concavo-convex process on an end face on the first semiconductor layer side as viewed from the light emitting layer. A base having a plate-like structure;
A plurality of semiconductor light emitting devices each having a group III nitride semiconductor layer;
A bonding portion for bonding a plurality of the semiconductor light emitting elements in an aligned state to one surface of the base portion;
An element group forming substrate having a plurality of external electrodes formed so as to penetrate through the base and the junction corresponding to each of the plurality of semiconductor light emitting elements and supplying power to each of the plurality of semiconductor light emitting elements .   A plurality of the semiconductor light emitting elements are attached through the group III nitride semiconductor layer, and are used in the growth process of the group III nitride semiconductor layer to form the plurality of semiconductor light emitting elements. The element group forming substrate according to claim 12, further comprising a growth substrate disposed to face the base through the light emitting element and the joint. The plurality of semiconductor light emitting elements are configured of a first semiconductor layer composed of a group III nitride semiconductor having a first conductivity type, a group III nitride semiconductor, provided in contact with the first semiconductor layer, and energized. A light emitting layer that emits light and a group III nitride semiconductor having a second conductivity type opposite to the first conductivity type, and a second semiconductor layer provided in contact with the light emitting layer,
The external electrode is provided through the base and the joint, and has one end electrically connected to the first semiconductor layer in the semiconductor light emitting device and the other end exposed to the outside from the base. And a second electrode that is provided through the base and the junction, has one end electrically connected to the second semiconductor layer in the semiconductor light emitting element, and the other end exposed to the outside from the base. The element group forming substrate according to claim 12 or 13,

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