JP2013015334A - Battery voltage detection system - Google Patents

Abstract

A cell voltage of a plurality of battery cells connected in series constituting a battery is detected with high accuracy with a simple configuration.
A battery voltage detection system according to the present invention includes a selector (120) that sequentially selects and outputs terminal voltages of a plurality of battery cells, and a level shifter that includes an input impedance circuit element (C1) and level-shifts the output of the selector. (130), the analog / digital converter (140) for analog / digital conversion of the output of the level shifter, and the output of the analog / digital converter for each cell voltage based on the control signal The first-stage digital processor (150) for converting the digital value into a digital value, and the digital value output from the first-stage digital processor is digitally corrected to remove an error component based on the bias dependence of the input impedance circuit element, and then output. A post-stage digital processor (160).
[Selection] Figure 1

Description

  The present invention relates to a battery voltage detection system.

  As one of the safety measures for a battery in which a plurality of battery cells are connected in series and modularized, management of voltages of the plurality of battery cells (hereinafter referred to as cell voltages) can be mentioned. Specifically, charge / discharge control based on values obtained by measuring each cell voltage is performed. In particular, a battery mounted on a hybrid electric vehicle (HEV) or an electric vehicle (EV) has a higher output voltage, energy density, and efficiency than other secondary batteries. Lithium ion batteries are used. However, it is known that the charge and discharge of lithium ion batteries is difficult to control and has a risk of bursting or firing. Therefore, when a lithium ion battery is used as a vehicle-mounted battery, various safety measures are indispensable in charge / discharge control.

  For example, Patent Document 1 proposes a battery voltage detection system that detects each cell voltage of a battery in which a plurality of battery cells are connected in series with high accuracy. FIG. 9 is a diagram showing the configuration of the battery voltage detection system disclosed in Patent Document 1. As shown in FIG.

  The battery voltage detection system 10A shown in FIG. 9 has an operational amplifier 20 in which the reference voltage Vref1 of the power supply 30 is applied to one input terminal and one end of the capacitor C1 is connected to the other input terminal, and the other input terminal of the operational amplifier 20. And a capacitor C2 provided between the output terminals, and a circuit for sequentially applying one and other terminal voltages V1 to V4 of the four battery cells BV1 to BV4 to the other end of the capacitor C1 (switches SW0 to SW5, power supply 31). A circuit (switch SW6, transistors 41 to 47) for discharging the capacitor C2 in accordance with the discharge start signal CHG, the reference voltage Vref1 is applied to one input terminal, and the other input terminal is the output terminal of the operational amplifier 20 And the output signal C of the comparator 25 after the discharge start signal CHG is input. A counter 50 that measures the time until P changes, and a switch control circuit 35 that controls on / off of the switches SW0 to SW6 based on a signal input from the microcomputer 55, are applied to the other input terminal of the operational amplifier 20. An offset is provided so that the output signal CMP of the comparator 25 changes when the applied voltage becomes a voltage of a predetermined level lower than the reference voltage Vref1.

  For example, when detecting the cell voltage of the battery cell BV4, the counter 50 is turned on and off sequentially in a predetermined sequence so that the counter 50 has a time corresponding to the ground voltage Vss and a reference The time according to voltage Vref2 and the time according to cell voltage VBV4 of battery cell BV4 are each measured. The microcomputer 55 compares the measured times to detect the cell voltage of the battery cell BV4 so that the influence due to the change in the clock frequency is canceled out.

JP 2010-60435 A

  Incidentally, the battery voltage detection system shown in FIG. 9 has a problem that it is necessary to control a complicated switch in order to detect the cell voltage with high accuracy. Therefore, for example, when the cell voltage of the battery cell BV4 is detected without providing the counter 50 shown in FIG. 9, the switches SW3 and SW4 are turned on and the other switches SW0, SW1 and SW2 are turned off. As a result, a voltage corresponding to the difference between the positive terminal voltage V4 and the negative terminal voltage V3 of the battery cell BV4 is output as the output voltage Vout of the operational amplifier 20, and the analog / digital converter (not shown) outputs the output voltage Vout. Is converted into a digital value, the microcomputer 55 can detect the cell voltage of the battery cell BV4. The cell voltages of the other battery cells BV1 to BV3 can be similarly detected.

  However, in this case, the bias voltage applied between both electrodes of the capacitor C1 connected to the other input terminal of the operational amplifier 20 changes every time the battery cell to be detected for the cell voltage is different. For example, when a lithium ion battery is adopted as the battery cells BV1 to BV4, it is known that the battery cells BV1 to BV4 at the time of full charge reach close to 4.5V.

  Here, it is assumed that the voltages of the battery cells BV1 to BV4 are all 5V and the reference voltage Vref1 is 2.5V. That is, V0 = 0V, V1 = 5V, V2 = 10V, V3 = 15V, and V4 = 20V. In this case, if the offset of the operational amplifier 20 is not taken into consideration, the bias voltage applied between both electrodes of the capacitor C1 is −2.5V (= Vss−Vref1), 2.5V (= V1−Vref1), 7.5V. (= V2-Vref1), 12.5V (= V3-Vref1), or 17.5V (= V4-Vref1). Thus, although the cell voltages of the battery cells BV1 to BV4 are all 5V, the bias voltages applied between the two electrodes of the capacitor C1 are different, so that the cell voltages of the battery cells BV1 to BV4 are detected. The generated voltage differs depending on the bias dependency of the capacitor C1.

  For example, when the bias dependency of the capacitor C1 is expressed as an error of 0.1 (% / V), the voltage detected as the cell voltage of the battery cell BV1 is 0.25% (= 2.5 × 0. 1) A voltage error (−25 mV) is generated, and the voltage detected as the cell voltage of the battery cell BV2 is 0.75% (= 7.5 × 0.1) maximum voltage error (−75 mV). The voltage detected as the cell voltage of the battery cell BV3 causes a voltage error (−125 mV) of 1.25% (= 12.5 × 0.1) at the maximum, and is detected as the cell voltage of the battery cell BV4. This causes a voltage error (−175 mV) of 1.75% (= 17.5 × 0.1) at maximum. Thus, although each cell voltage of battery cell BV1-BV4 is all 5V, there existed a problem that each cell voltage was not able to be detected appropriately.

  In addition to the configuration of the voltage detection system shown in FIG. 9, for example, even when the capacitors C1 and C2 are replaced with resistors in the voltage detection system shown in FIG. Problems will arise.

  The present invention has been made to solve such a problem, and can detect battery voltages of a plurality of battery cells connected in series constituting a battery with a simple configuration with high accuracy. The purpose is to provide a system.

  In order to solve the above-described problem, a battery voltage detection system according to an aspect of the present invention is configured such that a terminal voltage of each of a plurality of battery cells connected in series constituting a battery is input and the terminal voltage is selected. A selector for multiplexing based on a signal, a level shifter for level-shifting the output of the selector, the level shifter provided with an input impedance circuit element on the input side, and an output of the level shifter for analog / digital An analog / digital converter for converting and outputting, a pre-stage digital processor for converting an output of the analog / digital converter into a digital value corresponding to a cell voltage of each of the plurality of battery cells based on a control signal, and The input impedance circuit is applied to the digital value output from the preceding digital processor. And subsequent digital processor which outputs the digital correction to remove the error component based on the bias dependence of the elements, in which and a control unit for generating at least the selector signal and the control signal.

  According to this configuration, an error component based on the bias dependency of the input impedance circuit element due to the output of the selector, that is, the terminal voltage of each of the plurality of battery cells can be removed, and the cell voltage of each of the plurality of battery cells Can be detected with high accuracy.

  In the battery voltage detection system, the pre-stage digital processor is offset from the output of the analog / digital converter before the output of the analog / digital converter is separated into a digital value corresponding to the cell voltage. It may be configured to perform correction and gain correction.

  According to this configuration, before removing the error component based on the bias dependency of the input impedance circuit element of the level shifter, the offset error and the gain error component of the selector and the level shifter are removed, so that the cell voltages of each of the plurality of battery cells are obtained. Furthermore, it becomes possible to detect with high accuracy.

  In the battery voltage detection system, the input impedance circuit element is a capacitor, and the post-stage digital processor is configured to perform digital correction to remove an error component based on bias dependency of the capacitor. Also good.

  According to this configuration, it is possible to remove an error component based on the bias dependency of the capacitor as the input impedance circuit element of the level shifter, and to detect the cell voltages of each of the plurality of battery cells with higher accuracy. .

  In the battery voltage detection system, the input impedance circuit element is a resistor, and the post-stage digital processor is configured to perform digital correction to remove an error component based on the bias dependency of the resistor. Also good.

  According to this configuration, it is possible to remove an error component based on the bias dependency of the resistance as an input impedance circuit element of the level shifter, and to detect the cell voltages of each of the plurality of battery cells with higher accuracy. .

  ADVANTAGE OF THE INVENTION According to this invention, the battery voltage detection system which can detect the cell voltage of each of the several battery cell connected in series which comprises a battery with a simple structure with high precision can be provided.

FIG. 1 is a diagram showing a configuration example of a battery voltage detection system according to Embodiment 1 of the present invention. FIG. 2 is a functional block diagram relating to digital correction of the pre-stage digital processor shown in FIG. FIG. 3 is a conceptual diagram for explaining the contents of digital correction by the preceding digital processor shown in FIG. FIG. 4 is a functional block diagram relating to digital correction of the latter-stage digital processor shown in FIG. FIG. 5 is a functional block diagram of the arithmetic unit shown in FIG. FIG. 6 is another functional block diagram of the arithmetic unit shown in FIG. FIG. 7 is a waveform diagram of main signals of the battery voltage detection system shown in FIG. FIG. 8 is a diagram showing a configuration example of a battery voltage detection system according to Embodiment 2 of the present invention. FIG. 9 is a diagram showing a configuration of a conventional battery voltage detection system.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. In the following description, the same or corresponding elements are denoted by the same reference symbols throughout the drawings, and redundant description thereof is omitted.

(Embodiment 1)
[Configuration example]
Hereinafter, Embodiment 1 of the present invention will be described with reference to FIG. In addition, FIG. 1 is a figure which shows the structural example of the battery voltage detection system which concerns on Embodiment 1 of this invention.

  The battery voltage detection system shown in FIG. 1 converts the cell voltage of each of the four battery cells BV1 to BV4 constituting the battery 110 into a continuous digital value by multiplexing, and converts the continuous digital value into a plurality of cells. This is a system configured to demultiplex individual digital values according to the voltage and output them to an external system controller. In the battery shown in FIG. 1, four battery cells BV <b> 1 to BV <b> 4 are connected in series. However, the configuration is not limited to this. The cell voltages of the four battery cells BV1 to BV4 may be uniform values or different values. For example, all the cell voltages of the battery cells BV1 to BV4 may be 5V, the cell voltage of the battery cell BV1 is 2.5V, the cell voltage of the battery cell BV2 is 5V, the cell voltage of the battery cell BV3 is 1V, The cell voltage of the battery cell BV4 may be 4V.

  The battery voltage detection system shown in FIG. 1 includes a selector 120, a level shifter 130, an analog / digital converter 140, a pre-stage digital processor 150, a post-stage digital processor 160, a register 170, and a controller 180. I have.

  The selector 120 receives the terminal voltages VC0 to VC4 of each of the four battery cells BV1 to BV4, selects one of these terminal voltages VC0 to VC4 according to the selector signal from the controller 180, and converts it into a level shifter. The input voltage signal Vin is output as 130. Specifically, the selector 120 is configured by switches SW0 to SW4 that are input with terminal voltages VC0 to VC4 at one end and are commonly connected to the other ends. Since the terminal voltages VC0 to VC4 are cyclically selected based on the selector signal from the controller 180, the input voltage signal Vin output from the selector 120 toward the level shifter 130 is continuously repeated with the terminal voltages VC0 to VC4. Configured to do.

  The level shifter 130 is configured to output an output voltage signal Vout obtained by level shifting the input voltage signal Vin from the selector 120. In the present embodiment, the level shifter 130 is realized as an inverting amplifier circuit in which the capacitors C1, C2, and C3 are connected to the differential amplifier 131. Specifically, the level shifter 130 includes a differential amplifier 131, a voltage source 132 that applies a reference voltage Vref to the non-inverting input terminal of the differential amplifier 131, and one electrode connected to the output of the selector 120. The capacitor C1 whose electrode is connected to the inverting input terminal of the differential amplifier 131, the capacitor C2 whose one electrode is connected to the other electrode of the capacitor C1 and the inverting input terminal of the differential amplifier 131, and the differential amplifier A capacitor C3 provided between the inverting input terminal and the output terminal of 131, a switch SW_N provided between the other electrode of the capacitor C2 and the ground, and the other electrode of the capacitor C2 and the reference voltage Vref are generated. A switch SW_P1 provided between the voltage source 133 and the switch SW_P2 connected in parallel with the capacitor C3. It made. The level shifter 130 may be configured without using the differential amplifier 131, or may be configured to be included in an input unit of an analog / digital converter 140 described later.

  The analog / digital converter 140 converts the analog output signal Vout from the level shifter 130 into a digital output signal ADCOUT. The output signal ADCOUT of the analog / digital converter 140 is configured such that the digital conversion values of the terminal voltages VC0 to VC4 of the battery cells BV1 to BV4 are continuous. The analog / digital converter 140 may be of any type such as a delta sigma (ΔΣ) type or a successive approximation type (SAR) type. In the case of the ΔΣ type, a digital filter is required in the subsequent stage.

  The pre-stage digital processor 150 is configured to demultiplex and output individual digital values Data1 to Data4 corresponding to the cell voltages of the four battery cells BV1 to BV4 from the output signal ADCOUT of the analog / digital converter 140. ing. Further, the pre-stage digital processor 150 performs digital correction before the output signal ADCOUT of the analog / digital converter 140 is output to the sub-stage digital processor 160 in order to remove the influence of the offset error and gain error of the selector 120 and the level shifter 130. Is configured to do. The pre-stage digital processor 150 is realized by a DSP, a logic circuit, or the like. Further, the pre-stage digital processor 150 may be configured to output continuous digital values Data1 to Data4 without demultiplexing the output signal ADCOUT of the analog / digital converter 140. Even in this case, the pre-stage digital processor 150 is configured to digitally correct the output signal ADCOUT of the analog / digital converter 140 in order to remove the influence of the offset error and gain error of the selector 120 and the level shifter 130.

  The post-stage digital processor 160 digitally corrects the individual digital values Data1 to Data4 output from the pre-stage digital processor 150 in order to remove an error component based on the bias dependency of the capacitor C1, and the result is a corresponding register 170a. ˜170d is stored in each. For example, when the bias dependency of the capacitor C1 is 0.1% / V, the error component ΔV generated with respect to the difference voltage (VC1−Vref) between the terminal voltage VC1 and the reference voltage Vref is 0.001 × (VC1−Vref). The post-stage digital processor 160 performs digital correction to remove this error component ΔV. The post-stage digital processor 160 is realized by a DSP, a logic circuit, or the like, like the pre-stage digital processor 150.

  The registers 170a to 170d are configured to be accessible by an external system controller (not shown) that manages measurement data. The system controller is, for example, a microcontroller or CPU.

  The controller 180 controls the entire battery voltage detection system. In particular, the controller 180 cyclically turns on and off the switches SW0 to SW4 of the selector 120, and turns on and off the switches SW_P1, SW_P2, and SW_N of the level shifter 130. A control signal for controlling the demultiplexing in the pre-stage digital processor 150, and the like. The controller 180 is realized by a DSP, a logic circuit, or the like. Moreover, the form which the several controller 180 carries out the distributed process of the below-mentioned control may be sufficient. Alternatively, the controller 180 may be configured integrally with an external system controller.

[Pre-stage digital processor]
FIG. 2 is a functional block diagram relating to digital correction of the pre-stage digital processor 150. As shown in FIG. 2, the pre-stage digital processor 150 includes an offset correction adder 151 that adds a correction value k1 to the input signal. And a gain correction multiplier 152 that multiplies the output of the adder 151 by a correction value k2. FIG. 3 is a conceptual diagram for explaining the contents of digital correction by the pre-stage digital processor 150 shown in FIG. As shown in FIG. 3, after the correction value k1 is added to the input signal (offset correction) so that the output according to the center code (median value) of the input signal becomes the output center, the full code (maximum of the input signal) Value) and zero code (minimum value), the input signal after offset correction is multiplied by a correction value k2 (gain correction) so that the output corresponding to the zero code (minimum value) approaches the ideal value.

  As described above, the digital correction by the post-stage digital processor 160 is executed with high accuracy by performing the offset correction and the gain correction by the pre-stage digital processor 150 prior to the digital correction by the post-stage digital processor 160. Can do.

[Second-stage digital processor]
FIG. 4 is a functional block diagram relating to digital correction of the post-stage digital processor 160. In the figure, Data1 is a digital value corresponding to the cell voltage (= VC1-VC0) of the battery cell BV1, Data2 is a digital value corresponding to the cell voltage (= VC2-VC1) of the battery cell BV2, and Data3 is It is a digital value corresponding to the cell voltage (= VC3-VC2) of the battery cell BV3, and Data4 is a digital value corresponding to the cell voltage (= VC4-VC3) of the battery cell BV4.

  The post-stage digital processor 160 shown in FIG. 4 includes an adder 161a that adds the digital value Data1 and the digital value Data2, an adder 161b that adds the output Data2B (= Data1 + Data2) of the adder 161a and the digital value Data3, An adder 161c that adds the output Data3B (= Data1 + Data2 + Data3) of the adder 161b and the digital value Data4 is provided. The output Data4B of the adder 161c is “Data1 + Data2 + Data3 + Data4”. Here, the digital value Data1, the output Data2B of the adder 161a, the output Data3B of the adder 161b, and the output Data4B of the adder 161c correspond to the respective terminal voltages of the battery cells BV1 to BV4 as shown in the following equations.

Data1 = VC1-VC0 (1-1)
Data2B = Data1 + Data2
= VC1-VC0 + VC2-VC1
= VC2-VC0 (1-2)
Data3B = Data1 + Data2 + Data3
= VC1 + VC2-VC1 + VC3-VC2
= VC3-VC0 (1-3)
Data4B = Data1 + Data2 + Data3 + Data4
= VC1 + VC2-VC1 + VC3-VC2 + VC4-VC3
= VC4-VC0 (1-4)
That is, in the pre-stage digital processor 150, the terminal voltages VC0 to VC4 of the battery cells BV1 to BV4 included in the output signal ADCOUT of the analog / digital converter 140 are converted to the cell voltages of the battery cells BV1 to BV4. Therefore, the digital values Data1 to Data4 corresponding to the cell voltages of the battery cells BV1 to BV4 are temporarily returned to digital values corresponding to the terminal voltages VC1 to VC4 of the battery cells BV1 to BV4 by the adders 161a to 161c.

  Further, the post-stage digital processor 160 shown in FIG. 4 includes an arithmetic unit 162a that digitally corrects the digital value Data1 based on the correction value k3, an arithmetic unit 162b that digitally corrects the output Data2B of the adder 161a based on the correction value k3, An arithmetic unit 162c that digitally corrects the output Data3B of the adder 161b based on the correction value k3, and an arithmetic unit 162d that digitally corrects the output Data4B of the adder 161c based on the correction value k3.

  In other words, the arithmetic units 162a to 162d perform digital correction on the values returned to the digital values corresponding to the terminal voltages VC1 to VC4 of the battery cells BV1 to BV4 by the adders 161a to 161d.

  Further, the post-stage digital processor 160 shown in FIG. 4 subtracts the output Dout1B of the computing unit 162a from the output Dout2B of the computing unit 162b, and subtracts the output Dout2B of the computing unit 162b from the output Dout3B of the computing unit 162c. A subtractor 163b; and a subtractor 163c that subtracts the output Dout3B of the calculator 162c from the output Dout4B of the calculator 162d. Here, the output Dout1 of the calculator 162a, the output Dout2 of the subtractor 163a, the output Dout3 of the subtractor 163b, and the output Dout4 of the subtractor 163c satisfy the condition of “input = output” in all the calculators 162a to 162d. Then, the cell voltages of the battery cells BV <b> 1 to BV <b> 4 are as shown in the following formulas.

Dout1 = VC1-VC0 (2-1)
Dout2 = Dout2B−Dout1B
= VC2-VC1 (2-2)
Dout3 = Dout3B−Dout2B
= VC3-VC2 (2-3)
Dout4 = Dout4B-Dout3B
= VC4-VC3 (2-4)
That is, the digital values corresponding to the terminal voltages VC1 to VC4 of the battery cells BV1 to BV4 after digital correction by the arithmetic units 162a to 162d correspond to the cell voltages of the battery cells BV1 to BV4 by the subtractors 163a to 163d. Is returned to the digital value.

  FIG. 5 is a functional block diagram of the computing unit 162 (162a to 162d) shown in FIG. The arithmetic unit 162 shown in FIG. 5 includes a multiplier 164 that multiplies the square of the input Din by the correction value k3, and a subtractor 165 that subtracts the output of the multiplier 164 from the input Din. That is, the output Dout of the subtracter 165 is a quadratic function of the input Din as shown in the following equation.

  Dout = Din−k3 · Din ^ 2 (3)

  FIG. 6 is another functional block diagram of the calculator 162 (162a to 162) shown in FIG. In addition to the multiplier 164 and the subtractor 165 shown in FIG. 5, the arithmetic unit 162 shown in FIG. 6 includes a multiplier 166 that squares the input Din, and a correction value that is different from the correction value k3 with respect to the output of the multiplier 166. A multiplier 167 that multiplies k4 and a subtracter 168 that subtracts the output of the multiplier 167 from the output of the subtractor 165 are provided. That is, the output Dout of the subtracter 168 is a quadratic function of the input Din as shown in the following equation.

Dout = Din (1−k3−k4 · Din) (4)
Note that the calculators 162 (162a to 162d) shown in FIG. 4 are not limited to the configuration examples shown in FIGS. 5 and 6, and may be configured to be, for example, a third-order function or more of the input Din. As will be described later, the order of the function of the input Din realized by the calculator 162 is determined according to the order of the function that defines the bias dependency of the capacitor C1.

[System operation example]
An operation example of the battery voltage detection system shown in FIG. 1 will be described with reference to FIG. FIG. 7 is a waveform diagram of main signals of the battery voltage detection system shown in FIG.

  The operation of detecting the cell voltage of the battery cell BV1 will be described.

  First, the switch SW0 of the selector 120 is turned on, and the switches SW_P1 and SW_P2 of the level shifter 130 are turned on. The other switches SW1 to SW4 and SW_N are all turned off. At this time, the electrode voltages of the capacitors C1 and C3 on the inverting input end side of the differential amplifier 131 are equal to the reference voltage Vref applied to the non-inverting input end of the differential amplifier 131. Here, since the electrode voltage of the capacitor C1 on the selector 120 side is one terminal voltage VC0 of the battery cell BV1, the capacitor C1 has a difference voltage (VC0−) between the one terminal voltage VC0 of the battery cell BV1 and the reference voltage Vref. Vref) is applied. At this time, if the charge accumulated in the capacitor C1 is represented as Q1A, the charge Q1A is represented by the following equation.

Q1A = (VC0−Vref) × C1 (5)
The electrode voltage of the capacitor C3 on the output end side of the differential amplifier 131 is the reference voltage Vref. Here, since the electrode voltage of the capacitor C3 on the inverting input end side of the differential amplifier 131 is also the reference voltage Vref, both electrodes of the capacitor C3 are short-circuited, and the charge already charged in the capacitor C3 is reset. (Discharged).

  Next, the switch SW0 of the selector 120 is switched from on to off, and the switches SW_P1 and SW_P2 of the level shifter 130 are switched from on to off. Then, the switch SW1 of the selector 120 is switched from OFF to ON, and the switch SW_N of the level shifter 130 is switched from OFF to ON. At this time, the electrode voltage of the capacitor C1 on the selector 120 side becomes the other terminal voltage VC1 of the battery cell BV1. Further, the electrode voltage of the capacitor C1 on the inverting input end side of the differential amplifier 131 becomes equal to the reference voltage Vref. For this reason, the electric charge corresponding to the voltage (VC1-Vref) between both electrodes of the capacitor C1 is transferred to the capacitor C2. If the charge transferred to the capacitor C2 at this time is represented as Q1B, the charge Q1B is represented by the following equation.

Q1B = (VC1-Vref) × C1 (6)
The capacitor C3 is charged with a charge corresponding to the difference voltage between the reference voltage Vref and the ground, and the same charge is charged to the capacitor C2. At this time, if the charge accumulated in the capacitors C2 and C3 is represented as Q3B, the charge Q3B is represented by the following equation.

Q3B = −Vref × C3 (7)
As a result, the output voltage Vout of the differential amplifier 131 corresponding to the cell voltage of the battery cell BV1 is expressed as the following expression as the sum of the voltage between both electrodes of the capacitor C3 and the voltage between both electrodes of the capacitor C2. The

Vout = Q1A-Q1B-Q3B
= Vref * C3 / C2-{(VC1-VC0) * C1 / C2} (8)

  Next, the cell voltage detection operation of the battery cell BV2 will be described.

  First, the switch SW1 of the selector 120 is turned on, and the switches SW_P1 and SW_P2 of the level shifter 130 are turned on. The other switches SW0, SW2 to SW4, SW_N are all off. At this time, the electrode voltages of the capacitors C1 and C3 on the inverting input end side of the differential amplifier 131 are equal to the reference voltage Vref applied to the non-inverting input end of the differential amplifier 131. Here, since the electrode voltage of the capacitor C1 on the selector 120 side is the one terminal voltage VC1 of the battery cell BV2, the voltage difference between the one terminal voltage VC1 of the battery cell BV2 and the reference voltage Vref (VC1−VC1). Vref) is applied. The electrode voltage of the capacitor C3 on the output end side of the differential amplifier 131 is the reference voltage Vref. Therefore, the capacitor C3 is short-circuited and the charge already charged in the capacitor C3 is reset (discharged).

  Next, the switch SW1 of the selector 120 is switched from on to off, and the switches SW_P1 and SW_P2 of the level shifter 130 are switched from on to off. Then, the switch SW2 of the selector 120 is switched from OFF to ON, and the switch SW_N of the level shifter 130 is switched from OFF to ON. At this time, the electrode voltage of the capacitor C1 on the selector 120 side becomes the other terminal voltage VC2 of the battery cell BV2. Further, the electrode voltage of the capacitor C1 on the inverting input end side of the differential amplifier 131 becomes equal to the reference voltage Vref. For this reason, the electric charge corresponding to the voltage (VC2-Vref) between both electrodes of the capacitor C1 is transferred to the capacitor C2. In addition, due to a virtual short circuit between the inverting input terminal and the non-inverting input terminal of the differential amplifier 131, the capacitor C3 is charged with a charge corresponding to the reference voltage Vref. As a result, the output voltage Vout of the differential amplifier 131 corresponding to the cell voltage of the battery cell BV2 is expressed by the following equation.

  Vout = Vref * C3 / C2-{(VC2-VC1) * C1 / C2} (9)

  Next, the cell voltage detection operation of the battery cell BV3 will be described.

  First, the switch SW2 of the selector 120 is turned on and the switches SW_P1 and SW_P2 of the level shifter 130 are turned on. The other switches SW0, SW1, SW3, SW4, SW_N are all off. At this time, the electrode voltages of the capacitors C1 and C3 on the inverting input end side of the differential amplifier 131 are equal to the reference voltage Vref applied to the non-inverting input end of the differential amplifier 131. Here, since the electrode voltage of the capacitor C1 on the selector 120 side is the one terminal voltage VC2 of the battery cell BV3, the capacitor C1 has a difference voltage (VC0−) between the one terminal voltage VC2 of the battery cell BV3 and the reference voltage Vref. Vref) is applied. The electrode voltage of the capacitor C3 on the output end side of the differential amplifier 131 is the reference voltage Vref. Therefore, both electrodes of the capacitor C3 are short-circuited, and the charge already charged in the capacitor C3 is reset (discharged).

  Next, the switch SW2 of the selector 120 is switched from on to off, and the switches SW_P1 and SW_P2 of the level shifter 130 are switched from on to off. Then, the switch SW3 of the selector 120 is switched from OFF to ON, and the switch SW_N of the level shifter 130 is switched from OFF to ON. At this time, the electrode voltage of the capacitor C1 on the selector 120 side becomes the other terminal voltage VC3 of the battery cell BV3. Further, the electrode voltage of the capacitor C1 on the inverting input end side of the differential amplifier 131 becomes equal to the reference voltage Vref. For this reason, the electric charge corresponding to the voltage (VC3-Vref) between both electrodes of the capacitor C1 is transferred to the capacitor C2. In addition, due to a virtual short circuit between the inverting input terminal and the non-inverting input terminal of the differential amplifier 131, the capacitor C3 is charged with a charge corresponding to the reference voltage Vref. As a result, the output voltage Vout of the differential amplifier 131 corresponding to the cell voltage of the battery cell BV3 is expressed by the following equation.

  Vout = Vref * C3 / C2-{(VC3-VC2) * C1 / C2} (10)

  Next, the cell voltage detection operation of the battery cell BV4 will be described.

  First, the switch SW3 of the selector 120 is turned on, and the switches SW_P1 and SW_P2 of the level shifter 130 are turned on. The other switches SW0 to SW2, SW4, and SW_N are all off. At this time, the electrode voltages of the capacitors C1 and C3 on the inverting input end side of the differential amplifier 131 are equal to the reference voltage Vref applied to the non-inverting input end of the differential amplifier 131. Here, since the electrode voltage of the capacitor C1 on the selector 120 side is the one terminal voltage VC3 of the battery cell BV4, the capacitor C1 has a difference voltage (VC3-) between the one terminal voltage VC3 of the battery cell BV4 and the reference voltage Vref. Vref) is applied. The electrode voltage of the capacitor C3 on the output end side of the differential amplifier 131 is the reference voltage Vref. Therefore, the capacitor C3 is short-circuited, and the charge already charged in the capacitor C3 is reset (discharged).

Next, the switch SW3 of the selector 120 is switched from on to off, and the switches SW_P1 and SW_P2 of the level shifter 130 are switched from on to on. Then, the switch SW4 of the selector 120 is switched from OFF to ON, and the switch SW_N of the level shifter 130 is switched from OFF to ON. At this time, the electrode voltage of the capacitor C1 on the selector 120 side becomes the other terminal voltage VC4 of the battery cell BV4. Further, the electrode voltage of the capacitor C1 on the inverting input end side of the differential amplifier 131 becomes equal to the reference voltage Vref. For this reason, the electric charge corresponding to the voltage (VC4-Vref) between both electrodes of the capacitor C1 is transferred to the capacitor C2. In addition, due to a virtual short circuit between the inverting input terminal and the non-inverting input terminal of the differential amplifier 131, the capacitor C3 is charged with a charge corresponding to the reference voltage Vref. As a result, the output voltage Vout of the differential amplifier 131 corresponding to the cell voltage of the battery cell BV4 is expressed by the following equation.

Vout = Vref * C4 / C2-{(VC4-VC2) * C1 / C2} (11)
By repeating the above operation, the detection voltage of the difference voltage (VC2-VC1) between the two terminals of the battery cell BV2 is detected as Vdata1 which is the detection voltage of the difference between the two terminals of the battery cell BV1 (VC1-VC0). Vdata3, which is a detection voltage of a difference voltage (VC3-VC2) between both terminal voltages of a certain Vdata2, battery cell BV3, and Vdata4, which is a detection voltage of a difference voltage (VC4-VC3) of both terminal voltages of the battery cell BV4, is a difference. The output voltage Vout of the dynamic amplifier 131 is sequentially output.

Vdata1 = Vref * C3 / C2-{(VC1-VC0) * C1 / C2} (12)
Vdata2 = Vref * C3 / C2-{(VC2-VC1) * C1 / C2} (13)
Vdata3 = Vref * C3 / C2-{(VC3-VC2) * C1 / C2} (14)
Vdata4 = Vref × C3 / C2-{(VC4-VC3) × C1 / C2} (15)
The detection voltages Vdata1 to Vdata4 of the battery cells BV1 to BV4 obtained as the output voltage Vout of the differential amplifier 131 are converted into digital values by the analog / digital converter 140, and offset correction and gain correction are performed by the pre-stage digital processor 150. After that, it is demultiplexed into individual digital values Data1 to Data4. Further, digital correction is performed on the digital values Data1 to Data4 input from the pre-stage digital processor 150 in order to remove an error component based on the bias dependency of the capacitor C1 by the post-stage digital processor 160. As a result, the registers 170a to 170d store the cell voltages of the battery cells BV1 to BV4 from which the error components based on the offset error and gain error of the selector 120 and the level shifter 130 and the bias dependency of the capacitor C1 are removed. It will be.

[Example of removing error components based on bias dependence]
Incidentally, the bias dependence of the capacitor C1 represents the alpha, the potential difference between the electrodes of the capacitor C1 represents a C1 ₀ a capacitance value at 0V, when the voltage applied between the opposing electrodes of the capacitor C1 and [Delta] V, the capacitor C1 The capacitance value of is expressed as follows.
C1 = C1 ₀ × (1 + α × ΔV) (16)
When the formula (13) is applied to the formulas (5), (6), and (7), the charges Q1A, Q1B, and Q3B are respectively expressed as the following formulas.
Q1A = (VC0−Vref) × C1 ₀ × {1 + α × (VC0−Vref)} (17)
Q1B = (VC1-Vref) × C1 ₀ × {1 + α × (VC1-Vref)) (18)
Q3B = −Vref × C3 (19)

Here, the detection voltage of the battery cell BV1 that appears as the output voltage Vout of the differential amplifier 131 when the reference voltage Vref is 0 V without considering the bias dependency of the capacitors C2 and C3 and for the sake of simplification of description. Vdata1 (α) is expressed as the following equation. For simplification of explanation, “C1 / C2” is set to “1”.
Vdata1 (α) = Q1A-Q1B-Q3B
= (VC0−VC1) × C1 / C2 + α × C1 / C2 (VC0 ² −VC1 ² )
= (VC0−VC1) + α × (VC0 ² −VC1 ² ) (20)
Therefore, the term “α × C1 / C2 (VC0 ² −VC1 ² )” in the equation (20) becomes an error component of Vdata1 (α) due to the influence of the bias dependency α of the capacitor C1. Here, this error component is expressed as ΔVe1.
ΔVe1 = α × (VC0 ² −VC1 ² ) (21)

Similarly, the detection voltage Vdata2 (α) of the battery cell BV2, the detection voltage Vdata3 (α) of the battery cell BV3, and the detection voltage Vdata4 (α) of the battery cell BV4 are expressed by the following equations, respectively.
Vdata2 (α) = (VC1−VC2) + α × (VC1 ² −VC2 ² ) (22)
Vdata3 (α) = (VC2−VC3) + α × (VC2 ² −VC3 ² ) (23)
Vdata4 (α) = (VC3−VC4) + α × (VC3 ² −VC4 ² ) (24)

Also, the error component ΔVe2 of Vdata2 (α), the error component ΔVe3 of Vdata3 (α), and the error component ΔVe4 of Vdata4 (α) are each expressed by the following equations.
ΔVe2 = α × (VC1 ² −VC2 ² ) (25)
ΔVe3 = α × (VC2 ² −VC3 ² ) (26)
ΔVe4 = α × (VC3 ² −VC4 ² ) (27)
Here, Data1, Data2B, Data3B, and Data4B of the post-stage digital processor 160 shown in FIG. 4 are expressed as follows.
Data1 = Vdata1 (α)
= (VC0-VC1) + α × (VC0 2 -VC1 2) ··· (28)
Data2B = Vdata1 (α) + Vdata2 (α)
= (VC0−VC2) + α × (V0 ² −V2 ² ) (29)
Data3B = Vdata1 (α) + Vdata2 (α) + Vdata3 (α)
= (VC0−VC3) + α × (V0 ² −V3 ² ) (30)
Data4B = Vdata1 (α) + Vdata2 (α) + Vdata3 (α) + Vdata4 (α)
= (VC0−VC4) + α × (V0 ² −V4 ² ) (31)

Since VC0 can be set to 0V as a reference voltage, Data1 and Data2B to 4B in the above expressions can be expressed as functions proportional to the absolute value of the cell voltage as in the following expression.
Data1 = −VC1−α × VC1 ² (32)
Data2B = −VC2−α × VC2 ² (33)
Data3B = −VC3−α × VC3 ² (34)
Data4B = −VC4−α × VC4 ² (35)
Here, it is assumed that the arithmetic units 162a to 162d of the post-stage digital processor 160 shown in FIG. 4 have the configuration shown in FIG. Taking the arithmetic unit 162a as an example, the output Deo of the multiplier 164 is approximated by the following equation when the correction value k3 is set to α. Note that the square of α is treated as being sufficiently smaller than α.
Deo = α × {−VC1−α × VC1 ² } ²
≒ α × VC1 ² (36)
Therefore, it can be seen that the error component ΔVe1 is canceled out from the output Dout1 of the calculator 162a as shown in the following equation.
Dout1 = Data1-Deo
= −VC1−α × VC1 ² + α × VC1 ²
= -VC1 (37)

In the above description, the bias dependency of the capacitor C1 is defined as a linear function as in the following equation.
C1 = C1 ₀ × (1 + α × ΔV) (38)
In addition to this, the bias dependence of the capacitor C1 may be defined as a quadratic function as in the following equation.
C1 = C1 ₀ × (1 + α × ΔV + β × ΔV2) (39)
In this case, the arithmetic units 162a to 162d of the post-stage digital processor 160 shown in FIG. 4 need to be configured according to a quadratic function as shown in FIG.

(Embodiment 2)
The second embodiment of the present invention will be described below with reference to FIG. In addition, FIG. 8 is a figure which shows the structural example of the battery voltage detection system which concerns on Embodiment 2 of this invention.

  The battery voltage detection system shown in FIG. 8 differs from the battery voltage detection system shown in FIG. 1 in the configuration of the selector 120, the level shifter 130, and the analog / digital converter 140. Other configurations are the same.

  The selector 120 receives the terminal voltages VC0 to VC4 of each of the four battery cells BV1 to BV4, and receives two terminal voltages corresponding to the cell voltages of the four battery cells BV1 to BV4 according to the selector signal from the controller 180. These are selected and output as differential input voltage signals VinP and VinN of the level shifter 130. Specifically, the selector 120 is supplied with terminal voltages VC0 to VC4 at one end and similarly connected to the switches SW0P to SW4P with the other ends connected in common, similarly to the terminal voltage VC0 to VC0 at one end. Switches SW0N to SW4N to which VC4 is input and the other ends are connected in common to each other, and one differential input voltage signal VinP is output from the other end of the switches SW0P to SW4P, and the switches SW0N to SW0N The other differential input voltage signal VinN is output from the other end of the SW4N. Note that the switches SW0P and SW0N, the switches SW1P and SW1N, the switches SW2P and SW2N, and the switches SW3P and 3N are configured to be simultaneously turned on and off by a selector signal from the controller 180.

  The level shifter 130 is configured to output differential output voltage signals VoutP and VoutN obtained by level shifting the differential input voltage signals VinP and VinN from the selector 120, respectively. In the present embodiment, the level shifter 130 is realized as two inverting amplifier circuits configured by two differential amplifiers 134 and 135. Specifically, the level shifter 130 includes a differential amplifier 134, a voltage source 136 that applies a reference voltage VrefP to the non-inverting input terminal of the differential amplifier 134, and one electrode connected to the output of the selector 120. The resistor R1P is connected to the inverting input terminal of the differential amplifier 134, and the resistor R2P is provided between the inverting input terminal and the output terminal of the differential amplifier 134. The output of the differential amplifier 134 is one differential output voltage signal VoutP. Further, the level shifter 130 includes a differential amplifier 135, a voltage source 137 for applying a reference voltage VrefN to the non-inverting input terminal of the differential amplifier 135, one electrode connected to the output of the selector 120, and the other electrode A resistor R1N connected to the inverting input terminal of the differential amplifier 135 and a resistor R2N provided between the inverting input terminal and the output terminal of the differential amplifier 135 are provided. The output of the differential amplifier 135 is one differential output voltage signal VoutN.

  The analog / digital converter 140 is configured to convert the differential voltage (VoutP−VoutN) between the differential output voltage signals VoutP and VoutN output from the level shifter 130 into a digital value and output the digital value to the pre-stage digital processor 150. Has been. That is, except for the differential input type, it is the same as the analog / digital converter 140 shown in FIG. 1, and there is no limitation on the type such as a delta sigma (ΔΣ) type or a successive approximation type (SAR) type.

  With the above configuration, the digital value is converted into a digital value by the analog / digital converter 140, and after being offset-corrected and gain-corrected by the pre-stage digital processor 150, it is demultiplexed into individual digital values Data1 to Data4. Further, digital correction is performed on the digital values Data1 to Data4 input from the pre-stage digital processor 150 in order to remove error components based on the bias dependence of the resistors R1P and R1N by the post-stage digital processor 160. As a result, the registers 170a to 170d store the cell voltages of the battery cells BV1 to BV4 from which the offset error and gain error of the selector 120 and the level shifter 130 and further the error based on the bias dependence of the resistors R1P and R1N are removed. Will be.

  From the foregoing description, many modifications and other embodiments of the present invention are obvious to one skilled in the art. Accordingly, the foregoing description should be construed as illustrative only and is provided for the purpose of teaching those skilled in the art the best mode of carrying out the invention. The details of the structure and / or function may be substantially changed without departing from the spirit of the invention.

  The present invention relates to a battery voltage detection system for detecting a cell voltage of each of a plurality of battery cells connected in series constituting a battery, in particular, a battery mounted on a vehicle when the plurality of battery cells are lithium ion batteries. This is useful for a battery voltage detection system for detecting each cell voltage.

BV1 to BV4 ... Battery cells VC0 to VC4 ... Terminal voltage 110 ... Battery 120 ... Selector SW0-SW4 ... Switch SW0P-SW4P, SW0N-SW4N ... Switch 130 ... Level shifter SW_P1, SW_P2, SW_N ... Switch C1 ... Capacitor (input impedance circuit element) )
C2 ... Capacitor C3 ... Capacitor 131 ... Differential amplifiers 132, 133 ... Voltage sources 134, 135 ... Differential amplifiers 136,137 ... Voltage source 140 ... Analog / digital converter 150 ... Pre-stage digital processor 151 ... Adder 152 ... Multiplication Unit 160... Post-stage digital processors 161 a to 161 c... Adders 162, 162 a to 162 d .. arithmetic units 163 a to 163 c .. subtracters 164, 166, 167 ... multipliers 165, 168. 180 ... Controllers R1P, R1N ... Resistance (input impedance circuit element)
R2P, R2N ... resistance

Claims (4)

A selector that inputs the terminal voltage of each of a plurality of battery cells connected in series constituting the battery and multiplexes the terminal voltage based on a selector signal;
A level shifter for level-shifting and outputting the output of the selector, the level shifter provided with an input impedance circuit element on its input side;
An analog / digital converter that performs analog / digital conversion on the output of the level shifter; and
A pre-stage digital processor that converts an output of the analog / digital converter into a digital value corresponding to a cell voltage of each of the plurality of battery cells based on a control signal;
A post-stage digital processor that digitally corrects and outputs an error component based on bias dependency of the input impedance circuit element with respect to the digital value output from the pre-stage digital processor;
A controller that generates at least the selector signal and the control signal;
A battery voltage detection system comprising:   The pre-stage digital processor performs offset correction and gain correction on the output of the analog / digital converter before the output of the analog / digital converter is separated into a digital value corresponding to the cell voltage. The battery voltage detection system according to claim 1, which is configured as follows. The input impedance circuit element is a capacitor;
The battery voltage detection system according to claim 1 or 2, wherein the latter-stage digital processor is configured to perform digital correction to remove an error component based on bias dependency of the capacitor. The input impedance circuit element is a resistor;
The battery voltage detection system according to claim 1 or 2, wherein the latter-stage digital processor is configured to perform digital correction so as to remove an error component based on bias dependency of the resistance.

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