JP2013098240A - Memory device, semiconductor device, and method of manufacturing semiconductor device - Google Patents

Abstract

A memory device, a semiconductor device, and a method for manufacturing the semiconductor device are provided.
A first chip mounted on a substrate and connected to the substrate by a bonding wire, and a second chip that is mounted on the substrate so as to be stacked on the first chip and is larger than the first chip. Is a method of manufacturing a semiconductor device having a chip. An insulating layer is applied to a portion corresponding to a portion where the bonding wire of the second chip is bonded to the first chip, and an adhesive layer is formed on the bonding surface of the second chip. The chip is pasted together.
[Selection] Figure 3

Description

  Embodiments described herein relate generally to a storage device, a semiconductor device, and a method for manufacturing the semiconductor device.

  A semiconductor device manufactured by laminating a plurality of semiconductor chips is known. In such a semiconductor device, a method is known in which each semiconductor chip is connected to a substrate by a bonding wire provided at the end of the semiconductor chip.

  In recent years, a configuration has been proposed in which a semiconductor chip larger than the lower chip (hereinafter referred to as the upper chip) is stacked on the semiconductor chip provided in the lower stage (hereinafter referred to as the lower chip). In such a configuration, in order to prevent the bonding wire at the end of the lower chip from coming into contact with the upper chip, the thickness of the adhesive layer connecting the upper chip and the lower chip is set to be higher than the height of the bonding wire protruding from the surface of the lower chip. It was also thick.

JP 2010-118395 A

Japanese Patent No. 4188337

  An object of the embodiments of the present invention is to provide a memory device, a semiconductor device, and a method for manufacturing the semiconductor device, which are low in manufacturing cost.

  A method for manufacturing a semiconductor device according to an embodiment includes a first chip mounted on a substrate and connected to the substrate by a bonding wire, and mounted on the substrate so as to be stacked on the first chip. A method of manufacturing a semiconductor device having a second chip larger than the first chip, wherein an insulating layer is formed on a portion of the second chip corresponding to a portion where a bonding wire is formed on an adhesive surface with the first chip Is applied, a bonding layer is formed on the bonding surface of the second chip, and the substrate and the second chip are bonded together.

1 is a plan view illustrating a configuration example of a semiconductor device according to a first embodiment. It is a side view of the semiconductor device. 4 is a flowchart showing a method for manufacturing the semiconductor device according to the embodiment. It is the schematic for demonstrating the 1st process of the manufacturing method. It is the schematic for demonstrating the 1st heat processing of the manufacturing method. It is the schematic for demonstrating the 2nd process of the manufacturing method. It is the schematic for demonstrating the 3rd process of the manufacturing method. It is the schematic for demonstrating the structure manufactured by the 3rd process of the manufacturing method.

[First Embodiment]
[overall structure]
FIG. 1 is a plan view illustrating a configuration example of the semiconductor device according to the first embodiment, and FIG. 2 is a side view of the semiconductor device. The semiconductor device according to this embodiment includes a substrate 1, a first chip 3 connected to the substrate 1 by a bonding wire 2, an adhesive layer 4 covering the entire first chip 3, and a substrate via the adhesive layer 4. 1 has a laminated body 5 connected to 1. The stacked body 5 includes a second chip 51 bonded to the substrate 1 and the first chip 3 through the adhesive layer 4 and a plurality of chips 52 stacked on the surface of the second chip 51. The second chip 51 and the plurality of chips 52 are connected to the substrate 1 by bonding wires 53 for the laminate. An insulating layer 6 is formed on a portion of the bonding surface of the second chip 51 to the first chip 3 that faces the bonding wire 2 provided on the first chip 3. For example, a semiconductor memory can be used for the second chip 51, and a memory controller for controlling the second chip 51 can be used for the first chip 3. When the area of the semiconductor memory is larger than the area of the memory controller, the storage capacity can be increased, which is suitable for the storage device using this embodiment.

[Production method]
Next, a method for manufacturing the semiconductor device according to the present embodiment will be described. FIG. 3 is a flowchart showing the method for manufacturing the semiconductor device according to the present embodiment.

  In the method for manufacturing a semiconductor device according to the present embodiment, as shown in FIG. 4, first, an insulating resin 6 </ b> A that becomes the insulating layer 6 is formed on the bonding surface of the silicon wafer 51 </ b> A that becomes the second chip 51 with a thickness of 5 to 10 μm, for example. Apply (step S1). In the present embodiment, a thermosetting epoxy-based insulating resin is used as the insulating resin 6A, but it is also possible to use an insulator that is cured by a method other than heat. The insulating resin 6 </ b> A is applied so as to draw a plurality of identical patterns for each portion that is later cut out from the silicon wafer 51 </ b> A to become a plurality of second chips 51. As the pattern, for example, a pattern with a width of 2 to 3 mm covering the periphery of the first chip 3 can be applied. For application of the insulating resin 6A, it is possible to use means such as an ink jet method.

  Next, as shown in FIG. 5, the silicon wafer 51A coated with the insulating resin 6A is subjected to a first heat treatment at 90 ° C. for about 1 hour, for example, to increase the viscosity of the insulating resin 6A to obtain the insulating resin 6B ( Step S2). Next, as shown in FIG. 6, a sheet-like adhesive 4A is attached to the bonding surface of the silicon wafer 51A (step S3), and the silicon wafer 51A is cut into a plurality of second chips 51 (step S4). As the adhesive 4A, a thermoplastic adhesive can be applied, and an acrylic or polyimide adhesive can also be used.

  Next, a second heat treatment is performed on the second chip 51 (step S5). The viscosity of the adhesive 4A is lowered by the second heat treatment, and becomes the adhesive 4B. In the second heat treatment, for example, the second chip 51 is placed on a preheated flat plate (not shown) for a few seconds, the second chip 51 is moved using a collet 7 which will be described later, This is performed by using heat transmitted from the substrate 1 heated in advance. Thereby, the adhesive 4A can be heated.

  As shown in FIG. 7, the second chip 51 is pasted on the first chip 3 by the collet 7 (step S6). The adhesive 4B has a reduced viscosity in the second heat treatment. When the first chip 3 and the second chip 51 are bonded together, the partial surface of the substrate 1, the bonding wire 2, and the first chip 3 are formed on the bonding surface of the second chip 51. Embedded in 4B. In addition, an insulating layer 6B is formed on a part of the bonding surface of the second chip 51 facing the bonding wire 2 to prevent the bonding wire 2 and the second chip 51 from contacting each other.

  In order to realize the above method, it is necessary to increase the viscosity of the insulating layer 6B to a certain level or more so that the bonding wire 2 does not penetrate. The necessary viscosity can be adjusted as appropriate depending on the diameter of the bonding wire 2 and the thickness of the insulating layer 6B. For example, when the bonding wire 2 having a diameter of 30 μm or less is used, the insulation can be obtained by setting the viscosity to about 100,000 Pas. The thickness of the layer 6B can be suppressed to 15 μm or less.

  Next, as shown in FIG. 8, a third heat treatment is performed on the semiconductor device in an atmosphere of, for example, 100 to 150 ° C. for about 1 hour (step S7). Cured by the third heat treatment, the viscosity of the insulating resin 6 </ b> B further increases and becomes the insulating layer 6. Similarly, the adhesive 4 </ b> B is cured to become the adhesive 4. Thereafter, a plurality of chips 52 are stacked on the second chip 51, the stacked body 5 is formed, and various contact wirings such as bonding wires 53 are formed, whereby a semiconductor device is manufactured.

  In the above manufacturing method, the second chip 51 and the bonding wire 2 are insulated by providing an insulating layer on the bonding surface of the second chip 51. Therefore, even when the thickness of the adhesive layer 4 is thinner than the height of the bonding wire 2 protruding from the surface of the first chip 3, the first chip 3 and the second chip 51 can be insulated. It is. Compared with the means for forming the adhesive layer up to the height of the bonding wire 2 protruding from the surface of the first chip 3, the above method can reduce the material cost of the adhesive layer, or from the surface of the first chip 3. A margin for processing variations in the height of the protruding bonding wire 2 is improved, and further miniaturization of the semiconductor device can be achieved.

  In addition, since the insulating layer 6 is provided only on the portion facing the bonding wire 2 instead of providing the insulating layer on the entire bonding surface of the second chip 51, the material cost of the insulating layer 6 can be suppressed. Furthermore, when the insulating resin 6A is applied by the ink jet method, the insulating resin 6A can be applied with high accuracy, and thus the material cost of the insulating layer 6 can be further reduced.

[Other Embodiments]
Although the embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 1 ... Board | substrate, 2 ... Bonding wire, 3 ... 1st chip | tip, 4 ... Adhesive layer, 5 ... Laminated body, 6 ... Insulating layer, 7 ... Collet, 51 ... Second chip, 52... Chip, 53.

Claims (6)

A first chip mounted on a substrate and connected to the substrate by a bonding wire;
A method of manufacturing a semiconductor device comprising: a second chip that is mounted on the substrate so as to be stacked on the first chip, and is larger than the first chip,
Applying an insulating layer to the portion corresponding to the portion where the bonding wire is formed on the bonding surface of the second chip with the first chip using an inkjet method,
A first heat treatment is performed after application of the insulating layer,
Forming an adhesive layer on the adhesive surface of the second chip;
After the formation of the adhesive layer, a second heat treatment is performed,
Bonding the substrate and the second chip,
A method for manufacturing a semiconductor device, wherein a third heat treatment is performed after the second chip is bonded. A first chip mounted on a substrate and connected to the substrate by a bonding wire;
A method of manufacturing a semiconductor device comprising: a second chip that is mounted on the substrate so as to be stacked on the first chip, and is larger than the first chip,
Applying an insulating layer to a portion of the second chip corresponding to the portion where the bonding wire is formed on the bonding surface with the first chip;
Forming an adhesive layer on the adhesive surface of the second chip;
A method of manufacturing a semiconductor device, wherein the substrate and the second chip are bonded together.   3. The method of manufacturing a semiconductor device according to claim 2, wherein the insulating layer is applied by an ink jet method. A first heat treatment is performed after applying the insulating layer and before applying the adhesive layer,
4. The method of manufacturing a semiconductor device according to claim 2, wherein a second heat treatment is performed after the adhesive layer is attached and before the second chip is attached. 5. A first chip mounted on the substrate and connected to the substrate by a plurality of bonding wires;
Mounted on the substrate so as to be stacked on the first chip, and having a second chip larger than the first chip,
Applying an insulating layer to a portion of the second chip corresponding to the portion where the bonding wire is formed on the bonding surface with the first chip;
Affixing an adhesive layer on the adhesive surface of the second chip;
A semiconductor device manufactured by bonding the first chip and the second chip together. A first chip mounted on the substrate and connected to the substrate by a plurality of bonding wires;
Mounted on the substrate so as to be stacked on the first chip, and having a second chip larger than the first chip,
A memory is used for the first chip,
The second chip uses a controller for controlling the memory,
Applying an insulating layer to a portion of the second chip corresponding to the portion where the bonding wire is formed on the bonding surface with the first chip;
Affixing an adhesive layer on the adhesive surface of the second chip;
A storage device manufactured by bonding the first chip and the second chip together.

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