JP2012039520A - Semiconductor device circuit - Google Patents

Abstract

In a semiconductor device circuit using an MTCMOS circuit, there is provided a semiconductor device circuit which does not impair access speed, has a small standby current, and quickly recovers from a standby state.
In a semiconductor device circuit including a functional circuit including a first PMOSFET and a first NMOSFET, the first PMOSFET is connected to a power supply voltage source in an active mode and is not connected to a power supply voltage source in a standby mode. A second PMOSFET for controlling the power supply, a second NMOSFET for controlling the first NMOSFET to be connected to the ground side voltage source in the active mode and not to be connected to the ground side voltage source in the standby mode, and a power source voltage source. A third PMOSFET connected and connected in parallel to the first PMOSFET and holding its output signal; and a third PMOSFET connected to the ground side voltage source and connected in parallel to the first NMOSFET and holding its output signal. And NMOSFET.
[Selection] Figure 2

Description

  The present invention relates to a semiconductor device circuit using an MTCMOS (Multi-Threshold Complementary Metal Oxide Semiconductor) circuit configured using a plurality of threshold voltage CMOS transistors.

  In the MTCMOS circuit, a MOS transistor having a relatively high threshold voltage (Vt) is connected in series between a power supply voltage or a ground voltage and a predetermined logic circuit, and in the active mode, the MOS transistor is turned on to supply the power supply voltage. Alternatively, the operation speed of the logic circuit is improved by supplying the ground voltage to the logic circuit having a relatively low threshold voltage (Vt), while the MOS transistor is turned off in the sleep mode to supply the logic circuit with the power supply voltage or the ground voltage. This is a technique for reducing the leakage current and subthreshold current of a logic circuit by cutting off. In particular, the MTCMOS circuit is very useful for reducing the power consumption of an LSI chip for portable equipment, in which the time in the sleep mode is much longer than the time in the active mode (see Patent Documents 1 to 5). The “MOS field effect transistor” is referred to as a “MOS transistor”. The P-type MOS transistor is called a PMOS transistor, and the N-type MOS transistor is called an NMOS transistor.

JP 2004-159338 A. Japanese Patent Application Laid-Open No. 2004-187198. JP-A-2005-318600. JP 2006-246486 A. Japanese Patent Application Laid-Open No. 2007-110728.

  However, in the above-described MTCMOS circuit that combines a relatively low threshold voltage (Vt) and a relatively high threshold voltage (Vt), only the latch information is retained, so the access speed is relatively fast. The current consumption in standby mode (also called sleep mode), which is an operation mode that reduces current consumption, is relatively small, but recovery from standby mode is slow, and voltage drops due to current consumption when returning from standby mode. Occurred, and it took a long time to recover. For this reason, there is a problem that a device having a very short signal voltage setup time of the chip enable signal CE cannot satisfy a predetermined specification.

  An object of the present invention is to provide a semiconductor device circuit that solves the above-described problems, and that has a low standby current and quick recovery from a standby state without impairing access speed in a semiconductor device circuit using an MTCMOS circuit. is there.

According to a first aspect of the present invention, there is provided a semiconductor device circuit including a functional circuit including a first PMOS transistor and a first NMOS transistor.
A second PMOS transistor for controlling the first PMOS transistor to be connected to the power supply voltage source in the active mode, but not to connect the first PMOS transistor to the power supply voltage source in the standby mode;
A second NMOS transistor for controlling the first NMOS transistor to be connected to the ground side voltage source in the active mode, but not to connect the first NMOS transistor to the ground side voltage source in the standby mode;
A third first voltage having a predetermined first threshold absolute value voltage, connected to the power supply voltage source and connected in parallel to the first PMOS transistor, and holding an output signal of the first PMOS transistor; A PMOS transistor;
A third voltage having a predetermined second threshold absolute value voltage, connected to the ground-side voltage source and connected in parallel to the first NMOS transistor, and holding an output signal of the first NMOS transistor With NMOS transistors,
The threshold absolute value voltage of the first PMOS transistor is configured to have a third threshold absolute value voltage lower than the first threshold absolute value voltage. The threshold absolute value voltage is configured to have a fourth threshold absolute value voltage lower than the second threshold absolute value voltage.

A semiconductor device circuit according to a second invention is a semiconductor device circuit including a functional circuit including a first PMOS transistor and a first NMOS transistor.
A second NMOS transistor for controlling the first NMOS transistor to be connected to the ground side voltage source in the active mode, but not to connect the first NMOS transistor to the ground side voltage source in the standby mode;
A third voltage having a predetermined first threshold absolute value voltage, connected to the ground-side voltage source and connected in parallel to the first NMOS transistor, and holding an output signal of the first NMOS transistor With NMOS transistors,
A threshold absolute value voltage of the first NMOS transistor is configured to have a second threshold absolute value voltage lower than the first threshold absolute value voltage.

A semiconductor device circuit according to a third invention is a semiconductor device circuit including a functional circuit including a first PMOS transistor and a first NMOS transistor.
A second PMOS transistor for controlling the first PMOS transistor to be connected to the power supply voltage source in the active mode, but not to connect the first PMOS transistor to the power supply voltage source in the standby mode;
A third first voltage having a predetermined first threshold absolute value voltage, connected to the power supply voltage source and connected in parallel to the first PMOS transistor, and holding an output signal of the first PMOS transistor; With PMOS transistor,
The threshold absolute value voltage of the first PMOS transistor is configured to have a second threshold absolute value voltage lower than the first threshold absolute value voltage.

In the semiconductor device circuit according to the first invention, the first PMOS transistor is connected to the power supply voltage source via the second PMOS transistor,
The first NMOS transistor is connected to the ground-side voltage source through the second NMOS transistor.

  In the semiconductor device circuit according to the second invention, the first NMOS transistor is connected to the ground-side voltage source via the second NMOS transistor.

  In the semiconductor device circuit according to the third aspect of the invention, the first PMOS transistor is connected to the power supply voltage source via the second PMOS transistor.

In the semiconductor device circuit according to the first invention, the second PMOS transistor is connected to the power supply voltage source via the first PMOS transistor.
The second NMOS transistor is connected to the ground-side voltage source through the first NMOS transistor.

  In the semiconductor device circuit according to the second aspect of the invention, the second NMOS transistor is connected to the ground side voltage source via the first NMOS transistor.

  In the semiconductor device circuit according to the third aspect of the invention, the second PMOS transistor is connected to the power supply voltage source through the first PMOS transistor.

Furthermore, in the semiconductor device circuit according to the first invention, the semiconductor device circuit comprises a plurality of the functional circuits,
The second PMOS transistor and the second NMOS transistor are provided in common for the functional circuit having the same logical value of the output signal among the plurality of functional circuits.

Furthermore, in the semiconductor device circuit according to the second invention, the semiconductor device circuit includes a plurality of the functional circuits,
The second NMOS transistor is provided in common for the functional circuit having the same logical value of the output signal among the plurality of functional circuits.

Furthermore, in the semiconductor device circuit according to the third aspect of the present invention, the semiconductor device circuit includes a plurality of the functional circuits,
The second PMOS transistor is provided in common for the functional circuit having the same logical value of the output signal among the plurality of functional circuits.

  Still further, in the semiconductor device circuit according to the first, second and third inventions, the functional circuit is an inverter circuit, a gate circuit, a multiplexer, a flip-flop circuit, or a latch circuit of a memory device. To do.

  According to the semiconductor device circuit of the present invention, in the semiconductor device circuit including the functional circuit including the first PMOS transistor and the first NMOS transistor, the first PMOS transistor is connected to the power supply voltage source in the active mode. However, the second PMOS transistor that controls the first PMOS transistor not to be connected to the power supply voltage source in the standby mode, and the first NMOS transistor is connected to the ground side voltage source in the active mode. A second NMOS transistor for controlling the first NMOS transistor not to be connected to the ground-side voltage source in a standby mode; a predetermined first threshold absolute value voltage; and connected to the power supply voltage source And connected in parallel to the first PMOS transistor, A third PMOS transistor for holding the output signal of the PMOS transistor, and a predetermined second threshold absolute value voltage, connected to the ground-side voltage source and connected in parallel to the first NMOS transistor And a third NMOS transistor that holds the output signal of the first NMOS transistor, and the threshold absolute value voltage of the first PMOS transistor is lower than the first threshold absolute value voltage. The fourth threshold absolute value voltage is configured to have a third threshold absolute value voltage, and the threshold absolute value voltage of the first NMOS transistor is lower than the second threshold absolute value voltage. It was configured to have a value voltage. Accordingly, since the output signal immediately before entering the standby mode is held by the third PMOS transistor and the third NMOS transistor, the original signal level is immediately restored when the standby mode is restored to the active mode. In addition, in a semiconductor device circuit using an MTCMOS circuit, it is possible to provide a semiconductor device circuit in which the access speed is not impaired, the standby current is small, and the recovery from the standby state is quick.

(A) is a circuit diagram which shows the structure of the differential amplifier circuit based on a prior art, (b) is a circuit diagram which shows the structure of the differential amplifier circuit which concerns on 1st Embodiment. (A) is a circuit diagram which shows the structure of the inverter circuit which concerns on a prior art, (b) is a circuit diagram which shows the structure of the inverter circuit which concerns on 2nd Embodiment. (A) is a circuit diagram which shows the structure of the NAND gate circuit based on a prior art, (b) is a circuit diagram which shows the structure of the NAND gate circuit which concerns on 3rd Embodiment. (A) is a circuit diagram which shows the structure of the multiplexer circuit based on a prior art, (b) is a circuit diagram which shows the structure of the multiplexer circuit which concerns on 4th Embodiment. It is a circuit diagram which shows the structure of the flip-flop circuit based on a prior art. It is a circuit diagram which shows the structure of the flip-flop circuit which concerns on 5th Embodiment. FIG. 3 is a circuit diagram showing a configuration of latch circuits L1, L2 and their peripheral circuits of a NAND flash memory circuit according to a conventional technique. FIG. 10 is a circuit diagram illustrating configurations of a latch circuit L1a and a driver circuit 10 according to a sixth embodiment. It is a circuit diagram which shows the structure of the latch circuit L1b and driver circuit 10a which concern on 7th Embodiment. It is a circuit diagram which shows the structure of the latch circuit L2a and the driver circuit 10b which concern on 8th Embodiment. It is a circuit diagram which shows the structure of the latch circuit L2b and the driver circuit 10b which concern on 9th Embodiment. It is a circuit diagram which shows the structure of the latch circuit L1c which concerns on 10th Embodiment. It is a circuit diagram which shows the structure of the latch circuit L1ca which concerns on the modification of 10th Embodiment. It is a circuit diagram which shows the structure of the latch circuit L1d based on 11th Embodiment. (A) is a circuit diagram which shows the structure of the inverter circuit which concerns on a prior art, (b) is a circuit diagram which shows the structure of the inverter circuit which concerns on 12th Embodiment. (A) is a circuit diagram which shows the structure of the inverter circuit which concerns on a prior art, (b) is a circuit diagram which shows the structure of the inverter circuit which concerns on 13th Embodiment. It is a circuit diagram which shows the 1st partial structure of the inverter circuit which concerns on 14th Embodiment. It is a circuit diagram which shows the 2nd partial structure of the inverter circuit which concerns on 14th Embodiment. It is a circuit diagram which shows the structure of the 1st virtual power supply circuit used for the inverter circuit of FIG. It is a circuit diagram which shows the structure of the 2nd virtual power supply circuit used for the inverter circuit of FIG. FIG. 3 is a circuit diagram for explaining a problem of the inverter circuit of FIG. 2. (A) is a circuit diagram which shows the structure of the inverter circuit which concerns on a prior art, (b) is a circuit diagram which shows the structure of the inverter circuit which concerns on 15th Embodiment. It is a circuit diagram which shows the structure of the latch circuit L2aa and driver circuit 10b which concern on 16th Embodiment. It is a table | surface which shows the comparison result of the MTCMOS circuit which concerns on a prior art, and the circuit of embodiment which concerns on this invention. 22 is a table showing standby mode control signals and states of the circuits in the NAND flash memory circuits of FIGS. 7 to 13 and FIG. 21. It is a circuit diagram which shows the inversion relationship of each signal of the standby mode control signal used in each embodiment. FIG. 9 is a diagram illustrating an operation of the latch circuit L1a of FIG. 8 and is a timing chart illustrating changes in each control signal. FIG. 10 is a timing chart showing changes of each control signal, illustrating the operation of the latch circuit L1b of FIG. 9; FIG. 12B is a timing chart showing changes in each control signal, illustrating the operation of the latch circuit L1c in FIG. 12A. FIG. 13B is a timing chart showing changes in each control signal, illustrating the operation of the latch circuit L1ca in FIG. 12B. FIG. 14 is a timing chart showing changes of each control signal, illustrating the operation of the latch circuit L1d of FIG. 13; FIG. 11 is a diagram illustrating an operation of the latch circuit L2a in FIG. 10 and is a timing chart illustrating changes in each control signal. 12 is a diagram illustrating an operation of the latch circuit L2b in FIG. 11 and is a timing chart illustrating changes in each control signal. FIG. It is a figure which shows operation | movement of each embodiment except FIGS. 16-18, Comprising: It is a timing chart which shows the change of each control signal, the output node of each element, and the internal voltage of a latch. It is a figure which shows the operation | movement of embodiment of FIGS. 16-18, Comprising: It is a timing chart which shows the change of each control signal and the output node of each element.

  Hereinafter, embodiments according to the present invention will be described with reference to the drawings. In addition, in each following embodiment, the same code | symbol is attached | subjected about the same component.

Outline of the embodiment according to the present invention.
For example, in a low voltage device circuit such as a low voltage MOS transistor that operates at a low voltage of about 1.8 V (all low voltage MOS transistors are used in this embodiment),
(A1) A relatively high threshold absolute value whose threshold voltage (Vt) is, for example, −0.65 V to −0.8 V and whose threshold absolute value voltage is, for example, 0.65 V to 0.8 V. A high-threshold PMOS transistor having voltage (hereinafter referred to as a high-threshold PMOS transistor. In each figure, the illustrated width of the gate is illustrated with a normal line width. For example, see Q31 in FIG. 1B. (B1) refers to a PMOS transistor other than the low threshold PMOS transistor.)
(A2) A relatively high threshold voltage having a threshold voltage (Vt) of +0.65 to +0.8 V, for example, and a threshold voltage of 0.65 to 0.8 V, for example. A high threshold NMOS transistor (hereinafter referred to as a high threshold NMOS transistor. In each figure, the gate width is indicated by a normal line width. For example, see Q40 in FIG. 1B. That is, (B2 ) NMOS transistors other than the low threshold NMOS transistor)),
(B1) A relatively low threshold absolute value whose threshold voltage (Vt) is, for example, −0.3 V to −0.4 V and whose threshold absolute value voltage is, for example, 0.3 V to 0.4 V. Drain-source current having a voltage (having a threshold absolute value voltage lower than that of the high-threshold PMOS transistor of (A1)) and off (when the gate voltage is, for example, the power supply voltage source VDD) (Hereinafter referred to as off-current) Low-threshold PMOS transistor (hereinafter referred to as low-threshold PMOS transistor) whose Ioff is 1 μA, for example. In each figure, the gate width is larger than the normal line width. For example, see Q33a in FIG.
(B2) A relatively low threshold voltage having a threshold voltage (Vt) of, for example, + 0.3V to + 0.4V and a threshold voltage of, for example, 0.3V to 0.4V. Off-state current Ioff at the time of off (when the gate voltage is 0 V, for example) is 1 μA, for example (having a lower threshold absolute value voltage than the high threshold NMOS transistor of (A2)) Low-threshold NMOS transistor (hereinafter referred to as a low-threshold NMOS transistor. In each figure, the gate is shown with a line width larger than the normal line width. For example, see Q37a in FIG. 1B.) When,
Has been used to invent a circuit configuration that does not impair access speed, has a low standby current, and is quick to recover from a standby state.

  That is, a voltage holding MOS transistor is combined with a functional circuit or a functional element using the MTCMOS technology according to the prior art. Further, the MOS transistors for reducing the off current Ioff can be shared. Since the output voltage is held, the recovery from the standby mode (generally also referred to as the sleep mode) is quick and the voltage drop does not occur at the time of recovery, so that the chip enable signal CE changes from the low level to the high level. In this case (that is, when the inverted signal CEB of the chip enable signal changes from the high level to the low level), it can be immediately changed to a predetermined appropriate voltage. The voltage holding MOS transistor has a minimum size, and has a feature that the internal voltage can be changed to an appropriate voltage in accordance with the change of the chip enable signal CE. Hereinafter, detailed embodiments will be described.

First embodiment.
FIG. 1A is a circuit diagram showing a configuration of a differential amplifier circuit according to the prior art, and FIG. 1B is a circuit diagram showing a configuration of a differential amplifier circuit according to the first embodiment. It should be noted that a predetermined bias voltage is applied to an unsigned gate in the gate of each MOS transistor.

In FIG. 1A, the differential amplifier circuit according to the prior art includes two input terminals T1a and T1b, an output terminal T2, PMOS transistors Q31 to Q36, and NMOS transistors Q37 to Q39. . On the other hand, FIG. 1B according to the first embodiment is characterized in that it is configured as follows compared to FIG. 1A.
(1) The PMOS transistors Q33 and Q36 are replaced with low threshold PMOS transistors Q33a and Q36a, respectively.
(2) The NMOS transistors Q37 to Q39 are replaced with low threshold NMOS transistors Q37a to Q39a, respectively, and
(3) The high threshold NMOS transistor Q40 that is turned on / off in response to the chip enable signal CE is inserted between the NMOS transistor Q39a and the ground terminal.

  By configuring as described above, for example, when the chip enable signal CE becomes low level, the output voltage of the MOS transistor pair (Q33a, Q37a) and the output voltage of the MOS transistor pair (Q36a, Q38a) are respectively floating. The output voltage of the MOS transistor pair (Q33a, Q37a) immediately before that is applied to the gate of another MOS transistor pair (Q36a, Q38a) and held by the low threshold MOS transistors Q36a, Q38a. The output voltage of the MOS transistor pair (Q36a, Q38a) is applied to the gate of another MOS transistor pair (Q33a, Q37a) and is held by the low threshold MOS transistors Q33a, Q37a, but the chip enable signal CE is turned off. For short term It can hold.

Second embodiment.
FIG. 2A is a circuit diagram showing a configuration of an inverter circuit according to the prior art, and FIG. 2B is a circuit diagram showing a configuration of an inverter circuit according to the second embodiment.

2A, the inverter circuit is configured by connecting a PMOS transistor Q1 and an NMOS transistor Q2 in series between an input terminal T1 and an output terminal T2. On the other hand, in FIG. 2B according to the second embodiment, the inverter circuit INV1a is characterized in that it is configured as follows, compared to FIG.
(1) The PMOS transistor Q1 is replaced with a low threshold PMOS transistor Q1a.
(2) The NMOS transistor Q2 is replaced with a low threshold NMOS transistor Q2a.
(3) An off-current reducing high threshold PMOS transistor Q21 that is turned on / off in response to the inverted signal CEB of the chip enable signal is inserted between the PMOS transistor Q1a and the power supply voltage source VDD.
(4) An off-current reducing high threshold NMOS transistor Q22 that is turned on / off in response to the chip enable signal CE is inserted between the NMOS transistor Q2a and the ground terminal.
(5) A voltage holding high threshold PMOS transistor Q11 is connected in parallel with the PMOS transistor Q1a (ie, the gate of the PMOS transistor Q11 is connected to the gate of the PMOS transistor Q1a, and the drain of the PMOS transistor Q11 is connected to the PMOS transistor) Connected to the drain of Q1a, but the source of the PMOS transistor Q11 is connected to the power supply voltage source VDD), and
(6) The voltage holding high threshold NMOS transistor Q12 is connected in parallel with the NMOS transistor Q2a (that is, the gate of the NMOS transistor Q12 is connected to the gate of the NMOS transistor Q2a, and the drain of the NMOS transistor Q12 is the NMOS transistor). (It is connected to the drain of Q2a, but the source of the NMOS transistor Q12 is grounded).

  FIG. 24 is a circuit diagram showing the inversion relationship of each signal of the standby mode control signal used in each embodiment. In FIG. 24A, the chip enable signal CE is an inverted signal of the inverted signal CEB. Here, when the chip enable signal CE is at a high level and its inverted signal is at a low level, the inverter circuit is in an active mode (operating state), while the chip enable signal CE is at a low level and its inverted signal is When it is at a high level, the inverter circuit enters a standby mode (or sleep mode). In FIG. 24B, the busy signal BUSY is an inverted signal of the ready signal RDY and is used in another embodiment described below.

  With the configuration as described above, in FIG. 2B, for example, when the chip enable signal CE is at a low level and the inverted signal CEB is at a high level, the output of the inverter composed of the MOS transistors Q1a and Q2a is output. Although the voltage is in a floating state, its output voltage is high threshold MOS transistors Q11 and Q12 (at least the threshold absolute value voltage of the PMOS transistor Q1a is lower than the threshold absolute value voltage of the PMOS transistor Q11, and the NMOS The threshold absolute value voltage of the transistor Q2a is held by an inverter composed of (lower than the threshold absolute value voltage of the NMOS transistor Q12). Therefore, when the chip enable signal CE changes from the low level to the high level and the inverted signal CEB changes from the high level to the low level, the output voltage can be immediately changed from the holding voltage to a predetermined appropriate voltage. .

Third embodiment.
FIG. 3A is a circuit diagram showing a configuration of a NAND gate circuit according to the prior art, and FIG. 3B is a circuit diagram showing a configuration of the NAND gate circuit according to the third embodiment.

In FIG. 3A, the NAND gate circuit according to the prior art includes input terminals T1A and T1B, an output terminal T2, PMOS transistors Q1 and Q3, and NMOS transistors Q2 and Q4. On the other hand, in FIG. 3B according to the third embodiment, the NAND gate circuit is characterized in that it is configured as follows as compared with FIG.
(1) The PMOS transistors Q1 and Q3 are replaced with low threshold PMOS transistors Q1a and Q3a, respectively.
(2) The NMOS transistors Q2 and Q4 are replaced with low threshold NMOS transistors Q2a and Q4a, respectively.
(3) An off-current reducing high threshold PMOS transistor Q21 that is turned on / off in response to the inverted signal CEB of the chip enable signal is inserted between the PMOS transistors Q1a and Q3a and the power supply voltage source VDD.
(4) An off-current reducing high threshold NMOS transistor Q22 that is turned on / off in response to the chip enable signal CE is inserted between the NMOS transistor Q4a and the ground terminal.
(5) A voltage holding high threshold PMOS transistor Q11 is connected in parallel with the PMOS transistor Q1a (ie, the gate of the PMOS transistor Q11 is connected to the gate of the PMOS transistor Q1a, and the drain of the PMOS transistor Q11 is connected to the PMOS transistor) Q1a is connected to the drain, but the source of the PMOS transistor Q11 is connected to the power supply voltage source VDD).
(6) The voltage holding high threshold NMOS transistor Q12 is connected in parallel with the NMOS transistor Q2a (that is, the gate of the NMOS transistor Q12 is connected to the gate of the NMOS transistor Q2a, and the drain of the NMOS transistor Q12 is the NMOS transistor). Connected to the drain of Q2a, the source of NMOS transistor Q12 is connected to the drain of NMOS transistor Q14).
(7) A voltage holding high threshold PMOS transistor Q13 is connected in parallel with the PMOS transistor Q3a (ie, the gate of the PMOS transistor Q13 is connected to the gate of the PMOS transistor Q3a, and the drain of the PMOS transistor Q13 is the PMOS transistor) Connected to the drain of Q3a, but the source of the PMOS transistor Q13 is connected to the power supply voltage source VDD), and
(8) The voltage holding high threshold NMOS transistor Q14 is connected in parallel with the NMOS transistor Q4a (ie, the gate of the NMOS transistor Q14 is connected to the gate of the NMOS transistor Q4a, and the drain of the NMOS transistor Q14 is the NMOS transistor) The source of the NMOS transistor Q14 is grounded while being connected to the source of the Q12, and the gates of the MOS transistors Q4a, Q14, Q3a, and Q13 are all connected to the input terminal T1B.)

  By configuring as described above, for example, when the chip enable signal CE is at a low level and the inverted signal CEB is at a high level, the output voltages of the MOS transistors Q1a, Q2a, and Q3a are in a floating state. However, the respective output voltages are high threshold MOS transistors Q11 to Q13 (at least the threshold absolute value voltages of the PMOS transistors Q1a and Q3a are lower than the threshold absolute value voltages of the PMOS transistors Q11 and Q13. The threshold absolute value voltage of Q2a is held lower than the threshold absolute value voltage of NMOS transistor Q12). Therefore, when the chip enable signal CE changes from the low level to the high level and the inverted signal CEB changes from the high level to the low level, the output voltage can be immediately changed from the holding voltage to a predetermined appropriate voltage. .

  Although the NAND gate circuit has been described in the above embodiment, the present invention is not limited to this, and can be applied to various gate circuits such as a NOR gate circuit, an AND gate circuit, or an OR gate circuit.

Fourth embodiment.
FIG. 4A is a circuit diagram showing a configuration of a multiplexer circuit according to the prior art, and FIG. 4B is a circuit diagram showing a configuration of a multiplexer circuit according to the fourth embodiment.

In FIG. 4A, the multiplexer circuit according to the prior art is
(1) An input terminal T1A and an inverter INV3 including a PMOS transistor Q41 and an NMOS transistor Q42;
(2) a transmission gate TG1 connected to the output terminal of the inverter INV3;
(3) an input terminal T1B and an inverter INV4 including a PMOS transistor Q43 and an NMOS transistor Q44;
(4) a transmission gate TG2 connected to the output terminal of the inverter INV4;
(5) An inverter INV5 including a PMOS transistor Q45 and an NMOS transistor Q46 is connected to the output terminals of the transmission gates TG1 and TG2 and connected to the output terminal T2.

  In FIG. 4A, each of the transmission gates TG1 and TG2 is a known transmission gate, and includes a PMOS transistor, an NMOS transistor, and an inverter as is well known. Here, the transmission gate TG2 is turned off when the transmission gate TG1 is turned on, while the transmission gate TG2 is turned on when the transmission gate TG1 is turned off.

  On the other hand, the multiplexer circuit according to the fourth embodiment in FIG. 4B is characterized in that it is configured as follows compared to the multiplexer circuit in FIG.

(1) The inverter INV3 is replaced with an inverter INV3a, specifically, the PMOS transistor Q41 is replaced with a low threshold PMOS transistor Q41a, the NMOS transistor Q42 is replaced with a low threshold NMOS transistor Q42a, and the PMOS transistor Q41a and the power supply voltage A high-threshold PMOS transistor Q21a for reducing off-current that is turned on / off in response to the inverted signal CEB of the chip enable signal is inserted between the source VDD and the chip between the NMOS transistor Q42a and the ground terminal. An off-current reducing high threshold NMOS transistor Q22a that is turned on / off in response to the enable signal CE is inserted.
(2) In order to improve the access speed, the transmission gate TG1 is replaced with a transmission gate TG1a using a low threshold MOS transistor pair.
(3) The inverter INV4 is replaced with an inverter INV4a, specifically, the PMOS transistor Q43 is replaced with a low threshold PMOS transistor Q43a, the NMOS transistor Q44 is replaced with a low threshold NMOS transistor Q44a, and the PMOS transistor Q43a and the power supply voltage A high-threshold PMOS transistor Q21b for reducing off-current that is turned on / off in response to the inverted signal CEB of the chip enable signal is inserted between the source VDD and the chip between the NMOS transistor Q44a and the ground terminal. An off-current reducing high threshold NMOS transistor Q22b that is turned on / off in response to the enable signal CE is inserted.
(4) In order to improve the access speed, the transmission gate TG2 is replaced with a transmission gate TG2a using a low threshold MOS transistor pair.
(5) The inverter INV5 is replaced with the inverter INV5a, specifically, the PMOS transistor Q45 is replaced with the low threshold PMOS transistor Q45a, the NMOS transistor Q46 is replaced with the low threshold NMOS transistor Q46a, and the PMOS transistor Q45a and the power supply voltage A high-threshold PMOS transistor Q21c for reducing off-current that is turned on / off in response to the inverted signal CEB of the chip enable signal is inserted between the source VDD and the chip between the NMOS transistor Q46a and the ground terminal. A high threshold NMOS transistor Q22c which is turned on / off in response to the enable signal CE is inserted.
(6) Furthermore, a voltage holding high threshold PMOS transistor Q11 is connected in parallel with the PMOS transistor Q45a (that is, the gate of the PMOS transistor Q11 is connected to the gate of the PMOS transistor Q45a, and the drain of the PMOS transistor Q11 is The drain of the PMOS transistor Q45a is connected, but the source of the PMOS transistor Q11 is connected to the power supply voltage source VDD.) In addition, a voltage holding high threshold NMOS transistor Q12 is connected in parallel with the NMOS transistor Q46a. (Ie, the gate of the NMOS transistor Q12 is connected to the gate of the NMOS transistor Q46a, and the drain of the NMOS transistor Q12 is connected to the drain of the NMOS transistor Q46a. The source of the OS transistor Q12 is grounded.).
(7) The following latch circuit LA11 is provided to hold the output voltage of each transmission gate TG1a, TG2a. In the latch circuit LA11, two inverters INV6 and INV7 are connected in cascade with each other in a loop, and the power supply voltage source VDD and the ground terminal are directly connected to the inverter INV6, but the chip enable signal CE is connected to the inverter INV7. The high threshold NMOS transistor Q22d is connected to the power supply voltage source VDD via the high threshold PMOS transistor Q21d which is turned on / off in response to and is turned on / off in response to the inverted signal CEB of the chip enable signal. The ground terminal is connected via

  As described above, the following latch circuit LA11 is provided to hold the output voltage of each transmission gate TG1a, TG2a, and the inverter INV5a is configured to hold the output voltage of the output terminal T2 of the multiplexer circuit. . Therefore, for example, when the chip enable signal CE becomes low level and the inverted signal CEB becomes high level, the output voltages of the transmission gates TG1a and TG2a and the output voltages of the MOS transistors Q45a and Q46a are in a floating state. However, the respective output voltages are the latch circuit LA11 and the inverter INV5a (at least the threshold absolute value voltage of the PMOS transistor Q45a is lower than the threshold absolute value voltage of the PMOS transistor Q11, and the threshold voltage of the NMOS transistor 46a). The absolute value voltage is held by the configuration of the NMOS transistor Q12). Therefore, when the chip enable signal CE changes from the low level to the high level and the inverted signal CEB changes from the high level to the low level, the output voltage can be immediately changed from the holding voltage to a predetermined appropriate voltage. .

Fifth embodiment.
FIG. 5 is a circuit diagram showing a configuration of a flip-flop circuit according to the prior art, and FIG. 6 is a circuit diagram showing a configuration of a flip-flop circuit according to a fifth embodiment.

In FIG. 5, the flip-flop circuit according to the prior art is configured to include inverters INV11 to INV17 and transmission gates TG11 to TG14. On the other hand, the flip-flop circuit according to the fifth embodiment of FIG. 6 is characterized in that it is configured as follows compared to the flip-flop circuit of FIG.
(1) The inverter INV11 is replaced with an inverter INV11a having the same configuration as the inverters INV3a and INV4a in FIG.
(2) The transmission gates TG11 to TG14 are replaced with transmission gates TG11a to TG14a having the same configuration as the inverters TG1a and TG2a of FIG.
(3) The inverters INV12 to 17V were replaced with inverters INV12a to 17a having the same configuration as the inverter INV5a in FIG.

  As described above, the transmission gates TG11a to TG14a are provided in order to improve the access speed, and are configured as described above to hold the output voltages of the inverters INV12a, INV13a, INV15a, INV16a, and INV17a. Therefore, for example, when the chip enable signal CE is at a low level and the inverted signal CEB is at a high level, the output voltages of the inverters INV12a, INV13a, INV15a, INV16a, and INV17a are in a floating state. The voltage is held by the configuration of the high threshold CMOS inverter circuit in the subsequent stage of each circuit. Therefore, when the chip enable signal CE changes from the low level to the high level and the inverted signal CEB changes from the high level to the low level, the output voltage can be immediately changed from the holding voltage to a predetermined appropriate voltage. .

Sixth embodiment.
FIG. 7 is a circuit diagram showing the configuration of the latch circuits L1 and L2 of the NAND flash memory circuit according to the prior art and its peripheral circuits. FIG. 8 shows the configuration of the latch circuit L1a and the driver circuit 10 according to the sixth embodiment. FIG.

  In FIG. 7, L1 is a first latch circuit L1, and two clocked inverters INV21 and INV22 are connected in cascade with each other. Lines L1BL and L1BL of both terminals of each clocked inverter INV21 and INV22 are formed. L1BLB is connected to the drain and source of an NMOS transistor Q101 that is turned on / off by an equalization control signal EQ that is equalized immediately before sensing data. Here, the clocked inverter INV21 is operated by latch control signals L1LAT and L1LATB, and the clocked inverter INV22 is operated by sense control signals L1SEN and L1SENB. The line L1BL connected to the output terminal of the clocked inverter INV21 is connected to the bit line BL2 via the NMOS transistor Q102 that is turned on / off by the enable control signal L1EN of the latch circuit L1. The bit line BL2 is connected to the bit line precharge voltage source VP via an NMOS transistor Q103 which is turned on / off by a precharge control signal PRECH and is turned on / off by a bit line path control signal BLPASS. To the bit line BL1 connected to the flash memory block.

  L2 is a first latch circuit L2, and is constituted by two clocked inverters INV23 and INV24 that are connected in cascade with each other in a loop. The line L2BLB connected to the output terminal of the clocked inverter INV24 is grounded via the NMOS transistor Q105 that is turned on / off by the reset control signal RESET, and the NMOS transistor Q106 that is turned on / off by the column selection signal CSL. To the data bus line DL. The line L2BL connected to the output terminal of the clocked inverter INV23 is connected to the data bus line ZDL via the NMOS transistor Q107 that is turned on / off by the column selection signal CSL. Further, the line L2BL is connected to the bit line BL2 via an NMOS transistor Q108 which is turned on / off by an enable control signal L2EN of the latch circuit L2.

  FIG. 23 is a table showing the standby mode control signal and the state of each circuit in the NAND type flash memory circuit of FIGS. The standby mode control signal is as shown in FIG. As is apparent from FIG. 23, the operating states (active mode or standby mode) of the latch circuits L1 and L2 are switched according to the chip enable signal CE and the busy signal BUSY.

In FIG. 8, the latch circuit L1a according to the sixth embodiment is characterized in that it is configured as follows compared to the prior art of FIG.
(1) The clocked inverter INV21 is replaced with a clocked inverter INV21a having the same configuration as the inverters INV3a and INV4a of FIG. 4B and including PMOS transistors Q51 and Q53 and NMOS transistors Q52 and Q54. It was. Here, the PMOS transistor Q53 is turned on by the data latch control signal L1LATB, and the NMOS transistor Q54 is turned on / off by the data latch control signal L1LAT.
(2) The clocked inverter INV22 is replaced with a clocked inverter INV22a having the same configuration as the inverters INV3a and INV4a in FIG. 4B and including PMOS transistors Q61 and Q63 and NMOS transistors Q62 and Q64. It was. Here, the PMOS transistor Q63 is turned on by the data sense control signal L1SENB, and the NMOS transistor Q64 is turned on / off by the data sense control signal L1SEN.
(3) The driver circuit 10 includes a NAND gate NAND1 and a NOR gate NOR1. The NAND gate NAND1 generates a data latch control signal L1LATB based on the busy signal BUSY and the data latch control signal L1LATBCTRL and outputs it to the gate of the PMOS transistor Q53. The NOR gate NOR1 generates a data sense control signal L1SEN based on the ready signal RDY and the data sense control signal L1SENCTRL, and outputs it to the gate of the NMOS transistor Q64.

  FIG. 25 is a diagram showing the operation of the latch circuit L1a of FIG. 8, and is a timing chart showing changes in each control signal. In FIG. 25, in the standby mode in which the ready signal RDY is at a high level, the line L1BL is at a low level and the line L1BLB is at a high level.

  As described above, the configuration described above is used to hold the output voltages of the clocked inverters INV21a and INV22a. Particularly, in the standby mode in which the clocked inverters INV21a and INV22a are used and the ready signal RDY is at a high level, the line L1BL is controlled to be at a low level and the line L1BLB is controlled to be at a high level. In the standby mode, each output voltage is held by a latch circuit in which the clocked inverters INV21a and INV22a are connected in cascade in a loop shape, so that the output voltage is immediately changed from the holding voltage to a predetermined appropriate voltage. Can do. Further, in the standby mode, the PMOS transistor Q53 is turned off by the latch control signal L1LATB, and the NMOS transistor Q64 is turned off by the sense control signal L1SEN, thereby reducing the leakage current flowing through the clocked inverters INV21a and INV22a.

Seventh embodiment.
FIG. 9 is a circuit diagram showing configurations of the latch circuit L1b and the driver circuit 10a according to the seventh embodiment.

In FIG. 9, the latch circuit L1b according to the seventh embodiment is characterized in that it is configured as follows compared to the prior art of FIG.
(1) The clocked inverter INV21 has the same configuration as that of the inverter 5a in FIG. 4B, and includes a PMOS transistor Q51, Q53, Q55 and NMOS transistors Q52, Q54, Q56. Replaced with. Here, the PMOS transistor Q53 is turned on by the data latch control signal L1LATB, and the NMOS transistor Q54 is turned on / off by the data latch control signal L1LAT. The PMOS transistor Q55 is connected in parallel to the PMOS transistor Q51, that is, the gate of the PMOS transistor Q55 is connected to the gate of the PMOS transistor Q51, the drain of the PMOS transistor Q55 is connected to the drain of the PMOS transistor Q51, and the PMOS transistor Q55. Are connected to the power supply voltage source VDD. Further, the NMOS transistor Q56 is connected in parallel to the NMOS transistor Q52, that is, the gate of the NMOS transistor Q56 is connected to the gate of the NMOS transistor Q52, the drain of the NMOS transistor Q56 is connected to the drain of the NMOS transistor Q52, and the NMOS transistor Q56. The source of is grounded.
(2) The clocked inverter INV22 has a configuration similar to that of the inverter 5a of FIG. 4B, and is configured by including PMOS transistors Q61, Q63, Q65 and NMOS transistors Q62, Q64, Q66. Replaced with. Here, the PMOS transistor Q63 is turned on by the data sense control signal L1SENB, and the NMOS transistor Q64 is turned on / off by the data sense control signal L1SEN. The PMOS transistor Q65 is connected in parallel to the PMOS transistor Q61, that is, the gate of the PMOS transistor Q65 is connected to the gate of the PMOS transistor Q61, the drain of the PMOS transistor Q65 is connected to the drain of the PMOS transistor Q61, and the PMOS transistor Q65. Are connected to the power supply voltage source VDD. Further, the NMOS transistor Q66 is connected in parallel to the NMOS transistor Q62, that is, the gate of the NMOS transistor Q66 is connected to the gate of the NMOS transistor Q62, the drain of the NMOS transistor Q66 is connected to the drain of the NMOS transistor Q62, and the NMOS transistor Q66. The source of is grounded.
(3) The driver circuit 10a includes NAND gates NAND1 and NAND2 and NOR gates NOR1 and NOR2. The NAND gate NAND1 generates a data latch control signal L1LATB based on the busy signal BUSY and the data latch control signal L1LATBCTRL and outputs it to the gate of the PMOS transistor Q53. The NOR gate NOR1 generates a data sense control signal L1SEN based on the ready signal RDY and the data sense control signal L1SENCTRL, and outputs it to the gate of the NMOS transistor Q64. Further, the NOR gate NOR2 generates a data sense control signal L1LAT based on the ready signal RDY and the data latch control signal L1LATCTRL and outputs it to the gate of the NMOS transistor Q54. Furthermore, the NAND gate NAND2 generates a data sense control signal L1SENBCTRL based on the busy signal BUSY and the data sense control signal L1SENCTRL and outputs it to the gate of the PMOS transistor Q63.

  FIG. 26 is a diagram showing the operation of the latch circuit L1b of FIG. 9, and is a timing chart showing changes in each control signal. As is apparent from FIGS. 9 and 26, in the standby mode, the output voltage of the MOS transistor pair Q51, Q52 and the output voltage of the MOS transistor pair Q61, Q62 are in a floating state, Since the MOS transistors Q55, Q56, Q65, and Q66 are provided, the immediately preceding voltage is held in the standby mode, and when the active mode is entered, the output voltage is immediately changed from the held voltage to a predetermined appropriate voltage. be able to. In the standby mode, the PMOS transistor Q53 is turned off by the latch control signal L1LATB, the NMOS transistor Q54 is turned off by the latch control signal L1LAT, the PMOS transistor Q63 is turned off by the sense control signal L1SENB, and the NMOS transistor is turned on by the sense control signal L1SEN. By turning off the transistor Q64, it is possible to reduce the leakage current flowing through each clocked inverter INV21b, INV22b.

Eighth embodiment.
FIG. 10 is a circuit diagram showing configurations of the latch circuit L2a and the driver circuit 10b according to the eighth embodiment.

In FIG. 10, the latch circuit L2a according to the eighth embodiment is characterized in that it is configured as follows compared to the prior art of FIG.
(1) The clocked inverter INV23 has the same configuration as that of the inverter 5a in FIG. 4B, and includes a PMOS transistor Q71, Q73, Q75 and NMOS transistors Q72, Q74, Q76. Replaced with. The NMOS transistors Q106 and Q107 controlled by the column selection signal CSL are replaced with low threshold NMOS transistors Q106a and Q107a, respectively. Here, the PMOS transistor Q73 is turned on by the data latch control signal L2LATB, and the NMOS transistor Q74 is turned on / off by the data latch control signal L2LAT. The PMOS transistor Q75 is connected in parallel to the PMOS transistor Q71, that is, the gate of the PMOS transistor Q75 is connected to the gate of the PMOS transistor Q71, the drain of the PMOS transistor Q75 is connected to the drain of the PMOS transistor Q71, and the PMOS transistor Q75. Are connected to the power supply voltage source VDD. Further, the NMOS transistor Q76 is connected in parallel to the NMOS transistor Q72, that is, the gate of the NMOS transistor Q76 is connected to the gate of the NMOS transistor Q72, the drain of the NMOS transistor Q76 is connected to the drain of the NMOS transistor Q72, and the NMOS transistor Q76. The source of is grounded.
(2) The clocked inverter INV24 has the same configuration as that of the inverter 5a in FIG. 4B, and includes a PMOS transistor Q81, Q83, Q85 and NMOS transistors Q82, Q84, Q86. Replaced with. Here, the PMOS transistor Q83 is turned on by the data sense control signal L2SENB, and the NMOS transistor Q84 is turned on / off by the data sense control signal L2SEN. The PMOS transistor Q85 is connected in parallel to the PMOS transistor Q81, that is, the gate of the PMOS transistor Q85 is connected to the gate of the PMOS transistor Q81, the drain of the PMOS transistor Q85 is connected to the drain of the PMOS transistor Q81, and the PMOS transistor Q85. Are connected to the power supply voltage source VDD. Further, the NMOS transistor Q86 is connected in parallel to the NMOS transistor Q82, that is, the gate of the NMOS transistor Q86 is connected to the gate of the NMOS transistor Q82, the drain of the NMOS transistor Q86 is connected to the drain of the NMOS transistor Q82, and the NMOS transistor Q86. The source of is grounded.
(3) The driver circuit 10b includes NAND gates NAND3 and NAND4 and NOR gates NOR3 and NOR4. The NAND gate NAND3 generates a data latch control signal L2LATB based on the busy signal BUSY, the chip enable signal CE, and the data latch control signal L2LATBCTRL and outputs the data latch control signal L2LATB to the gate of the PMOS transistor Q73. The NOR gate NOR3 generates a data latch control signal L2LAT based on the ready signal RDY, the inverted signal CEB of the chip enable signal, and the data latch control signal L2LATCTRL, and outputs it to the gate of the NMOS transistor Q74. Further, the NAND gate NAND4 generates a data sense control signal L2SENB based on the busy signal BUSY, the chip enable signal CE, and the data sense control signal L2SENBCTRL, and outputs it to the gate of the PMOS transistor Q83. The NOR gate NOR4 generates the data sense control signal L2SEN based on the ready signal RDY, the inverted signal CEB of the chip enable signal, and the data sense control signal L2SENCTRL, and outputs the data sense control signal L2SEN to the gate of the NMOS transistor Q84.

  29 is a diagram showing the operation of the latch circuit L2a of FIG. 10, and is a timing chart showing changes in the control signals. As is apparent from FIGS. 10 and 29, in the standby mode, the output voltages of the MOS transistor pair Q71 and Q72 and the output voltage of the MOS transistor pair Q81 and Q82 are in a floating state. Since the MOS transistors Q75, Q76, Q85, and Q86 are provided, the immediately preceding voltage is held in the standby mode, and when the active mode is entered, the output voltage is immediately changed from the held voltage to a predetermined appropriate voltage. be able to. In the standby mode, the PMOS transistor Q73 is turned off by the latch control signal L2LATB, the NMOS transistor Q74 is turned off by the latch control signal L2LAT, the PMOS transistor Q83 is turned off by the sense control signal L2SENB, and the NMOS transistor is turned on by the sense control signal L2SEN. By turning off the transistor Q84, it is possible to reduce a leakage current flowing through each of the clocked inverters INV23b and INV24b.

Ninth embodiment.
FIG. 11 is a circuit diagram showing configurations of the latch circuit L2b and the driver circuit 10b according to the ninth embodiment.

In FIG. 11, the latch circuit L2b and the driver circuit 10b according to the ninth embodiment are characterized by being configured as follows compared to the eighth embodiment of FIG.
(1) The clocked inverter INV23a is replaced with the clocked inverter INV23b. Specifically, the low threshold NMOS transistor Q72 is replaced with the high threshold NMOS transistor Q72z, and the NMOS transistor Q76 is deleted.
(2) The clocked inverter INV24a is replaced with the clocked inverter INV24b. Specifically, the low threshold NMOS transistor Q82 is replaced with the high threshold NMOS transistor Q82z, and the NMOS transistor Q86 is deleted.

  FIG. 30 shows the operation of the latch circuit L2b of FIG. 11, and is a timing chart showing changes in each control signal. As is apparent from FIGS. 11 and 30, in the standby mode, the output voltage of the MOS transistor pair Q71 and the output voltage of the MOS transistor pair Q81 are in a floating state, but the voltage holding MOS transistor Q75, Since Q85 is provided, the immediately preceding voltage can be held in the standby mode, and when the active mode is entered, the output voltage can be immediately changed from the held voltage to a predetermined appropriate voltage. Further, in the standby mode, the PMOS transistor Q73 is turned off by the latch control signal L2LATB, and the PMOS transistor Q83 is turned off by the sense control signal L2SENB, thereby reducing the leakage current flowing through the clocked inverters INV23b and INV24b.

Tenth embodiment.
FIG. 12A is a circuit diagram showing a configuration of a latch circuit L1c according to the tenth embodiment.

In FIG. 12A, the latch circuit L1c according to the tenth embodiment is characterized in that it is configured as follows compared to the sixth embodiment of FIG.
(1) The clocked inverter INV21a is replaced with a clocked inverter INV21c. Specifically, the low threshold MOS transistors Q51 and Q52 are replaced with high threshold MOS transistors Q51z and Q52z.
(2) The clocked inverter INV22a is replaced with a clocked inverter INV22c. Specifically, the high threshold MOS transistors Q63 and Q64 are replaced with low threshold NMOS transistors Q63a and Q64a.
(3) In this embodiment, the off currents of the low threshold NMOS transistors Q62 and Q64a are sufficiently smaller than the off currents of the low threshold PMOS transistors Q61 and Q63a (for example, 1/10 to 1 / 1000 or less, typically 1/100 or less.) This is a case that can be ignored.

  FIG. 27A is a diagram showing the operation of the latch circuit L1c in FIG. 12A, and is a timing chart showing changes in each control signal. As apparent from FIGS. 12A and 27A, in the standby mode in which the ready signal RDY is at the high level, the line L1BLB is controlled to the high level and the line L1BL is controlled to the low level, so that the leakage current is reduced. . In the present embodiment, since the clocked inverter INV21c and the clocked inverter INV22c are connected to each other in a loop shape, each output voltage can be held.

Modified example of the tenth embodiment.
FIG. 12B is a circuit diagram showing a configuration of a latch circuit L1ca according to a modification of the tenth embodiment.

In FIG. 12B, the latch circuit L1ca according to the modification of the tenth embodiment is characterized in that it is configured as follows compared to the tenth embodiment of FIG. 12A.
(1) The clocked inverter INV21c including the high threshold PMOS transistors Q53 and Q51z and the high threshold NMOS transistors Q52z and Q54 in FIG. 12A is replaced with the low threshold PMOS transistors Q53a and Q51 and the low threshold. The clocked inverter INV21ca constituted by including the value NMOS transistors Q52 and Q54a was replaced.
(2) The clocked inverter INV22c including the low threshold PMOS transistors Q63a and Q61 and the low threshold NMOS transistors Q62 and Q64a in FIG. 12A is replaced with the high threshold PMOS transistors Q63 and Q61z and the high threshold. The clocked inverter INV22ca constituted by including the value NMOS transistors Q62z and Q64 was replaced.

  FIG. 27B is a diagram showing the operation of the latch circuit L1ca in FIG. 12B, and is a timing chart showing changes in each control signal. As apparent from FIGS. 12B and 27B, in the standby mode in which the ready signal RDY is at the high level, the line L1BLB is controlled to the low level and the line L1BL is controlled to the high level, so that the leakage current is reduced. . In the present modification, the clocked inverter INV21ca and the clocked inverter INV22ca are connected in cascade with each other, so that each output voltage can be held.

Eleventh embodiment.
FIG. 13 is a circuit diagram showing a configuration of the latch circuit L1d according to the eleventh embodiment.

In FIG. 13, the latch circuit L1d according to the eleventh embodiment is characterized in that it is configured as follows compared to the tenth embodiment of FIG. 12A.
(1) The source of the low threshold PMOS transistor Q63a is connected to the power supply voltage source VDD via the high threshold PMOS transistor Q67 which is turned on by the data sense control signal SENSEB.
(2) The source of the low threshold PMOS transistor Q63a is connected to the power supply voltage source VDD via the high threshold PMOS transistor Q68 controlled by the voltage of the line L1BL.
(3) In this embodiment, the off currents of the low threshold NMOS transistors Q62 and Q64a are sufficiently smaller than the off currents of the low threshold PMOS transistors Q61 and Q63a (for example, 1/10 to 1 / 1000 or less, typically 1/100 or less.) This is a case that can be ignored.

  FIG. 28 shows the operation of the latch circuit L1d in FIG. 13, and is a timing chart showing changes in the control signals. In FIG. 28, VBL is a bit line voltage or a voltage obtained by primary amplification of the bit line voltage. As is apparent from FIGS. 13 and 28, the data sense control signal SENSEB is at a low level during data sensing and is at a high level during latching, and the off currents of the PMOS transistors 63a and Q61 in the latch can be reduced. In the present embodiment, since the clocked inverter INV21c and the clocked inverter INV22d are connected in cascade with each other in a loop, each output voltage can be held.

Twelfth embodiment.
FIG. 14A is a circuit diagram showing the configuration of an inverter circuit according to the prior art, and FIG. 14B is a circuit diagram showing the configuration of the inverter circuit according to the twelfth embodiment.

  In FIG. 14A, an inverter INV31 including a PMOS transistor Q111 and an NMOS transistor Q112 and an inverter INV32 including a PMOS transistor Q113 and an NMOS transistor Q114 are connected in cascade between an input terminal T1 and an output terminal T2. Is done.

In FIG. 14B, the inverter circuit according to the twelfth embodiment is characterized in that it is configured as follows compared to the inverter circuit according to the prior art of FIG.
(1) The inverter INV31 is replaced with an inverter INV31a, specifically, the PMOS transistor Q111 is replaced with a low threshold PMOS transistor Q111a, the NMOS transistor Q112 is replaced with a low threshold NMOS transistor Q112a, and the NMOS transistor Q112a and the ground terminal A high-threshold NMOS transistor Q115 that is turned on / off in response to the chip enable signal CE is inserted. A voltage holding high threshold NMOS transistor Q116 is connected in parallel with the NMOS transistor Q112a. That is, the gate of the NMOS transistor Q116 is connected to the gate of the NMOS transistor Q112a, the drain of the NMOS transistor Q116 is connected to the drain of the NMOS transistor Q112a, and the source of the NMOS transistor Q116 is grounded.
(2) The inverter INV32 is replaced with the inverter INV32a, specifically, the PMOS transistor Q113 is replaced with the low threshold PMOS transistor Q113a, the NMOS transistor Q114 is replaced with the low threshold NMOS transistor Q114a, and the NMOS transistor Q114a and the ground terminal A high-threshold NMOS transistor Q117 that is turned on / off in response to the chip enable signal CE is inserted. A voltage holding high threshold NMOS transistor Q118 is connected in parallel with the NMOS transistor Q114a. That is, the gate of the NMOS transistor Q118 is connected to the gate of the NMOS transistor Q114a, the drain of the NMOS transistor Q118 is connected to the drain of the NMOS transistor Q114a, but the source of the NMOS transistor Q118 is grounded.
(3) In this embodiment, the off current of the low threshold PMOS transistors Q111a and Q113a is sufficiently smaller than the off current of the low threshold NMOS transistors Q112a and Q114a (for example, 1/10 to 1 / 1000 or less, typically 1/100 or less.) This is a case that can be ignored.

  In the present embodiment, as compared with the inverter INV1a of FIG. 2, the leakage current is reduced by controlling the power supply by the chip enable signal CE only on the ground side, and the voltages are held only in the NMOS transistors Q112a and Q114a on the ground side. It is characterized in that high threshold NMOS transistors Q116 and Q118 are connected. Even with this configuration, the output voltage of each of the inverters INV31a and INV32a is held at the immediately preceding voltage in the standby mode, and when the active mode is entered, the output voltage is immediately set to the predetermined voltage from the held voltage. It can be changed to an appropriate voltage.

Thirteenth embodiment.
FIG. 15A is a circuit diagram showing a configuration of an inverter circuit according to the prior art, and FIG. 15B is a circuit diagram showing a configuration of an inverter circuit according to the thirteenth embodiment. The inverter circuit of FIG. 15A is the same circuit as FIG.

In FIG. 15B, the inverter circuit according to the thirteenth embodiment is characterized in that it is configured as follows compared to the inverter circuit according to the prior art of FIG.
(1) The inverter INV31 is replaced with the inverter INV31b. Specifically, the PMOS transistor Q111 is replaced with the low threshold PMOS transistor Q111a, the NMOS transistor Q112 is replaced with the low threshold NMOS transistor Q112a, and the PMOS transistor Q112a is connected to the power supply voltage. A high threshold PMOS transistor Q121 that is turned on / off in response to the inverted signal CEB of the chip enable signal is inserted between the source VDD and the source VDD. A voltage holding high threshold PMOS transistor Q122 is connected in parallel with the PMOS transistor Q111a. That is, the gate of the PMOS transistor Q122 is connected to the gate of the PMOS transistor Q111a, the drain of the PMOS transistor Q122 is connected to the drain of the PMOS transistor Q111a, and the source of the PMOS transistor Q122 is connected to the power supply voltage source VDD.
(2) The inverter INV32 is replaced with an inverter INV32b, specifically, the PMOS transistor Q113 is replaced with a low threshold PMOS transistor Q113a, the NMOS transistor Q114 is replaced with a low threshold NMOS transistor Q114a, and the PMOS transistor Q113a and the power supply voltage A high threshold PMOS transistor Q123 that is turned on / off in response to the inverted signal CEB of the chip enable signal is inserted between the source VDD and the source VDD. A voltage holding high threshold PMOS transistor Q124 is connected in parallel with the PMOS transistor Q113a. That is, the gate of the PMOS transistor Q124 is connected to the gate of the PMOS transistor Q113a, the drain of the PMOS transistor Q124 is connected to the drain of the PMOS transistor Q113a, and the source of the PMOS transistor Q124 is connected to the power supply voltage source VDD.
(3) In this embodiment, the off currents of the low threshold NMOS transistors Q112a and Q114a are sufficiently smaller than the off currents of the low threshold PMOS transistors Q111a and Q113a (for example, 1/10 to 1 / 1000 or less, typically 1/100 or less.) This is a case that can be ignored.

  In the present embodiment, compared with the inverter INV1a in FIG. 2, only the power supply voltage source VDD side performs power supply control by the inverted signal CEB of the chip enable signal, thereby reducing the leakage current and the PMOS on the power supply voltage source VDD side. Only the transistors Q111a and Q113a are connected to voltage holding high threshold PMOS transistors Q122 and Q124, respectively. Even with this configuration, the output voltage of each inverter INV31b, INV32b is held at the immediately preceding voltage in the standby mode, and when the active mode is entered, the output voltage is immediately set to the predetermined voltage from the held voltage. It can be changed to an appropriate voltage.

Fourteenth embodiment.
16A and 16B are circuit diagrams showing the configuration of the inverter circuit according to the fourteenth embodiment, and FIG. 17 is a circuit diagram showing the configuration of the first virtual power supply circuit used in the inverter circuit of FIG. 18 is a circuit diagram showing a configuration of a second virtual power supply circuit used in the inverter circuit of FIG. Note that VSS is a ground side voltage source and includes a ground terminal and the like.

  In FIG. 16A, four inverters INV41 to INV44 are connected in cascade, and the inverters INV41 and INV43 are supplied with power from the virtual voltage source Virtual VDD1, Virtual VSS1, and the inverters INV42 and INV44 are supplied with power from the virtual voltage source Virtual VDD2, Virtual VSS2. Is done. In addition, four inverters INV45 to INV48 are cascaded, power is supplied to the inverters INV45 and INV47 from the virtual voltage source Virtual VDD3 and Virtual VSS3, and power is supplied to the inverters INV46 and INV48 from the virtual voltage source Virtual VDD4 and Virtual VSS4. .

  The circuit in FIG. 16B includes a NAND gate circuit having the same configuration as that in FIG. 3B and a circuit in which four inverters INV45 to INV48 are connected in cascade in the subsequent stage. The output signal from the inverter INV44 and the output signal from the inverter INV48 in FIG. 16A are input to the NAND gate circuit. Here, the inverters INV49 and INV51 are supplied with power from the virtual voltage source Virtual VDD5 and Virtual VSS5, and the inverters INV50 and INV52 are supplied with power from the virtual voltage source Virtual VDD6 and Virtual VSS6.

  In the first virtual power supply circuit of FIG. 17, the power supply voltage source VDD is generated as a virtual voltage source Virtual VDD1 via a high threshold NMOS transistor Q141 controlled by an inverted signal CEB of the chip enable signal. 16B and the virtual voltage source Virtual VDD2 is generated through the high threshold NMOS transistor Q142 controlled by the inverted signal CEB of the chip enable signal and is supplied to the circuit of FIGS. 16A and 16B. The same applies to the virtual voltage sources Virtual VDD3 to Virtual VDD6. The ground-side voltage source VSS generates a virtual voltage source Virtual VSS1 via a high threshold NMOS transistor Q143 controlled by the chip enable signal CE and supplies power to the circuits of FIGS. 16A and 16B. A virtual voltage source Virtual VSS2 is generated through the high threshold NMOS transistor Q144 controlled by the chip enable signal CE and supplied to the circuits of FIGS. 16A and 16B. Hereinafter, the virtual voltage sources Virtual VSS3 to Virtual VSS6 will be described. The same applies hereinafter.

  In the second virtual power supply circuit of FIG. 18 (used in place of the first virtual power supply circuit), the pump circuit 11 pumps the voltage of the power supply voltage source VDD, for example, 1.8V to a pump voltage of, for example, about 3V. After that, the data is output to the level shifter circuits 12 and 13. The level shifter circuit 12 generates a chip enable signal inverted signal HCEB having a maximum pump voltage by using an inverted signal CEB (for example, a maximum of 1.8V) of the chip enable signal and a pump voltage, and generates a low threshold PMOS. Output to the gates of transistors Q145 and Q146. The level shifter circuit 13 generates a chip enable signal CE having a maximum pump voltage by using a chip enable signal CE (for example, a maximum of 1.8 V) and a pump voltage, and generates high threshold NMOS transistors Q147 and Q148. Output to each gate. As the power supply voltage source VDD, a virtual voltage source Virtual VDD1 is generated through a low threshold PMOS transistor Q145 controlled by an inverted signal HCEB of the chip enable signal and supplied to the circuits of FIGS. 16A and 16B. A virtual voltage source Virtual VDD2 is generated via the low threshold PMOS transistor Q146 controlled by the inverted signal HCEB of the chip enable signal and is supplied to the circuits of FIGS. 16A and 16B. Hereinafter, the virtual voltage source Virtual VDD3 The same applies to Virtual VDD6. The ground-side voltage source VSS generates a virtual voltage source Virtual VSS1 via a high threshold NMOS transistor Q147 controlled by the chip enable signal HCE and supplies power to the circuits of FIGS. 16A and 16B. A virtual voltage source Virtual VSS2 is generated through the high threshold NMOS transistor Q148 controlled by the chip enable signal HCE and supplied to the circuits of FIGS. 16A and 16B. Hereinafter, the virtual voltage sources Virtual VSS3 to Virtual VSS6 will be described. The same applies hereinafter. In the second virtual power supply circuit described above, the leakage current can be reduced also in the low threshold PMOS transistors Q145 and Q146.

  In this embodiment, in the circuits of FIGS. 16A and 16B, the first or second virtual power supply circuit is used, and the power supply voltage source and the ground side for each inverter circuit having the same output voltage logical value in the standby mode. By sharing the voltage source, there is an advantage that the layout of the entire semiconductor chip becomes easy and the chip area can be reduced.

Fifteenth embodiment.
FIG. 19 is a circuit diagram for explaining the problems of the inverter circuit of FIG. 2, FIG. 20 (a) is a circuit diagram showing the configuration of the inverter circuit according to the prior art, and FIG. It is a circuit diagram which shows the structure of the inverter circuit which concerns on this embodiment.

  As shown in FIG. 19, in the standby mode, when the input terminal T1 is at the high level and the output terminal is at the low level, the off-current reducing high threshold PMOS transistor Q21 and the low threshold PMOS transistor Q1a While the node N1 is discharged by the off-current Idisch, when the input terminal T1 is low level and the output terminal is high level, the off-current reducing high threshold NMOS transistor Q22 and the low threshold NMOS transistor Q2a Since the node N2 is charged up by the off-current, there is a problem that current is consumed when returning from the standby mode.

  In order to solve this problem, the following configuration is provided as shown in FIG. The PMOS transistor Q1a, the PMOS transistor Q21, the NMOS transistor Q22, and the NMOS transistor Q2a are connected in this order between the power supply voltage source VDD and the ground terminal. That is, as compared with FIG. 19 (FIG. 2), the arrangement positions of the PMOS transistors Q21 and Q1a are exchanged, and the arrangement positions of the NMOS transistors Q22 and Q2a are exchanged. Thereby, current consumption when returning from the standby mode can be reduced. The configuration method can be applied to other embodiments.

Sixteenth embodiment.
FIG. 21 is a circuit diagram showing configurations of the latch circuit L2aa and the driver circuit 10b according to the sixteenth embodiment.

In FIG. 21, the latch circuit L2aa according to the sixteenth embodiment applies the configuration method of the fifteenth embodiment as compared with the latch circuit L2a according to the eighth embodiment of FIG. It is characterized by being configured.
(1) The clocked inverter INV23a is replaced with the clocked inverter INV23aa. Specifically, the arrangement positions of the PMOS transistors Q73 and Q71 are exchanged, and the arrangement positions of the NMOS transistors Q72 and Q74 are exchanged.
(2) The clocked inverter INV24a is replaced with the clocked inverter INV24aa. Specifically, the arrangement positions of the PMOS transistors Q83 and Q81 are exchanged, and the arrangement positions of the NMOS transistors Q82 and Q84 are exchanged.

  With the above configuration, current consumption when returning from the standby mode can be reduced.

Summary of Embodiments FIG. 22 is a table showing a comparison result between the MTCMOS circuit according to the prior art and the circuit according to each embodiment of the present invention. FIG. 31 is a diagram showing the operations of the sixth to eleventh and sixteenth embodiments excluding FIGS. 16 to 18, and is a timing chart showing changes in control signals, output nodes of the elements, and internal voltages of the latches. It is. FIG. 32 shows the operation of the fourteenth embodiment shown in FIGS. 16 to 18, and is a timing chart showing the change of each control signal and the output node of each element. In FIG. 32, VDDH is a higher voltage pumped up than the voltage of the power supply voltage source VDD.

  As is apparent from FIGS. 22, 31, and 32, according to the embodiment of the present invention, the output voltage of each element in the standby mode is set to the voltage of the power supply voltage source VDD or the voltage of the ground side voltage source VSS, or By configuring so as to hold the logical value of the immediately preceding active mode, it is possible to significantly reduce the current consumption during the transition from the standby mode to the active mode.

  In the circuit of the twelfth embodiment of FIG. 14, when the sixteenth embodiment is applied, only the upper circuit of FIG. 17 or the upper right circuit of FIG. 18 may be used.

  In the circuit of the thirteenth embodiment shown in FIG. 15, when the sixteenth embodiment is applied, only the lower circuit of FIG. 17 or the lower right circuit of FIG. 18 may be used.

  According to the semiconductor device circuit of the present invention, in the semiconductor device circuit including the functional circuit including the first PMOS transistor and the first NMOS transistor, the first PMOS transistor is connected to the power supply voltage source in the active mode. However, the second PMOS transistor that controls the first PMOS transistor not to be connected to the power supply voltage source in the standby mode, and the first NMOS transistor is connected to the ground side voltage source in the active mode. A second NMOS transistor for controlling the first NMOS transistor not to be connected to the ground-side voltage source in a standby mode; a predetermined first threshold absolute value voltage; and connected to the power supply voltage source And connected in parallel to the first PMOS transistor, A third PMOS transistor for holding the output signal of the PMOS transistor, and a predetermined second threshold absolute value voltage, connected to the ground-side voltage source and connected in parallel to the first NMOS transistor And a third NMOS transistor that holds the output signal of the first NMOS transistor, and the threshold absolute value voltage of the first PMOS transistor is lower than the first threshold absolute value voltage. The fourth threshold absolute value voltage is configured to have a third threshold absolute value voltage, and the threshold absolute value voltage of the first NMOS transistor is lower than the second threshold absolute value voltage. It was configured to have a value voltage. Accordingly, since the output signal immediately before entering the standby mode is held by the third PMOS transistor and the third NMOS transistor, the original signal level is immediately restored when the standby mode is restored to the active mode. In addition, in a semiconductor device circuit using an MTCMOS circuit, it is possible to provide a semiconductor device circuit in which the access speed is not impaired, the standby current is small, and the recovery from the standby state is quick.

10 to 10b ... driver circuit,
INV1 to INV51 ... inverter,
L1 to L1d, L2 to L2b, LA11... Latch circuit,
NAND1 to NAND4 ... NAND gate,
NOR1 to NOR4: NOR gate,
Q1-Q148 ... MOS transistors,
T1, T1a, T1b, T1A, T1B ... input terminals,
T2: Output terminal,
TG1 to TG14a: Transmission gate.

Claims (13)

In a semiconductor device circuit including a functional circuit including a first PMOS transistor and a first NMOS transistor,
A second PMOS transistor for controlling the first PMOS transistor to be connected to the power supply voltage source in the active mode, but not to connect the first PMOS transistor to the power supply voltage source in the standby mode;
A second NMOS transistor for controlling the first NMOS transistor to be connected to the ground side voltage source in the active mode, but not to connect the first NMOS transistor to the ground side voltage source in the standby mode;
A third first voltage having a predetermined first threshold absolute value voltage, connected to the power supply voltage source and connected in parallel to the first PMOS transistor, and holding an output signal of the first PMOS transistor; A PMOS transistor;
A third voltage having a predetermined second threshold absolute value voltage, connected to the ground-side voltage source and connected in parallel to the first NMOS transistor, and holding an output signal of the first NMOS transistor With NMOS transistors,
The threshold absolute value voltage of the first PMOS transistor is configured to have a third threshold absolute value voltage lower than the first threshold absolute value voltage. A semiconductor device circuit configured to have a fourth threshold absolute value voltage which is lower than the second threshold absolute value voltage. In a semiconductor device circuit including a functional circuit including a first PMOS transistor and a first NMOS transistor,
A second NMOS transistor for controlling the first NMOS transistor to be connected to the ground side voltage source in the active mode, but not to connect the first NMOS transistor to the ground side voltage source in the standby mode;
A third voltage having a predetermined first threshold absolute value voltage, connected to the ground-side voltage source and connected in parallel to the first NMOS transistor, and holding an output signal of the first NMOS transistor With NMOS transistors,
A semiconductor device characterized in that a threshold absolute value voltage of the first NMOS transistor has a second threshold absolute value voltage lower than the first threshold absolute value voltage. circuit. In a semiconductor device circuit including a functional circuit including a first PMOS transistor and a first NMOS transistor,
A second PMOS transistor for controlling the first PMOS transistor to be connected to the power supply voltage source in the active mode, but not to connect the first PMOS transistor to the power supply voltage source in the standby mode;
A third first voltage having a predetermined first threshold absolute value voltage, connected to the power supply voltage source and connected in parallel to the first PMOS transistor, and holding an output signal of the first PMOS transistor; With PMOS transistor,
A semiconductor device characterized in that a threshold absolute value voltage of the first PMOS transistor has a second threshold absolute value voltage lower than the first threshold absolute value voltage. circuit. The first PMOS transistor is connected to the power supply voltage source via the second PMOS transistor,
2. The semiconductor device circuit according to claim 1, wherein the first NMOS transistor is connected to the ground-side voltage source via the second NMOS transistor.   3. The semiconductor device circuit according to claim 2, wherein the first NMOS transistor is connected to the ground-side voltage source through the second NMOS transistor.   4. The semiconductor device circuit according to claim 3, wherein the first PMOS transistor is connected to the power supply voltage source via the second PMOS transistor. The second PMOS transistor is connected to the power supply voltage source via the first PMOS transistor,
2. The semiconductor device circuit according to claim 1, wherein the second NMOS transistor is connected to the ground-side voltage source via the first NMOS transistor.   3. The semiconductor device circuit according to claim 2, wherein the second NMOS transistor is connected to the ground-side voltage source via the first NMOS transistor.   4. The semiconductor device circuit according to claim 3, wherein the second PMOS transistor is connected to the power supply voltage source via the first PMOS transistor. A plurality of the functional circuits according to claim 1, 4 or 7,
2. The second PMOS transistor and the second NMOS transistor are provided in common with respect to a functional circuit having the same logical value of an output signal among the plurality of functional circuits. Semiconductor device circuit. A plurality of the functional circuits according to claim 2, 5 or 8,
3. The semiconductor device circuit according to claim 2, wherein the second NMOS transistor is provided in common for the functional circuit having the same logical value of the output signal among the plurality of functional circuits. A plurality of the functional circuits according to claim 3, 6 or 9,
4. The semiconductor device circuit according to claim 3, wherein the second PMOS transistor is provided in common for the functional circuit having the same logical value of the output signal among the plurality of functional circuits.   13. The semiconductor device circuit according to claim 1, wherein the functional circuit is an inverter circuit, a gate circuit, a multiplexer, a flip-flop circuit, or a latch circuit of a memory device.

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