JP2012038748A - Semiconductor device and method for manufacturing semiconductor device - Google Patents

Abstract

Provided is a semiconductor device capable of preventing connection failure due to misalignment of a conductive material layer and increasing the degree of integration by miniaturization.
A first electrode 2 having a recess 4 formed in a central portion of an upper surface, and a second electrode formed in at least a part of the recess 4 and self-aligned with the recess 4 of the first electrode 2. A semiconductor device including the electrode 6 is configured. Further, the resistance value is changed by application of a voltage to constitute a resistance change type memory element, and a semiconductor device including a resistance change layer 7 formed in contact with the second electrode 6 is constituted.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device having a memory element, a semiconductor device having a multilayer wiring layer connected by a plug layer, and a method for manufacturing these semiconductor devices.

Currently, semiconductor devices including EEPROM (Electrically Erasable and Programmable ROM) and non-volatile memory cells such as flash memory are generally used in various fields.
Improvements in reliability such as the number of times of rewriting of nonvolatile memory cells and data retention resistance and miniaturization of structures are important issues.

In recent years, resistance change type memories have been attracting attention because they are advantageous in terms of reliability and miniaturization with respect to flash memory structures represented by floating types already on the market (for example, patents). Reference 1).
Examples of the resistance change type memory include ARAM, RRAM, PCRAM, MRAM, and SpinRAM. These resistance change memories are said to be suitable for high performance and high integration in combination with a simple structure, high-speed rewriting performance, and multi-value technology, and are attracting attention.

  In a resistance change type nonvolatile memory, it is possible to increase the current density and to concentrate the electric field as the area where the resistance change layer whose resistance value changes and the lower electrode are in contact with each other is reduced. It is possible to increase the degree of integration by reducing the area.

In addition, in the variable resistance nonvolatile memory, a configuration in which a memory element that forms a memory cell is arranged above a transistor that drives the memory element formed on a semiconductor substrate has been proposed.
With this configuration, it is possible to reduce the area in the horizontal direction and reduce the size of the nonvolatile memory chip.

JP 2002-537627 A

  In the nonvolatile memory configured as described above, in order to electrically connect the memory element and the transistor formed in the lower semiconductor substrate, a plug made of a conductive material embedded in a via hole formed in the interlayer insulating layer Use layers.

However, there are only a limited number of conductive materials that can be embedded well in narrow via holes, and in order to increase the degree of integration, it is necessary to refine the via holes using the limited conductive materials.
On the other hand, for the electrode layer in contact with the resistance change layer of the memory element, it is desirable to use an electrode material that has a small contact resistance with the resistance change layer and sufficiently obtains the characteristics of the memory element.
For these reasons, if the resistance change layer of the memory element is formed directly on the plug layer embedded in the via hole, the contact resistance may increase or the characteristics of the memory element may not be sufficiently obtained.

Therefore, it is conceivable to form the plug layer and the electrode layer in contact with the resistance change layer of the memory element separately from each other with different materials and connect the electrode layer on the plug layer.
Thereby, the material of the plug layer and the electrode layer can be optimized.
Further, since the plug layer is embedded in the via hole, there is a limit to reduction due to the limitation of the photolithography technique, but the electrode layer can be further reduced by etching or the like after forming the electrode material layer. That is, the area of the electrode layer can be made smaller than that of the plug layer.

  However, when the electrode layer is formed on the plug layer, if the misalignment between the plug layer and the electrode layer occurs, poor contact between the plug layer and the electrode layer may occur.

In addition to a semiconductor device including a memory element, an upper wiring layer and a lower wiring layer are connected using a plug layer also in a semiconductor device or the like having a multilayer wiring.
The plug layer has a limit in the ratio of height to width (aspect) due to the embedding property of the conductive material. Therefore, when the difference in height between the upper wiring layer and the lower wiring layer is large, the upper and lower wiring layers are connected by forming a plurality of plug layers stacked one above the other.
At this time, connection failure may occur due to misalignment of the upper and lower plug layers.

In order to prevent connection failure due to misalignment of the upper and lower plug layers, conventionally, the upper surface of the plug layer is formed wider than the lower surface, so that connection failure does not occur even if there is some misalignment. .
However, if the upper surface of the plug layer is formed wider, it becomes difficult to increase the degree of integration by miniaturizing the plug layer and the wiring layer.

  In order to solve the above-described problems, the present invention provides a semiconductor device and a method for manufacturing the semiconductor device that can prevent poor connection due to misalignment of the conductive material layer and can increase the degree of integration by miniaturization. To do.

  The semiconductor device of the present invention includes a first electrode having a recess formed in the center of the upper surface, a second electrode embedded in at least a part of the recess and formed in self-alignment with the recess of the first electrode, including.

According to the above-described configuration of the semiconductor device of the present invention, the second electrode is embedded in at least a part of the recess in the central portion of the upper surface of the first electrode, and the second electrode is self-relative to the recess of the first electrode. It is formed consistently.
As a result, the first electrode and the second electrode do not cause misalignment.

The semiconductor device of the present invention includes a first electrode having a recess formed in the center of the upper surface, a second electrode embedded in at least a part of the recess and formed in self-alignment with the recess of the first electrode, including.
Further, the resistance value is changed by application of a voltage to form a resistance change type memory element, and includes a resistance change layer formed in contact with the second electrode.

According to the above-described configuration of the semiconductor device of the present invention, the second electrode is embedded in at least a part of the recess in the central portion of the upper surface of the first electrode, and the second electrode is self-relative to the recess of the first electrode. It is formed consistently.
As a result, the first electrode and the second electrode do not cause misalignment.
And since the resistance change layer which comprises a resistance change type memory element is formed in contact with this 2nd electrode, the 1st electrode, the 2nd electrode, and the resistance change layer are electrically connected. A current and a voltage can be supplied from the first electrode to the resistance change layer.

The method for manufacturing a semiconductor device according to the present invention includes a step of forming a first electrode embedded in a via hole by embedding an electrode material in a via hole formed in an interlayer insulating layer so that a recess is formed in a central portion. Forming an insulating layer on one electrode.
In addition, the method includes a step of exposing at least an upper portion of the first electrode on the side wall of the recess by etching, and a step of forming an electrode material layer so as to fill at least a part of the recess and directly contact the exposed first electrode. .
And the process of forming the 2nd electrode which consists of an electrode material layer by removing the electrode material layer on an insulating layer is included.

According to the semiconductor device manufacturing method of the present invention described above, the first electrode is formed by embedding the electrode material so that a recess is formed in the central portion in the via hole, and the insulating layer is formed on the first electrode. An insulating layer is formed on one electrode, and an insulating film is formed on the side wall of the recess.
In addition, since at least the upper part of the first electrode on the concave sidewall is exposed by etching, at least the upper part of the insulating film on the concave sidewall is removed.
Then, the electrode material layer is formed so as to fill at least a part of the recess, and the electrode material layer on the insulating layer is removed to form the second electrode made of the electrode material layer. The part and the second electrode are in direct contact with each other. Thereby, the first electrode and the second electrode can be electrically connected.
Since the second electrode formed by filling at least a part of the recess is formed at the position of the recess, the second electrode is formed in self-alignment with the recess at the center of the upper surface of the first electrode. There is no misalignment between the two electrodes.

The method for manufacturing a semiconductor device according to the present invention includes a step of forming a first electrode embedded in a via hole by embedding an electrode material in a via hole formed in an interlayer insulating layer so that a recess is formed in a central portion. Forming an insulating layer on one electrode.
In addition, the method includes a step of exposing at least an upper portion of the first electrode on the side wall of the recess by etching, and a step of forming an electrode material layer so as to fill at least a part of the recess and directly contact the exposed first electrode. .
And the process of forming the 2nd electrode which consists of an electrode material layer by removing the electrode material layer on an insulating layer is included.
Further, the method includes a step of forming a resistance change layer that is in contact with the second electrode and changes its resistance value by application of a voltage to constitute a resistance change type memory element.

According to the semiconductor device manufacturing method of the present invention described above, the first electrode is formed by embedding the electrode material so that a recess is formed in the central portion in the via hole, and the insulating layer is formed on the first electrode. An insulating layer is formed on one electrode, and an insulating film is formed on the side wall of the recess.
In addition, since at least the upper part of the first electrode on the concave sidewall is exposed by etching, at least the upper part of the insulating film on the concave sidewall is removed.
Then, the electrode material layer is formed so as to fill at least a part of the recess, and the electrode material layer on the insulating layer is removed to form the second electrode made of the electrode material layer. The part and the second electrode are in direct contact with each other. Thereby, the first electrode and the second electrode can be electrically connected.
Since the second electrode formed by filling at least a part of the recess is formed at the position of the recess, the second electrode is formed in self-alignment with the recess in the center of the upper surface of the first electrode. There is no misalignment.
Further, the resistance value is changed by application of a voltage in contact with the second electrode to form a resistance change type memory element, so that the first electrode, the second electrode, the resistance change layer, Can be electrically connected.

  According to the present invention described above, since the first electrode and the second electrode do not cause misalignment, connection failure caused by misalignment can be prevented.

  In addition, since the second electrode is buried in the depression at the center of the upper surface of the first electrode, the second electrode can be formed smaller than the upper surface of the first electrode. As a result, the second electrode and the variable resistance layer and the wiring layer formed on and in contact with the second electrode can be miniaturized to increase the degree of integration of the semiconductor device. In particular, when the variable resistance layer is formed on the second electrode, the electric field and current can be more concentrated in the variable resistance layer by forming the second electrode small.

  Further, according to the present invention, since the first electrode and the second electrode are formed separately, these electrodes can be formed using different conductive materials, and the electrode material of each electrode is optimal. It is possible to

1 is a schematic configuration diagram (cross-sectional view) of a first embodiment of a semiconductor device of the present invention. A and B are diagrams in which electrode portions of the semiconductor device of FIG. 1 are extracted. FIG. 2 is a manufacturing process diagram illustrating a method for manufacturing the semiconductor device of FIG. 1; FIG. 2 is a manufacturing process diagram illustrating a method for manufacturing the semiconductor device of FIG. 1; FIG. 2 is a manufacturing process diagram illustrating a method for manufacturing the semiconductor device of FIG. 1; FIG. 2 is a manufacturing process diagram illustrating a method for manufacturing the semiconductor device of FIG. 1; FIG. 2 is a manufacturing process diagram illustrating a method for manufacturing the semiconductor device of FIG. 1; It is a schematic block diagram (sectional drawing) of 2nd Embodiment of the semiconductor device of this invention. It is a schematic block diagram (sectional drawing) of 3rd Embodiment of the semiconductor device of this invention. It is a schematic block diagram (sectional drawing) of 4th Embodiment of the semiconductor device of this invention. FIG. 11 is a manufacturing process diagram illustrating a method of manufacturing the semiconductor device of FIG. 10; FIG. 11 is a manufacturing process diagram illustrating a method of manufacturing the semiconductor device of FIG. 10; It is a schematic block diagram (sectional drawing) of 5th Embodiment of the semiconductor device of this invention. It is a schematic block diagram (sectional drawing) of 6th Embodiment of the semiconductor device of this invention. It is a schematic block diagram (sectional drawing) of 7th Embodiment of the semiconductor device of this invention. It is a schematic block diagram (sectional drawing) of 8th Embodiment of the semiconductor device of this invention. It is a schematic block diagram (sectional drawing) of 9th Embodiment of the semiconductor device of this invention. It is a schematic block diagram (sectional drawing) of 10th Embodiment of the semiconductor device of this invention. A and B are schematic configuration diagrams of an eleventh embodiment of a semiconductor device of the present invention. It is the top view which arranged the 1st electrode and 2nd electrode of FIG. 19 in the horizontal direction. It is a schematic block diagram (sectional drawing) of 12th Embodiment of the semiconductor device of this invention.

Hereinafter, the best mode for carrying out the invention (hereinafter referred to as an embodiment) will be described.
The description will be given in the following order.
1. First Embodiment 2. FIG. Second Embodiment 3. FIG. Third embodiment 4. 4. Fourth embodiment Fifth Embodiment Sixth Embodiment Seventh embodiment Eighth Embodiment 9 Ninth embodiment 10. Tenth Embodiment Eleventh Embodiment 12th embodiment

<1. First Embodiment>
FIG. 1 shows a schematic configuration diagram (cross-sectional view) of a semiconductor device according to a first embodiment of the present invention.
This semiconductor device includes a storage element constituting a memory cell of a nonvolatile resistance change memory.
As shown in FIG. 1, the 1st electrode 2 is formed in the inside of the 1st interlayer insulation layer 1 formed on the board | substrate which is not shown in figure.
The first electrode 2 has a hole called a seam 4 formed at the center thereof. The seam 4 forms a recess in the central portion of the upper surface of the first electrode 2.
A thin insulating film 3 is formed on the side wall of the seam 4.
A second electrode 6 is formed immediately above the seam 4. The second electrode 6 is formed so as to be partially embedded in the seam 4 formed on the first electrode 2, thereby self-aligning with the seam 4 of the first electrode 2.
A second interlayer insulating layer 5 is formed around the second electrode 6.

For the first electrode 2, metals such as W and Cu, polycrystalline silicon, and the like that are generally used as electrode materials for semiconductor devices can be used.
The material of the second electrode 6 should be selected in combination with the material on the second electrode 6 formed in the subsequent process, but Pt, Ti, TiN or the like can be used.
For the first interlayer insulating layer 1 and the second interlayer insulating layer 5, an electrically insulating material such as TEOS or p-SiO ₂ can be used. The first interlayer insulating layer 1 and the second interlayer insulating layer 5 may be formed of the same material or different materials.
The insulating layer 3 on the side wall of the seam 4 is not particularly limited as long as it is an insulating material, but when manufactured by the manufacturing method described later, the insulating layer 3 and the second interlayer insulating layer 5 are formed of the same insulating material. .

  On the second electrode 6, a resistance change layer 7 is formed which includes a memory layer 11 made of a metal oxide and an ion source layer 12 that is formed on the memory layer 11 and supplies metal ions to the memory layer 11. ing. Furthermore, an upper electrode 8 is formed on the resistance change layer 7.

As the metal oxide of the memory layer 11, it is possible to use one or a mixture of two or more selected from gadolinium oxide, tantalum oxide, niobium oxide, aluminum oxide, hafnium oxide, and zirconium oxide. it can.
The ion source layer 12 contains any element selected from Cu, Ag, Zn, and Al and a chalcogenide element selected from Te, S, and Se. Examples thereof include CuTe, GeSbTe, CuGeTe, AuGeTe, AgTe, ZnTe, ZnGeTe, CuS, CuGeS, CuSe, and CuGeSe.
For the upper electrode 8, for example, WN, TiN, W, Ti, Au, Pt, Ag, Ru, Te or the like can be used.

  Then, the second electrode 6 serving as the lower electrode is formed below the resistance change layer 7 and the upper electrode 8 is formed on the resistance change layer 7, whereby these layers 6, 7 (11, 12) are formed. , 8 constitute a storage element. A memory can be configured by arranging a large number of memory cells using this memory element as one memory cell.

Next, information recording and erasing operations of the storage element will be described.
First, for example, a positive potential (+ potential) is applied to the upper electrode 8 in contact with the ion source layer 12, and a positive voltage is applied to the storage element so that the second electrode 6 side becomes negative. Thereby, Cu, Ag, Zn, and Al contained in the ion source layer 12 are ionized from the ion source layer 12 and diffused in the memory layer 11, and are combined with electrons on the second electrode 6 side. To precipitate. Alternatively, it remains diffused in the storage layer 11.
Then, a current path containing a large amount of Cu, Ag, Zn, and Al is formed in the memory layer 11, or many defects due to Cu, Ag, Zn, and Al are formed in the memory layer 11. The resistance value of the memory layer 11 is lowered. Since the resistance value of each layer other than the memory layer 11 is originally low and sufficiently lower than the resistance value of the memory layer 11 before recording, the resistance value of the memory element as a whole is lowered by reducing the resistance value of the memory layer 11. .
After that, when the positive voltage is removed and the voltage applied to the memory element is eliminated, the resistance value is kept low. This makes it possible to record information. When used in a storage device that can be recorded only once, so-called PROM, the recording is completed only by the recording process.

On the other hand, when applied to a storage device capable of erasing recorded information, such as RAM or EEPROM, an erasing process is necessary. In the erasing process, for example, a negative potential (−potential) is applied to the upper electrode 8 in contact with the ion source layer 12, and a negative voltage is applied to the storage element so that the second electrode 6 side becomes negative. As a result, Cu, Ag, Zn, and Al constituting current paths or defects (impurity levels) formed in the memory layer 11 are ionized, move in the memory layer 11, and return to the ion source layer 12. .
Then, current paths or defects due to Cu, Ag, Zn, and Al disappear from the memory layer 11, and the resistance value of the memory layer 11 increases. Since the resistance value of each layer other than the memory layer 11 is originally low and sufficiently lower than the resistance value of the memory layer 11, increasing the resistance value of the memory layer 11 also increases the resistance value of the entire memory element.
After that, when the negative voltage is removed and the voltage applied to the memory element is eliminated, the resistance value is kept high. As a result, the recorded information can be erased.

  By repeating such a process, it is possible to repeatedly record (write) information on the storage element and erase the recorded information.

Here, in FIG. 1, an electrode portion below the resistance change layer 7 is extracted, FIG. 2A shows a cross-sectional view, and FIG. 2B shows a top view of the electrode portion. 2A is a cross-sectional view taken along line AA ′ of FIG. 2B.
As shown in FIGS. 2A and 2B, the first electrode 2 is formed in a cylindrical shape, and the upper surface of the second electrode 6 formed on the seam 4 at the center is circular.

In the configuration shown in FIG. 1, the second electrode 6 has a diameter smaller than that of the first electrode 2, so that the resistance change layer 7 is compared with the configuration in which the resistance change layer 7 is formed directly on the first electrode 2. It is easy to concentrate the electric field inside.
Further, as shown in FIGS. 1 and 2A, the insulating film 3 is not formed on the wall surface of the seam 4 at the uppermost portion of the first electrode 2, and the first electrode 2 and the second electrode 6 are in direct contact with each other. Yes. The first electrode 2 and the second electrode 6 can be electrically connected at this directly contacting portion. Since the resistance change layer 7 is formed on and in contact with the second electrode 6, the first electrode 2, the second electrode 6, and the resistance change layer 7 are electrically connected, and the resistance from the first electrode 2 is increased. A voltage or current can be supplied to the change layer 7.
Furthermore, since the first electrode 2 has a diameter larger than that of the second electrode 6, the heat capacity is large, and heat generated in the resistance change layer 7 can be easily radiated to the lower part through the first electrode 2. Thereby, deterioration of the memory element due to heat can be suppressed, and the number of rewrites and the reliability of data retention can be improved.

  The second electrode 6 is embedded in a part of the seam 4 formed at the center of the first electrode 2 and is self-aligned with the seam 4 of the first electrode 2. Thereby, the misalignment between the first electrode 2 and the second electrode 6 does not occur.

The semiconductor device of the present embodiment can be manufactured, for example, as described below.
First, the first electrode 2 is formed by a general via formation process. That is, a via hole is formed in the first interlayer insulating layer 2 by lithography, and after filling the via hole to form an electrode material layer, the electrode material layer on the first interlayer insulating layer 2 is removed and the first interlayer insulating layer is removed. A first electrode 2 is formed in the via hole of the layer 2.
At this time, the inside of the via hole is not completely filled with the electrode material layer, so that a hole called a seam 4 remains as a recess in the center of the via hole as shown in FIG.
The seam (hole) 4 is naturally formed in a normal semiconductor process, but the diameter of the seam 4 is adjusted to some extent by changing the electrode material and the film formation conditions. Is possible.

Next, as shown in FIG. 4, an insulating layer 21 is formed on the surface. At this time, the insulating layer 21 is formed on the first electrode 2, and the insulating layer 21 is thinly formed on the side wall of the seam 4.
Further, the insulating layer 21 is retracted by anisotropic etching such as dry etching to expose the upper portion of the first electrode 2 on the side wall of the seam 4 as shown in FIG. Thereby, the insulating film 3 on the side wall of the seam 4 made of the insulating layer 21 and the second interlayer insulating layer 5 made of the insulating layer 21 are formed separately.

Subsequently, by forming an electrode material layer 22 to be the second electrode 6, as shown in FIG. 6, the electrode material layer 22 is directly in contact with the exposed portion of the first electrode 2 and embedded in the upper portion of the seam 4. A structure in which the material layer 22 and the first electrode 2 are electrically connected is formed.
Thereafter, the electrode material layer 22 on the second interlayer insulating layer 5 is removed by a CMP (Chemical Mechanical Polishing) method, etching, or the like, so that the inner side of the second interlayer insulating layer 5 is formed as shown in FIG. The second electrode 6 made of the electrode material layer 22 is formed.
In this way, the electrode structure shown in FIGS. 1 and 2A can be formed.
Thereafter, the memory layer 11, the ion source layer 12, and the upper electrode 8 are formed in order, whereby the semiconductor device shown in FIG. 1 can be manufactured.

According to the above-described configuration of the present embodiment, the first electrode 2 is embedded in the upper portion of the seam 4 formed in the central portion of the upper surface, and is self-aligned with the seam 4 of the first electrode 2. Two electrodes 6 are formed.
Thereby, in the 1st electrode 2 and the 2nd electrode 6, position misalignment does not arise and the connection failure resulting from misalignment can be prevented.

In addition, since the second electrode 6 is formed by being embedded in the upper part of the seam 4 formed in the central portion of the first electrode 2, the diameter of the second electrode 6 corresponds to the diameter of the seam 4. It is smaller than the diameter of one electrode 2.
Accordingly, the contact area between the second electrode 6 and the resistance change layer 7 (11, 12) can be reduced as compared with the configuration in which the resistance change layer 7 (11, 12) is directly formed on the first electrode 2. Therefore, the electric field and current can be more concentrated in the resistance change layer 7. In this way, the performance of the memory element composed of the resistance change layer 7 can be improved. In addition, since the degree of integration of the memory elements can be increased, the memory can be downsized and the storage capacity can be increased.
Even if the diameter of the first electrode 2 is reduced to the limit of lithography, the diameter of the second electrode 6 can be made smaller than the limit of lithography.
On the other hand, since the diameter of the first electrode 2 is larger than the diameter of the second electrode 6, the heat capacity of the first electrode 2 is larger than the heat capacity of the second electrode 6. As a result, even if the second electrode 6 is miniaturized in order to improve the performance and integration of the memory element, the effect of the heat sink can be obtained by the first electrode 2 having a large heat capacity, so that heat can be released from the memory element. Further, damage to the memory element due to heat accumulation can be prevented. Therefore, the reliability of a semiconductor device including a nonvolatile memory including a memory element can be improved.

Further, according to the configuration of the present embodiment, since the first electrode 2 and the second electrode 6 are formed separately, the first electrode 2 and the second electrode 6 are made of different conductive materials. Can be formed.
For example, the first electrode 2 is formed using Cu having a high thermal conductivity, and the second electrode 6 is formed using Pt that improves the resistance change performance of the memory element. It is possible to achieve both improvement.
For example, the manufacturing cost can be reduced by forming the first electrode 2 using an inexpensive conductive material such as W or polysilicon (polycrystalline silicon).

<2. Second Embodiment>
FIG. 8 shows a schematic configuration diagram (cross-sectional view) of a semiconductor device according to a second embodiment of the present invention.
In the present embodiment, the resistance change layer 7 between the second electrode 6 and the upper electrode 8 is formed of only the metal oxide layer 13 to constitute a memory element.

As the metal oxide layer 13, for example, an oxide layer of a transition metal element such as a nickel oxide layer, a titanium oxide layer, a zinc oxide layer, or a niobium oxide layer can be used.
Moreover, it is good also as a structure which laminated | stacked two types of metal oxide layers. For example, a configuration in which an oxide layer obtained by adding titanium to nickel oxide is stacked on a titanium oxide layer, a configuration in which a tantalum oxide layer is stacked on a cobalt oxide layer, or the like is possible.

In the memory element of the semiconductor device according to the present embodiment, when a voltage is applied between the second electrode 6 and the upper electrode 8, the resistance value of the resistance change layer 7 formed of the metal oxide layer 13 changes.
Accordingly, since the amount of current flowing through the resistance change layer 7 changes, information on “0” and “1” can be recorded and read out from the storage element by using the difference in the amount of current.

  The other configuration is the same as that of the first embodiment shown in FIG. 1, and therefore, the same reference numerals are given and redundant description is omitted.

According to the configuration of the present embodiment described above, the first electrode 2 is embedded in the upper portion of the seam 4 formed at the center of the upper surface of the first electrode 2, as in the first embodiment. The second electrode 6 is formed in self-alignment with the seam 4.
Thereby, in the 1st electrode 2 and the 2nd electrode 6, position misalignment does not arise and the connection failure resulting from misalignment can be prevented.

In addition, since the second electrode 6 is formed by being embedded in the upper part of the seam 4 formed in the central portion of the first electrode 2, the diameter of the second electrode 6 corresponds to the diameter of the seam 4. It is smaller than the diameter of one electrode 2.
Thereby, compared with the structure which formed the resistance change layer 7 (13) directly on the 1st electrode 2, since the contact area of the 2nd electrode 6 and the resistance change layer 7 (13) can be made small, In the resistance change layer 7, the electric field and current can be more concentrated. In this way, the performance of the memory element composed of the resistance change layer 7 can be improved. In addition, since the degree of integration of the memory elements can be increased, the memory can be downsized and the storage capacity can be increased.
Even if the diameter of the first electrode 2 is reduced to the limit of lithography, the diameter of the second electrode 6 can be made smaller than the limit of lithography.
On the other hand, since the diameter of the first electrode 2 is larger than the diameter of the second electrode 6, the heat capacity of the first electrode 2 is larger than the heat capacity of the second electrode 6. As a result, even if the second electrode 6 is miniaturized in order to improve the performance and integration of the memory element, the effect of the heat sink can be obtained by the first electrode 2 having a large heat capacity, so that heat can be released from the memory element. Further, damage to the memory element due to heat accumulation can be prevented. Therefore, the reliability of a semiconductor device including a nonvolatile memory including a memory element can be improved.

Further, according to the configuration of the present embodiment, since the first electrode 2 and the second electrode 6 are formed separately, the first electrode 2 and the second electrode 6 are made of different conductive materials. Can be formed.
For example, by forming the first electrode 2 using Cu having high thermal conductivity and forming the second electrode 6 using a material that improves the resistance change performance of the memory element, the heat dissipation and the characteristics of the memory element are achieved. It is possible to achieve both improvement.
For example, it is possible to reduce the manufacturing cost by forming the first electrode 2 using an inexpensive conductive material such as W or polysilicon (polycrystalline silicon).

<3. Third Embodiment>
FIG. 9 shows a schematic configuration diagram (cross-sectional view) of the third embodiment of the semiconductor device of the present invention.
In the present embodiment, the electrode portion shown in FIG. 2 of the first embodiment is applied to a semiconductor device having a multilayer wiring.
As shown in FIG. 9, an upper wiring layer 14 is formed in direct contact with the second electrode 6. Accordingly, the lower wiring layer (not shown) and the wiring layer 14 can be electrically connected via the first electrode 2 and the second electrode 6.

  The other configuration is the same as that of the first embodiment shown in FIG. 1, and therefore, the same reference numerals are given and redundant description is omitted.

According to the configuration of the present embodiment described above, the first electrode 2 is embedded in the upper portion of the seam 4 formed at the center of the upper surface of the first electrode 2, as in the first embodiment. The second electrode 6 is formed in self-alignment with the seam 4.
Thereby, in the 1st electrode 2 and the 2nd electrode 6, position misalignment does not arise and the connection failure resulting from misalignment can be prevented.

In addition, since the second electrode 6 is formed by being embedded in the upper part of the seam 4 formed in the central portion of the first electrode 2, the diameter of the second electrode 6 corresponds to the diameter of the seam 4. It is smaller than the diameter of one electrode 2.
Thereby, compared with the structure which formed the wiring layer 14 directly on the 1st electrode 2, the area of the electrode which the 2nd electrode 6 and the wiring layer 14 contact can be made small. As a result, the wiring layer 14 can be miniaturized and the degree of integration of the semiconductor device can be increased.
Even if the diameter of the first electrode 2 is reduced to the limit of lithography, the diameter of the second electrode 6 can be made smaller than the limit of lithography.

Furthermore, in this embodiment, since the wiring layer 14 is in contact with the second electrode 6, there is no restriction on the material of the second electrode 6 due to the characteristics of the memory element.
For this reason, in the present embodiment, the same conductive material can be used for the first electrode 2 and the second electrode 6.
By using the same conductive material for the first electrode 2 and the second electrode 6, for example, it is possible to reduce the material cost by using an inexpensive material, and to each of the first electrode 2 and the second electrode 6. It is possible to reduce the cost of the manufacturing process by forming the electrode material layer with the same apparatus.

<4. Fourth Embodiment>
FIG. 10 shows a schematic configuration diagram (cross-sectional view) of a fourth embodiment of the semiconductor device of the present invention.
In FIG. 10, as in FIG. 2A, the electrode portion of the semiconductor device is extracted and shown.
As shown in FIG. 10, the cross-sectional shape of the upper part of the second electrode 6 is different from that of FIG. 1 and FIG. 2A, which is uniformly formed with the lower part of the second electrode. ing.

The other configuration is the same as that of the electrode portion of the first embodiment shown in FIG. 2A, and therefore, the same reference numerals are given and redundant description is omitted.
In the configuration of the electrode portion of the fourth embodiment, the configuration on the second electrode 6 can be the same as the configurations of the first to third embodiments. That is, the resistance change layer 7 and the wiring layer 14 of the memory element can be formed on the second electrode 6.

The semiconductor device of the present embodiment can be manufactured, for example, as described below.
When the insulating layer 21 to be the second interlayer insulating layer 5 and the insulating film 3 is formed from the same state as that shown in FIG. 3, depending on the formation conditions of the insulating layer 21, the same state as that shown in FIG. Instead, as shown in FIG. 11, the insulating layer 21 may remain on the seam 4 in an eaves shape.
By combining isotropic etching such as wet etching and anisotropic etching with the insulating layer 21 having this shape, the upper portion of the first electrode 2 is exposed as shown in FIG. The upper part of the second interlayer insulating layer 5 can be retreated.
Thereafter, an electrode material layer is formed so as to be directly in contact with the exposed portion of the first electrode 2 and embedded in the upper portion of the seam 4, and the electrode material layer on the second interlayer insulating layer 5 is further removed. Thus, the second electrode 6 made of the electrode material layer is formed. As a result, the second electrode 6 having an upper portion wider than the lower portion can be formed in accordance with the second interlayer insulating layer 5 whose upper portion is recessed, as shown in FIG.

According to the configuration of the present embodiment described above, the first electrode 2 is embedded in the upper portion of the seam 4 formed at the center of the upper surface of the first electrode 2, as in the first embodiment. The second electrode 6 is formed in self-alignment with the seam 4.
Thereby, in the 1st electrode 2 and the 2nd electrode 6, position misalignment does not arise and the connection failure resulting from misalignment can be prevented.

In addition, since the second electrode 6 is formed by being embedded in the upper part of the seam 4 formed in the central portion of the first electrode 2, the diameter of the second electrode 6 corresponds to the diameter of the seam 4. It is smaller than the diameter of one electrode 2.
Thereby, compared with the structure which formed the resistance change layer and the wiring layer directly on the 1st electrode 2, the contact area of the 2nd electrode 6 and a resistance change layer and a wiring layer can be made small.
When the resistance change layer of the memory element is formed on the second electrode 6, the electric field and current can be more concentrated in the resistance change layer, and the performance of the memory element including the resistance change layer can be improved. . In addition, the degree of integration of the storage elements can be increased to reduce the size of the memory and increase the storage capacity.
When a wiring layer is formed on the second electrode 6, the area of the electrode in contact with the wiring layer can be reduced, so that the wiring layer can be miniaturized and the degree of integration of the semiconductor device can be increased.

Even if the diameter of the first electrode 2 is reduced to the limit of lithography, the diameter of the second electrode 6 can be made smaller than the limit of lithography.
On the other hand, since the diameter of the first electrode 2 is larger than the diameter of the second electrode 6, the heat capacity of the first electrode 2 is larger than the heat capacity of the second electrode 6. As a result, when the resistance change layer of the memory element is formed on the second electrode 6, heat is released from the memory element even if the second electrode 6 is miniaturized in order to improve the performance and integration of the memory element. And damage to the memory element due to heat accumulation can be prevented. Therefore, the reliability of a semiconductor device including a nonvolatile memory including a memory element can be improved.

Further, according to the configuration of the present embodiment, since the first electrode 2 and the second electrode 6 are formed separately, the first electrode 2 and the second electrode 6 are made of different conductive materials. Can be formed.
For example, by forming the first electrode 2 using Cu having high thermal conductivity and forming the second electrode 6 using a material that improves the resistance change performance of the memory element, the heat dissipation and the characteristics of the memory element are achieved. It is possible to achieve both improvement.
For example, it is possible to reduce the manufacturing cost by forming the first electrode 2 using an inexpensive conductive material such as W or polysilicon (polycrystalline silicon).

<5. Fifth embodiment>
FIG. 13 shows a schematic configuration diagram (cross-sectional view) of a semiconductor device according to a fifth embodiment of the present invention.
In FIG. 13, as in FIG. 2A, the electrode portion of the semiconductor device is extracted and shown.
As shown in FIG. 13, the cross-sectional shape of the portion between the second interlayer insulating layers 5 in the second electrode 6 is a shape close to a semicircle.

Further, in the present embodiment, the thickness of the second interlayer insulating layer 5 is made thinner than those of the previous embodiments.
This is because, in the present embodiment, since the cross-sectional shape of the second electrode 6 spreads upward in the entire thickness direction of the second interlayer insulating layer 5, when the second interlayer insulating layer 5 is formed thick, This is because the diameter of the second electrode 6 is approximately the same as the diameter of the first electrode 2 or exceeds the diameter of the first electrode 2.
In the configuration in which the memory element is formed on the second electrode 6 and the electric field is concentrated on the resistance change layer of the memory element, the diameter of the second electrode 6 is smaller than the diameter of the first electrode 2 as shown in FIG. It is desirable to do.
When there is no problem even if the diameter of the second electrode 6 is approximately the same as the diameter of the first electrode 2 or exceeds the diameter of the first electrode 2, the thickness of the second interlayer insulating layer 5 is shown above. The thickness may be the same as the thickness of the second interlayer insulating layer 5 in each embodiment.

The other configuration is the same as that of the electrode portion of the first embodiment shown in FIG. 2A, and therefore, the same reference numerals are given and redundant description is omitted.
In the configuration of the electrode portion of the fifth embodiment, the configuration on the second electrode 6 can be the same as the configurations of the first to third embodiments. That is, the resistance change layer 7 and the wiring layer 14 of the memory element can be formed on the second electrode 6.

The semiconductor device of the present embodiment can be manufactured, for example, as described below.
From the state shown in FIG. 11, only the isotropic etching is performed on the insulating layer 21. Thereby, although not shown, the upper portion of the first electrode 2 is exposed, and the second interlayer insulating layer 5 recedes into a round shape.
Thereafter, an electrode material layer is formed so as to be directly in contact with the exposed portion of the first electrode 2 and embedded in the upper portion of the seam 4, and the electrode material layer on the second interlayer insulating layer 5 is further removed. Thus, the second electrode 6 made of the electrode material layer is formed. As a result, the second electrode 6 that expands toward the top can be formed in accordance with the second interlayer insulating layer 5 that has receded into a round shape, as shown in FIG.

According to the configuration of the present embodiment described above, the first electrode 2 is embedded in the upper portion of the seam 4 formed at the center of the upper surface of the first electrode 2, as in the first embodiment. The second electrode 6 is formed in self-alignment with the seam 4.
Thereby, in the 1st electrode 2 and the 2nd electrode 6, position misalignment does not arise and the connection failure resulting from misalignment can be prevented.

In addition, since the second electrode 6 is formed by being embedded in the upper part of the seam 4 formed in the central portion of the first electrode 2, the diameter of the second electrode 6 corresponds to the diameter of the seam 4. It is smaller than the diameter of one electrode 2.
Thereby, compared with the structure which formed the resistance change layer and the wiring layer directly on the 1st electrode 2, the contact area of the 2nd electrode 6 and a resistance change layer and a wiring layer can be made small.
When the resistance change layer of the memory element is formed on the second electrode 6, the electric field and current can be more concentrated in the resistance change layer, and the performance of the memory element including the resistance change layer can be improved. . In addition, the degree of integration of the storage elements can be increased to reduce the size of the memory and increase the storage capacity.
When a wiring layer is formed on the second electrode 6, the area of the electrode in contact with the wiring layer can be reduced, so that the wiring layer can be miniaturized and the degree of integration of the semiconductor device can be increased.

Even if the diameter of the first electrode 2 is reduced to the limit of lithography, the diameter of the second electrode 6 can be made smaller than the limit of lithography.
On the other hand, since the diameter of the first electrode 2 is larger than the diameter of the second electrode 6, the heat capacity of the first electrode 2 is larger than the heat capacity of the second electrode 6. As a result, when the resistance change layer of the memory element is formed on the second electrode 6, heat is released from the memory element even if the second electrode 6 is miniaturized in order to improve the performance and integration of the memory element. And damage to the memory element due to heat accumulation can be prevented. Therefore, the reliability of a semiconductor device including a nonvolatile memory including a memory element can be improved.

Further, according to the configuration of the present embodiment, since the first electrode 2 and the second electrode 6 are formed separately, the first electrode 2 and the second electrode 6 are made of different conductive materials. Can be formed.
For example, by forming the first electrode 2 using Cu having high thermal conductivity and forming the second electrode 6 using a material that improves the resistance change performance of the memory element, the heat dissipation and the characteristics of the memory element are achieved. It is possible to achieve both improvement.
For example, it is possible to reduce the manufacturing cost by forming the first electrode 2 using an inexpensive conductive material such as W or polysilicon (polycrystalline silicon).

In each of the above-described embodiments, the second electrode 6 is embedded only in the upper part of the seam 4.
On the other hand, in the present invention, the seam formed at the center of the first electrode may be filled with the electrode material of the second electrode.
It is possible to fill the seam by selecting the material for the second electrode and the method for forming the electrode material layer to be the second electrode.
An embodiment of this configuration is shown below.

<6. Sixth Embodiment>
FIG. 14 shows a schematic configuration diagram (cross-sectional view) of a sixth embodiment of the semiconductor device of the present invention.
In FIG. 14, as in FIG. 2A, an electrode portion of the semiconductor device is extracted and shown.
As shown in FIG. 14, the second electrode 6 completely fills the seam formed at the center of the first electrode 2. Thereby, the second electrode 6 filling the seam is formed in self-alignment with the seam of the first electrode 2.
Further, there is no insulating film 3 between the second electrode 6 and the first electrode 2 above the first electrode 2, and the second electrode 6 and the first electrode 2 are in direct contact with each other as in the previous embodiment. These electrodes 6 and 2 are electrically connected.

The other configuration is the same as that of the electrode portion of the first embodiment shown in FIG. 2A, and therefore, the same reference numerals are given and redundant description is omitted.
Further, in the configuration of the electrode portion of the sixth embodiment, the configuration on the second electrode 6 can be the same as that of each of the first to third embodiments. That is, the resistance change layer 7 and the wiring layer 14 of the memory element can be formed on the second electrode 6.

The semiconductor device of the present embodiment can be manufactured, for example, as described below.
When the electrode material layer to be the second electrode 6 is formed from the state shown in FIG. 5, the seam 4 at the center of the first electrode 2 is selected by selecting the material of the electrode material layer or the film forming method. Filled to form an electrode material layer.
Thereby, as shown in FIG. 14, the second electrode 6 can be formed so as to completely fill the seam 4 and to be in direct contact with the upper portion of the first electrode 2.

According to the configuration of the present embodiment described above, the second electrode 6 is embedded in the seam formed at the center of the upper surface of the first electrode 2 and is self-aligned with the seam of the first electrode 2. Is formed.
Thereby, in the 1st electrode 2 and the 2nd electrode 6, position misalignment does not arise and the connection failure resulting from misalignment can be prevented.

In addition, since the second electrode 6 is formed by being embedded in a seam formed in the central portion of the first electrode 2, the diameter of the second electrode 6 corresponds to the diameter of the seam. It is smaller than the diameter.
Thereby, compared with the structure which formed the resistance change layer and the wiring layer directly on the 1st electrode 2, the contact area of the 2nd electrode 6 and a resistance change layer and a wiring layer can be made small.
When the resistance change layer of the memory element is formed on the second electrode 6, the electric field and current can be more concentrated in the resistance change layer, and the performance of the memory element including the resistance change layer can be improved. . In addition, the degree of integration of the storage elements can be increased to reduce the size of the memory and increase the storage capacity.
When a wiring layer is formed on the second electrode 6, the area of the electrode in contact with the wiring layer can be reduced, so that the wiring layer can be miniaturized and the degree of integration of the semiconductor device can be increased.

Even if the diameter of the first electrode 2 is reduced to the limit of lithography, the diameter of the second electrode 6 can be made smaller than the limit of lithography.
On the other hand, since the diameter of the first electrode 2 is larger than the diameter of the second electrode 6, the heat capacity of the first electrode 2 is larger than the heat capacity of the second electrode 6. As a result, when the resistance change layer of the memory element is formed on the second electrode 6, heat is released from the memory element even if the second electrode 6 is miniaturized in order to improve the performance and integration of the memory element. And damage to the memory element due to heat accumulation can be prevented. Therefore, the reliability of a semiconductor device including a nonvolatile memory including a memory element can be improved.

Further, according to the configuration of the present embodiment, since the first electrode 2 and the second electrode 6 are formed separately, the first electrode 2 and the second electrode 6 are made of different conductive materials. Can be formed.
For example, by forming the first electrode 2 using Cu having high thermal conductivity and forming the second electrode 6 using a material that improves the resistance change performance of the memory element, the heat dissipation and the characteristics of the memory element are achieved. It is possible to achieve both improvement.
For example, it is possible to reduce the manufacturing cost by forming the first electrode 2 using an inexpensive conductive material such as W or polysilicon (polycrystalline silicon).

  Further, according to the configuration of the present embodiment, since the seam is completely filled with the second electrode 6, the configuration in which the second electrode 6 is embedded in a part of the seam as in each of the embodiments described above, In comparison, the volume of the second electrode 6 embedded in the seam can be greatly increased. Thereby, the effect of further improving the heat dissipation effect of unnecessary heat can be expected.

<7. Seventh Embodiment>
FIG. 15 shows a schematic configuration diagram (cross-sectional view) of a seventh embodiment of the semiconductor device of the present invention.
In FIG. 15, as in FIG. 2A, the electrode portion of the semiconductor device is extracted and shown.
As shown in FIG. 15, the second electrode 6 completely fills the seam formed at the center of the first electrode 2. Furthermore, there is no insulating film 3 between the second electrode 6 and the first electrode 2 that existed in the previous embodiment, and the second electrode 6 inside the first electrode 2 is entirely the first electrode 2. Is in direct contact with.
Further, the portion of the second electrode 6 between the upper portions of the second interlayer insulating layers 5 is between the lower portions of the second interlayer insulating layers 5 as in the configuration of the fourth embodiment shown in FIG. It is wider than the part.

The other configuration is the same as that of the sixth embodiment shown in FIG.
Further, in the configuration of the electrode portion of the seventh embodiment, the configuration on the second electrode 6 can be the same as that of each of the first to third embodiments. That is, the resistance change layer 7 and the wiring layer 14 of the memory element can be formed on the second electrode 6.

The semiconductor device of the present embodiment can be manufactured, for example, as described below.
From the state shown in FIG. 11, isotropic etching such as wet etching and anisotropic etching are combined with the insulating layer 21. At this time, the insulating film 3 remaining on the side wall of the seam 4 shown in FIG. 12 can be removed by selecting the etching conditions. Thereby, the 1st electrode 2 is exposed in the whole side wall of a seam.
Thereafter, when the electrode material layer to be the second electrode 6 is formed, the material of the electrode material layer or the film forming method is selected to fill the seam 4 at the center of the first electrode 2, thereby forming the electrode material layer. Form.
Thereby, as shown in FIG. 15, the second electrode 6 can be formed so as to completely fill the seam 4 and to be in direct contact with the first electrode 2.

According to the configuration of the present embodiment described above, the second electrode 6 is embedded in the seam formed at the center of the upper surface of the first electrode 2 and is self-aligned with the seam of the first electrode 2. Is formed.
Thereby, in the 1st electrode 2 and the 2nd electrode 6, position misalignment does not arise and the connection failure resulting from misalignment can be prevented.

In addition, since the second electrode 6 is formed by being embedded in a seam formed in the central portion of the first electrode 2, the diameter of the second electrode 6 corresponds to the diameter of the seam. It is smaller than the diameter.
Thereby, compared with the structure which formed the resistance change layer and the wiring layer directly on the 1st electrode 2, the contact area of the 2nd electrode 6 and a resistance change layer and a wiring layer can be made small.
When the resistance change layer of the memory element is formed on the second electrode 6, the electric field and current can be more concentrated in the resistance change layer, and the performance of the memory element including the resistance change layer can be improved. . In addition, the degree of integration of the storage elements can be increased to reduce the size of the memory and increase the storage capacity.
When a wiring layer is formed on the second electrode 6, the area of the electrode in contact with the wiring layer can be reduced, so that the wiring layer can be miniaturized and the degree of integration of the semiconductor device can be increased.

Even if the diameter of the first electrode 2 is reduced to the limit of lithography, the diameter of the second electrode 6 can be made smaller than the limit of lithography.
On the other hand, since the diameter of the first electrode 2 is larger than the diameter of the second electrode 6, the heat capacity of the first electrode 2 is larger than the heat capacity of the second electrode 6. As a result, when the resistance change layer of the memory element is formed on the second electrode 6, heat is released from the memory element even if the second electrode 6 is miniaturized in order to improve the performance and integration of the memory element. And damage to the memory element due to heat accumulation can be prevented. Therefore, the reliability of a semiconductor device including a nonvolatile memory including a memory element can be improved.

Further, according to the configuration of the present embodiment, since the first electrode 2 and the second electrode 6 are formed separately, the first electrode 2 and the second electrode 6 are made of different conductive materials. Can be formed.
For example, by forming the first electrode 2 using Cu having high thermal conductivity and forming the second electrode 6 using a material that improves the resistance change performance of the memory element, the heat dissipation and the characteristics of the memory element are achieved. It is possible to achieve both improvement.
For example, it is possible to reduce the manufacturing cost by forming the first electrode 2 using an inexpensive conductive material such as W or polysilicon (polycrystalline silicon).

  Furthermore, according to the configuration of the present embodiment, the seam is completely filled with the second electrode 6, and the insulating film 3 on the side wall of the seam in FIG. 2A is absent. For this reason, the volume of the second electrode 6 embedded in the seam can be significantly increased, and the contact area between the second electrode 6 and the second electrode can be greatly increased. Thereby, the effect of further reducing the contact resistance between the first electrode and the second electrode and further improving the heat dissipation effect of unnecessary heat can be expected.

<8. Eighth Embodiment>
FIG. 16 shows a schematic configuration diagram (cross-sectional view) of an eighth embodiment of the semiconductor device of the present invention.
In FIG. 16, as in FIG. 2A, the electrode portion of the semiconductor device is extracted and shown.
As shown in FIG. 16, the second electrode 6 completely fills the seam formed at the center of the first electrode 2.
Similarly to the seventh embodiment shown in FIG. 15, the second electrodes 6 inside the first electrode 2 are all in direct contact with the first electrode 2.
Further, in the second electrode, the portion between the second interlayer insulating layers 5 has a semicircular shape in which the cross-sectional shape expands upward as in the configuration of the fifth embodiment shown in FIG. It has become.

Other configurations are the same as the configuration of the fifth embodiment shown in FIG. 13 and the configuration of the seventh embodiment shown in FIG.
Further, in the configuration of the electrode portion of the eighth embodiment, the configuration on the second electrode 6 can be the same as that of each of the first to third embodiments. That is, the resistance change layer 7 and the wiring layer 14 of the memory element can be formed on the second electrode 6.

  When there is no problem even if the diameter of the second electrode 6 is approximately the same as the diameter of the first electrode 2 or exceeds the diameter of the first electrode 2, the thickness of the second interlayer insulating layer 5 is set to the first to first thicknesses. 4. It may be the same as the thickness of the second interlayer insulating layer 5 in each of the sixth to seventh embodiments.

The semiconductor device of the present embodiment can be manufactured, for example, as described below.
From the state shown in FIG. 11, only the isotropic etching is performed on the insulating layer 21. Thereby, although not shown, the upper portion of the first electrode 2 is exposed, and the second interlayer insulating layer 5 recedes into a round shape. At this time, it is possible to remove the insulating film 3 remaining on the side wall of the seam 4 shown in FIG. 12 by selecting isotropic etching conditions. Thereby, the 1st electrode 2 is exposed in the whole side wall of a seam.
Thereafter, when the electrode material layer to be the second electrode 6 is formed, the material of the electrode material layer or the film forming method is selected to fill the seam 4 at the center of the first electrode 2, thereby forming the electrode material layer. Form.
As a result, the second electrode 6 that spreads toward the top can be formed in accordance with the second interlayer insulating layer 5 that has receded into a round shape, as shown in FIG.

According to the configuration of the present embodiment described above, the second electrode 6 is embedded in the seam formed at the center of the upper surface of the first electrode 2 and is self-aligned with the seam of the first electrode 2. Is formed.
Thereby, in the 1st electrode 2 and the 2nd electrode 6, position misalignment does not arise and the connection failure resulting from misalignment can be prevented.

In addition, since the second electrode 6 is formed by being embedded in a seam formed in the central portion of the first electrode 2, the diameter of the second electrode 6 corresponds to the diameter of the seam. It is smaller than the diameter.
Thereby, compared with the structure which formed the resistance change layer and the wiring layer directly on the 1st electrode 2, the contact area of the 2nd electrode 6 and a resistance change layer and a wiring layer can be made small.
When the resistance change layer of the memory element is formed on the second electrode 6, the electric field and current can be more concentrated in the resistance change layer, and the performance of the memory element including the resistance change layer can be improved. . In addition, the degree of integration of the storage elements can be increased to reduce the size of the memory and increase the storage capacity.
When a wiring layer is formed on the second electrode 6, the area of the electrode in contact with the wiring layer can be reduced, so that the wiring layer can be miniaturized and the degree of integration of the semiconductor device can be increased.

Even if the diameter of the first electrode 2 is reduced to the limit of lithography, the diameter of the second electrode 6 can be made smaller than the limit of lithography.
On the other hand, since the diameter of the first electrode 2 is larger than the diameter of the second electrode 6, the heat capacity of the first electrode 2 is larger than the heat capacity of the second electrode 6. As a result, when the resistance change layer of the memory element is formed on the second electrode 6, heat is released from the memory element even if the second electrode 6 is miniaturized in order to improve the performance and integration of the memory element. And damage to the memory element due to heat accumulation can be prevented. Therefore, the reliability of a semiconductor device including a nonvolatile memory including a memory element can be improved.

Further, according to the configuration of the present embodiment, since the first electrode 2 and the second electrode 6 are formed separately, the first electrode 2 and the second electrode 6 are made of different conductive materials. Can be formed.
For example, by forming the first electrode 2 using Cu having high thermal conductivity and forming the second electrode 6 using a material that improves the resistance change performance of the memory element, the heat dissipation and the characteristics of the memory element are achieved. It is possible to achieve both improvement.
For example, it is possible to reduce the manufacturing cost by forming the first electrode 2 using an inexpensive conductive material such as W or polysilicon (polycrystalline silicon).

  Furthermore, according to the configuration of the present embodiment, the seam is completely filled with the second electrode 6, and the insulating film 3 on the side wall of the seam in FIG. 2A is absent. For this reason, the volume of the second electrode 6 embedded in the seam can be significantly increased, and the contact area between the second electrode 6 and the second electrode can be greatly increased. Thereby, the effect of further reducing the contact resistance between the first electrode and the second electrode and further improving the heat dissipation effect of unnecessary heat can be expected.

<9. Ninth Embodiment>
FIG. 17 shows a schematic configuration diagram (cross-sectional view) of a ninth embodiment of the semiconductor device of the present invention.
In FIG. 17, as in FIG. 2A, the electrode portion of the semiconductor device is extracted and shown.
As shown in FIG. 17, a hole 9 is formed in a cylindrical shape in the center of the first electrode 2, and a recess is formed in the center of the upper surface of the first electrode 2 by the hole 9. Further, the outer wall and the inner wall of the first electrode 2 are substantially parallel, and the first electrode 2 is formed in a cylindrical shape.
The second electrode 6 is formed by being partially embedded in the hole 9.
An insulating film 3 is formed on the inner wall of the first electrode 2, but since the insulating film 3 is not formed on the upper portion of the first electrode 2, the first electrode 2 is in direct contact with the second electrode 6. .

By using a material with good coverage such as Ti or TiN as the electrode material of the first electrode 2, the inner wall of the first electrode 2 can be formed in the cylindrical shape shown in FIG.
Also at this time, since the hole 9 is naturally formed in the central portion of the first electrode 2 as in the case of the seam (hole) 4 of the first embodiment, the manufacturing method of the first embodiment By the same manufacturing method, the second electrode 6 can be formed in a self-aligned manner with respect to the holes 9 of the first electrode 2.

The other configuration is the same as that of the electrode portion of the first embodiment shown in FIG. 2A, and therefore, the same reference numerals are given and redundant description is omitted.
Further, in the configuration of the electrode portion of the ninth embodiment, the configuration on the second electrode 6 can be the same as that of each of the first to third embodiments. That is, the resistance change layer 7 and the wiring layer 14 of the memory element can be formed on the second electrode 6.

According to the above-described configuration of the present embodiment, the first electrode 2 is embedded in the upper portion of the hole 9 formed in the center of the upper surface and is self-aligned with the hole 9 of the first electrode 2. The second electrode 6 is formed.
Thereby, in the 1st electrode 2 and the 2nd electrode 6, position misalignment does not arise and the connection failure resulting from misalignment can be prevented.

Further, according to the configuration of the present embodiment, since the first electrode 2 and the second electrode 6 are formed separately, the first electrode 2 and the second electrode 6 are made of different conductive materials. Can be formed.
For example, by forming the first electrode 2 using Cu having high thermal conductivity and forming the second electrode 6 using a material that improves the resistance change performance of the memory element, the heat dissipation and the characteristics of the memory element are achieved. It is possible to achieve both improvement.
For example, it is possible to reduce the manufacturing cost by forming the first electrode 2 using an inexpensive conductive material such as W or polysilicon (polycrystalline silicon).

  Furthermore, the configuration of the present embodiment is effective when the diameter of the via hole formed in the interlayer insulating layer has been miniaturized, and the variation in the dimensions of the second electrode 6 and the like is reduced as compared with the method using the seam. The effect that can be suppressed can be expected.

<10. Tenth Embodiment>
FIG. 18 shows a schematic configuration diagram (cross-sectional view) of the tenth embodiment of the semiconductor device of the present invention.
In FIG. 18, as in FIG. 2A, the electrode portion of the semiconductor device is extracted and shown.
As shown in FIG. 18, a hole 9 is formed in the central portion of the first electrode 2 so as to penetrate the top and bottom of the first electrode. Is formed. Further, the cylindrical first electrode 2 is formed so that the thickness thereof becomes thinner toward the upper surface.
The second electrode 6 is formed by being partially embedded in a hole 9 formed in the central portion of the first electrode 2.
An insulating film 3 is formed on the inner wall of the first electrode 2, but since the insulating film 3 is not formed on the upper portion of the first electrode 2, the first electrode 2 is in direct contact with the second electrode 6. .

  After the electrode material layer of the first electrode 2 is formed, anisotropic etching is used so that the first electrode 2 becomes thinner toward the top, like a sidewall with respect to the first interlayer insulating layer 1. Can be formed.

  The diameter of the hole 9 can be adjusted by forming the first electrode 2 like a sidewall by anisotropic etching and then cutting it in the depth direction using a planarization technique such as CMP. is there.

Other configurations are the same as those of the first embodiment shown in FIG.
In the configuration of the electrode portion of the tenth embodiment, the configuration on the second electrode 6 can be the same as the configurations of the first to third embodiments. That is, the resistance change layer 7 and the wiring layer 14 of the memory element can be formed on the second electrode 6.

According to the above-described configuration of the present embodiment, the first electrode 2 is embedded in the upper portion of the hole 9 formed in the center of the upper surface and is self-aligned with the hole 9 of the first electrode 2. The second electrode 6 is formed.
Thereby, in the 1st electrode 2 and the 2nd electrode 6, position misalignment does not arise and the connection failure resulting from misalignment can be prevented.

Further, according to the configuration of the present embodiment, since the first electrode 2 and the second electrode 6 are formed separately, the first electrode 2 and the second electrode 6 are made of different conductive materials. Can be formed.
For example, by forming the first electrode 2 using Cu having high thermal conductivity and forming the second electrode 6 using a material that improves the resistance change performance of the memory element, the heat dissipation and the characteristics of the memory element are achieved. It is possible to achieve both improvement.
For example, it is possible to reduce the manufacturing cost by forming the first electrode 2 using an inexpensive conductive material such as W or polysilicon (polycrystalline silicon).

  Furthermore, the configuration of the present embodiment is effective in the case of a fine structure in which the diameter of the hole 9 above the first electrode 2 cannot be sufficiently secured.

<11. Eleventh embodiment>
A schematic configuration diagram of an eleventh embodiment of a semiconductor device of the present invention is shown in FIGS. 19A and 19B. FIG. 19A shows a cross-sectional view, and FIG. 19B shows a plan view of the electrode portion.
FIG. 19A shows an extracted electrode portion of the semiconductor device, as in FIG. 2A.
In the present embodiment, as shown in FIG. 19B, the first electrode 2 and the second electrode 6 are formed in an elliptical shape when viewed from above.
Accordingly, as shown in the plan view of FIG. 20, the first electrode 2 and the second electrode 6 can be arranged at a short interval in the lateral direction, so that a memory element is formed particularly on these electrodes 2 and 6. In this case, the degree of integration of memory cells can be increased.

The other configuration is the same as that of the first embodiment shown in FIG.
In the configuration of the electrode portion of the eleventh embodiment, the configuration on the second electrode 6 can be the same as that of each of the first to third embodiments. That is, the resistance change layer 7 and the wiring layer 14 of the memory element can be formed on the second electrode 6.

When manufacturing the configuration of the present embodiment, an elliptical via hole is formed in the first interlayer insulating layer 1 and the first electrode 2 is formed in an elliptical shape. Thereby, the seam (hole) 4 becomes substantially elliptical, and the second electrode 6 can be formed elliptically.
Thus, by making the second electrode 6 elliptical, for example, when applied to a memory cell array, it is possible to secure a contact area and a heat radiation volume while preventing a short circuit between the second electrodes 6 of adjacent memory cells. The effect can be expected.

For example, when the electrode structure in the present invention is applied to a semiconductor device including a variable resistance nonvolatile memory, an effect of improving performance can be expected.
However, when the electrode structure according to the present invention is applied to other peripheral circuit elements such as transistors formed on the same substrate as the memory element of the nonvolatile memory, the element performance decreases with increasing contact resistance. Concerned.
A configuration that solves this problem is shown below.

<12. Twelfth Embodiment>
FIG. 21 shows a schematic configuration diagram (cross-sectional view) of the twelfth embodiment of the semiconductor device of the present invention.
FIG. 21 shows an extracted electrode portion of the semiconductor device.
As shown in FIG. 21, in the memory cell part 31 forming the memory element, the configuration of the second electrode 6 is the same as that in FIG. 1A. On the other hand, in the peripheral circuit portion 32 where no memory element is formed, the second electrode 6 is removed from the second electrode 6 above the first electrode 2 except for the portion embedded in the seam 4.

  In addition, in the configuration of the electrode portion of the twelfth embodiment, the configuration on the second electrode 6 of the memory cell unit 31 can be the same as that of the first to second embodiments. is there. That is, the resistance change layer 7 of the memory element can be formed on the second electrode 6.

In order to manufacture this structure, the second interlayer insulating layer 5 on the first electrode 2 and the second electrode 6 above the first electrode 2 may be removed by the photolithography in the peripheral circuit portion 32. .
In the case where the resistance change layer 7 of the memory element is formed on the second electrode 6, after the resistance change layer 7 is formed, the resistance change layer 7 of the memory cell unit 31 is covered with a mask, and the peripheral circuit is formed. The resistance change layer 7 of the portion 32, the second electrode 6 and the second interlayer insulating layer 5 above the first electrode 2 are removed.
In this way, the electrode structure generally used in a semiconductor device and the electrode structure according to the present invention can be separately produced in the same semiconductor device.

According to the present embodiment, all the second electrodes are left in the memory cell portion 31, and the second interlayer insulating layer on the first electrode 2 and the second electrode 6 above the first electrode 2 are left in the peripheral circuit portion 32. And remove.
Thereby, in the peripheral circuit part 32, the exposed first electrode 2 can be connected to the upper layer, and a sufficiently large contact area is ensured between the upper surface of the first electrode 2 and the upper surface of the second electrode 6, thereby making contact. Resistance can be reduced.

In each of the above-described embodiments, the first electrode 2 and the second electrode 6 are configured such that the shape of the horizontal cross section is a circle or an ellipse. And the diameter of the 1st electrode 2 and the diameter of the 2nd electrode 6 were compared.
In the present invention, the shapes of the horizontal cross sections of the first electrode and the second electrode are not limited to these shapes, and other shapes are possible. For example, a rectangular shape (square or rectangular shape) or a shape with rounded corners of the rectangle may be used.
In consideration of other shapes, by making the area of the upper surface of the second electrode smaller than the area of the upper surface of the first electrode, the diameter of the second electrode is made larger than the diameter of the first electrode in a circular or elliptical cross-sectional shape. Similar effects can be obtained with the reduced configuration.

In the present invention, the electrode materials of the first electrode and the second electrode are not limited to the materials described above.
For example, the same material or different metal materials selected from Ti, TiN, W, WN, Cu, Ta, and Pt can be used for the first electrode and the second electrode.

  The present invention is not limited to the above-described embodiment, and various other configurations can be taken without departing from the gist of the present invention.

DESCRIPTION OF SYMBOLS 1 1st interlayer insulation layer, 2 1st electrode, 3 insulation film, 4 seam (vacancy), 5 2nd interlayer insulation layer, 6 2nd electrode, 7 Resistance change layer, 8 Upper electrode, 9 Hole, 11 Memory Layer, 12 ion source layer, 13 metal oxide layer, 14 wiring layer, 21 insulating layer, 22 electrode material layer, 31 memory cell part, 32 peripheral circuit part

Claims (19)

A first electrode having a recess formed in the center of the upper surface;
A semiconductor device comprising: a second electrode embedded in at least a part of the recess and formed in self-alignment with the recess of the first electrode.   2. The semiconductor device according to claim 1, wherein an area of an upper surface of the second electrode is smaller than an area of an upper surface of the first electrode.   The semiconductor device according to claim 1, wherein the recess of the first electrode is a hole generated when the electrode material of the first electrode is embedded.   The semiconductor device according to claim 1, wherein the recess is formed so as to penetrate above and below the first electrode, and the thickness of the first electrode is formed so as to be thinner toward an upper surface.   The semiconductor device according to claim 1, wherein the first electrode is formed in a cylindrical shape in which an outer wall and an inner wall are parallel.   The semiconductor device according to claim 1, wherein the first electrode and the second electrode use a metal material selected from Ti, TiN, W, WN, Cu, Ta, and Pt.   The semiconductor device according to claim 1, wherein the electrode material of the first electrode and the electrode material of the second electrode are different materials.   The semiconductor device according to claim 1, wherein an electrode material of the first electrode and an electrode material of the second electrode are the same material. A first electrode having a recess formed in the center of the upper surface;
A second electrode embedded in at least a portion of the recess and formed in self-alignment with the recess of the first electrode;
A semiconductor device comprising: a resistance change layer that is formed in contact with the second electrode, the resistance value of which changes when a voltage is applied, constitutes a resistance change type memory element.   The semiconductor device according to claim 9, wherein an area of an upper surface of the second electrode is smaller than an area of an upper surface of the first electrode.   The semiconductor device according to claim 9, wherein the recess of the first electrode is a hole generated when the electrode material of the first electrode is embedded.   10. The semiconductor device according to claim 9, wherein the recess is formed so as to penetrate above and below the first electrode, and the thickness of the first electrode is increased toward the upper surface.   The semiconductor device according to claim 9, wherein the first electrode is formed in a cylindrical shape in which an outer wall and an inner wall are parallel.   The semiconductor device according to claim 9, wherein the first electrode and the second electrode use a metal material selected from Ti, TiN, W, WN, Cu, Ta, and Pt.   The semiconductor device according to claim 9, wherein the electrode material of the first electrode and the electrode material of the second electrode are different materials.   The semiconductor device according to claim 9, wherein planar shapes of the first electrode and the second electrode are elliptical. A step of embedding an electrode material into a via hole formed in the interlayer insulating layer so that a recess is formed in the center, and forming a first electrode embedded in the via hole;
Forming an insulating layer on the first electrode;
Exposing at least an upper portion of the first electrode on the side wall of the recess by etching;
Forming an electrode material layer so as to fill at least part of the recess and directly contact the exposed first electrode;
Forming a second electrode made of an electrode material layer by removing the electrode material layer on the insulating layer. A step of embedding an electrode material into a via hole formed in the interlayer insulating layer so that a recess is formed in the center, and forming a first electrode embedded in the via hole;
Forming an insulating layer on the first electrode;
Exposing at least an upper portion of the first electrode on the side wall of the recess by etching;
Forming an electrode material layer so as to fill at least part of the recess and directly contact the exposed first electrode;
Forming a second electrode comprising an electrode material layer by removing the electrode material layer on the insulating layer;
Forming a resistance change layer which is in contact with the second electrode and changes its resistance value by applying a voltage to form a resistance change type memory element. A method for manufacturing a semiconductor device.   In the memory cell portion including the memory element, the resistance change layer is covered with a mask, and in the peripheral circuit portion not including the memory element, the resistance change layer and the second electrode above the first electrode are provided. The method of manufacturing a semiconductor device according to claim 18, further comprising a step of removing the electrode to expose the first electrode.

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