JP2012033910A - Porous insulator and field effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a new insulator usable also, for example, as a gate insulator of a field effect transistor with an active layer of strontium titanate.SOLUTION: A porous insulator comprises a plurality of pores of 5 to 100 nm in diameter in an insulating material. The porosity, a ratio of a volume occupied by the pores to the whole volume, is 20 vol.% or higher. The pores contain water. A volumetric water content, a ration of the volume of the water to the volume of the pores is 23 to 100 vol.%.

Description

  The present invention relates to a porous insulator and a field effect transistor.

Strontium titanate (SrTiO ₃ ) is a composite oxide of strontium and titanium, and is known as a transparent insulator. This material is preferably used as a dielectric of a ceramic capacitor because it exhibits a high dielectric constant and the temperature change of the dielectric constant is small. In recent years, it has been found that strontium titanate is easily converted into a semiconductor by being doped with a metal such as niobium, and its use as a semiconductor material such as a varistor has been proposed (for example, Patent Document 1). See).

On the other hand, the use of strontium titanate, which is an insulator, as an active layer of a field effect transistor has also been studied. For example, Non-Patent Document 1 proposes a field effect transistor in which 12CaO · 7Al ₂ O ₃ glass is formed as a gate insulator on the surface of a single crystal of strontium titanate. This transistor induces a thermoelectromotive force between a source and a drain when a gate voltage is applied. In this transistor, 12CaO · 7Al ₂ O ₃ glass used as a gate insulating film is formed as a uniform and dense amorphous film.

  Non-Patent Document 2 proposes an electric double layer transistor in which a gate electrode is formed on the surface of a single crystal of strontium titanate via an electrolyte. In this transistor, an electric double layer is formed at the interface between the electrolyte and strontium titanate when a gate voltage is applied. By such an action, conduction carriers are induced at a high density on the surface of the single crystal of strontium titanate, and the surface of strontium titanate, which was an insulator, becomes conductive.

JP-A-4-31357

Ohta, H .; Masuoka, Y .; Asahi, R .; , Kato, T .; , Ikuhara, Y .; Nomura, K .; , & Hosono, H. Field-modulated thermopower in SrTiO3-based field-effect transducers with amorphous 12CaO.7Al2O3 glass gate insulator, Appl., Field-modulated thermopower in SrTiO3-based field-effect transducers. Phys. Lett. 95, 113505 (2009). Ueno, K .; Nakamura, S .; Shimotani, H .; , Ohtomo, A .; Kimura, N .; Nojima, T .; Aoki, H .; Iwasa, Y .; , & Kawasaki, M .; , Nature Mater. 7, 855-858 (2008).

  The electric double layer transistor described in Non-Patent Document 2 can make a resistance value between a source and a drain a conductive state of 100 kΩ or less while using strontium titanate, which is an insulator, as an active layer. Use as a semiconductor device is expected. However, the electrolyte used as a gate insulator in this electric double layer transistor is liquid at room temperature and is organic, so it is flammable and may ignite at temperatures above room temperature. Therefore, further study is necessary to use this transistor as a practical device.

  The present invention has been made in view of the above situation, and provides a novel insulator that can be used as a gate insulator of a field effect transistor using, for example, strontium titanate as an active layer. For the purpose. Another object of the present invention is to provide a novel thermoelectric conversion material in which the active layer and the insulator are combined in a different aspect from the above.

  The present inventors have found that a porous insulator having a plurality of fine pores having a diameter of 5 to 100 nm in a material exhibiting insulating properties and containing a predetermined amount of moisture exhibits unique electrical characteristics, The present invention has been completed. In addition, the inventors of the present invention have surprisingly found that a field effect transistor having a porous insulator as a gate insulator and a metal oxide such as strontium titanate as an active layer is provided with a non-porous insulator. It has been found that the thermoelectric conversion efficiency is higher than that of the effect transistor.

  The first aspect of the present invention has a plurality of pores having a diameter of 5 to 100 nm in an insulating material, and the porosity, which is the ratio of the volume occupied by the pores to the entire volume, is 20% by volume. In the porous insulator, moisture is contained in the pores, and a moisture occupancy ratio, which is a ratio of the volume occupied by the moisture to the pore volume, is 23 to 100% by volume.

  Moreover, the 2nd aspect of this invention is a field effect transistor which uses the said porous insulator as a gate insulator.

  Moreover, the 3rd aspect of this invention is the thermoelectric conversion material formed by joining the said porous insulator and the active layer which consists of metal oxides.

  According to the present invention, for example, a novel insulator that can be used as a gate insulator of a field effect transistor using strontium titanate as an active layer is provided. Moreover, according to this invention, the novel thermoelectric conversion material which combined the said active layer and the said insulator is provided.

It is a perspective view which shows one Embodiment of the porous insulator of this invention. It is a perspective view which shows one Embodiment of the field effect transistor in which the porous insulator of this invention was used as a gate insulator. It is a perspective view which shows the field effect transistor produced in Examples 1-3 and Comparative Example 1. FIG. (A) is the graph which plotted the drain current Id with respect to the gate voltage Vg in the field effect transistor of Example 2. FIG. (B) is the graph which plotted the gate current Ig with respect to the gate voltage Vg in the field effect transistor of Example 2. FIG. (C) is the graph which plotted the gate capacity with respect to the gate voltage Vg in the field effect transistor of Example 2. FIG. (D) is the graph which plotted the drain current Id with respect to the gate voltage Vg in the field effect transistor of the comparative example 1. FIG. (E) is the graph which plotted the gate current Ig with respect to the gate voltage Vg in the field effect transistor of the comparative example 1. FIG. (F) is the graph which plotted the gate capacity with respect to the gate voltage Vg in the field effect transistor of the comparative example 1. FIG. (A) is the graph which plotted the drain current Id with respect to the gate voltage Vg of the field effect transistor of Example 2 in 25 degreeC. (B) is the graph which plotted the drain current Id with respect to the gate voltage Vg of the field effect transistor of Example 2 in 0 degreeC. (A) is a plot of Seebeck coefficient (thermoelectric power) against gate voltage (V _g ). (B) is a plot of the sheet electron concentration of the transistor channel against the gate voltage (V _g ). (C) And (d) is a plot of the gate voltage application time dependence of thermoelectric power and sheet electron concentration. It is a plot which shows the sheet electron concentration dependence of the thermoelectric power in room temperature about the field effect transistor provided with the porous gate insulator, and the field effect transistor provided with the precise | minute gate insulator.

  Hereinafter, an embodiment of the porous insulator of the present invention will be described with reference to the drawings. FIG. 1 is a perspective view showing an embodiment of the porous insulator of the present invention. In FIG. 1, a part of the porous insulator 1 is cut out so that the internal structure of the porous insulator 1 becomes clear.

  The porous insulator 1 is formed by forming a plurality of pores 3 in an insulating material 2. The holes 3 are formed on the surface and inside of the porous insulator 1 and have a fine structure called a nanopore. The diameter of the air holes 3 is 5 to 100 nm, more preferably 5 to 50 nm, and further preferably 5 to 20 nm. Examples of the shape of the holes 3 include a spherical shape, but are not particularly limited.

The insulating material 2 is a material exhibiting insulating properties, and an oxide insulator is preferably exemplified. Examples of such oxide insulators include 12CaO · 7Al ₂ O ₃ , CaO, Al ₂ O ₃ , 12SrO · 7Al ₂ O ₃ , Y ₂ O ₃ , HfO ₂ , SiO ₂ , MgO, LaAlO ₃ , ZrO ₂ , Examples are MgAl ₂ O ₄ , Nb ₂ O ₅ , Ta ₂ O ₅ , Si ₃ N ₄ , SrTiO ₃ , BaTiO ₃ , CaTiO ₃ , SrZrO ₃ , CaZrO ₃ , and BaZrO ₃ . The insulating material 2 can include one or more of these insulating materials.

  Since a plurality of holes 3 are formed on the surface and inside of the porous insulator 1, the total volume of all the holes 3 occupies a part of the entire volume of the porous insulator 1. Here, the ratio of the total volume of all the pores 3 to the total volume of the porous insulator 1 is called the porosity. In the porous insulator 1 of the present embodiment, this porosity is 20% by volume or more. That is, in the porous insulator 1, 20% by volume or more of the entire volume is occupied by the pores 3. In other words, the insulating material 2 occupies 80% by volume or less of the entire volume of the porous insulator 1. The porosity is preferably 5 to 70% by volume, and more preferably 20 to 50% by volume.

  The pores 3 contain moisture 4. Here, the ratio of the total volume of all moisture 4 to the total volume of all pores 3 in the porous insulator 1 is referred to as moisture occupancy. In the porous insulator 1 of the present embodiment, this moisture occupancy is 23 to 100% by volume. In addition, the volume occupation rate of the water | moisture content 4 in each hole 3 does not necessarily need to be 23-100 volumes. The moisture occupancy is preferably 50 to 100% by volume, and more preferably 80 to 100% by volume.

  As described above, the moisture occupancy in the porous insulator 1 of the present embodiment is a numerical value of 23% by volume or more. This numerical value is a larger numerical value than the above-mentioned moisture occupancy ratio in a general porous body having pores with a diameter of 5 to 100 nm. That is, even a general porous body having pores with a diameter of 5 to 100 nm can adsorb moisture inside the pores. In this case, the moisture occupancy is less than 23% by volume. It becomes a numerical value. This will be described next.

When a general porous body adsorbs moisture, water molecules are adsorbed as a single molecule on the surface of pores included in the porous body. When the porous body has pores having a diameter of 5 to 100 nm as in the porous insulator 1 of the present embodiment, the water occupancy is the largest value when the diameter of the pores is the smallest. That is, the porous body has pores with a diameter of 5 nm. When the water occupancy in this case is calculated, water molecules having a diameter of 3 mm (0.3 nm) are adsorbed on the surface of the pores having a radius of 2.5 nm (diameter 5 nm).
Moisture occupancy (volume%) = [1- (pore radius 2.5 nm−water molecule diameter 0.3 nm) ² / (hole radius 2.5 nm) ² ] × 100 = 22.56
And about 22.6% by volume. For this reason, in the normal porous body, the water occupancy is not 23% by volume or more.

  In the porous insulator 1, the moisture occupancy of 23% by volume or more means that the amount of moisture 4 exceeding the monomolecular adsorption is contained in the pores 3. Since the porous insulator 1 contains such a large amount of moisture 4 in the pores 3, the moisture 4 undergoes electrolysis when an electric field is applied, and exhibits a specific electrochemical behavior. Next, the electrochemical behavior exhibited by the porous insulator 1 when an electric field is applied will be described.

  Since the porous insulator 1 includes the insulating material 2 as described above, when an electric field is applied in the thickness direction by the positive and negative counter electrodes provided so as to sandwich the porous insulator 1, the porous insulator 1 Among the surfaces of 1, polarization is performed so that the surface close to the positive electrode becomes negative and the surface close to the negative electrode becomes positive. At this time, the moisture 4 contained in the porous insulator 1 undergoes electrolysis and dissociates into hydrogen ions and hydroxide ions. The dissociated hydrogen ions and hydroxide ions are attracted or repelled by the electric field applied to the porous insulator 1, and among the surfaces of the porous insulator 1, the hydroxide ions having a negative charge are close to the positive electrode. It is considered that hydrogen ions having a positive charge move to the surface and move to the surface close to the negative electrode. As a result, positively charged hydrogen ions gather near the surface of the positively polarized porous insulator 1 and negatively charged hydroxide ions gather near the negatively polarized porous insulator surface. Become. By such an action, the porous insulator 1 can be polarized more largely than a normal insulator by an electric field applied thereto, and the presence of hydrogen ions and hydroxide ions collected near the surface makes it unique. It becomes possible to cause a chemical reaction. Further details regarding these properties will be described later.

  Next, an example of a method for producing the porous insulator 1 of the present embodiment will be described. In this example, the porous insulator 1 is formed on the surface of a substrate (not shown) by a pulse laser deposition method.

  The substrate (not shown) for forming the porous insulator 1 is not particularly limited, and may be appropriately selected according to the purpose of use of the porous insulator 1. For example, if the porous insulator 1 is used as a gate insulator of a field effect transistor, a substrate (not shown, the same applies hereinafter) becomes an active layer of the field effect transistor.

In order to form the porous insulator 1 by the pulse laser deposition method, a target made of an insulating material is irradiated with a pulse laser in a reduced pressure chamber according to a conventional method, and the generated plume is brought into contact with the substrate. Just do it. Base pressure of the chamber ^is in the range of ¹⁰ -7 ~10 0 Pa. In performing pulse laser deposition, it is necessary to introduce oxygen into the chamber and set the oxygen pressure inside the chamber to a range of 10 ⁻¹ to 10 ² Pa. By setting the oxygen pressure inside the chamber within the above range, the porosity of the porous insulator 1 can be set to 20% by volume or more. That is, the present invention has been completed by finding that the porosity in the porous insulator 1 to be formed changes as the oxygen pressure in the pulse laser deposition method is changed. For example, as shown in the following examples and comparative examples, when the oxygen pressure inside the chamber in the pulse laser deposition method is 0.1 Pa or less, the porosity of the insulator to be formed becomes 0%, resulting in a dense film. However, when the oxygen pressure inside the chamber in the pulse laser deposition method is 5 Pa, the porosity of the formed insulator is 42%. What is necessary is just to set suitably the oxygen pressure inside a chamber so that the porous insulator 1 may be formed with the desired porosity. The oxygen pressure inside the chamber when performing pulsed laser deposition is preferably 10 ⁻¹ to 10 ² Pa, and more preferably ¹ to 10 Pa.

As the laser beam used in the pulse laser deposition method, a known laser beam can be used, and an example thereof is a KrF excimer laser. The generated laser light is collected by a lens and introduced into the chamber. The target made of an insulating material is installed in the vicinity of the focal point of the laser beam at an angle of 45 ° inside the decompressed chamber as described above, and the substrate on which the porous insulator 1 is formed is a generated plume. It is fixed so that it is perpendicular to and parallel to the target. When a pulse laser is irradiated onto a target made of an insulating material, the insulating material is vaporized from the surface of the target to form a plume, and this plume comes into contact with the surface of the substrate, so that the insulating material 2 is deposited on the surface of the substrate. To do. At this time, the insulating material 2 is rapidly cooled on the surface of the substrate immediately after becoming a high temperature plume by the irradiation of the pulse laser. For this reason, the insulating material 2 cannot be crystallized and is deposited on the surface of the substrate in an amorphous state. It is preferable that the insulating material 2 is deposited in an amorphous state because the flexibility and low current leakage characteristics of the porous insulator 1 are better than those of the porous crystal thin film.
Examples of laser light used in the pulse laser deposition method include Nd: YAG fourth harmonic laser, ArF excimer laser, and the like in addition to the above KrF excimer laser.

  The conditions for generating the pulse laser are not particularly limited, but when a KrF excimer laser is used, the wavelength is 248 nm, the pulse width is 20 ns, and the repetition frequency is 10 Hz.

  When the porous insulator 1 is formed on the surface of the substrate, the reduced pressure in the chamber is released to normal pressure. At this time, moisture contained in the air is taken into the pores 3 existing inside the porous insulator 1 and the moisture 4 is contained. At this time, an amount of moisture 4 exceeding the amount based on single molecule adsorption is contained in the pores 3. As described above, the porous insulator of the present embodiment is formed on the surface of the substrate.

  In the method for manufacturing the porous insulator 1 described above, the pulse laser deposition method has been described as an example, but the method for manufacturing the porous insulator 1 is not limited thereto. As a method for manufacturing the porous insulator 1, in addition to the pulse laser deposition method, a sputtering method, a coating method in which a precursor of the insulator is applied, and then heated and baked, a CVD method, an atomic layer deposition method, etc. Is mentioned.

  Next, as one application example of the porous insulator 1 of the above embodiment, an embodiment of a field effect transistor 5 in which the porous insulator 1 is used as a gate insulator will be described with reference to the drawings. . FIG. 2 is a perspective view showing an embodiment of a field effect transistor 5 in which the porous insulator 1 of the present invention is used as a gate insulator. In FIG. 2, for easy understanding, the ratio of dimensions of each member is described so as to be different from the actual one.

  In the field effect transistor 5 of this embodiment, a film of the porous insulator 1 is formed on the surface of the active layer 6 as a gate insulator. Further, a source electrode 8 and a drain electrode 9 are formed on the surface of the active layer 6 so as to face each other so as to sandwich the porous insulator 1 from the left end and the right end thereof. The source electrode 8 and the drain electrode 9 are arranged so that each part thereof bites into the left end or the right end of the porous insulator 1. A gate electrode 7 is formed on the surface of the porous insulator 1. The gate electrode 7 can apply an electric field in a direction perpendicular to the energizing direction between the source electrode 8 and the drain electrode 9 arranged to face each other. The field effect transistor 5 is electrically connected between the source electrode 8 and the drain electrode 9 by applying a charge to the gate electrode 7, and exhibits a switching characteristic that is a characteristic of the field effect transistor.

The active layer 6 is made of a metal oxide that is an insulator. Examples of such a metal oxide include SrTiO ₃ , ZnO, TiO ₂ , NiO, and the like, but SrTiO ₃ is preferably used because the on / off ratio of the transistor can be increased. The active layer 6 is preferably composed of a single crystal, and is not particularly limited, but the porous insulator 1 is formed on the (001) plane. The active layer 6 may be a thin film of 0.4 to 1000 nm or a bulk single crystal of 1000 nm or more.

  The thickness of the porous insulator 1 formed on the surface of the active layer 6 may be appropriately set according to the desired characteristics of the field effect transistor 5. Examples of the film thickness of the porous insulator 1 include 10 to 1000 nm, but are not particularly limited.

  The gate electrode 7 is formed of a conductive material. Examples of such a gate electrode 7 include a film or a layer of titanium, gold, nickel, aluminum, molybdenum, or the like. The thickness of the gate electrode 7 may be set as appropriate according to the desired characteristics of the field effect transistor 5. Although 10-30 nm is illustrated as thickness of the gate electrode 7, it is not specifically limited.

  The source electrode 8 and the drain electrode 9 are made of a conductive material. Examples of the source electrode 8 and the drain electrode 9 include a film or a layer of titanium, gold, nickel, aluminum, molybdenum, or the like independently. The thicknesses of the source electrode 8 and the drain electrode 9 may be appropriately set according to the desired characteristics of the field effect transistor 5 independently. The thicknesses of the source electrode 8 and the drain electrode 9 are each independently 10 to 30 nm, but are not particularly limited.

  Next, a possible mechanism for the reason why the field effect transistor 5 as described above exhibits the switching characteristics which are characteristics of the field effect transistor will be described. As described above, since the active layer 6 of the field effect transistor 5 is an insulator made of a metal oxide, no current flows between the source electrode 8 and the drain electrode 9 when no electric field is applied from the gate electrode 7. .

  When a positive charge is applied to the gate electrode 7 and a negative charge is applied to the source electrode 8, an electric field is generated in the porous insulator 1 from the gate electrode 7 toward the active layer 6. Then, a positive charge is induced on the surface of the porous insulator 1 that is a dielectric, which is a boundary with the active layer 6, and the induced positive charge causes the porous insulator 1 on the surface of the active layer 6 to Electrons gather on the surface that becomes the boundary of. The electrons gathered on the surface of the active layer 6 become carriers and give a slight conductivity to the very surface portion of the active layer 6. The surface of the active layer 6 to which conductivity is imparted is electrically connected to the source electrode 8 and has a negative charge like the source electrode 8. The surface of the active layer 6 to which conductivity is imparted is referred to as a conductive active layer surface (not shown, the same applies hereinafter).

  The porous insulator 1 is sandwiched between the gate electrode 7 having a positive charge located on the upper portion thereof, and the source electrode 8 having a negative charge located on the lower portion thereof and the surface of the conductive active layer. Therefore, the moisture 4 present inside the porous insulator 1 is electrolyzed and dissociated into hydrogen ions and hydroxide ions by the electric field formed by the gate electrode 7, the source electrode 8, and the conductive active layer surface. To do.

  Hydrogen ions generated by electrolysis move inside the porous insulator 1 while being attracted by an electric field, and are near the surface of the source electrode 8 and the conductive active layer having negative charges (that is, active with the porous insulator 1 and the active material). At the boundary with the layer 6). At this time, some of the hydrogen ions gathered at the boundary between the porous insulator 1 and the active layer 6 extract oxygen atoms from the metal oxide existing on the surface of the active layer 6 to metallize the surface of the active layer 6. Conduction is performed between the source electrode 8 and the drain electrode 9. With such a mechanism, the field effect transistor 5 is considered to exhibit a switching action.

  The above mechanism is inferred from the fact that the switching effect of the field effect transistor 5 is different between the temperature at which the moisture 4 existing inside the hole 3 is not frozen and the temperature at which it is frozen. Further, the plot shape of the source-drain current-gate voltage characteristics in the prototype field effect transistor 5 is very similar to the behavior of the ionic current in the electrochemical reaction, and from this, it is based on the electrolysis action of the moisture 4. The above mechanism is inferred.

  Note that the conduction state between the source electrode 8 and the drain electrode 9 disappears when an electric field in the opposite direction to that described above is applied between the gate electrode 7 and the source electrode 8, and the electric field in the same direction as above. Is applied again between the gate electrode 7 and the source electrode. Thus, the switching effect of the field effect transistor 5 is reversible.

  The gate voltage necessary for conducting the source electrode 8 and the drain electrode 9 is about 1 to 50V. Here, the gate voltage is a voltage of the gate electrode 7 with respect to the source electrode 8. By applying such a gate voltage, the sheet resistance (the value obtained by dividing the resistance between the source electrode 8 and the drain electrode 9 by the ratio of channel length / channel width) in the field effect transistor 5 is 100 kΩ or less. Become. The channel length here is the length between the source electrode 8 and the drain electrode 9, and the channel width is orthogonal to the channel length in a plane in the portion where the source-drain current is generated. Means the width.

  As mentioned above, the example of the field effect transistor 5 was shown and the specific use of the porous insulator 1 was demonstrated, However, The use of the porous insulator 1 is not limited to this. As described above, since the porous insulator 1 exhibits a large polarization based on the electrolysis action of the moisture 4 existing therein, it is also preferably used as an electrolytic capacitor. In addition, since the porous insulator 1 exhibits high hydrogen ion conduction, it can be used for fuel cell applications.

  In the field effect transistor 5, the present inventors applied a voltage to the gate electrode 7 to generate an electric field from the gate electrode 7 toward the active layer 6. When the thermoelectric power was measured by giving a temperature difference between the two, it was found that a higher thermoelectric conversion effect can be obtained than a field effect transistor having a gate insulator that is not the porous insulator 1. In this case, the active layer 6 exhibits a thermoelectric conversion action, and a thermoelectromotive force is generated due to a temperature difference between the temperature of the active layer 6 on the source electrode 8 side and the temperature of the active layer 6 on the drain electrode 9 side. The thermoelectromotive force can be taken out as a potential difference between the source electrode 8 and the drain electrode 9. The method of giving a temperature difference between the channels (between the source and drain electrodes) is not particularly limited, but the cooling means is brought into contact with the lower surface of the active layer 6 on the source electrode 8 side to activate the drain electrode 9 side. The method of making a heating means contact the lower surface of the layer 6 is illustrated. Examples of such heating means and cooling means include the use of Peltier elements.

That is, as described in Non-Patent Document 1, a field effect transistor using a metal oxide such as strontium titanate as an active layer and an insulator such as 12CaO · 7Al ₂ O ₃ glass as a gate insulator The thermoelectric conversion action that generates a voltage between the source electrode and the drain electrode by applying a temperature difference between the channels (between the source and drain electrodes) is provided as the porous insulator 1 of the present invention. Thus, the present inventors have found that the thermoelectric conversion efficiency is improved even though the composition of the gate insulator is the same.

  From this, it is understood that the porous insulator 1 of the present invention is also useful for producing a thermoelectric conversion material. A thermoelectric conversion material obtained by bonding the porous insulator 1 and an active layer made of a metal oxide based on such knowledge is also one aspect of the present invention.

  EXAMPLES Hereinafter, although an Example is shown and it demonstrates further more concretely about the porous insulator and field effect transistor of this invention, this invention is not limited to a following example at all.

<Fabrication of field effect transistor>
[Example 1]
A field effect transistor 5 having the structure shown in FIG. 3 was produced. In FIG. 3, for easy understanding, the ratio of dimensions of each member is described so as to be different from the actual one.
First, on the surface of SrTiO ₃ single crystal (surface orientation 001, 10 mm × 10 mm × thickness 0.5 mm, manufactured by Shinko Co., Ltd.) whose surface was planarized at the atomic level by the method described in Non-Patent Document 1, Ti The source electrode 8 and the drain electrode 9 were formed by evaporating an electron beam by 400 μm × 400 μm × thickness 20 nm. The separation width between the source electrode 8 and the drain electrode 9 was 400 μm. The SrTiO ₃ single crystal becomes the active layer 6 of the field effect transistor 5. Next, 12CaO.7Al ₂ O ₃ in an amorphous state is deposited on the surface of the active layer 6 and the surfaces of the source electrode 8 and the drain electrode 9 by pulse laser deposition under an oxygen pressure of 1.5 Pa. A porous insulator 1 (gate insulator) was formed. The chamber base pressure (pressure inside the chamber before introducing oxygen) at this time was 1 × 10 ⁻⁶ Pa. The size of the porous insulator 1 was 800 μm × 1000 μm × thickness 200 nm. The conditions for performing the pulse laser deposition method were as follows: no substrate heating, KrF excimer laser, laser energy density 3 J / cm ² , pulse width 20 ns, and repetition frequency 10 Hz. Finally, the gate electrode 7 was formed on the surface of the formed porous insulator 1 by electron beam evaporation of Ti at 500 μm × 800 μm × thickness 20 nm, and the field effect transistor of Example 1 was obtained. The gate electrode 7 was formed so as to be located at the center of the porous insulator 1 in plan view.

[Example 2]
A field effect transistor of Example 2 was produced in the same procedure as in Example 1 except that the oxygen pressure when performing the pulse laser deposition method was 3 Pa.

[Example 3]
A field effect transistor of Example 3 was produced in the same procedure as in Example 1 except that the oxygen pressure at the time of performing the pulse laser deposition method was set to 5 Pa.

[Comparative Example 1]
A field effect transistor of Comparative Example 1 was produced in the same procedure as in Example 1 except that the oxygen pressure when performing the pulse laser deposition method was 0.1 Pa.

<Observation of pores in porous insulator 1>
The cross section of the porous insulator 1 in the field effect transistor of Example 2 was observed with a scanning transmission electron microscope (HAADF-STEM). As a result, it was found that the porous insulator 1 contained an infinite number of pores and the pore diameter was about 10 nm. As a result of performing the same observation on the porous insulator 1 in the field effect transistors of Examples 1 and 3, it was confirmed that these porous insulators also contained innumerable holes having a diameter of about 10 nm. In addition, it was confirmed that the porous insulators of Examples 1 and 3 also contained an infinite number of pores having a diameter of about 10 nm.
On the other hand, as a result of performing the same observation on the (porous) insulator 1 in the field effect transistor of Comparative Example 1, the (porous) insulator does not include pores and has a dense structure. I understood. Therefore, it was confirmed that the gate insulator in the field effect transistor of Comparative Example 1 was not a porous insulator like the gate insulators of Examples 1 to 3, but a simple insulator.

<Measurement of porosity and moisture occupancy>
Only porous insulators were produced in the same manner as the porous insulator 1 formed by the field effect transistors of Examples 1 to 3 and Comparative Example 1. These porous insulators have the same structure as the porous insulator 1 in the field effect transistors of Examples 1 to 3 and Comparative Example 1, respectively.
The porosity and moisture occupancy were measured for each of the produced porous insulators. The results are shown in Table 1.
The meanings of the terms porosity and moisture occupancy are as described above.
The porosity (%) was determined by measuring the film density of the formed porous insulator made of 12CaO · 7Al ₂ O ₃ by X-ray reflectivity measurement, and the film density a and 12CaO · 7Al ₂ O ₃ Using the film density b when the film was densely formed, it was calculated from the formula (ba) / b × 100.
Furthermore, the moisture occupancy (%) is the amount of water contained in the porous insulator by the temperature programmed desorption method in which the moisture released from the porous insulator is mass analyzed when heated from room temperature to 400 ° C. The volume of moisture contained in the porous insulator was calculated from the amount of moisture, and further calculated by the formula of volume of moisture / (volume of porous insulator × porosity) × 100. In addition, the specific gravity of the water | moisture content used when calculating | requiring the volume of a water | moisture content was 1.0 g / cm < ³ >. Here, the moisture contained in the (porous) insulating film when the oxygen pressure is 0.1 Pa was calculated as 0.9 vol% by the temperature programmed desorption method, but the (porous) insulation at this time Since the porosity of the film is 0%, it is presumed that the moisture was not contained in the pores but adhered to the surface of the (porous) insulating film. In this case, since there are no holes that should be occupied by moisture, the moisture occupancy cannot be calculated. Therefore, in Table 1, the moisture occupancy when the oxygen pressure is 0.1 Pa is described as “−”.

<Measurement of electric characteristics of field effect transistor>
FIG. 4A shows a graph plotting the drain current Id against the gate voltage Vg at room temperature in the field effect transistor of Example 2. FIG. FIG. 4B shows a graph in which the gate current Ig is plotted against the gate voltage Vg in the field effect transistor of Example 2. FIG. 4C is a graph plotting the gate capacitance against the gate voltage Vg in the field effect transistor of Example 2. FIG. 4D shows a graph plotting the drain current Id against the gate voltage Vg at room temperature in the field effect transistor of Comparative Example 1. FIG. 4E shows a graph plotting the gate current Ig with respect to the gate voltage Vg in the field effect transistor of Comparative Example 1. FIG. 4F shows a graph in which the gate capacitance with respect to the gate voltage Vg in the field effect transistor of Comparative Example 1 is plotted.

As shown in FIG. 4A, a large counterclockwise hysteresis is seen in the drain current Id-gate voltage Vg characteristic in the field effect transistor of Example 2, and the hysteresis also increases with an increase in the applied gate voltage. There was a tendency to increase. On the other hand, in the field effect transistor of Comparative Example 1, the hysteresis effect as described above was not observed as shown in FIG.
Further, as a result of investigating the gate current Ig-gate voltage Vg characteristics, as shown in FIGS. 4B and 4E, the field effect transistor of Example 2 is 100 as compared with the field effect transistor of Comparative Example 1. A gate current more than doubled was observed, and a hysteresis effect of a gate current much larger than that of the field effect transistor of Comparative Example 1 was observed.
Further, as shown in FIG. 4C, in the field effect transistor of Example 2, a large hysteresis is observed also in the gate capacitance-gate voltage Vg characteristic, and the gate capacitance is 160 pF to 20 pF as the gate voltage changes. Changed in width. In contrast, as shown in FIG. 4F, such hysteresis was not observed in the field effect transistor of Comparative Example 1.

  By the way, the shape of the current-voltage characteristic in the field effect transistor of Example 2 shown in FIG. 4A or FIG. 4B is similar to the behavior of the ionic current in the electrochemical reaction. From this, it was expected that the electrical characteristics as described above in the field effect transistor of Example 2 were based on the electrolysis current of moisture contained in the porous insulator 1 (gate electrode).

Therefore, in order to evaluate the influence of moisture contained in the porous insulator 1 on the electrical characteristics, the drain effect Id-gate voltage Vg characteristics of the field effect transistor of Example 2 at room temperature (25 ° C.) and 0 ° C. I investigated. The result is shown in FIG. FIG. 5A is a graph plotting the drain current Id against the gate voltage Vg of the field effect transistor of Example 2 at 25 ° C. FIG. FIG. 5B is a graph plotting the drain current Id against the gate voltage Vg of the field effect transistor of Example 2 at 0 ° C. FIG.
As shown in FIG. 5A, in the field effect transistor of Example 2, a large hysteresis was observed in the drain current Id-gate voltage Vg characteristics at room temperature (25 ° C.). However, at 0 ° C., the temperature at which water freezes, as shown in FIG. 5B, almost no hysteresis of the drain current Id-gate voltage Vg characteristic is observed, and the drain current Id-gate in a general field effect transistor is observed. A voltage Vg characteristic was observed.
This behavior is presumed to be observed because the water contained in the porous insulator 1 becomes ice and electrolysis does not occur when the gate voltage is applied.

  Furthermore, in order to investigate the influence of electrolysis, the gate voltage application time dependence of the drain current Id was measured for the field effect transistor of Example 2. The result is shown in FIG. In FIG. 4 (a), there are a plurality of hysteresis curves, which are respectively the drain current Id with respect to the gate voltage Vg when the gate voltage application time is changed to 1, 2, 3, 4 and 5 minutes. It is a plot. As shown in FIG. 4A, in the field effect transistor of Example 2, as the gate voltage application time increased, the drain current Id increased, and the source-drain resistance was divided by the ratio of channel length / channel width. The sheet resistance as a value decreased to 2 kΩ.

  The above electric characteristics were observed also in the field effect transistors of Examples 1 and 3, and even with these field effect transistors, a sheet resistance of 10 kΩ or less could be realized. However, in the field effect transistor of Comparative Example 1, the sheet resistance could not be made 100 kΩ or less.

In the field effect transistor of Comparative Example 1, as shown in FIG. 4D, the drain current Id-gate voltage Vg characteristic similar to that of a general field effect transistor was observed. The gate current at this time was sufficiently small (see FIG. 4E) and had no effect on the measured drain current Id-gate voltage Vg characteristics. Further, as shown in FIG. 4F, the gate capacitance in the field effect transistor of Comparative Example 1 is 210 pF, and the gate is calculated from the relative dielectric constant (= 12) of 12CaO · 7Al ₂ O _{3 in} the amorphous state. Consistent with capacity.

<Measurement of thermoelectric characteristics of field effect transistor>
Thermoelectric characteristics of the field effect transistor of Example 3 and the field effect transistor of Comparative Example 1 were measured. The field effect transistor of Example 3 includes the porous insulator 1 according to the present invention as a gate insulator, and the field effect transistor of Comparative Example 1 is an insulator having a dense structure unlike the porous insulator 1. Is provided as a gate insulator. That is, the field effect transistor of Example 3 has a structure in which the porous insulator 1 and the active layer made of a metal oxide are joined.

  A gate voltage was applied to the field effect transistor of Example 3 to obtain a Seebeck coefficient at room temperature, which is an index of thermoelectric performance, in a state where carrier electrons on the surface of the active layer were accumulated. A commercially available Peltier is formed on the lower surface of the active layer 6 corresponding to the channel (between the source and drain electrodes) of the field effect transistor (the surface existing on the back side of the surface of the active layer 6 on which the source electrode 8 and the like are provided). Two elements (not shown, the same shall apply hereinafter) are installed, and the source electrode 8 and the drain electrode are used while gradually changing the temperature difference between the channels (between the source and drain electrodes) using the Peltier element. 9 was measured, and the temperature dependence of the thermoelectromotive force generated between 9 and 9 was measured, and the Seebeck coefficient was calculated from the slope of the plot. One of the two Peltier elements was installed on the lower surface of the active layer 6 on the source electrode 8 side for cooling, and the other was installed on the lower surface of the active layer 6 on the drain electrode 9 side for heating. By cooling and heating by these two Peltier elements, a temperature gradient is generated between the channels (between the source and drain electrodes), with the drain electrode 9 side being the high temperature side and the source electrode 8 side being the low temperature side. A thermoelectromotive force is generated between 8 and the drain electrode 9. At this time, the temperature difference between both ends of the channel (between the source and drain electrodes) was measured using an ultrafine thermocouple (K type). In the above calculation, about 5 ° C. was given as the temperature difference between the channels (between the source and drain electrodes). Further, a digital multimeter (manufactured by Advantest Corporation, model R6552) was used for measurement of the thermoelectromotive force. In the same procedure, the Seebeck coefficient in the field effect transistor of Comparative Example 1 was calculated.

FIG. 6A shows the Seebeck coefficient (thermopower | S |; hereinafter also referred to as “thermopower”) with respect to the gate voltage (V _g ). FIG. 6B shows the sheet electron concentration (n _sheet ) of the transistor channel with respect to the gate voltage (V _g ). The sheet electron concentration is an electron concentration (cm ⁻² ) between regions (channels) sandwiched between the source electrode 8 and the drain electrode 9 and was calculated by measuring the Hall effect. All the Seebeck coefficients (thermoelectric power) were measured at room temperature. 6 and 7, the measurement result for the field effect transistor of Example 3 is indicated as “porous C12A7”, and the measurement result for the field effect transistor of Comparative Example 1 is indicated as “dense C12A7”.

  In the field effect transistor 5 of Example 3 (hereinafter, also referred to as “field effect transistor having a porous gate insulator”) provided with the porous insulator 1 of the present invention as a gate insulator, the gate voltage is reduced. Although the thermoelectric power once decreased with the increase, the thermoelectric power increased around the gate voltage of 22V. On the other hand, the field effect transistor of Comparative Example 1 (hereinafter also referred to as “field effect transistor having a dense gate insulator”) having a dense insulator as a gate insulator exhibited high thermoelectric power. As the gate voltage increased, the thermoelectric power decreased monotonously.

Further, in the case of a field effect transistor having a dense gate insulator, the sheet electron density remained at about 10 ¹³ cm ⁻² even when the gate voltage was set to 40 V, but the sheet electron density was provided with a porous gate insulator. In the case of the field effect transistor, a high value exceeding 10 ¹⁵ cm ⁻² was obtained. 6 (a) and 6 (b), the point indicated by the arrow indicates the point where the reduced thermoelectric power is recovered in the field effect transistor including the porous gate insulator. The thermoelectric power and the sheet electron concentration were 270 μVK ⁻¹ and 2.5 × 10 ¹⁴ cm ⁻² , respectively.

Next, a constant gate voltage (a voltage that is any one of 15V, -15V, -20V, -30V, and -40V) is applied to a field effect transistor having a porous gate insulator, and thermoelectric power and sheet electron concentration are applied. The gate voltage application time dependence of was investigated. The results are shown in FIGS. 6 (c) and (d). When a gate voltage of +15 V was applied, the thermoelectric power once decreased to 270 μVK ⁻¹ with the passage of the gate voltage application time and then increased. At this time, the sheet electron concentration monotonously increased with the lapse of the gate voltage application time. Moreover, when a negative gate voltage was applied, the thermoelectric power further increased, while the sheet electrons decreased only slightly.

  Based on the above results, the relationship between thermoelectric power and sheet electron concentration is considered. FIG. 7 is a plot showing the sheet electron concentration dependence of thermoelectric power at room temperature for a field effect transistor with a porous gate insulator and a field effect transistor with a dense gate insulator. The broken line in the figure indicates the sheet electron concentration dependence of the thermoelectric power calculated by theoretical calculation (using a semiconductor device simulator, ATLAS manufactured by Silvaco).

As shown in FIG. 7, the field effect transistor having a dense gate insulator showed a decrease in thermoelectric power almost as the theoretical value as the sheet electron concentration increased. On the other hand, the field effect transistor provided with the porous gate insulator has almost the theoretical value as the sheet electron concentration increases in the range of the sheet electron concentration up to 2.5 × 10 ¹⁴ cm ⁻² . In the range where the sheet electron concentration exceeds 2.5 × 10 ¹⁴ cm ⁻² , the thermoelectric power decreased greatly from the theoretical value as the sheet electron concentration increased. It was found that the thermoelectric power is about 5 times the theoretical value.

The performance index ZT, which is an index for evaluating the performance of the thermoelectric material, is expressed by ZT = S ² σTκ ⁻¹ (S: thermoelectric power, σ: conductivity, T: absolute temperature, κ: thermal conductivity), The fact that a thermoelectric power of about 5 times the theoretical value was obtained, that is, the figure of merit ZT was about 25 times. From this, it can be seen that the thermoelectric conversion material of the present invention formed by bonding the porous insulator of the present invention and the active layer made of metal oxide has high thermoelectric performance.

By the way, a two-dimensional electron gas having a dielectric heterostructure (International Publication No. 2006/054550: Thermoelectric conversion material and method for producing thermoelectric conversion material) and SrTiO ₃ artificial superlattice (International Publication No. 2007/132782: Thermoelectric conversion material). It is already known that infrared sensors and image production devices) exhibit ZT of more than 2 at room temperature. In both cases, the localization of high-concentration carrier electrons in the ultrathin layer of SrTiO ₃ causes the electronic state density to be discretized, called the quantum size effect, and realizes a giant thermoelectric power. In the field effect transistor of Example 3 as well, a very thin electron layer having a thickness of about 2 nm was induced at the interface between the porous insulator 1 and the active layer 6 made of SrTiO ₃ single crystal by the gate voltage. It is considered that the giant thermoelectric power was about 5 times that of the field effect transistor of Comparative Example 1 having

DESCRIPTION OF SYMBOLS 1 Porous insulator 2 Insulation material 3 Hole 4 Moisture 5 Field effect transistor 6 Active layer

Claims (7)

It has a plurality of holes having a diameter of 5 to 100 nm in the insulating material,
The porosity, which is the ratio of the volume occupied by the pores to the entire volume, is 20% by volume or more,
A porous insulator in which moisture is contained in the pores and a moisture occupancy ratio, which is a ratio of a volume occupied by the moisture to a volume of the pores, is 23 to 100% by volume.   The porous insulator according to claim 1, wherein the pore has a diameter of 5 to 20 nm. The material is 12CaO · 7Al ₂ O ₃ , CaO, Al ₂ O ₃ , 12SrO · 7Al ₂ O ₃ , Y ₂ O ₃ , HfO ₂ , SiO ₂ , MgO, LaAlO ₃ , ZrO ₂ , MgAl ₂ O ₄ , Nb _{2 3. The} method according to claim 1, comprising at least one selected from the group consisting of O ₅ , Ta ₂ O ₅ , Si ₃ N ₄ , SrTiO ₃ , BaTiO ₃ , CaTiO ₃ , SrZrO ₃ , CaZrO ₃ , and BaZrO ₃ . Porous insulator.   The porous insulator according to claim 1, wherein the material is an amorphous oxide.   A field effect transistor comprising the porous insulator according to claim 1 as a gate insulator.   6. The field effect transistor according to claim 5, wherein the active layer is made of a metal oxide.   The thermoelectric conversion material formed by joining the porous insulator of any one of Claims 1-4, and the active layer which consists of metal oxides.

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