JP2012027169A - Liquid crystal display device and method of driving the same - Google Patents

Abstract

Deterioration of display image uniformity (uniformity) due to variations in threshold voltages of source follower transistors in a pixel is suppressed to a minimum.
A correction gradation calculation unit sets a maximum value of a reference lamp voltage to Rmax, a minimum value to Rmin, input video data to N bits, and an average value Vap of positive-side voltages of all pixels for each pixel. If the intermediate potential of the difference Yn with respect to the difference Xn and the average value Vam of the negative side voltage of all the pixels is Vcor, the correction gradation Dcor of each pixel is calculated by the following equation (where α is a coefficient).
Dcor = Vcor / {(Rmax−Rmin) / 2 ^N }
−α × | {(Vap−Vam) / 2} −Vcor |
As a result, the drive voltages of the pixels B, C, and D are reduced by (b3 + b4), (c3 + c4), and (d3 + d4), which are the correction voltages indicated by the second term on the right side of the above equation.
[Selection] Figure 12

Description

  The present invention relates to a liquid crystal display device and a driving method thereof, and more particularly to an active matrix type liquid crystal display device by a driving method having both advantages of an analog driving method and a digital driving method and a driving method thereof.

  In recent years, a liquid crystal display device of LCOS (Liquid Crystal on Silicon) type is often used as a central part for projecting images in projector devices and projection televisions. This LCOS type liquid crystal display device has a structure in which a transparent electrode, a liquid crystal layer, a reflective electrode arranged in a matrix, a liquid crystal driving element in which a liquid crystal driving circuit is formed on a silicon substrate, and the like overlap. It is widely used for liquid crystal projectors and projection televisions in home, office, and industrial information display terminals.

  In a conventional liquid crystal display device, pixels are arranged in a matrix at each intersection of a plurality of data lines (column signal lines) and a plurality of gate lines (row scanning lines). As shown in FIG. 13, each pixel includes a pixel selection transistor Q, a signal holding capacitor Cs, and a liquid crystal element LC. The pixel selection transistor Q has a gate connected to a gate line (row scanning line) G and a drain connected to a data line (column signal line) D. Further, as shown in FIG. 13, the liquid crystal element LC has a configuration in which a liquid crystal display (liquid crystal layer) LCM is sandwiched between a reflective electrode (pixel drive electrode) PE and a counter electrode (common electrode) CE facing each other. Has been.

  In the liquid crystal element LC, the fixed voltage Vcom is applied to the common electrode CE, and various voltages according to the video signal are supplied to the reflective electrode (pixel drive electrode) PE, thereby controlling the light modulation rate of the liquid crystal display LCM. Display as video. Normally, the liquid crystal element LC can be stabilized for a long time by AC driving, so that the reflection electrode (pixel driving electrode) PE receives light according to the video signal with respect to the fixed voltage Vcom of the common electrode CE. AC driving is performed by alternately applying positive and negative voltages that have the same modulation rate.

  In some cases, there is an application example where the common voltage of the common electrode is switched according to the timing of driving with the positive and negative voltages for the purpose of reducing the dynamic range of the video signal, but the basic idea is The same.

  In the conventional liquid crystal display device, the video signal is normally written to each pixel once per frame, and the video signal on the positive side and the negative side is signaled alternately with respect to the common electrode CE every frame. After writing into the storage capacitor Cs, the storage voltage is applied to the reflective electrode (pixel drive electrode) PE to drive the liquid crystal element LC with alternating current. In this case, there is an example of double speed driving in which the liquid crystal is AC driven at a frequency twice as high as the writing frequency, but the frequency is about 60 Hz to 120 Hz, and is not a high frequency in any case.

  On the other hand, if the liquid crystal element LC is AC driven at a higher frequency so that the DC component between the reflective electrode (pixel driving electrode) PE and the common electrode CE can be reduced to zero, the reliability can be improved by preventing burn-in. And the display quality of the image is improved.

  Until now, prevention of deterioration of written signals such as countermeasures against feedthrough caused by parasitic capacitance of the pixel selection transistor (for example, refer to Patent Document 1) and countermeasures for leakage of a storage capacitor (for example, refer to Patent Document 2). A method is disclosed. However, it seems that efforts to drive alternating current at higher frequencies have not been studied much.

  For each of a plurality of pixels connected to the same scanning line, the storage capacitor of each pixel is alternately connected to the storage capacitor line corresponding to the scanning line and another storage capacitor line corresponding to the adjacent scanning line. The compensation voltage for compensating the direct current component between the pixel drive electrode and the common electrode is inverted for each storage capacitor line, so that the image quality degradation caused by the potential fluctuation of the common electrode line or the common electrode is reduced. A liquid crystal display device that prevents generation thereof has been conventionally known (see, for example, Patent Document 3).

JP 2006-10897 A JP 2002-250938 A JP 2004-354742 A

  As described above, it is desirable to drive the liquid crystal element with an alternating current at a high frequency as a means for improving reliability such as prevention of burn-in of the liquid crystal element. It is difficult to alternately write video signals on the negative side and the negative side at high speed, and conventionally, the frequency of AC drive is only performed at a frame rate or about twice that frequency.

  Further, in the liquid crystal display device described in Patent Document 3, the polarity of the compensation voltage can be reversed only for each frame, and the image signal voltage has two types of voltages, positive and negative, with respect to the common electrode voltage Vcom. is necessary.

  There are mainly two methods for driving the liquid crystal display element: an analog driving method using amplitude modulation and a digital driving method using pulse width modulation. The analog drive method has the advantage of being excellent in continuous tone expression, but there are problems in terms of long-term reliability of the liquid crystal element because high-precision electrical adjustment is necessary and high-frequency drive of the liquid crystal element is difficult. Have. On the other hand, the digital drive method has advantages such as easier electrical adjustment compared to the analog method and improved long-term reliability of the liquid crystal element for high-frequency drive, Inferior in key expression.

  Therefore, a third driving method that combines the advantages of the analog driving method and the digital driving method, which enables both continuous gradation expression by amplitude modulation and long-term reliability by high-frequency driving of liquid crystal elements, is desired. ing. In the third driving method, it is necessary to correct the deterioration of the uniformity (uniformity) of the display image due to the variation in the threshold voltage of the transistor.

  The present invention has been made in view of the above points, and a liquid crystal display device and a driving method thereof that minimize deterioration of display image uniformity (uniformity) due to variations in threshold voltages of source follower transistors in a pixel. The purpose is to provide.

In order to achieve the above object, the liquid crystal display device according to the first aspect of the present invention is provided at an intersection where a plurality of sets of data lines and a plurality of gate lines intersect each other. Are provided for each of a plurality of pixels each having a liquid crystal element and a plurality of sets of data lines, and after being turned on at the beginning of each horizontal scanning period, a set of two lines until it is turned off. A plurality of analog switches that supply a positive video signal to one of the data lines and a negative video signal to the other data line in units of a plurality of data lines and a plurality of data lines Vertical direction driving means for performing vertical direction driving for selecting each gate line for each horizontal scanning period, and continuously changing in one horizontal scanning period from the black level to the white level, and the level change directions are set opposite to each other. Positive polarity lamp signal and negative A ramp signal generating means for generating a sex ramp signal, a latch means for latching a digital video signal composed of video data of N bits (N is a natural number of 2 or more) in units of one line, and latched by the latch means. The value of each pixel of one line of the digital video signal and the counter value that makes a round within one horizontal scanning period are compared in units of pixels. The analog switch provided is turned off, and the potential of the positive polarity ramp signal and the polarity negative polarity ramp signal immediately before the analog switch is turned off is output to a set of data lines connected to the analog switch that is turned off. Comparing means for sampling and holding the potential in the holding capacitor of the pixel connected to the data line, and a positive polarity lamp for each of the plurality of pixels After sampling and holding the signal, the difference between the drive voltage applied to the pixel drive electrode of the liquid crystal element through the first source follower transistor with respect to the average value Vap of all the pixels is Xn, and the negative ramp signal is sampled and held. The difference between the drive voltage applied to the pixel drive electrode of the liquid crystal element through the source follower transistor and the average value Vam of all the pixels is Yn, the coefficient is α, the maximum value of the positive polarity ramp signal and the negative polarity ramp signal is Rmax, and the minimum When the value is Rmin, the following equation: Dcor = {(Yn−Xn) / 2} / {(Rmax−Rmin) / 2 ^N }
−α × | {(Vap−Vam) / 2} − {(Yn−Xn) / 2} |
Correction gradation addition means for adding correction gradation data Dcor calculated in pixel units to an N-bit digital video signal in pixel units and latching the data in a latch means.

In order to achieve the above object, the liquid crystal display device of the second invention includes a plurality of pixels of the first invention,
A liquid crystal element in which a liquid crystal layer is sandwiched between an opposing pixel drive electrode and a common electrode, and one data line to which a positive polarity ramp signal is supplied out of a set of two data lines. Is supplied as a positive video signal, the first sampling and holding means for sampling and holding the positive ramp signal, and a negative ramp signal among a set of two data lines. A second sampling and holding means for supplying a potential held on the other data line to which the negative polarity is supplied as a negative video signal, sampling the negative ramp signal and holding the same for a certain period, and a first sampling And a first source follower transistor connected between the holding means and the pixel driving electrode, and a second source connected between the second sampling and holding means and the pixel driving electrode. The pixel inspection switching connected between the follower transistor and one of the two data lines of the same set and the pixel drive electrode, and is turned off in the pixel writing mode and turned on in the pixel reading mode. Means, and in the pixel readout mode, the voltage of the positive-polarity ramp signal held in the first sampling and holding means applied to the pixel driving electrode through the first source follower transistor, and the pixel through the second source follower transistor After reading one voltage of the negative ramp signal held in the second sampling and holding means applied to the drive electrode to one data line through the inspection switching means, the voltage of the other ramp signal is read Switching means for reading to one data line via the inspection switching means It is characterized in.

In order to achieve the above object, a driving method of a liquid crystal display device according to a third aspect of the present invention is a latch for latching a digital video signal composed of N bits (N is a natural number of 2 or more) of the same gradation in units of one line. A step of comparing each pixel value of one line of the digital video signal latched in the latch step with a counter value that makes a round in one horizontal scanning period, and two data lines Among a plurality of pixels each having a liquid crystal element provided at an intersection where a plurality of sets of data lines and a plurality of gate lines intersect with each other, pixels having a matching comparison result obtained in the comparison step When one of the pair of connected data lines is immediately before the comparison result of the coincidence of the positive polarity ramp signal that continuously changes from one of the black level and the white level to the other within one horizontal scanning period. Is output to the holding capacitor of the pixel, and the positive polarity ramp signal is connected to the other of the pair of data lines connected to the pixel for which the comparison result of matching is obtained in the second step. Is that the level change direction is set in the opposite direction and the potential at the time immediately before the comparison result of the comparison of the negative ramp signal whose level changes continuously within one horizontal scanning period is output, and the storage capacitor of the pixel A holding step for sampling and holding the positive voltage ramp signal held in the holding capacity of each pixel by the holding step, and the holding voltage of the positive polarity ramp signal among the positive polarity ramp signal and the first source follower in the pixel The first driving voltage when applied to the pixel driving electrode of the liquid crystal element in the same pixel through the transistor and the holding voltage of the negative ramp signal are used as the second source follower in the pixel. A measuring step of measuring each of the second driving voltages when applied to the pixel driving electrodes of the liquid crystal elements in the same pixel through the transistor for all pixels, and the first and second driving of all the pixels measured in the measuring step An intermediate potential calculating step of calculating an intermediate potential {(Vap−Vam) / 2} between the average value Vap of the first drive voltage of all the pixels and the average value Vam of the second drive voltage of all the pixels based on the voltage; For each of the plurality of pixels, the difference Xn of the first drive voltage of each pixel with respect to the average value Vap of the first drive voltage and the second drive voltage of each pixel with respect to the average value Vam of the second drive voltage Based on the difference calculating step for calculating the difference Yn, the intermediate potential {(Vap−Vam) / 2} calculated in the intermediate potential calculating step, and the differences Xn and Yn for each pixel calculated in the difference calculating step. The coefficient α When the maximum value of the positive polarity ramp signal and the negative-polarity ramp signal was Rmin Rmax, the minimum value, the following equation Dcor = {(Yn-Xn) / 2} / {(Rmax-Rmin) / 2 N}
−α × | {(Vap−Vam) / 2} − {(Yn−Xn) / 2} |
A correction gradation calculation step (S6, S7) for calculating the correction gradation Dcor in pixel units by
An addition output step of adding the data of the correction gradation Dcor to the N-bit digital video signal in units of pixels and outputting it as a digital video signal to be displayed.

  According to the present invention, it is possible to minimize deterioration of display image uniformity (uniformity) due to variations in threshold voltages of source follower transistors in a pixel.

It is a block diagram of one embodiment of the liquid crystal display device of the present invention. FIG. 2 is an equivalent circuit diagram of an example of one pixel in FIG. 1. 3 is a timing chart for explaining the operation of FIG. 2. It is explanatory drawing of an example of a positive video signal and a negative video signal. 2 is a timing chart for explaining the operation of FIG. 1. FIG. 3 is a diagram illustrating an example of input / output characteristics of a source follower transistor in the pixel of FIG. 2. It is a flowchart of the principal part of one Embodiment of the liquid crystal display device of this invention, and its drive method. It is a figure which shows an example of the drive voltage of arbitrary four pixels A, B, C, D among all the pixels temporarily hold | maintained at the correction voltage calculation part in FIG. FIG. 9 is a diagram illustrating a state in which correction voltages are added and subtracted when the pixels A, B, C, and D in FIG. 8 are controlled so that the difference potential between the positive drive voltage and the negative drive voltage is constant. FIG. 9 is a diagram illustrating a drive voltage when the pixels A, B, C, and D of FIG. 8 are controlled so that the difference potential between the positive side drive voltage and the negative side drive voltage is constant. When the pixels A, B, C, and D in FIG. 8 are controlled so that the difference potential between the positive drive voltage and the negative drive voltage is constant, the intermediate potential of the drive voltage of each pixel and the average intermediate potential of all the pixels FIG. FIG. 9 is a diagram illustrating drive voltages when the positive side drive voltage and the negative side drive voltage are controlled according to an embodiment of the present invention for the pixels A, B, C, and D in FIG. 8. It is an equivalent circuit schematic of an example of the conventional liquid crystal display element.

  Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a configuration diagram of an embodiment of a liquid crystal display device according to the present invention. As shown in the figure, the liquid crystal display device 100 of the present embodiment includes shift register circuits 101a and 101b, a one-line latch circuit 102, a comparator 103, a gradation counter 104, an analog switch 105, and a horizontal direction. M, n pixels vertically arranged in a matrix, 106 _{11 to} 106 _nm , timing generator 107, polarity switching control circuit 108, vertical shift register and level shifter 109, inverter INV, 2 It consists of n sets of AND circuits, each of which includes AND circuits AND-1 and AND-2. Further, the liquid crystal display device 100 includes a ramp signal generator 110, a correction voltage calculation unit 111, a correction gradation calculation unit 112, and a correction gradation addition unit 113.

  The horizontal driver circuit including the shift register circuits 101 a and 101 b, the one-line latch circuit 102, the comparator 103, and the gray scale counter 104 constitutes a data line driving circuit together with the analog switch 105. Note that the comparator 103 is shown as one block in FIG. 1 for simplicity of illustration, but is actually provided for each pixel column.

The analog switch 105 shown in FIG. 1 has a configuration in which a pair of sampling analog switches for positive polarity and negative polarity are arranged for each pixel column. The pixels 106 _{11 to} 106 _nm shown in FIG. 1 have m sets of data lines (D1 + and D1-,..., Dm + and Dm−) and n gate lines (G1,. .., arranged at the intersection with Gn). Each of these n · m 106 ₁₁ to 106 _nm (hereinafter, collectively referred to as a pixel is referred to as 106) has a configuration shown in FIG. 2, for example.

  FIG. 2 shows an equivalent circuit diagram of an example of one pixel in the liquid crystal display device according to the present invention. In the figure, one pixel 106 includes pixel selection transistors Q1 and Q2 for writing positive and negative pixel signals, and two independent holding capacitors C1 that hold image signal voltages of respective polarities in parallel. And C2, transistors Q3 to Q6, Q9 and Q10, and a liquid crystal element LC having the same configuration as that of the liquid crystal element shown in FIG. 13, which includes a reflective electrode (hereinafter referred to as a pixel drive electrode) PE and the like. Transistors Q1-Q6, Q9, and Q10 are N-channel field effect transistors (FETs).

  The transistor Q1 and the holding capacitor C1 constitute a first sampling and holding means that samples a positive ramp signal described later and holds it for a certain period. The transistor Q2 and the holding capacitor C2 constitute second sampling and holding means for sampling a negative ramp signal, which will be described later, and holding it for a certain period. The transistor Q3 is a first source follower transistor, and the transistor Q4 is a second source follower transistor, each of which constitutes an impedance conversion source follower circuit.

  The transistor Q5 whose drain is connected to the source of the transistor Q3 and the transistor Q6 whose drain is connected to the source of the transistor Q4 are switching transistors. The sources of the transistors Q5 and Q6 are connected to the pixel drive electrode PE of the liquid crystal element LC. The transistor Q9 is a constant current load transistor that forms a source follower buffer. The transistor Q9 is arranged at the subsequent stage of the polarity switching switching transistors Q5 and Q6, that is, at the node of the pixel drive electrode PE, and has both positive and negative source follower circuits. Functions in common as a load.

  The pixel portion data line is composed of a pair of positive data line D + and negative data line D- for each pixel, and video signals having different polarities sampled by a data line driving circuit (not shown) are provided. Supplied. The drain terminals of the pixel selection transistors Q1 and Q2 are respectively connected to the positive polarity data line Di + (any one of D1 + to Dm + in FIG. 1) and the negative polarity data line Di− (D1 to Dm− in FIG. 1). Any one) is connected, and each gate terminal is connected to the row scanning line Gj (corresponding to any one of the gate lines G1 to Gn in FIG. 1) for the same row.

  Further, a transistor Q10 is provided as a switching means for inspection between the pixel drive electrode PE and the positive video signal writing data line Di +. In each of the transistors Q10 in a plurality of pixels in the same row, a gate that is a read control terminal is commonly wired to a selection line RD of the read switch. The selection control signal applied to the gate of the transistor Q10 through the selection line RD controls the transistors Q10 in all the pixel rows to be in an off state in the normal image display mode (hereinafter also referred to as pixel writing mode). In the mode (hereinafter also referred to as pixel readout mode), the transistors Q10 in the pixel row to be inspected are sequentially turned on in units of pixel rows. Here, the pixel inspection mode is a mode in which pixel values are read out to the data line pixel by pixel from a pixel portion in which a plurality of pixels are arranged in a matrix, and the presence or absence of defects is inspected pixel by pixel. Accordingly, in the pixel inspection mode, the video signal for writing is not input to the data line, and the pixel portion is set to the reading mode.

  The row selection means in such a pixel inspection mode is realized with the same configuration as that of the vertical driving circuit formed of a shift register, similarly to the writing of the video signal. It is also possible to share the shift register of the vertical driving circuit for signal writing with the row selection means in the pixel inspection mode.

Returning to FIG. The pixels 106 are provided in n rows in the vertical direction and m columns in the horizontal direction. A gate line G1 and a read switch selection line RD1 are commonly connected to the m pixels 106 _{11 to} 106 _1m in the first row. A gate line Gn and a read switch selection line RDn are commonly connected to the m pixels 106 _{n1 to} 106 _nm in the n-th row. Similarly, in each of the m pixels 106 _{i1 to} 106 _im in each other row i, the gate line Gi and the read switch selection line RDi are commonly connected to each pixel row.

  The AND 1-1 performs a logical AND operation on the selection control signal from the control terminal WT / RD and the vertical driving signal from the output terminal of the first row of the vertical shift register and level shifter 109, and outputs the result to the gate line G1. AND1-2 performs an AND operation on the signal obtained by logically inverting the selection control signal from the control terminal WT / RD by the inverter INV and the vertical driving signal from the output terminal of the first row of the vertical shift register and level shifter 109. And output to the read switch selection line RD1.

  ANDn-1 performs a logical AND operation on the selection control signal from the control terminal WT / RD and the vertical driving signal from the output terminal of the nth row of the vertical shift register and level shifter 109, and outputs the result to the gate line Gn. ANDn-2 performs a logical AND operation on the signal obtained by logically inverting the selection control signal from the control terminal WT / RD by the inverter INV and the vertical driving signal from the output terminal of the nth row of the vertical shift register and level shifter 109. And output to the selection line RDn of the read switch.

  Similarly, each pixel circuit in the other pixel row i performs a logical product operation on the selection control signal and the vertical direction drive signal from the i-th row output terminal of the vertical shift register and level shifter 109 and outputs the result to the gate line Gi. An AND circuit ANDi-1, a signal obtained by logically inverting the selection control signal by the inverter INV, and a vertical direction drive signal from the output terminal of the i-th row of the vertical shift register and the level shifter 109 are subjected to a logical product operation and read switch Is connected to an AND circuit ANDi-2 that outputs to the selection line RDi. These selection lines RD1 to RDn are connected to the gate of the transistor Q10 shown in FIG. 2 in the pixels 106 in the same pixel row.

  The control terminal WT / RD is supplied with a high-level selection control signal in the normal image display mode (pixel writing mode) and supplied with a low-level selection control signal in the pixel inspection mode (pixel readout mode). . A normal image display mode (pixel writing mode) is realized by a gate function of AND circuits (AND1-1, AND1-2,..., ANDn-1, ANDn-2) configured in each output stage of the vertical shift register and level shifter 109. ) Sometimes selection pulses are sequentially output to the gate lines G1,.

  On the other hand, in the pixel inspection mode (pixel readout mode), the gate switch function of the AND circuit (AND1-1, AND1-2,..., ANDn-1, ANDn-2) selects the read switch selection line RD1,. .., Selection pulses are sequentially output to RDn. Thus, the mode can be switched by sharing the vertical shift register and the level shifter 109 by the selection control signal input via the control terminal WT / RD.

  In the pixel inspection mode, the transistor Q10 shown in FIG. 2 in the pixel 106 in the selected pixel row is turned on by a selection pulse applied to the gate through the selection line RD of the readout switch. As a result, the pixel drive electrode PE and the data line become conductive, and the pixel drive electrode voltage is output to the data line. At this time, when the buffer amplifier (load element) of the pixel circuit in the selected row in the pixel inspection mode is activated and one of the switching transistors Q5 and Q6 is turned on, the pixel drive electrode is driven by the buffer output during that period. Thus, the pixel drive electrode voltage applied to the pixel drive electrode can be read out to the data line side as a voltage output.

  The pixel drive electrode voltage read to the data line side is supplied to the video data common input terminal (Ref_Ramp (+) in the example of FIG. 1) via the analog switch 105 by driving the horizontal driver circuit of FIG. Output as a series signal. By detecting this time series signal, inspection of the pixel circuit (detection of pixel defects) can be performed.

  In the conventional active matrix liquid crystal display device, the pixel is driven by the voltage held in the form of the charge held in the holding capacitor, so the pixel readout inspection is a highly accurate detection that detects a minute current change during charge movement. Whereas an amplifier or the like is required, in the combination of the pixel circuit according to the present embodiment and its inspection / reading means, the voltage of the pixel drive electrode, that is, the voltage of the pixel drive electrode driven with a low output impedance by the buffer amplifier output itself Therefore, pixel defect detection and pixel characteristic detection can be performed more easily.

  Next, an outline of the AC drive control of the pixel 106 will be described with reference to the timing chart of FIG. 3A shows the vertical synchronization signal VD, and FIG. 3B shows a load characteristic control signal of the wiring B applied to the gate of the transistor Q9 in the pixel 106 of FIG. 3C shows the gate control signal of the wiring S + applied to the gate of the switching transistor Q5 that transfers the positive drive voltage in the pixel 106, and FIG. 3D shows the negative electrode in the pixel 106. 4 shows each signal waveform of a gate control signal of the wiring S− applied to the gate of the switching transistor Q6 that transfers the active drive voltage.

  FIG. 4 shows the relationship from the black level to the white level of the positive video signal I and the negative video signal II written to the pixel. The positive video signal I has a black level when the level is minimum and a white level when the level is maximum, whereas the negative video signal II has a white level when the level is minimum and a black level when the level is maximum. The inversion center of the positive video signal I and the negative video signal II is indicated by III.

  In FIG. 4, the positive polarity video signal I is the black level of the minimum gradation when the level is minimum, the white level of the maximum gradation when the level is maximum, and the negative polarity video signal II is the maximum level when the level is minimum. In this example, the tone white level and the black level of the minimum gradation when the level is the maximum are shown. However, in the pixel circuit of the liquid crystal display device of the present invention, the positive polarity video signal I is the white level of the maximum gradation when the level is minimum, the black level of the minimum gradation when the level is maximum, and the negative polarity video signal II. May be the black level of the minimum gradation when the level is the minimum, and the white level of the maximum gradation when the level is the maximum.

  2, the positive polarity side switching transistor Q5 is turned on while the gate control signal of the wiring S + shown in FIG. 3C is at a high level, and the load characteristic control signal supplied to the wiring B during this period is shown in FIG. As shown in FIG. 5B, when the level is high, the source follower buffer circuit becomes active, and the pixel drive electrode PE node is charged to the positive video signal level. When the potential of the pixel drive electrode PE is fully charged, the load characteristic control signal of the wiring B is set to a low level, and at that time, the gate control signal of the wiring S + is also switched to a low level. The drive electrode PE is in a floating state, and a positive drive voltage is held in the liquid crystal capacitor.

  On the other hand, when the gate control signal of the wiring S− shown in FIG. 3D is at a high level, the negative polarity side switching transistor Q6 is turned on, and the load characteristic control signal supplied to the wiring B during this period is shown in FIG. ), The source follower buffer circuit becomes active and the pixel drive electrode PE node is charged to the negative video signal level. When the potential of the pixel drive electrode PE is fully charged, the load characteristic control signal of the wiring B is set to the low level, and the gate control signal of the wiring S- is also switched to the low level at that time. The drive electrode PE is in a floating state, and the negative drive voltage is held in the liquid crystal capacitor.

  Thereafter, in synchronization with the switching in which the switching transistors Q5 and Q6 are alternately turned on, the operation of intermittently activating the transistor Q9 by the load characteristic control signal of the wiring B is repeated, thereby driving the pixel of the liquid crystal element LC. As shown in FIG. 3E, a drive voltage VPE converted into an alternating current with each of positive and negative video signals is applied to the electrode PE.

  Further, Vcom shown in FIG. 3F represents a voltage applied to the common electrode CE formed on the counter substrate of the liquid crystal display device. The substantial AC drive voltage of the liquid crystal display LCM is a difference voltage between the applied voltage Vcom of the common electrode CE and the applied voltage of the pixel drive electrode PE. In the present embodiment, as shown in FIG. 3F, the applied voltage Vcom of the common electrode CE is synchronized with pixel polarity switching with respect to a reference level substantially equal to the inversion reference level Vc of the pixel drive electrode potential. Inverted. As a result, the absolute value of the potential difference between the applied voltage Vcom of the common electrode CE and the applied voltage of the pixel drive electrode PE is always the same, and the liquid crystal display LCM has an AC voltage having no DC component as shown in FIG. VLC is applied.

  Further, the gate control signal supplied alternately to the wirings S + and S- can give the liquid crystal drive signal that is inverted to the positive polarity and the negative polarity to the pixel drive unit by alternately turning on the switching transistors Q5 and Q6. . In the conventional active matrix liquid crystal display device, the polarity inversion can be realized only in the vertical scanning period, whereas in the present embodiment, the pixel circuit itself has a polarity inversion function, which can be controlled at high speed. Therefore, AC driving at a high frequency without restriction of the vertical scanning frequency is possible.

  Returning again to FIG. The polarity switching control circuit 108 shown in FIG. 1 is based on the timing signal from the timing generator 107, the positive polarity gate control signal for the wiring S +, the negative polarity gate control signal for the wiring S-, and the wiring B. Each of the load characteristic control signals is output.

  Next, the operation in the normal image display mode (pixel writing mode) of FIG. 1 will be described with reference to the timing chart of FIG. In FIG. 1, pixel data (DATA) of N bits (N is a natural number of 2 or more) shown in FIG. 5B, which is synchronized with the horizontal synchronizing signal HD shown in FIG. The digital video signal is input to the shift register circuits 101a and 101b through a correction gradation adding unit 113, which will be described later, and sequentially developed as data for one line. When the development for one line is completed, the one-line latch circuit 102 is obtained. Is latched on.

  Of the pixel data (DATA) shown in FIG. 5 (B), horizontal even-numbered column pixel data DATA (even) shown every other white background is supplied to the shift register circuit 101a, and the remaining hatched portions. Every other odd-numbered pixel data DATA (odd) in the horizontal direction is supplied to the shift register circuit 101b. This is because it is easy to cope with high-speed operation on a high-resolution panel.

  The one-line latch circuit 102 is a one-line period of the same line composed of odd-numbered column pixel data DATA (odd) output from the shift register circuit 101a and even-numbered column pixel data DATA (even) output from the shift register circuit 101b. After the pixel data DATA is held as schematically shown in FIG. 5D, it is supplied to the first data input section of the comparator 103 of each pixel column.

  The gradation counter 104 counts the clock Count-CK shown in FIG. 5E, and as shown in FIG. 5F, a plurality of gradation values make a round from the minimum value to the maximum value within the horizontal scanning period. A count value (reference gradation data) C-out is output for each horizontal scanning period and supplied to the second data input unit of the comparator 103 of each pixel column. The comparator 103 compares the value of the input pixel data DATA of the first data input unit with the value of the input reference gradation data C-out (gradation value) of the second data input unit, and the two values match. A coincidence pulse is generated and output at the same timing.

  Of the pair of sampling analog switches SW + and SW− for positive polarity and negative polarity constituting the analog switch 105, the sampling analog switch SW + for positive polarity has a ramp signal connected to the input-side common wiring. A reference ramp voltage Ref_Ramp (+), which is a positive polarity ramp signal, is applied from the generator 110. On the other hand, the negative sampling analog switch SW− is applied with the reference ramp voltage Ref_Ramp (−), which is a negative ramp signal, from the ramp signal generator 110 to the input-side common wiring.

  Of the reference ramp voltages Ref_Ramp (+) and Ref_Ramp (−), Ref_Ramp (+) increases in the level from the black level to the white level in the horizontal scanning period as shown in FIG. It is a periodic sweep signal that changes to. On the other hand, the reference ramp voltage Ref_Ramp (−) is a periodic sweep signal that changes in a direction in which the level decreases from the black level of the video to the white level in the horizontal scanning period as shown in FIG. . Therefore, the reference lamp voltages Ref_Ramp (+) and Ref_Ramp (−) have an inversion relationship with respect to a predetermined reference potential.

  The analog switch 105 receives the SW-Start signal shown in FIG. 5 (G), turns on at the same time at the start of each horizontal scanning period, and turns off when a matching pulse is received from the comparator 103 of the corresponding pixel. Open / close control is performed on a pixel-by-pixel basis so as to shift to

  In the timing chart of FIG. 5, as an example, the opening / closing timing of the analog switch 105 of the pixel column corresponding to the pixel data DATA of the gradation level k is illustrated as a waveform SPk shown in FIG. As a result, the reference ramp voltage Ref_Ramp (+) at the time when the pair of sampling analog switches for positive polarity and negative polarity constituting the analog switch 105 of the pixel column are simultaneously turned off in response to the coincidence pulse. And Ref_Ramp (−) corresponding levels (points P and Q in FIGS. 5I and 5J) are simultaneously sampled and output to the pixel data lines D (+) and D (−) of the pixel column. Is done. The reference ramp voltage levels at points P and Q in FIGS. 5I and 5J are analog voltages obtained by digital-analog conversion of the pixel data DATA at the gradation level k.

  The analog switches 105 are all turned on at the same time at the beginning of each horizontal scanning period. The timing at which they are turned off, that is, the timing at which the reference lamp voltage is sampled and held depends on the pattern to be displayed at that time. It differs for each provided pixel, and may be all simultaneous or separate. The turn-off order is not fixed, and the turn-off order varies depending on the pattern. The liquid crystal display device 100 according to the present embodiment has a feature that the linearity is good by the operation of the DA conversion method using the ramp signal.

  In the pixel circuit of FIG. 2, in the source follower transistors Q3 and Q4, as shown in FIG. 6, the input voltage Vin to the gate is equal to or higher than the threshold voltage Vth, and a voltage is output from the source according to the input voltage. The output voltage Vout is saturated at an input voltage equal to or higher than a predetermined value. However, the threshold voltage Vth of the above input / output characteristics varies from transistor to transistor due to manufacturing process variations. Therefore, even if data of the same gradation (reference ramp voltage having the same value) is given to the pixel, the positive reference ramp voltage is obtained by sampling the input / output characteristics of the source follower transistors Q3 and Q4 for each pixel. The pixel drive electrode voltage is different from the pixel drive electrode voltage obtained by sampling the negative reference ramp voltage. As a result, the display luminance varies, and the display uniformity is lowered.

  The liquid crystal display device 100 according to the present embodiment is characterized by a configuration that suppresses the decrease in display uniformity to a minimum, and this configuration and operation will be described in detail below.

  FIG. 7 is a flowchart for explaining the operation of the main part of an embodiment of the liquid crystal display device and the driving method thereof according to the present invention. Before the operation of the flowchart of FIG. 7 starts, the liquid crystal display device 100 is driven in advance in the pixel writing mode (image display mode) described above, and the same voltage is written in all the pixels 106. It is assumed that a positive sampling voltage and a negative sampling voltage of the same gradation are held as reference voltages in the holding capacitors C1 and C2 shown in FIG.

  Subsequently, the liquid crystal display device 100 is driven in the pixel reading mode (image inspection mode) described above, and the holding voltages (reference voltages) of the holding capacitors C1 and C2 of the pixels 106 in the selected row pass through the read-only wiring. To be read out. That is, in the pixel readout mode, the transistor Q10 shown in FIG. 2 in the pixel 106 in the selected pixel row is turned on by a selection pulse applied to the gate via the selection line RD of the readout switch. The transistor Q5 is turned on by a high level positive polarity gate control signal applied to its gate.

  As a result, the reference voltage held in the holding capacitor C1 is supplied to the pixel drive electrode PE on the positive polarity side (hereinafter referred to as the pixel drive voltage PE) of the liquid crystal element LC via the gate and source of the transistor Q3 and the drain and source of the transistor Q5. , Simply referred to as a drive voltage) to drive the liquid crystal element LC. The drive voltage on the positive polarity side applied to the pixel drive electrode at that time is read from the data line Di + to the read-only wiring of the panel through the transistor Q10 as a voltage output. Therefore, the drive voltage on the positive polarity side is a voltage reflecting variations in the threshold voltage of the transistor Q3.

  The correction voltage calculation unit 111 in FIG. 1 outputs a time series signal to the video data common input terminal (Ref_Ramp (+) in the example of FIG. 1) via the analog switch 105 by driving the horizontal driver circuit in FIG. The drive voltage on the positive polarity side for each pixel is temporarily held.

  Subsequently, the positive polarity gate control signal becomes low level, the transistor Q5 is turned off, and the transistor Q6 is turned on by the high level negative polarity gate control signal applied to the gate thereof. As a result, the reference voltage held in the holding capacitor C2 is applied as a negative drive voltage to the pixel drive electrode PE of the liquid crystal element LC via the gate and source of the transistor Q4 and the drain and source of the transistor Q6. The liquid crystal element LC is driven. The drive voltage on the negative polarity side applied to the pixel drive electrode at that time is read from the data line Di + to the read-only wiring of the panel through the transistor Q10 as a voltage output. Therefore, this negative side drive voltage reflects the variation in the threshold voltage of the transistor Q4.

  The correction voltage calculation unit 111 in FIG. 1 outputs a time series signal to the video data common input terminal (Ref_Ramp (+) in the example of FIG. 1) via the analog switch 105 by driving the horizontal driver circuit in FIG. The drive voltage on the negative polarity side for each pixel is temporarily held.

  It is assumed that the common electrode voltage Vcom of the liquid crystal element LC does not vary, and the liquid crystal driving voltage corresponds to the driving voltage. Therefore, the driving voltage is measured, and a correction voltage Vcor described later is calculated based on the measurement result. It shall be. However, it goes without saying that the correction voltage Vcor may be calculated based on the liquid crystal drive voltage obtained by subtracting the known common electrode voltage Vcom from the measurement result.

FIG. 8 shows an example of drive voltages of arbitrary four pixels A, B, C, and D among all the pixels 106 temporarily held in the correction voltage calculation unit 111 by the above operation. FIG. 8A shows the drive voltage V _{A1 on} the positive polarity side and the drive voltage V _A2 on the negative polarity side of the pixel A. Similarly, FIG. 8B shows the drive voltage V _B1 on the positive polarity side of the pixel B and the drive voltage V _B2 on the negative polarity side, and FIG. 8C shows the drive voltage V _C1 on the positive polarity side of the pixel C. the driving voltage V _C2 of sexual side, FIG. 8 (d) shows a driving voltage V _D1 of the positive polarity side of the pixel D, the negative polarity side drive voltage V _D2, respectively.

In this state, the correction voltage calculation unit 111 calculates an average value Vap of the positive side drive voltages (hereinafter also referred to as positive side voltages) of all the pixels temporarily held (step S1 in FIG. 7). Subsequently, the correction voltage calculation unit 111 calculates the average value Vam of the negative polarity side drive voltages (hereinafter also referred to as negative side voltages) of all the pixels temporarily held (step S2 in FIG. 7). In the example of FIG. 8, the drive voltage V _A1 on the positive polarity side of the pixel A coincides with the average value (average potential) Vap of the positive voltage on all the pixels. Further, the negative side drive voltage V _A2 of the pixel A and the negative side drive voltage V _{B2 of the} pixel B coincide with the average value (average potential) Vam of the negative side voltages of all the pixels. However, in the other pixels B, C, and D, the drive voltage on the positive polarity side does not match the average value (average potential) Vap of the positive voltage on all the pixels, and the negative side of the pixels C and D. Is not equal to the average value (average potential) Vam of the negative side voltages of all the pixels.

  Next, the correction voltage calculation unit 111 calculates an intermediate potential (= (Vap−Vam) / 2) between the average value Vap of the positive side voltages of all the pixels and the average value Vam of the negative side voltages of all the pixels. (Step S3 in FIG. 7). Subsequently, the correction voltage calculation unit 111 obtains a difference (= Xn) with respect to the average value Vap of the positive side voltage of all the pixels for each pixel 106 (step S4 in FIG. 7), and the negative polarity of all the pixels for each pixel 106. A difference (= Yn) with respect to the average value Vam of the side voltage is obtained (step S5).

  Then, the correction voltage calculation unit 111 calculates the intermediate potential between the difference Xn and the difference Yn for each pixel 106 as the correction voltage Vcor (step S6 in FIG. 7). The correction voltage Vcor is calculated by the following equation because the change in potential of the drive voltage is in the opposite direction for the same gradation on the positive polarity side and the negative polarity side.

Vcor = {Yn + (-Xn)} / 2 (1)
Here, when the drive voltage on the positive polarity side and the drive voltage on the negative polarity side of each pixel are corrected on the basis of the correction voltage Vcor, as shown in FIGS. For the pixels B, C, and D that do not match the average values Vap and Vam of the pixels, the correction potentials b1, b2, c1, c2, d1, and d2 are added or subtracted, as shown in FIGS. Thus, the difference potential between the drive voltage on the positive polarity side and the drive voltage on the negative polarity side becomes equal to the difference potential Vp (= Vt) between the average values Vap and Vam of all pixels. At this time, the drive voltage on the positive polarity side of the pixel B is V _B3 , the drive voltage on the negative polarity side is V _B4 , the drive voltage on the positive polarity side of the pixel C is V _C3 , and the drive voltage on the negative polarity side is V _C4 . The drive voltage on the positive polarity side of D is V _D3 , and the drive voltage on the negative polarity side is V _D4 . As shown in FIG. 10A, the drive voltage V _A1 on the positive polarity side of the pixel A originally matches the average value Vap of the positive polarity side voltage, and the drive voltage V _A2 on the negative polarity side is the negative voltage on the negative side. Therefore, the drive voltage is not changed.

  By the way, as described above, AC driving is indispensable in terms of reliability and the like for the liquid crystal element, but the driving voltage on the positive polarity side and the negative polarity side is set so as not to cause a difference in the light modulation rate in the liquid crystal element in the AC driving. And the average intermediate potential Vm of all the pixels must be the same.

  However, as shown in FIG. 10, the difference potential between the drive voltage on the positive polarity side and the drive voltage on the negative polarity side of each pixel is corrected to be equal to the difference potential Vp between the average values Vap and Vam of all pixels. In this case, the difference potential Vp between the drive voltage on the positive polarity side and the drive voltage on the negative polarity side of each pixel is a potential calculated from the average values Vap and Vam of all the pixels, so as shown in FIG. The intermediate potential (center potential) Vp / 2 of the drive voltages on the positive and negative sides of each pixel is different from the average intermediate potential Vm (= Vt / 2) of all the pixels. For this reason, the difference potential between the drive voltage on the positive polarity side and the drive voltage on the negative polarity side of each pixel is corrected so as to be equal to the difference potential Vp (= Vt) between the average values Vap and Vam of all the pixels. In the method, the light modulation rate in the liquid crystal element is not the same in each pixel, and as a result, it is difficult to make the display image uniform.

  Therefore, in the present embodiment, the correction gradation calculation unit 112 is caused by the shift of the intermediate potential between the drive voltage on the positive polarity side and the negative polarity side of each pixel from the correction voltage Vcor according to the equation (2). A correction gradation Dcor in which the luminance change is corrected is generated (step S7 in FIG. 7).

  That is, the correction gradation calculation unit 112 calculates the correction gradation Dcor of each pixel by the following equation, assuming that the maximum value of the reference lamp voltage is Rmax, the minimum value is Rmin, and the input video data is N bits.

Dcor = Vcor / {(Rmax−Rmin) / 2 ^N }
−α × | {(Vap−Vam) / 2} −Vcor |
= {(Yn-Xn) / 2} / {(Rmax-Rmin) / ^2N }
−α × | {(Vap−Vam) / 2} − {(Yn−Xn) / 2} | (2)
Here, the sign of the correction gradation Dcor indicates an increase / decrease in gradation, and α indicates a coefficient depending on factors such as the characteristics of the liquid crystal element, the cell structure, and the alignment film. The coefficient α is generally a fixed value in a liquid crystal display device in which parameters constituting the liquid crystal element are determined, but may be variable according to the temperature characteristics of the liquid crystal element.

  In the above equation (2), the first term on the right side indicates a value obtained by converting the correction voltage Vcor of the equation (1) into the gradation of the N-bit video data. As shown in FIG. 11, the gradation shown in the first term on the right side has the same difference potential Vp between the drive voltage on the positive polarity side and the drive voltage on the negative polarity side of each pixel. The intermediate potential Vp / 2 indicates a gradation that is shifted with respect to the intermediate potential Vm between the drive voltage on the positive polarity side and the drive voltage on the negative polarity side of all pixels.

  On the other hand, the second term on the right side of the equation (2) is an intermediate potential Vm (= (Vap−) between the average value Vap of the drive voltage on the positive polarity side of all pixels and the average value Vam of the drive voltage on the negative polarity side of all pixels. Vam) / 2) and the absolute value of the value obtained by subtracting the above-described difference Xn and the difference Yn between each pixel (that is, the average intermediate potential Vm of the positive side drive voltage and the negative side drive voltage of all pixels) , The value obtained by multiplying the coefficient α by the voltage corresponding to the deviation from the intermediate potential, which is the absolute value of the difference between the positive polarity side drive voltage and the negative polarity side drive voltage of each pixel and the intermediate potential Vp / 2. . The value of the second term on the right side is subtracted from the gradation of the first term on the right side as the light response characteristics of the liquid crystal element when the intermediate potential between the drive voltages on the positive and negative sides is shifted. This is because the direct current component is added to the drive voltage and becomes brighter than the normal state where the brightness is not corrected.

  The correction gradation adding unit 113 shown in FIG. 1 shifts the data of the correction gradation Dcor calculated for each pixel in the correction gradation calculation unit 112 by adding it to the N-bit input video data in units of pixels. The signals are alternately supplied to the register circuits 101a and 101b. The one-line latch circuit 102 is a one-line period of the same line composed of odd-numbered column pixel data DATA (odd) output from the shift register circuit 101a and even-numbered column pixel data DATA (even) output from the shift register circuit 101b. Is stored in the first data input section of the comparator 103 of each pixel column. As a result, in the image display mode, the analog voltage of each pixel 106 added to the data lines Di + and Di− by the correction gradation Dcor is output from the analog switch 105 and held in each pixel 106 as described above. .

FIG. 12 shows an example of the driving voltages of the four pixels A, B, C, and D described above among all the pixels 106 based on the pixel data to which the data of the correction gradation Dcor is added according to the present embodiment. FIG. 12A shows the drive voltage V _{A1 on} the positive polarity side and the drive voltage V _A2 on the negative polarity side of the pixel A. 12B shows the drive voltage V _{B5 on} the positive polarity side and the drive voltage V _B6 on the negative polarity side of the pixel _B , and FIG. 12C shows the drive voltage V _C3 on the positive polarity side of the pixel C and the negative polarity. the driving voltage V _C4 side, FIG. 12 (d) shows the drive voltage V _D3 of the positive polarity side of the pixel D, the negative polarity side drive voltage V _D4 respectively.

For the pixels B, C, and D whose drive voltage does not match the average value Vap or Vam of all the pixels, the drive voltage on the positive polarity side corrected by the correction voltage Vcor shown in FIGS. As shown in FIGS. 12B to 12D, V _B3 , V _C3 , and V _D3 are subtracted by the correction voltages b3, c3, and d3 to become V _B5 , V _C5 , and V _D5 . Further, the negative side drive voltages V _B4 , V _C4 , and V _D4 corrected by the correction voltage Vcor shown in FIGS. 10B to 10D are as shown in FIGS. 12B to 12D. The correction voltages b4, c4, and d4 are added to obtain V _B6 , V _C6 , and V _D6 . As a result, as shown in FIGS. 12A to 12D, the difference potential between the drive voltage on the positive polarity side and the drive voltage on the negative polarity side does not change with Va for the pixel A, but the pixels B and C , D change to Vb, Vc, Vd, respectively.

  According to the present embodiment, intermediate potential potentials Vb, Vc and Vd between the positive side drive voltage and the negative side drive voltage calculated for each pixel shown in FIGS. The potential is the same as the intermediate potential of the difference potential between the positive drive voltage and the negative drive voltage when corrected only by the correction voltage Vcor shown in FIGS. It does not coincide with the intermediate potential Vm between the drive voltage Vap on the positive polarity side of the pixel and the drive voltage Vam on the negative polarity side of all the pixels.

  However, in the present embodiment, the difference potentials Vb, Vc, Vd between the drive voltage on the positive polarity side and the drive voltage on the negative polarity side calculated for each pixel are the positive polarity when corrected only by the correction voltage Vcor. Compared with the difference potential between the drive voltage on the negative side and the drive voltage on the negative side, as shown in FIGS. 12B to 12D, the correction voltage shown in the second term on the right side of the equation (2) By decreasing by a certain amount (b3 + b4), (c3 + c4) and (d3 + d4), the luminance corresponding to the voltage corresponding to the amount of deviation from the intermediate potential is darkened. As a result, according to the present embodiment, luminance non-uniformity due to the shift in the intermediate potential of all the pixels 106 is greatly suppressed regardless of variations in the threshold voltages Vth of the transistors Q3 and Q4 for each pixel 106. The uniformity (uniformity) of the displayed image can be improved.

  The present invention is not limited to the above embodiment. For example, the liquid crystal display device 100 after product shipment does not include the correction voltage calculation unit 111 and the correction gradation calculation unit 112, and the manufacturer side In this case, the correction gradation may be obtained in advance in units of pixels, and only the correction gradation addition unit 113 that adds the correction gradations to the input video data in units of pixels may be provided.

100 liquid crystal display device 101a, 101b shift register circuit 102 1 line latch circuit 103 comparator 104 gradation counter 105 analog switches 106, 106 ₁₁ - 106 _nm pixel 107 timing generator 108 polarity switching control circuit 109 the vertical shift register / shifter 110 ramp signal Generator 111 Correction voltage calculation unit 112 Correction gradation calculation unit 113 Correction gradation addition unit D1 + to Dm +, Di +, D1- to Dm-, Di- data line G1 to Gn, Gj gate line B Load characteristic control signal line S + , S-gate control signal line PE pixel drive electrode CE common electrode LCM display (liquid crystal layer)
LC liquid crystal element Q1, Q2 pixel selection transistor Q3, Q4 source follower transistor Q5, Q6 switching transistor Q9 constant current load transistor Q10 inspection mode transistor C1, C2 signal holding capacitance

Claims (3)

A plurality of pixels each provided with a liquid crystal element provided at an intersection where a plurality of sets of data lines and a plurality of gate lines intersect each other, each including two data lines;
A positive video signal is provided for each of the plurality of sets of data lines and is turned on at the beginning of each horizontal scanning period and then on one of the two sets of data lines until it is turned off. And supplying a negative video signal to the other data line, a plurality of analog switches that perform a set unit for the plurality of data lines, and
Vertical driving means for performing vertical driving for selecting a plurality of the gate lines for each horizontal scanning period;
A ramp signal generating means for generating a positive polarity ramp signal and a negative polarity ramp signal that continuously change from a black level to a white level in one horizontal scanning period and whose level change directions are opposite to each other;
Latch means for latching a digital video signal composed of video data of N bits (N is a natural number of 2 or more) in units of one line;
The pixel value of one line of the digital video signal latched by the latch means is compared with a counter value that makes a round within one horizontal scanning period, and a coincidence pulse is output when they coincide, The analog switch provided in correspondence among the plurality of analog switches is turned off, and the positive-polarity ramp signal and the negative-polarity signal are connected to the set of data lines connected to the turned-off analog switch. A comparator that outputs a potential of the ramp signal immediately before the analog switch is turned off, and samples and holds the potential in a storage capacitor of the pixel connected to the data line;
For each of the plurality of pixels, after sampling and holding the positive-polarity ramp signal, the difference between the driving voltage applied to the pixel driving electrode of the liquid crystal element through the first source follower transistor and the average value Vap of all the pixels is expressed as Xn. After the negative ramp signal is sampled and held, the difference of the drive voltage applied to the pixel drive electrode of the liquid crystal element through the second source follower transistor with respect to the average value Vam of all the pixels is Yn, the coefficient is α, and the positive electrode When the maximum value of the sexiness ramp signal and the negative polarity ramp signal is Rmax, and the minimum value is Rmin, the following formula: Dcor = {(Yn−Xn) / 2} / {(Rmax−Rmin) / 2 ^N }
−α × | {(Vap−Vam) / 2} − {(Yn−Xn) / 2} |
And a correction gradation adding means for adding the data of the correction gradation Dcor calculated in pixel units to the N-bit digital video signal in pixel units and latching the data in the latch means. . Each of the plurality of pixels is
The liquid crystal element in which a liquid crystal layer is sandwiched between the pixel drive electrode and the common electrode facing each other;
Of the set of the two data lines, the potential held in one data line to which the positive polarity ramp signal is supplied is supplied as the positive polarity video signal, and the positive polarity ramp signal is sampled. First sampling and holding means for holding for a certain period of time;
The potential held in the other data line to which the negative ramp signal is supplied is supplied as the negative video signal, and the negative ramp signal is sampled. Second sampling and holding means for holding for a certain period of time,
The first source follower transistor connected between the first sampling and holding means and the pixel driving electrode;
The second source follower transistor connected between the second sampling and holding means and the pixel driving electrode;
Switching means for pixel inspection connected between one data line of the two data lines of the same set and the pixel drive electrode, turned off in the pixel writing mode, and turned on in the pixel reading mode; ,
In the pixel readout mode, the voltage of the positive polarity ramp signal held in the first sampling and holding means applied to the pixel drive electrode through the first source follower transistor, and the second source follower After one of the voltages of the negative ramp signal held in the second sampling and holding means applied to the pixel drive electrode through the transistor is read out to the one data line via the inspection switching means. The liquid crystal display device according to claim 1, further comprising: a switching unit that reads the voltage of the other ramp signal to the one data line via the inspection switching unit. A latch step for latching digital video signals of N bits (N is a natural number of 2 or more) of the same gradation in units of one line;
A comparison step of comparing the value of each pixel of one line of the digital video signal latched in the latching step with a counter value that makes a round in one horizontal scanning period in units of pixels;
Among a plurality of pixels each having a liquid crystal element provided at an intersection where a plurality of data lines and a plurality of gate lines intersect each other, each of which includes two data lines as a set, the same in the comparison step. The positive polarity ramp signal that continuously changes in one horizontal scanning period from one of the black level and the white level to the other on one of the set of data lines connected to the pixel for which the comparison result is obtained. Output the potential immediately before outputting the comparison result and sample and hold it in the storage capacitor of the pixel. Also, a set of data lines connected to the pixel for which a coincidence comparison result was obtained in the second step. On the other hand, the positive polarity ramp signal has a level change direction opposite to that of the positive polarity ramp signal, and the level of the negative polarity ramp signal continuously changing in one horizontal scanning period immediately before the output of the coincidence comparison result. potential A holding step of sampling stored in the storage capacitor of the pixel outputs,
Of the positive-polarity ramp signal and the negative-polarity ramp signal held in the retention capacitor of each pixel in the retention step, the retention voltage of the positive-polarity ramp signal is set to the same pixel through the first source follower transistor in the pixel. The first driving voltage when applied to the pixel driving electrode of the liquid crystal element and the holding voltage of the negative ramp signal are applied to the liquid crystal element in the same pixel through the second source follower transistor in the pixel. A measurement step of measuring each of the second drive voltages when applied to the pixel drive electrodes for all pixels;
Based on the first and second drive voltages of all the pixels measured in the measurement step, an average value Vap of the first drive voltage of all the pixels and an average value Vam of the second drive voltage of all the pixels An intermediate potential calculating step of calculating an intermediate potential {(Vap−Vam) / 2} of
For each of the plurality of pixels, the difference Xn of the first drive voltage of each pixel with respect to the average value Vap of the first drive voltage and the second value of each pixel with respect to the average value Vam of the second drive voltage. A difference calculating step for calculating a difference Yn between the drive voltages of
Based on the intermediate potential {(Vap−Vam) / 2} calculated in the intermediate potential calculation step and the differences Xn and Yn for each pixel calculated in the difference calculation step, the coefficient is α, When the maximum value of the positive polarity ramp signal and the negative polarity ramp signal is Rmax, and the minimum value is Rmin, the following expression Dcor = {(Yn−Xn) / 2} / {(Rmax−Rmin) / 2 ^N }
−α × | {(Vap−Vam) / 2} − {(Yn−Xn) / 2} |
A correction gradation calculation step for calculating the correction gradation Dcor in pixel units by:
An addition output step of adding the data of the correction gradation Dcor to the N-bit digital video signal in units of pixels and outputting it as a digital video signal to be displayed. .

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