JP2012023327A - Semiconductor device manufacturing method - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a reverse blocking insulated gate bipolar transistor (IGBT) in which a separation layer is formed by proton irradiation.

  A conventional IGBT (insulated gate type bipolar transistor) having a planar pn junction structure is used under a DC power source in an inverter circuit or a chopper circuit, which is a main application, so there is no problem as long as a forward breakdown voltage can be secured. In spite of the presence of reverse withstand voltage bonding, the junction end surface of the reverse withstand voltage junction has been made exposed on the side surface of the chip cut portion without considering the reliability from the element design stage.

  Recently, however, some DC (direct current) / AC conversion circuits, such as AC (alternating current) / AC conversion circuits, current type DC / AC conversion circuits, and new three-level circuits, which are direct link type conversion circuits such as matrix converters, etc. Therefore, it has been studied to use a switching element having a reverse breakdown voltage to reduce the size, weight, efficiency, speed response, and cost of a circuit. For this reason, an IGBT having a highly reliable reverse withstand voltage has been demanded.

  A reverse blocking type semiconductor device requires a reverse voltage blocking capability equivalent to a forward voltage blocking capability. In order to ensure this reverse blocking capability, a structure is intended to ensure reliability by extending the junction termination surface of the pn junction on the back collector side that maintains the reverse breakdown voltage to the surface of the semiconductor chip instead of the side surface of the chip cutting portion. There is a need to. Thus, the diffusion layer for changing the junction end surface of the pn junction on the back collector side from the side surface to the surface is the separation layer.

  FIG. 5 is a cross-sectional view of a principal part of a semiconductor substrate showing a method for forming a conventional reverse blocking IGBT separation layer in the order of manufacturing steps. FIG. 5 shows a method of forming a separation layer by coating diffusion. First, a thermal oxide film 2 having a film thickness of about 2.5 μm is formed as a dopant mask on a semiconductor substrate (hereinafter referred to as wafer 1) (FIG. 5A). Next, an opening 3 for forming a separation layer is formed in the thermal oxide film 2 by patterning and etching (FIG. 5B). Next, a boron source 4 is applied to the opening 3 and then heat treatment is performed at a high temperature for a long time in a diffusion furnace to form a p-type diffusion layer having a depth of about several hundred μm (FIG. 5C). )). Thereafter, although not shown in FIG. 5C, the MOS gate structure 14 and the emitter electrode 8a are formed on the front surface side of the wafer 1 as shown in the cross-sectional view of the main part in FIG. As shown in FIG. 5C, the wafer 1 is thinned by grinding to the position of the broken line reaching the p-type diffusion layer. When the back surface structure composed of the p collector layer 7 and the collector electrode 8b shown in the cross-sectional view of the main part of FIG. 6 is formed on the ground surface, the p-type diffusion layer is connected to the p collector layer 7 and the separation layer 5 Become. As a result, the junction end surface of the collector junction is moved to the surface side by the separation layer 5. When the wafer 1 is cut into a lattice shape along the scribe line 6 located at the center of the separation layer 5, a reverse blocking IGBT chip 200 is formed.

  FIG. 7 is a cross-sectional view of a main part of a semiconductor substrate showing different methods for forming a separation layer of a conventional reverse blocking IGBT in the order of manufacturing steps. FIG. 7 shows a method for avoiding the high-temperature and long-time heat treatment necessary for forming the p-type diffusion layer as described in FIG. 5, and a trench having a high aspect ratio is dug in a semiconductor substrate. In this method, a diffusion layer is formed on the side wall to form a separation layer. First, a thick oxide film 2 of several μm is formed on the surface of the wafer 1 (FIG. 7A). Next, a trench 11 having a depth of about several hundred μm from the surface of the wafer 1 is formed by dry etching (FIG. 7B). Next, impurities are introduced into the sidewalls of the trench by vapor phase diffusion, and thermal diffusion is performed to form the separation layer 12 (FIG. 7C). After filling the trench 11 with a reinforcing material (not shown) such as polysilicon or insulating film, the MOS gate structure 14 and the metal electrode on the surface side having the same structure as in FIG. 6 are formed, and then along the scribe line 6. When the IGBT chip is cut out from the wafer 1 by dicing, a reverse blocking IGBT 200 shown in FIG. 8 is completed.

  As described above, with respect to the method of digging the trench 11 on the surface of the wafer 1 and forming the isolation layer 12 on the sidewall thereof, each device region in the wafer 1 is disposed so as to surround the active portion from the front surface to the back surface side pn junction. Forming a isolation layer by forming a diffusion layer on the side wall of the trench and extending the peripheral breakdown voltage structure of the reverse blocking pn junction on the back side of each device region to the surface of the device region Is known (Patent Document 1). Similarly, there is a description of a method of forming a trench having a reverse blocking capability by forming a trench reaching the reverse blocking pn junction from the front surface of the device region and forming a diffusion layer on the sidewall of the trench (patent) References 2, 3).

JP-A-2-22869 JP 2001-185727 A JP 2002-76017 A

  However, in the method of forming the separation layer reaching the back surface from the front surface of the semiconductor substrate by thermal diffusion of impurities, if the thickness of the semiconductor substrate is increased in order to obtain a high breakdown voltage semiconductor device, the corresponding thick oxide film is formed. In addition, high temperature and / or long time diffusion is required for impurity diffusion. As a result, there is a problem that the high temperature and the diffusion time become long, and the semiconductor characteristics and the quality of parts used in the diffusion furnace are greatly adversely affected.

  The problem will be specifically described below. In the method of forming the reverse blocking IGBT separation layer shown in FIG. 5 described above, the higher the breakdown voltage, the thicker the semiconductor substrate becomes when the boron source is applied from the surface and boron is diffused by heat treatment to form the separation layer. Therefore, high temperature, long time diffusion treatment is required. As a result, sag of quartz jigs such as quartz boards, quartz tubes (quartz tubes), quartz nozzles constituting the diffusion furnace, contamination from heaters, strength reduction due to devitrification of the quartz jigs, and the like occur. Furthermore, the formation of the separation layer by this coating diffusion method requires the formation of an oxide film with high mask resistance. A high-quality thick oxide film is indispensable for an oxide film with high mask resistance. As a method for obtaining a high-quality oxide film having high mask resistance, a thermal oxidation method is most preferable. However, in order to prevent boron from penetrating the mask oxide film in the diffusion treatment of the separation layer with boron at a high temperature for a long time (for example, 1500 ° C., 200 hours), a thick thermal oxide film having a thickness of about 2.5 μm or more is formed. It is necessary to let Preferred conditions necessary for the formation of this thermal oxide film having a thickness of 2.5 μm are, for example, a temperature of 1150 ° C., a dry (dry oxygen atmosphere) oxidizing atmosphere in which a good quality oxide film is obtained, and an oxidation time of about 200 hours. is there. Although the film quality is slightly inferior, wet or pyrogenic oxidation which requires a shorter oxidation time than the dry oxidation requires a long oxidation time of about 15 hours. In addition, during these oxidation processes, a large amount of oxygen is introduced into the silicon wafer, so that crystal defects such as oxygen precipitates and oxidation-induced stacking faults are introduced, and device characteristics due to the generation of oxygen donors. Deterioration and deterioration of reliability occur.

  Furthermore, even during thermal diffusion after boron source coating, interstitial oxygen is introduced into the wafer because diffusion treatment is usually performed in an oxidizing atmosphere at a high temperature for a long time. Even in this process, oxygen precipitates and oxygen donor phenomenon Then, crystal defects such as oxidation-induced stacking fault (OSF) and slip dislocation are introduced. In a wafer device in which these crystal defects are introduced in the vicinity of the pn junction, the leakage current tends to increase. Furthermore, it is known that the breakdown voltage and reliability of an insulating film formed on a wafer by thermal oxidation are significantly reduced. In addition, oxygen taken in during diffusion becomes a donor, which causes a negative effect that the breakdown voltage is reduced. Further, in the method for forming the separation layer shown in FIG. 5, since the diffusion by boron proceeds substantially isotropically from the opening of the mask oxide film to the silicon bulk, the boron diffusion of 200 μm is performed in the depth direction. Inevitably, boron is diffused by 160 μm also in the lateral direction, which is an obstacle to reduction in device pitch and chip size.

There is also a problem in the case where the isolation layer is formed using the trench shown in FIG. In this method, a trench 11 having a high aspect ratio is formed by anisotropic dry etching using the oxide film 2 formed on the surface of the wafer 1 as an etching mask, and boron is introduced into the side wall of the formed trench 11 to separate the separation layer 12. Form. Thereafter, the trench 11 is filled with a reinforcing material such as an insulating film. The formation method of the separation layer shown in FIG. 7 is more advantageous for the purpose of reducing the device pitch than the formation method of FIG. However, the time required for trench etching with a depth of about 200 μm requires a processing time of about 100 minutes per sheet when a typical dry etching apparatus is used, leading to an increase in lead time and the number of times the etching apparatus is maintained. Problems such as an increase in Further, when a deep trench is formed by dry etching, if a silicon oxide film (SiO ₂ ) is used as an insulating film mask, the selection ratio is as small as 50 or less, so a thick silicon oxide film of about several μm is required. As a result, there arises a problem that the yield rate decreases due to an increase in cost and the introduction of process-induced crystal defects such as oxidation-induced stacking faults and oxygen precipitates. Further, in the separation layer forming process using the high-aspect-ratio deep trench 11 by anisotropic dry etching, a chemical residue 13a, a resist residue 13b, etc. are generated in the trench 11 as shown in FIG. There is also a problem of causing adverse effects such as deterioration of reliability.

In general, when a dopant such as phosphorus or boron is introduced into the side wall of the trench 11, the side wall of the trench 11 is vertical. The dopant is introduced. However, introduction of the dopant into the sidewall of the trench 11 having a high aspect ratio results in a decrease in effective dose (accordingly, an increase in implantation time), a decrease in effective projection range, a loss in dose due to the screen oxide film, and a decrease in implantation uniformity. This causes harmful effects. Therefore, as a method for introducing impurities into the trench 11 having a high aspect ratio, vapor phase diffusion in which the wafer is exposed to a gasified dopant zero atmosphere such as B ₂ H ₆ (diborane) instead of ion implantation. Although the method is used, the precise controllability of the dose is inferior to that of the ion implantation method. In addition, when the trench 11 having a high aspect ratio is filled with an insulating film, a gap called a void is formed in the trench 11, and problems such as reliability occur. Moreover, in the manufacturing method of the said patent documents 1-3, in order to reduce a wafer crack, after filling a reinforcing material in a trench, the process of cut | disconnecting a wafer with a scribe line and forming a semiconductor chip may be needed. As a result, the manufacturing cost is high.

  The present invention has been made in view of the above points, and an object of the present invention is to easily form a separation layer having a depth reaching the back surface from the front surface of a thick semiconductor substrate for high withstand voltage. Another object is to provide a method for manufacturing a semiconductor device.

  In order to achieve the object of the present invention, the present invention irradiates protons from any one of the main surfaces of the p-type semiconductor substrate a plurality of times with varying acceleration energy, The semiconductor device manufacturing method includes a step of forming an n-type separation layer by forming the main surface from one main surface to the other main surface and then forming a donor by heat treatment. Further, the semiconductor device is a reverse blocking insulated gate bipolar transistor, and the n-type isolation layer is connected to the n-type collector layer.

  In order to achieve the object of the present invention, the present invention includes a first step of selectively forming an n-type base region on the surface of one of the main surfaces of a p-type semiconductor substrate; A second step of selectively forming a p-type emitter region in the surface region; and a gate insulating film on the surface of the n-type base region sandwiched between the surface of the semiconductor substrate and the surface of the p-type emitter region. A third step of forming a MOS gate structure including a gate electrode provided therebetween, an emitter electrode in common contact with the p-type emitter region and the n-type base region after the formation of the interlayer insulating film, and the p A fourth step of forming an n-type collector layer provided on the surface of the other main surface of the semiconductor substrate and grinding a collector electrode in contact with the n-type collector layer after grinding the other main surface of the semiconductor substrate; Manufacturing method of semiconductor device and Rukoto can also. Furthermore, it is preferable that the step of forming the separation layer is performed after the formation of the interlayer insulating film in the fourth step. Furthermore, it is preferable that the step of forming the separation layer is performed after the formation of the emitter electrode. Further, the step of forming the separation layer may be performed after the fourth step.

  Furthermore, in the present invention, in order to achieve the object of the present invention, protons are irradiated from the principal surface of any one of the p-type semiconductor substrates a plurality of times with varying acceleration energy, and proton implantation regions having different depths are obtained. Forming the n-type drift layer by forming the n-type drift layer by heat treatment and forming the p-type separation layer as a p-type separation layer; A method for manufacturing a semiconductor device is provided. Preferably, the semiconductor device is a reverse blocking insulated gate bipolar transistor, and the p-type isolation layer is connected to a p-type collector layer.

  In the present invention, in order to achieve the object of the present invention, a first step of selectively forming a p-type base region on the surface of one of the main surfaces of a p-type semiconductor substrate, A second step of selectively forming an n-type emitter region in the surface region; and a gate insulating film on the surface of the p-type base region sandwiched between the surface of the semiconductor substrate and the surface of the n-type emitter region. A third step of forming a MOS gate structure including a gate electrode provided therebetween, an emitter electrode in common contact with the n-type emitter region and the p-type base region after the formation of the interlayer insulating film, and the n A fourth step of forming a collector electrode in contact with the p-type collector layer and a p-type collector layer provided on the surface of the other major surface of the semiconductor substrate after grinding the other major surface of the semiconductor substrate. Manufacturing method of semiconductor device To. The n-type drift layer is preferably formed after the formation of the interlayer insulating film in the fourth step. The n-type drift layer is preferably formed after the emitter electrode is formed. Furthermore, it is preferable that the n-type drift layer is formed after the fourth step.

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the semiconductor device which forms easily the isolation | separation layer of the depth which reaches the back surface from the surface of the thick semiconductor substrate for high voltage | pressure resistance can be provided.

It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing process for demonstrating the manufacturing method of p channel type reverse blocking IGBT concerning this invention (the 1). It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing process for demonstrating the manufacturing method of p channel type reverse blocking IGBT concerning this invention (the 2). It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing process for demonstrating the manufacturing method of p channel type reverse blocking IGBT concerning this invention (the 3). It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing process for demonstrating the manufacturing method of p channel type | mold reverse blocking IGBT concerning this invention (the 4). It is principal part sectional drawing of the semiconductor substrate which shows in order the manufacturing process in the case of forming the said separation layer of the conventional reverse blocking IGBT by the application | coating diffusion method. It is principal part sectional drawing of reverse blocking IGBT formed with the conventional application | coating diffusion method. It is principal part sectional drawing of the semiconductor substrate which shows in order the manufacturing process at the time of forming the said isolation layer of the conventional reverse blocking IGBT by the trench method. It is principal part sectional drawing of the reverse blocking IGBT formed with the conventional trench method. It is sectional drawing of the trench part for demonstrating the problem at the time of forming the said isolation layer of the conventional reverse blocking IGBT by the trench method. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing process for demonstrating the manufacturing method of n channel type reverse blocking IGBT concerning this invention (the 1). It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing process for demonstrating the manufacturing method of n channel type reverse blocking IGBT concerning this invention (the 2). It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing process for demonstrating the manufacturing method of n channel type reverse blocking IGBT concerning this invention (the 3). It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing process for demonstrating the manufacturing method of n channel type reverse blocking IGBT concerning this invention (the 4).

  Hereinafter, embodiments of a method for manufacturing a semiconductor device according to the present invention will be described in detail with reference to the drawings. The present invention is not limited to the description of the examples described below unless it exceeds the gist.

  Hereinafter, a method for manufacturing a p-channel reverse blocking IGBT chip according to the present invention will be described. For the p-type wafer 15, the MOS gate structure 14 and the peripheral withstand voltage structure 10 are formed on the surface side of the p-type wafer 15 in accordance with a normal n-channel IGBT wafer process, the emitter electrode 20 is formed, and the passivation layer 22 is formed. Including the wafer process on the front side of the IGBT. However, the p-type and the n-type are opposite to each other. In more detail, as shown in FIG. 1B, which is an enlarged view of the portion of the MOS gate structure 14 in FIG. 1A, in the same manner as the manufacturing process of a normal n-channel IGBT, On the surface side of the p-type wafer 15, an n-type base region 16, a p-type emitter region 17, a MOS gate structure 14 including a gate insulating film 18 and a gate electrode 19, an interlayer insulating film 21, and the p-type emitter region 17. An emitter electrode 20 in common contact with the surface and the surface of the n-type base region 16 is formed in this order. The passivation layer 22, the field insulating film 23, and the like are also formed during a required process. The double broken line in the figure shows the omission of the same pattern portion repeatedly.

  Next, a proton injection region 24 by multistage proton irradiation is formed as shown in FIG. The fact that a plurality of proton implantation regions 24 formed with different implantation depths for each stage is formed is indicated by a broken line. The proton irradiation process will be described. Using an aluminum absorber (proton injection control film) (not shown) on which a chip pattern is drawn, only the separation layer forming region 25 is irradiated with protons accelerated by a cyclotron. A plurality of implantation depths changed so that the thickness after the backside grinding of the wafer can be connected to the separation layer forming region 25 formed separately by a plurality of proton irradiations from the front surface to the back surface. Each of the aluminum absorbers is irradiated with protons several times. For example, an n-type impurity layer having a range of 50 μm and a half width of about 10 μm is formed with an acceleration energy of 2 MeV, and an n-type impurity layer having a range of 180 μm and a half width of about 20 μm is formed with an acceleration energy of 4.5 MeV. . Therefore, for example, for a chip having a thickness of 200 μm, as shown by a broken line (proton implantation region 24) in the separation layer forming region 25 in FIG. 2, the acceleration energy is changed from 0.2 MeV to 4.5 MeV multiple times. It is good to irradiate in divided.

  The reason why proton irradiation is performed after completion of the wafer process on the front side is that a donor formed by proton irradiation disappears when it receives a thermal history of about 500 ° C. or higher. For this reason, after the proton irradiation process, proton irradiation is performed after a process stage in which there is no temperature increase of 500 ° C. or more.

  In Example 1, proton irradiation is performed after the formation process of the emitter electrode 20 and the passivation layer 22 on the surface side. However, even before the formation process of the emitter electrode 20, the above-described interlayer insulation that requires heat treatment at 1000 ° C. or higher is required. After the formation process of the film 21, there is usually no process for raising the temperature to 400 ° C. or higher, so any one of the process steps can be selected. That is, it is necessary to perform the proton irradiation process at least after the formation of the interlayer insulating film 21. However, when the n-type collector layer 27 is formed by phosphorus ion implantation and the activation process is required to be heated at a temperature of 400 ° C. or higher, the proton irradiation and annealing are performed on the surface-side emitter electrode 20. It is necessary to perform the formation and the n-type collector layer 27 forming process on the back side.

  The reason why proton irradiation is performed before the back surface grinding process of the p-type wafer 15 in Example 1 is that the p-type wafer 15 becomes thin and mechanically fragile after the back surface grinding of the wafer. This is because the risk of wafer cracking is reduced by performing the processing before the back grinding of 15 having a high mechanical strength. The proton irradiation direction may be from either the front surface side or the back surface side of the wafer, but irradiation from the front surface side having a short distance passing through the wafer bulk is preferable because heat generation can be further suppressed.

After the proton irradiation, the proton implantation region 24 is annealed at a temperature in the range of 300 ° C. to less than 400 ° C. for about 1 hour to form a donor to form an n-type region. It is desirable that the annealing process be performed before the high-strength back surface grinding process applied to the wafer. By this annealing treatment, the donor concentration can be changed from 10 ¹³ cm ⁻³ to 10 ¹⁵ cm ⁻³ by proton irradiation with a dose of 10 ¹¹ cm ⁻² to 10 ¹⁴ cm ⁻² .

  Next, the p-type wafer 15 is ground from the back surface to the back surface grinding line 26 having a required thickness determined by the pressure resistance, as indicated by a broken line in FIG. Next, as shown in FIG. 4, phosphorus ions that become an n-type impurity layer are implanted into the back surface of the p-type wafer 15 so that the temperature of the entire wafer does not rise, for example, a local temperature rise such as a laser or a flash lamp. An n-type collector layer 27 is formed by annealing by a possible temperature raising method. At this time, when the n-type collector layer 27 is formed by annealing the entire wafer at a temperature of about 400 ° C., if the annealing is performed for 1 hour or longer, the donor due to protons may disappear. It is necessary that the annealing process of protons is not performed before the collector layer is formed. After the n-type collector layer 27 is formed, a back electrode (collector electrode 28) is deposited, and then the wafer is diced by the scribe line 29 in the center of the n-type separation layer 25, whereby the p-channel reverse blocking IGBT chip 100 is obtained. it can.

  In the first embodiment described above, the p-channel type reverse blocking IGBT has been described. However, the p-type wafer is used and the above-described surface side MOS gate structure is not manufactured, and the n-type isolation layer is formed in the same manner as described above. A high voltage diode using the (separation layer forming region 25) can be manufactured.

  According to the first embodiment described above, the impurity regions having different depths are irradiated from the front side of the wafer to the back side by irradiating and activating the multi-stages using protons having a large range rather than boron ions or phosphorus ions having a short range. By forming the isolation layer so as to penetrate through to the surface, it is possible to easily form a deep n-type impurity layer in the wafer, so that the heat treatment time is shortened, and it is difficult to reduce the yield rate due to the long time heat treatment. And the difficulties associated with deep trenches can be overcome.

Hereinafter, a method for manufacturing an n-channel reverse blocking IGBT according to the present invention will be described. For a p-type wafer 32 having an impurity concentration of about 10 ¹³ cm ⁻³ , a p-type base region 33, an n-type emitter region 34, a MOS gate structure 31, a peripheral breakdown voltage are formed on the surface side in accordance with a normal n-channel IGBT wafer process. The structure 30 is formed, and the process on the surface side, including the formation of the emitter electrode 40 and the passivation layer 42, proceeds to the state shown in the cross-sectional view of FIG. As shown by the dotted line in FIG. 11, using the absorber on which the pattern of the IGBT chip is drawn, protons are applied only to the other element regions (active region 44 and peripheral breakdown voltage structure 45) except for the p-type isolation layer formation region 43. inject. Irradiation is performed a plurality of times using respective absorbers with different depth target settings so that a continuous n-type layer can be connected from the front surface to the back surface of the substrate thickness after back grinding. By changing the type of the absorber, the energy of protons incident on the IGBT chip can be changed. For example, an n-type impurity layer having a range of 50 μm and a half width of about 10 μm is formed with an acceleration energy of 2 MeV, and an n-type impurity layer having a range of 180 μm and a half width of about 20 μm is formed with an acceleration energy of 4.5 MeV. Therefore, for example, for a chip having a thickness of 200 μm, protons may be incident while changing acceleration energy from 0.2 MeV to 4.5 MeV. This process state is shown in FIG.

  The reason for irradiating protons after the completion of the surface structure fabrication process is that donors formed by protons disappear when the temperature is raised to about 1000 ° C., as in Example 1. This is because it is necessary to irradiate with protons in the process stage where the increase does not occur. Furthermore, even at a temperature of 1000 ° C. or lower, there is a risk of donor disappearance depending on the holding time at a temperature of 400 ° C. or higher.

  In the IGBT wafer process of the second embodiment, protons are implanted after the formation of the emitter electrode 40 and the passivation layer 42 on the surface side. However, after the formation of the interlayer insulating film 37 that always requires heat treatment at about 1000 ° C. If it is a process, the process which raises temperature to 400 degreeC or more can be avoided. Therefore, the proton implantation process may be performed at least after the formation of the interlayer insulating film 37. Further, when it is necessary to heat the p-type collector layer 48 at a temperature of 400 ° C. or higher, proton implantation, annealing, and formation of the emitter electrode 40 on the surface side also avoid a thermal history of 400 ° C. or higher. Both must be done after the collector layer is formed.

After proton implantation, annealing is performed at a temperature in the range of 300 ° C. to 400 ° C. for about 1 hour to form an n-type layer. It is desirable that the annealing be performed before the backside grinding where the wafer is strong. By this proton implantation and annealing, the proton implantation region 46 other than the surface structure formed on the p-type wafer 32 has a dose of 10 ¹¹ cm ⁻² to 10 ¹³ cm ⁻² and a donor concentration of 10 ¹³ cm ⁻³ to 10 ¹⁴ cm ^{−. 3} n ⁻ drift layers 48. As a result, the outermost peripheral portion of the chip where protons are not implanted remains as the p-type separation layer 47 (FIG. 12).

The back surface is ground to the desired wafer thickness, resulting in the state of FIG. As shown in FIG. 13, boron ions to be a p-type impurity layer are implanted into the back surface, and annealed by a method that does not increase the temperature of the entire wafer, for example, a laser or a flash lamp, to form a p-type collector layer 49. In the case where the p-type collector layer 49 is formed by annealing in a furnace at 400 ° C. or lower, it is conceivable that the proton annealing is not performed before grinding because the donor due to protons disappears due to the long-time annealing. After the formation of the p-type collector layer 49, the collector electrode 50 on the back surface is formed and then dicing is performed to obtain an n-channel reverse blocking IGBT chip shown in FIG. The impurity concentration on the lines AA ′ and BB ′ in FIG. 13A is a profile having an n ^- drift layer 48 having a high and low concentration reflecting the proton implantation distribution as shown in FIG. 13B. Become.

  As described in the second embodiment, the p-type wafer is activated by injecting and activating a large-range proton into the active region of the separation layer having a depth reaching the back surface from the surface of the thick semiconductor wafer for high withstand voltage. By making the n-type, the separation layer of the reverse blocking IGBT can be easily formed by leaving the outermost peripheral portion of the chip which has not been implanted as the p-type impurity layer.

14, 31 MOS gate structure 15, 32 p-type wafer 16 n-type base region 17 p-type emitter region 18, 35 Gate insulating film 19, 36 Gate electrode 20, 40 Emitter electrode 21, 37 Interlayer insulating film 22 Passivation film 23, 38 , 42 Field insulating film 24 Proton injection region 25 N-type separation layer 26 Back grinding line 27 N-type collector layer 28, 50 Collector electrode 29 Scribe line 33 p-type base region 34 n-type emitter region 43 Separation layer formation region 44 Active portion 45 Peripheral breakdown voltage structure 46 Proton implantation region 47 p-type isolation layer 48 n ^- drift layer 49 p-type collector layer 100 p-channel reverse blocking IGBT
300 n-channel reverse blocking IGBT

Claims (12)

Proton is irradiated from any one of the main surfaces of the p-type semiconductor substrate a plurality of times while changing the acceleration energy, and proton implantation regions having different depths are formed so as to be connected from the one main surface to the other main surface. Then, a method for manufacturing a semiconductor device comprising a step of forming an n-type isolation layer by forming a donor by heat treatment. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is a reverse blocking insulated gate bipolar transistor, and the n-type isolation layer is connected to an n-type collector layer. a first step of selectively forming an n-type base region on the surface of one of the main surfaces of the p-type semiconductor substrate; and a second step of selectively forming a p-type emitter region on the surface region of the n-type base region. Forming a MOS gate structure including a step and a gate electrode provided on a surface of the n-type base region sandwiched between the surface of the semiconductor substrate and the surface of the p-type emitter region via a gate insulating film And after forming the interlayer insulating film, grinding the emitter electrode in common contact with the p-type emitter region and the n-type base region, and the other main surface of the p-type semiconductor substrate, and then polishing the semiconductor substrate. 3. The method of manufacturing a semiconductor device according to claim 2, further comprising: an n-type collector layer provided on a surface of the other main surface of the first and a fourth step of forming a collector electrode in contact with the n-type collector layer. . 4. The method of manufacturing a semiconductor device according to claim 3, wherein the step of forming the isolation layer is performed after the formation of the interlayer insulating film in the fourth step. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the step of forming the separation layer is performed after the formation of the emitter electrode. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the step of forming the separation layer is performed after the fourth step. Proton is irradiated from any one of the main surfaces of the p-type semiconductor substrate a plurality of times while changing the acceleration energy, and proton implantation regions having different depths are formed so as to be connected from the one main surface to the other main surface. Then, a method of manufacturing a semiconductor device comprising the steps of forming an n-type drift layer by forming a donor by heat treatment and using the proton non-implanted region as a p-type separation layer. 8. The method of manufacturing a semiconductor device according to claim 7, wherein the semiconductor device is a reverse blocking insulated gate bipolar transistor, and the p-type isolation layer is connected to a p-type collector layer. a first step of selectively forming a p-type base region on the surface of one of the main surfaces of the p-type semiconductor substrate; and a second step of selectively forming an n-type emitter region on the surface region of the p-type base region. Forming a MOS gate structure including a step and a gate electrode provided via a gate insulating film on the surface of the p-type base region sandwiched between the surface of the semiconductor substrate and the surface of the n-type emitter region And after the formation of the interlayer insulating film, the emitter electrode in common contact with the n-type emitter region and the p-type base region, and the other main surface of the n-type semiconductor substrate are ground, and then the semiconductor substrate 9. A method of manufacturing a semiconductor device according to claim 8, further comprising: a p-type collector layer provided on a surface of the other main surface of the first and a fourth step of forming a collector electrode in contact with the p-type collector layer. . 10. The method of manufacturing a semiconductor device according to claim 9, wherein the formation of the n-type drift layer is performed after the formation of the interlayer insulating film in the fourth step. The method for manufacturing a semiconductor device according to claim 9, wherein the n-type drift layer is formed after the emitter electrode is formed. The method for manufacturing a semiconductor device according to claim 9, wherein the formation of the n-type drift layer is performed after the fourth step.