JP2015041720A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device having an isolation diffusion layer which can reduce crystal defects caused by a high concentration oxygen introduced into a semiconductor substrate in association with a high-temperature and long-time isolation diffusion process thereby to increase the percentage of non-defective products.SOLUTION: A semiconductor device manufacturing method comprises: a first process of forming on an outermost periphery, an annular p-type isolation diffusion layer 6 which extends from a surface to a rear face of an n-type semiconductor substrate 1; a second process of forming a semiconductor function region 15 on the surface in an inside region surrounded by the annular p-type isolation diffusion layer 6; and a third process of grinding the rear face to a substrate thickness compatible with reverse breakdown voltage of the semiconductor device. The first process includes the steps of: forming an ion implantation layer for forming the p-type isolation diffusion layer 6 on the surface; forming on the rear face, an ion implantation layer for forming a gettering layer having a diffusion depth at which all is to be removed from the semiconductor substrate in the third process; and subsequently performing a heat treatment for forming the annular p-type isolation diffusion layer 6.

Description

  The present invention relates to a method of manufacturing a semiconductor device having an isolation diffusion layer such as a diode or a reverse blocking insulated gate semiconductor device having bidirectional withstand voltage characteristics, which is used in a power conversion device or the like.

  Conventionally, an IGBT (Insulated Gate Bipolar Transistor), which is one of power semiconductor elements, is a high-speed switching characteristic and voltage driving characteristic of a MOSFET (Metal Oxide Semiconductor Field Transistor). And a power element having a low on-voltage characteristic of a bipolar transistor. The range of applications has expanded from industrial fields such as general-purpose inverters, AC servos, uninterruptible power supplies (UPS), or switching power supplies to consumer equipment fields such as microwave ovens, rice cookers, and strobes.

  Also, AC (AC) / AC conversion using a matrix converter such as a direct link type conversion circuit equipped with a bidirectional switching element can reduce the size, weight, efficiency, and response speed of the circuit. Research has been made to reduce costs. As the bidirectional switching element, a structure in which IGBTs having reverse breakdown voltages are connected in reverse parallel can be made simple. However, since normal IGBTs do not have reverse breakdown voltages, it is necessary to connect diodes in reverse series. For this reason, there is a demand from the market for the development and manufacture of an IGBT having an effective reverse breakdown voltage (hereinafter referred to as a reverse blocking IGBT) as compared with an IGBT that does not normally have an effective reverse breakdown voltage.

  FIG. 2 is a cross-sectional view of a main part of such a reverse blocking IGBT. FIG. 3 shows p-type separation that is not only indispensable for manufacturing reverse-blocking IGBTs from the introduction to the wafer process, but also easily causes heavy metal contamination and crystal defects. An outline of the process flow up to the layer forming process is shown in a cross-sectional view of the main part of the semiconductor substrate. A conventional reverse blocking IGBT manufacturing method will be described below with reference to FIGS. First, as shown in FIG. 3A, a p-type FZ semiconductor substrate 100 having a gettering polysilicon layer 100a having a thickness of 3 μm formed on the back surface thereof before p A mask thin film for selective diffusion for forming a mold separation layer is formed. As the mask material, a mask oxide film 101 formed by a thermal oxidation method is usually used. Thereafter, an opening 102 is formed in the mask oxide film 101 where a p-type isolation layer is to be formed by a photolithography process (FIG. 3B). A material containing p-type ion implantation or p-type impurities is applied to the opening 102 to form an ion implantation layer 102a (FIG. 3C) or a coating deposit layer, and then a drive diffusion heat treatment is performed at a high temperature. Then, the p-type isolation layer 103 deeper than the design thickness of the device substrate is formed (FIG. 3D). A portion of the gettering polysilicon layer 100a is single-crystallized by heat treatment during separation and diffusion. After the formation of the p-type isolation layer 103, the mask oxide film 101 is entirely removed (FIG. 3E).

  After that, although not shown, after forming a field oxide film on the surface side of the substrate 100 in the same manner as a general IGBT manufacturing process, a withstand voltage structure portion including an electric field relaxation structure such as a field limiting ring, and p A type base region, an n-type emitter region, an emitter electrode, and the like and an active region including a MOS structure are formed. After these surface structures are formed, in order to control the minority carrier lifetime, the substrate 100 is irradiated with an electron beam or light ions, and heat treatment is performed in an electric furnace so as to achieve a desired lifetime.

  After the above-described manufacturing process, in order to reduce the on-voltage, the semiconductor substrate 100 is mechanically ground from the back side by chemical grinding and chemicals more than the substrate thickness (design thickness of the device substrate) corresponding to the breakdown voltage class. The substrate 100 is thinned by etching. After the substrate 100 is thinned, a p-type impurity such as boron is ion-implanted on the back surface side and activated to form a p-type collector layer (FIG. 2) and at the bottom of the p-type isolation layer 103. Connect. The activation of the p-type collector layer is preferably performed by heat treatment in an electric furnace or laser irradiation. Finally, a collector electrode is formed on the surface of the p-type collector layer by sputtering vapor deposition or the like, and the manufacturing process (hereinafter referred to as a wafer process) in the semiconductor substrate 100 state is completed. After completion of the wafer process, dicing is performed at the center line portion of the p-type separation layer to form a device chip.

  Generally, it is introduced incidentally during a heat treatment process such as a diffusion process, and the adverse effect on the yield rate increases as the temperature increases for a long time, reducing crystal defects caused by heavy metal contamination and high concentration oxygen during thermal diffusion. Therefore, the aforementioned polysilicon layer 100a formed by the CVD method and a damage layer by the sandblast method are provided on the back surface of the semiconductor substrate before being put into the wafer process. (CVD: Chemical Vapor Deposition). By using these layers as gettering layers, crystal defects due to heavy metal contamination and high-concentration oxygen, which are likely to be problems particularly during heat treatment at high temperatures and long hours, are reduced, and a decrease in the yield rate is suppressed. Crystal defects caused by heavy metals or high-concentration oxygen incidentally introduced by a high-temperature and long-time heat treatment process are taken in and left in the back surface gettering layer (polysilicon layer 100a). As described above, the layer portion is removed by the mechanical grinding process on the back surface side, and does not remain on the semiconductor substrate after completion of the wafer process. As a result, it is possible to obtain a device wafer with less heavy metal contamination and less crystal defects, and a method for manufacturing an insulated gate semiconductor device that can obtain a high yield rate by reducing abnormalities in gate oxide film characteristics and leakage current. it can.

  For such a reverse blocking insulated gate semiconductor device, in order to further increase the yield rate of the reverse breakdown voltage characteristic, a semiconductor function is formed on the inner semiconductor substrate surface surrounded by the p-type isolation layer after the p-type isolation layer is formed. It describes a method for manufacturing a reverse blocking IGBT in which a rare gas element ion-implanted layer is formed on the back surface side before performing a heat treatment at 1000 ° C. or higher to form a region. Further, the impurity diffusion layer formed on the entire surface from the back surface to a thickness that is halved of the thickness of the semiconductor substrate functions as a gettering site, and defects due to high-concentration oxygen introduced when forming the p-type isolation layer There is also a description that the bidirectional withstand voltage is maintained by reducing or removing from the semiconductor function region on the surface side (Patent Document 1).

  By removing the stress layer on the back surface formed by back surface grinding after the completion of the p-type separation diffusion step, the front surface side semiconductor functional region forming step and the back surface grinding step, and before the p type collector layer forming step, There is a description about increasing the non-defective product rate of the reverse withstand voltage characteristic (Patent Document 2).

  After forming a p-type separation layer having a required depth from the surface of the semiconductor substrate, a phosphorous doped layer is formed on the back surface and a gettering layer is formed in this order by ion implantation of argon, followed by a process including heat treatment at 1000 ° C. or higher. Describes a method of manufacturing a reverse blocking IGBT having a step of reducing the thickness of the back surface side until the p-type isolation layer is exposed after a required semiconductor functional region is formed (Patent Document 3).

JP 2006-140309 A (summary, FIG. 5) JP 2006-147739 A (summary) Japanese Patent No. 4995172 (Claim 4)

  In the above-described reverse blocking IGBT manufacturing method, when forming the p-type separation layer at the initial stage of the semiconductor substrate input into the wafer process, a mask oxide film forming step by a thermal oxidation method of about 1100 ° C. and a temperature of about 1300 ° C. A high temperature and a long drive diffusion process of about 100 to 200 hours are required.

  However, the polysilicon layer already formed on the back surface of the substrate as a gettering layer is extremely effective in gettering the aforementioned heavy metals and crystal defects during the high-temperature and long-time separation diffusion layer diffusion process. It has been found that the polysilicon layer having a thickness of about 3 μm halves its gettering effect when the process after the separation and diffusion process is performed. This is considered due to the progress of partial crystallization of the polysilicon layer. In the case of the gettering layer based on the damaged layer by the sandblasting method, the gettering effect is reduced because the damaged layer is recovered by the high-temperature heat treatment as described above. If the gettering effect is reduced, heavy metals and crystal defects are left inside the substrate other than the polysilicon layer. The heavy metal left in the substrate is taken into the gate oxide film in a later process and causes an abnormality in the gate characteristics. In addition, crystal defects remaining on the semiconductor substrate cause problems such as leakage current abnormality. Therefore, when manufacturing reverse blocking IGBTs, a phosphorous doped layer or a gettering layer by ion implantation of argon is newly added to the back surface of the substrate after the separation and diffusion process, as described in Patent Document 3 above. There was a need to form. However, it is difficult to form a strong gettering layer by adding a process after the separation / diffusion process, and even if these additional gettering measures are taken, the yield rate may decrease, and the gettering effect is still not good. It was enough. Furthermore, since the gettering effect needs to be enhanced by another method, there is a problem that the number of steps increases.

  The present invention has been made in view of the above-described problems, and the object of the present invention is to provide crystal defects caused by heavy metals and high-concentration oxygen introduced into a semiconductor substrate during a high-temperature and long-time separation / diffusion process. It is an object of the present invention to provide a method of manufacturing a semiconductor device that can improve the yield rate by reducing the number of products.

  In order to achieve the above object, the present invention provides a first step of forming an annular second conductive type separation diffusion layer from the first main surface of the first conductive type semiconductor substrate toward the second main surface in the outermost periphery. A second step of forming a semiconductor functional region on the first main surface surrounded by the annular second conductivity type separation diffusion layer, and a substrate thickness corresponding to the reverse breakdown voltage of the semiconductor device. In the method of manufacturing a semiconductor device comprising: a third step of grinding the first main surface, the second main type is formed by forming an ion implantation layer for forming the second conductivity type separation diffusion layer on the first main surface, and After forming an ion implantation layer for forming a gettering layer having a diffusion depth removed from the semiconductor substrate in the third step on the surface, heat treatment is performed to form the annular second conductivity type separation diffusion layer It is set as the manufacturing method of the semiconductor device made into a process.

  It is preferable that the ion species to be ion-implanted into the second main surface is selected from boron, phosphorus, and a rare gas element. The rare gas element is desirably any element represented by the element symbols He, Ne, Ar, Kr, Xe, and Rn. It is particularly preferable that the rare gas element is Ar.

  According to the present invention, there is provided a semiconductor device manufacturing method capable of improving the yield rate by reducing crystal defects caused by heavy metals and high-concentration oxygen introduced into a semiconductor substrate along with a high-temperature and long-time separation / diffusion process. Can be provided.

It is principal part sectional drawing which shows the manufacturing process until it forms the p-type isolation layer of reverse blocking IGBT concerning the manufacturing method of the semiconductor device of this invention with the semiconductor substrate for every process. It is principal part sectional drawing of reverse blocking type IGBT. It is principal part sectional drawing which shows the manufacturing process until it forms the p-type isolation layer of the conventional reverse block type IGBT with the semiconductor substrate for every process. It is a reverse leakage current distribution figure which compares and shows the reverse leakage current of the reverse blocking IGBT produced by the present invention and the conventional manufacturing method, respectively.

  Embodiments of the method for manufacturing a semiconductor device according to the present invention will be described below in detail with reference to the drawings. In the present specification and the accompanying drawings, it means that electrons or holes are majority carriers in layers and regions with n or p, respectively. Further, + and − attached to n and p mean that the impurity concentration is relatively high or low, respectively. In the following description of the embodiments and the accompanying drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted. In addition, the accompanying drawings described in the embodiments are not drawn to an accurate scale and dimensional ratio for easy understanding and understanding. The present invention is not limited to the description of the examples described below unless it exceeds the gist.

  FIG. 1 shows an outline of the process flow from the introduction of a wafer to the formation of a p-type separation layer that is indispensable for the manufacture of a reverse blocking IGBT in the manufacturing process of the reverse blocking IGBT according to the present invention. Illustrated by diagram. (A) A selective diffusion mask for forming a p-type isolation layer on the surface of an n-type FZ semiconductor substrate 1 having a thickness of about 500 μm, in which a gettering polysilicon layer 1a is formed to a thickness of 3 μm on the back surface A thin film is formed. As the mask material, a mask oxide film 2 formed by a thermal oxidation method is usually used. Thereafter, (b) an ion implantation layer 3a is formed on the entire back surface by ion implantation for gettering. At this time, in order to protect the surface side, it is also preferable to apply a resist (not shown) to the surface side. As the ion species to be ion-implanted, boron, phosphorus, a rare gas element, or the like is preferable. The rare gas element can be selected from the element symbols He, Ne, Ar, Kr, Xe, Rn and the like, and Ar (argon) is particularly preferable. After forming an ion implantation layer 3a for gettering on the entire surface using, for example, boron as an ion species, the mask oxide film 2 on the front surface side is selectively etched by photolithography to form a p-type separation layer. An ion implantation opening 4 is provided. Thereafter, (d) an ion implantation layer 5 is formed by ion implantation of boron for the p-type separation layer, and then (e) high-temperature long-time drive diffusion heat treatment is performed to form the p-type separation layer 6. The heat treatment conditions are about 1 hour at 1300 ° C. for a device with a withstand voltage of 600V and about 200 hours at 1300 ° C. with a device with a withstand voltage of 1200V. When the above-mentioned resist coating for surface protection is performed, it is necessary to remove the resist before the p-type separation layer is diffused. At the time of this drive diffusion heat treatment for the p-type isolation layer, ion species (boron) are also diffused from the ion implantation layer 3a implanted into the back surface at the same time to form a deep gettering diffusion layer 3. In a device for a withstand voltage of 600 V, the p-type isolation layer 6 and the gettering layer both have a diffusion depth of about 120 μm from the front surface or the back surface. Further, the gettering polysilicon layer 1a is partially crystallized by heat treatment during p-type isolation diffusion, and the gettering effect is reduced. However, the gettering diffusion layer 3 has a high level as in the p-type isolation layer. Since distortion of the crystal lattice due to the introduction of concentration oxygen is formed, this distortion creates a new gettering effect. (F) After the formation of the p-type isolation layer 6, the mask oxide film 2 is entirely removed.

  Thereafter, although not shown in FIG. 1, the field limiting ring 7 (shown in the cross-sectional view of the main part of the reverse blocking IGBT shown in FIG. 2) is formed on the surface side of the substrate 1 in the same manner as a general IGBT manufacturing process. FLR), a breakdown voltage structure 9 including an electric field relaxation structure such as a field plate 8, a p-type base region 10, an n-type emitter region 11, an emitter electrode 12, and a MOS structure 13 (a gate electrode 13a and a gate oxide film on the substrate 1). 13b) and the like, the semiconductor functional region 15 including the active region 14 is formed. The heat treatment conditions for the FLR are 1150 ° C. and 200 minutes, and the heat treatment conditions for the p-type base region 10 are 1150 ° C. and 120 minutes.

  During the high-temperature heat treatment in this step, crystal defects due to oxygen can be taken into the gettering layer 3 on the back surface side from the semiconductor functional region 15 in the semiconductor substrate. The density of can be reduced. If necessary, a protective film (not shown) such as a polyimide film is deposited on the uppermost layer of the semiconductor substrate. Furthermore, in order to reduce the reverse leakage current after forming the MOS structure 13 on the substrate surface, it is preferable to introduce an electron beam at 6 Mrad.

  After the formation of the semiconductor functional region 15 on the surface side, the substrate 1 is irradiated with an electron beam or light ions and heat-treated with an electric furnace so as to have a desired lifetime in order to control the minority carrier lifetime. .

  After the above manufacturing process, in order to make the semiconductor substrate 1 have a substrate thickness corresponding to the breakdown voltage class, the substrate is thinned by performing mechanical grinding and chemical etching from the back side. In general, it is preferable to reduce the thickness of the wafer to about 100 μm for the withstand voltage class 600V and about 180 μm for 1200V. In order to remove stress and strain when the back surface is shaved, it is desirable to perform chemical etching or chemical mechanical polishing. In the case of chemical etching, the surface condition is improved by processing the chemical solution at an etching rate of 0.25 to 0.45 μm / sec. In the case of chemical mechanical polishing, the polishing amount is about 3 μm. When the chemical mechanical polishing process is performed, the rough surface after grinding can be made into a mirror surface. This is very effective in improving the reverse breakdown voltage characteristics of the reverse blocking IGBT.

After the substrate 1 is thinned by backside grinding, the ground surface of the backside is mirror-finished as described above, and then a p-type impurity such as boron with a dose of 5 × 10 ¹³ cm ⁻² is ion-implanted into the backside, and 400 ° C. Annealing is performed for about 1 hour to form a p-type collector layer 16 having a peak concentration of activated boron of about 1 × 10 ¹⁷ cm ⁻³ and a thickness of 1 μm or less. The activation of the p-type collector layer 16 is preferably performed by heat treatment in an electric furnace or laser irradiation. Finally, the collector electrode 17 is formed on the surface of the p-type collector layer 16 by sputtering deposition or the like, and the manufacturing process in the state of the semiconductor substrate 1 is completed. After the completion of the wafer process, dicing is performed at the center line portion of the p-type separation layer 6 to obtain a reverse blocking IGBT chip state.

  The order in which the gettering ion implantation is performed on the back surface is not limited to the order described above, and may be performed before the p-type separation layer diffusion process. In the present invention, it is important that ion implantation for gettering on the back surface is performed before the p-type separation layer diffusion step. Further, in the present invention, by performing the drive diffusion heat treatment step for forming the p-type isolation layer 6 and the gettering layer 3 at the same time, the deep gettering layer 3 is formed from the back surface to the region close to the MOS structure 13 on the front surface side. Therefore, a larger gettering effect can be obtained. In addition, as described above, the gettering layer 3 is removed from the semiconductor substrate in the back surface grinding process after the formation of the front surface MOS structure 13 is completed, so that the semiconductor substrate of the device that has finished the wafer process. It is important that it does not remain in For example, in the above-described reverse blocking IGBT of Patent Document 3, after forming a p-type separation layer, a phosphorous doped layer is formed on the back surface and a gettering layer is formed by argon ion implantation in this order. Since it is thin (cannot be made thick) and is far from the semiconductor functional region on the surface side, the gettering must be small.

  FIG. 4 shows the reverse blocking IGBT manufactured by the manufacturing method according to the present invention in which the gettering ion implantation is performed before the p-type separation layer is formed, and the gettering ion implantation after the p-type separation layer is formed. The histogram of each reverse leakage current distribution of the performed conventional reverse blocking IGBT is also shown. As shown in FIG. 4, the reverse blocking IGBT according to the present invention in which the ion implantation is performed before the formation of the p-type separation layer has a smaller reverse leakage current distribution and a narrower range distribution than the conventional reverse blocking IGBT. You can see that

  As described above, in the embodiment according to the present invention, the reverse blocking IGBT is used as the semiconductor device. However, the present invention is not limited to the reverse blocking IGBT, and the p-type separation layer straddling both main surfaces is not limited to the conductivity of the semiconductor substrate. As long as the bipolar device is used as a region having a conductivity type opposite to the type, it can be applied to other devices, for example, a diode manufacturing method using a p-type isolation layer.

  According to the semiconductor device manufacturing method of the present invention, the ion implantation layer is formed on the back surface before the high temperature and long time separation diffusion process, and the back surface gettering layer is formed on the entire surface simultaneously with the formation of the p-type separation layer. It can be a deep diffusion layer. The deep gettering layer formed on the entire back surface can sufficiently capture heavy metals and crystal defects in the back gettering layer and remove them by back grinding during the heat treatment step in the subsequent wafer process. . As a result, the number of crystal defects caused by high-concentration oxygen introduced in the separation and diffusion process at high temperature and long time can be reduced, the reverse leakage current can be reduced, and a semiconductor device with a high yield rate can be achieved stably. it can. Further, since a high-quality gate oxide film can be formed, high reliability can be achieved.

1 n-type semiconductor substrate 1a polysilicon layer 2 mask oxide film 2a field oxide film 2b interlayer insulating film 3 gettering layer 3a ion implantation layer 4 opening 5 ion implantation layer 6 p-type separation layer 7 field limiting ring 8 field plate 9 Breakdown voltage structure 10 p-type base layer 11 n-type emitter region 12 emitter electrode 13 MOS structure 13a gate electrode 13b gate oxide film 14 active region 15 semiconductor functional region 16 p-type collector layer 17 collector electrode

Claims (4)

A first step of forming an annular second conductivity type separation diffusion layer extending from the first main surface of the first conductivity type semiconductor substrate toward the second main surface in the outermost periphery; and the annular second conductivity type separation diffusion layer A semiconductor device comprising: a second step of forming a semiconductor functional region on the first inner main surface surrounded; and a third step of grinding the second main surface to a substrate thickness commensurate with the reverse breakdown voltage of the semiconductor device. In the manufacturing method, in the first step, an ion implantation layer for forming the second conductivity type separation diffusion layer is formed on the first main surface, and the second main surface is removed from the semiconductor substrate in the third step. Forming an ion-implanted layer for forming a gettering layer having a diffusion depth from the second main surface, and then performing a heat treatment for forming the annular second conductivity type separation diffusion layer. A method of manufacturing a semiconductor device. 2. The method of manufacturing a semiconductor device according to claim 1, wherein an ion species for forming an ion implantation layer on the second main surface is selected from boron, phosphorus, and a rare gas element. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the rare gas element is any one of elements represented by element symbols He, Ne, Ar, Kr, Xe, and Rn. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the rare gas element is Ar.

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