JP2012018988A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of chip size reduction and multiple bits.SOLUTION: A third chip pad line 4C positioned outside of ends of first and second chip pad lines 4A and 4B is aligned on an extension line of the center line between the first chip pad line 4A and the second chip pad line 4B. Therefore, chip pads 4 comprising the third chip pad line 4C can keep longer distance in Y direction to chip pads 6 comprising first and second bonding pad lines 6A and 6B than to chip pads 4 comprising the first and second chip pad lines 4A and 4B. As a result, angles to the Y-direction of bonding wires 7 connecting chip pads 4 to bonding pads 6 can be reduced.

Description

  The present invention relates to a semiconductor device in which a semiconductor chip is mounted on a package substrate.

  In recent years, the degree of integration of semiconductor chips has been improved year by year, and accordingly, the miniaturization and multilayering of wiring have been advanced. On the other hand, in order to achieve high-density mounting of a semiconductor package (semiconductor device), it is necessary to reduce the package size. For example, semiconductor packages such as BGA (Ball Grid Array) and CSP (Chip Size Package) have a structure in which a semiconductor chip is mounted on a package substrate and the semiconductor chip and the package substrate are connected by wire bonding or the like. is doing. In this case, since external connection terminals such as solder balls for external connection can be arranged on the entire back surface of the package substrate, the package form can cope with the increase in the number of pins.

A wBGA (window ball grid array) type semiconductor package 100 shown in FIG. 10 will be described as an example of a conventional semiconductor device.
In this semiconductor package 100, a semiconductor chip 101 is mounted on a package substrate 102, and a plurality of chip pads 103 are arranged on the surface of the semiconductor chip 101 facing the package substrate 102. . The plurality of chip pads 103 constitute two rows of the first chip pad row 103A and the second chip pad row 103B arranged in one direction (X direction shown in FIG. 10) in the central portion of the semiconductor chip 101. Yes.

  On the other hand, the package substrate 102 is provided with an opening 104 that allows the first and second chip pad rows 103A and 103B of the semiconductor chip 101 to face outward. A plurality of bonding pads 105 are disposed on the surface of the package substrate 102 opposite to the surface on which the semiconductor chip 101 is mounted. The plurality of bonding pads 105 includes one row of first bonding pad rows 105A arranged in the X direction on one side of a direction (Y direction shown in FIG. 10) orthogonal to one direction across the opening 104, On the other side, one row of second bonding pad rows 105B arranged in the X direction is formed.

  The chip pads 103 constituting the first chip pad row 103A are electrically connected to the bonding pads 105 constituting the first bonding pad row 105A and the bonding wires 106 in order in the arrangement direction (X direction). ing. Similarly, the chip pads 103 constituting the second chip pad row 103B are electrically connected to the bonding pads 105 constituting the second bonding pad row 105B and the bonding wires 106 in order in the arrangement direction (X direction). Has been.

  A plurality of solder balls 107 are provided on the surface of the package substrate 102 opposite to the surface on which the semiconductor chip 101 is mounted. The plurality of solder balls 107 are arranged side by side in the X direction and the Y direction, respectively, outside the first and second bonding pad rows 105A and 105B. A plurality of package wirings 108 are formed on the surface of the package substrate 102 opposite to the surface on which the semiconductor chip 101 is mounted, the bonding pads 105 are disposed at one end, and the solder is disposed at the other end. The ball 107 is arranged.

  By the way, with the recent reduction in chip size and the increase in the number of bits, the number of chip pads 103 arranged on the semiconductor chip 101 has increased and the pitch has been reduced. As a result, the layout of the package wiring 108 has become very difficult due to the constraints of the design rules.

  Specifically, in the semiconductor package 100 shown in an enlarged view in FIG. 11, there is a limit to the region (routing region) S in which the package wiring 108 can be routed from the bonding pad 105 on the package substrate 102 to the solder ball 107. . Therefore, as the chip size is reduced and the number of bits is increased, the number of chip pads 103 constituting the first and second bonding pad rows 105A and 105B is increased, and the interval (pitch) between adjacent chip pads 103 is increased. ) Becomes narrower, the angle of the bonding wire 106 connecting the chip pad 103 and the bonding pad 105 at both ends of the chip pad rows 103A and 103B shown in the encircled portion Z in FIG. May be exceeded.

  For example, as shown in FIG. 12, in the design rule in which the distance E between adjacent chip pads 103 in the X direction is 300 μm and the distance F between adjacent bonding pads 105 in the Y direction is 150 μm, the angle θ of the bonding wire 106 with respect to the Y direction Is defined to be 45 ° or less in order to prevent interference (short circuit) between the bonding wire 106 and the adjacent chip pad 103 or bonding pad 105. Note that the interval E between the chip pads 103 and the interval F between the bonding pads 105 are defined in order to prevent contact between the capillaries and the bonding wires 106 due to the size of the capillary (tool during bonding).

  However, when the number of bits increases as in DDR2 × 32, the number of package wirings 108 increases as compared to DDR2 × 16. For this reason, in the semiconductor package 100, even if two chip pad rows 103A and 103B having the minimum spacing B between the chip pads 103 are arranged, the spacing B between the bonding pads 105 is minimized, and In the arrangement of the bonding pad 105 giving priority to securing the routing area S, the angle θ of the bonding wire 106 exceeds 45 ° at both ends of the chip pad rows 103A and 103B, which violates the design rule.

  In order to solve such a problem, for example, as shown in FIG. 13, it is conceivable to arrange the bonding pads 105 in a staggered arrangement. However, in the staggered arrangement, instead of solving the problem that the angle θ of the bonding wire 106 exceeds the design rule, the package wiring 108 is excessively concentrated in a part of the routing region S on the package substrate 102, and the current situation According to the design rule, it is difficult to route all the package wirings 108.

  In addition, as a prior art document relevant to this invention, there exists the following patent document 1, for example. This patent document 1 describes a configuration including chip pads arranged in two rows in an axial contrast with a central portion of a semiconductor chip and chip pads arranged in one row. However, this Patent Document 1 does not describe the possibility that the angle θ of the bonding wire 106 that connects between the chip pad 103 and the bonding pad 105 described above may exceed the constraint conditions of the design rule. Only a configuration in which chip pads are arranged in two rows in order to cope with this is described.

JP-A-6-350052

  As described above, the number of chip pads 103 arranged on the semiconductor chip 101 increases with the recent reduction in chip size and the increase in the number of bits (specifically, the number of chip pad columns is changed from one to two). In addition, the pitch tends to be narrowed. Therefore, there is a demand for a layout that can meet the reduction in chip size and the number of bits while satisfying the design rules described above.

  A semiconductor device according to the present invention is a semiconductor device in which a semiconductor chip is mounted on a package substrate, and the semiconductor chip is located at a central portion of a surface facing the package substrate and has a plurality of chip pads. A first chip pad row and a second chip pad row arranged in parallel to the direction, and a third chip in which a plurality of chip pads are arranged in one direction, located outside the ends of the first and second chip pad rows And the package substrate is positioned on a surface opposite to the surface on which the semiconductor chip is mounted, and an opening for facing the first, second, and third chip pad rows of the semiconductor chip outward. The plurality of bonding pads are arranged along the opening end of the opening on the first chip pad row side, and the plurality of bonding pads are arranged along the opening end of the opening on the second chip pad row side. A second bonding pad row arranged in a row, and the chip pads constituting the first chip pad row are electrically connected to the bonding pads constituting the first bonding pad row via bonding wires, and the second chip pad row The chip pads constituting the third chip pad row are electrically connected to the bonding pads constituting the second bonding pad row via the bonding wire, and the chip pads constituting the third chip pad row are connected to the first or second bonding via the bonding wire. It is electrically connected to the bonding pads constituting the pad row, and the angle with respect to a direction orthogonal to one direction of each bonding wire is 45 ° or less.

  As described above, according to the present invention, a layout corresponding to a reduction in chip size and an increase in the number of bits can be achieved. Therefore, even when the number of chip pads arranged on a semiconductor chip increases, it is possible to secure a routing area for package wiring according to the number of chip pads on the package substrate without sacrificing reliability. It becomes. In addition, it is possible to avoid problems such as a short circuit between adjacent bonding wires and a short circuit between the bonding wire and the adjacent chip pad or bonding pad.

It is a top view which shows an example of the semiconductor package to which this invention is applied. It is a longitudinal cross-sectional view of the Y direction of the semiconductor package shown in FIG. It is a top view for demonstrating the angle of the bonding wire which connects between a chip pad and a bonding pad. It is a figure for demonstrating the manufacturing process of the semiconductor package shown in FIG. 1 in order, (a) is the top view, (b) is the sectional drawing. It is a figure for demonstrating the manufacturing process of the semiconductor package shown in FIG. 1 in order, (a) is the top view, (b) is the sectional drawing. FIG. 3 is a cross-sectional view for sequentially explaining the manufacturing process of the semiconductor package shown in FIG. 1. FIG. 3 is a cross-sectional view for sequentially explaining the manufacturing process of the semiconductor package shown in FIG. 1. FIG. 3 is a cross-sectional view for sequentially explaining the manufacturing process of the semiconductor package shown in FIG. 1. FIG. 3 is a cross-sectional view for sequentially explaining the manufacturing process of the semiconductor package shown in FIG. 1. It is a top view which shows an example of the conventional semiconductor package. It is a top view which expands and shows the principal part of the semiconductor package shown in FIG. FIG. 11 is a plan view showing a case where the angle θ of the bonding wire exceeds 45 ° at both ends of the chip pad row of the semiconductor package shown in FIG. 10. It is a top view which shows an example of the semiconductor package by which the bonding pad was zigzag-arranged.

Hereinafter, a semiconductor device to which the present invention is applied will be described in detail with reference to the drawings.
In addition, in the drawings used in the following description, in order to make the features easy to understand, there are cases where the portions that become the features are enlarged for the sake of convenience, and the dimensional ratios of the respective components are not always the same as the actual ones. Absent.

  First, as an example of a semiconductor device to which the present invention is applied, for example, a wBGA type semiconductor package 1 shown in FIGS. 1 and 2 will be described. 1 is a plan view showing the main part of the semiconductor package 1, and FIG. 2 is a cross-sectional view showing the main part of the semiconductor package 1. As shown in FIG.

  As shown in FIGS. 1 and 2, the semiconductor package 1 has a structure in which a semiconductor chip 2 having a rectangular shape in plan view is mounted on a package substrate 3 having a rectangular shape in plan view.

  The semiconductor chip 2 is smaller than the package substrate 3 and is adhesively fixed to the central portion of the mounting surface of the package substrate 3 via an adhesive layer 2a such as an adhesive or an adhesive film (DAF: Die Attached Film).

  A plurality of chip pads 4 are arranged on the surface of the semiconductor chip 2 facing the package substrate 3. The plurality of chip pads 4 are located at the central portion of the semiconductor chip 2 and are arranged in two rows of first chip pad rows 4A and second chips arranged in a straight line in one direction (X direction shown in FIG. 1). The pad row 4B and one third chip pad row 4C, which is located outside the end portions of the first and second chip pad rows 4A and 4B and is linearly arranged in the X direction, are configured. .

  Among these, the chip pads 4 constituting the first chip pad row 4A and the chip pads 4 constituting the second chip pad row 4B are arranged in parallel to each other. On the other hand, the chip pads 4 constituting the third chip pad row 4C are arranged side by side on an extension of the center line between the first chip pad row 4A and the second chip pad row 4B.

  The package substrate 3 is made of a printed wiring board, and a rectangular opening 5 is provided in the central portion thereof so that the first, second, and third chip pad rows 4A, 4B, 4C of the semiconductor chip 2 face outward. Is provided. The opening 5 forms a hole having a substantially rectangular shape in plan view that is larger than the semiconductor chip 2 in the X direction and smaller than the semiconductor chip 2 in the Y direction.

  A plurality of bonding pads 6 are arranged on the surface of the package substrate 3 opposite to the surface on which the semiconductor chip 2 is mounted. The plurality of bonding pads 6 include a first bonding pad row 6A arranged in a line along the opening end of the opening 5 on the first chip pad row 4A side, and a second chip pad row 4B in the opening 5. A second bonding pad row 6B arranged in a straight line along the opening end on the side is formed.

  The chip pads 4 constituting the first chip pad row 4A are electrically connected to the bonding pads 6 constituting the first bonding pad row 6A and the bonding wires 7 in order in the arrangement direction (X direction). ing. The chip pads 4 constituting the second chip pad row 4B are electrically connected to the bonding pads 6 constituting the second bonding pad row 6B via the bonding wires 7 in order in the arrangement direction (X direction). ing.

  On the other hand, the chip pads 4 constituting the third chip pad row 4C are sequentially passed through the bonding pads 6 and the bonding wires 7 constituting the first or second bonding pad row 6A, 6B in the arrangement direction (X direction). Electrically connected. Further, the chip pads 4 constituting the third chip pad row 4C are arranged such that, in the arrangement direction (X direction), the bonding pads 6 constituting the first bonding pad row 6A and the bonding pads constituting the second bonding pad row 6B. 6 and 6 are alternately (alternately) connected by bonding wires 7.

  A plurality of solder balls 8 serving as external connection terminals are provided on the surface of the package substrate 3 opposite to the surface on which the semiconductor chip 2 is mounted. The plurality of solder balls 8 are arranged outside the first and second bonding pad rows 6A and 6B in a grid pattern in the X direction and the Y direction, respectively.

  Further, a plurality of package wirings 9 are routed on the surface of the package substrate 3 opposite to the surface on which the semiconductor chip 2 is mounted, located on the first bonding pad row 6A side with the opening 5 interposed therebetween. A first routing region S1 and a second routing region S2 in which a plurality of package wirings 9 are routed are provided on the second bonding pad row 6B side with the opening 5 interposed therebetween.

  Bonding pads 6 constituting the first bonding pad row 6A are disposed at one end of the package wiring 9 disposed in the first routing area S1, and solder balls 8 are disposed at the other ends, respectively. Yes. On the other hand, the bonding pads 6 constituting the second bonding pads 6B are respectively arranged at one end of the package wiring 9 arranged in the second routing region S2, and the solder balls 8 are arranged at the other ends, respectively. Yes.

  In the semiconductor package 1, the opening 5 is sealed with a sealing resin (sealing material) 10 after the connection in order to protect the connection portion between the chip pad 4 and the bonding pad 6. In the semiconductor package 1, the surface of the package substrate 3 on which the semiconductor chip 2 is mounted is finally sealed with a sealing resin (sealing material) 11 in order to protect the semiconductor chip 2. These sealing resins 10 and 11 are made of, for example, a thermosetting resin such as an epoxy resin filled with a filler made of glass fiber or the like.

  On the other hand, the surface of the package substrate 3 opposite to the surface on which the semiconductor chip 2 is mounted is covered with an insulating film 12 such as a solder resist except for the portion where the bonding pads 6 and the solder balls 8 are disposed. Yes.

  In the semiconductor package 1 having the structure as described above, the third chip pad row 4C located outside the end portions of the first and second chip pad rows 4A and 4B is connected to the first chip pad row 4A and the second chip. Arranged side by side on an extension of the center line between the pad row 4B.

  Here, as shown in FIG. 3, an interval A between adjacent chip pads 4 in the X direction, an interval B between adjacent bonding pads 6 in the X direction, and an offset in the X direction between these chip pads 4 and bonding pads 6. When the amount C is the same, the distance in the Y direction between the chip pad 4 and the bonding pad 6 is the short distance D1 shown in FIG. 3A and the long distance D2 shown in FIG. 3B. When the angle with respect to the Y direction of the bonding wire 7 connecting the chip pad 4 and the bonding pad 6 is compared, the angle θ1 in the case where the distance D shown in FIG. When the distance D shown is longer, the angle θ2 can be relaxed (θ1> θ2).

  From this, the chip pad 4 constituting the third chip pad row 4C is more than the first or second bonding pad row 6A, 6B than the chip pad 4 constituting the first and second chip pad rows 4A, 4B. It is possible to ensure a large distance in the Y direction with respect to the bonding pad 6 constituting the. Therefore, the angle of the bonding wire 7 connecting the chip pad 4 and the bonding pad 6 with respect to the Y direction can be relaxed.

  Accordingly, in the conventional semiconductor package 100 shown in FIG. 10, the angle θ with respect to the Y direction of the bonding wire 106 exceeds 45 ° at both ends of the first and second chip pad rows 103A and 103B. In the semiconductor package 100 of the present invention shown in FIG. 1, the angle of each bonding wire 7 with respect to the Y direction can be set to 45 ° or less.

  As described above, in the semiconductor package 1 to which the present invention is applied, a layout corresponding to a reduction in chip size and an increase in the number of bits can be achieved. That is, even when the number of chip pads 4 arranged on the semiconductor chip 2 increases, the routing area S1 of the package wiring 9 according to the number of chip pads 4 on the package substrate 3 without sacrificing reliability. , S2 can be secured. In addition, it is possible to avoid problems such as a short circuit between adjacent bonding wires 7 and a short circuit between the bonding wire 7 and the adjacent chip pad 4 or bonding pad 6.

Next, the manufacturing process of the semiconductor package 1 will be described.
When manufacturing the semiconductor package 1, first, as shown in FIGS. 4A and 4B, a mother package substrate 30 in which a plurality of portions 30 a to be the package substrate 3 are formed side by side is prepared. The mother package substrate 30 is formed by arranging a plurality of portions 30a to be the package substrate 3 in a matrix inside the frame portion 30b. The openings 5 are formed in the portions 30a to be the package substrate 3, respectively. Is provided. The frame 30b is provided with a hole 30c for positioning the mother package substrate 30. Then, the mother package substrate 30 is finally cut along the dicing line L, so that the portions 30a to be the package substrate 3 can be cut out as individual package substrates 3.

  Next, as shown in FIGS. 5A and 5B, the semiconductor chip 2 is mounted on the portion of the mother package substrate 30 that becomes the mounting surface of each package substrate 3. Specifically, the first, second, and third chip pad rows 4A, 4B, and 4C of the semiconductor chip 2 are bonded to the portions 30a that become the package substrates 3 of the mother package substrate 30 so as to be exposed from the openings 5. The semiconductor chip 2 is fixed via the layer 2a.

  Next, as shown in FIG. 6, between the bonding pad 6 provided in the portion 30a to be each package substrate 3 and the chip pad 4 provided in each semiconductor chip 2, Au wire or Cu wire is provided. It connects with the bonding wire 7 which consists of etc.

  That is, the chip pads 4 constituting the first chip pad row 4A and the bonding pads 6 constituting the first bonding pad row 6A are connected in order in the arrangement direction (X direction) by the bonding wires 7. . Further, the bonding pads 7 are sequentially connected in the arrangement direction (X direction) between the chip pads 4 constituting the second chip pad row 4B and the bonding pads 6 constituting the second bonding pad row 6B. .

  On the other hand, the bonding wire 7 is sequentially formed between the chip pad 4 constituting the third chip pad row 4C and the bonding pad 6 constituting the first or second bonding pad row 6A, 6B in the arrangement direction (X direction). Connect with. Further, the chip pads 4 constituting the third chip pad row 4C are arranged in the arrangement direction (X direction) with the bonding pads 6 constituting the first bonding pad row 6A and the bonding pads constituting the second bonding pad row 6B. 6 and 6 are alternately (alternately) connected by bonding wires 7.

  In the present invention, as described above, the angle θ of the bonding wire 7 connecting the chip pad 4 and the bonding pad 6 with respect to the Y direction can be relaxed to 45 ° or less. A layout corresponding to bit conversion is possible.

  Next, as shown in FIG. 7, the opening 5 is sealed with a sealing resin (sealing material) 10 after the connection in order to protect the connection portion between the chip pad 4 and the bonding pad 6. Specifically, when the opening 5 is sealed with the sealing resin 10, the sealing resin 10 is removed from the gap of the opening 5 that protrudes outward from both ends in the X direction of the semiconductor chip 2. This can be done by pouring from the surface side where the semiconductor chip 2 is mounted.

  Further, in order to protect each semiconductor chip 2, the mounting surface of the portion 30 a that becomes each package substrate 3 of the mother package substrate 30 is sealed with a sealing resin (sealing material) 11. In this sealing step, for example, a molding method such as a transfer method or a potting method can be used.

  Next, as shown in FIG. 8, the solder balls 8 are arranged on the surface of the mother package substrate 30 opposite to the mounting surface of the portion 30 a that becomes each package substrate 3. The placement of the solder balls 8 is performed for each portion 30 a that becomes the package substrate 3 using the suction mechanism 41.

  Next, as shown in FIG. 9, after the dicing tape 42 is attached to the sealing material 11 side of the mother package substrate 30, the mother package substrate 30 is diced from the side opposite to the dicing tape 42 using a dicing blade 43. Cut along line L. Thus, the semiconductor package 1 is divided. Then, by peeling off these semiconductor packages 1 from the dicing tape 42, the semiconductor package 1 shown in FIG. 1 can be obtained.

  By going through the steps as described above, the semiconductor package 1 can be manufactured collectively. In the present invention, the semiconductor package 1 can be efficiently manufactured by using a production method for collectively sealing a plurality of semiconductor packages 1 called MAP (Mold Array Process). It is possible to reduce the manufacturing cost.

In addition, this invention is not necessarily limited to the thing of the said embodiment, A various change can be added in the range which does not deviate from the meaning of this invention.
Specifically, in the above embodiment, as the package substrate 3 and the mother package substrate 30, for example, a printed wiring board in which wiring made of a conductive material such as Cu is formed on the surface of a base material made of glass epoxy resin can be used. However, the present invention can be applied to a semiconductor package in which a semiconductor chip is mounted on a flexible printed wiring board made of polyimide resin or the like, for example, a TCP (Tape Carrier Package) type semiconductor device. is there.

  In the above embodiment, the package wiring 9 is arranged on one surface of the package substrate 3. However, the present invention is not limited to this configuration, and a plurality of printed wiring boards are stacked as the package substrate 3. It is also possible to use a multilayer printed wiring board.

  Moreover, although the said embodiment demonstrated the structure by which the opening part 5 was provided in the center part of the package substrate 3, the structure by which the package substrate 3 was divided | segmented into two by this opening part 5 may be sufficient.

  Moreover, although the said embodiment demonstrated the structure by which the one semiconductor chip 2 was mounted on the package board | substrate 3, the structure by which the several semiconductor chip 2 was mounted on the package board | substrate 3 may be sufficient.

  In the above embodiment, the case where the present invention is applied to a BGA type semiconductor device using solder balls as external connection terminals has been described. However, the present invention is applied to an LGA (Land Grid Array) type semiconductor device using electrode pads as external connection terminals. It is also possible to apply the present invention.

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor package 2 ... Semiconductor chip 2a ... Adhesion layer 3 ... Package board 4 ... Chip pad 4A ... 1st chip pad row | line | column 4B ... 2nd chip pad row | line | column 4B ... 3rd chip pad row | line | column 5 ... Opening part 6 ... Bonding pad 6A 1st bonding pad row 6B 2nd bonding pad row 7 Bonding wire 8 Solder ball (external connection terminal) 9 Package wiring 10, 11 Sealing resin (sealing material) 12 Insulating film 30 Mother package substrate

Claims (9)

A semiconductor device in which a semiconductor chip is mounted on a package substrate,
The semiconductor chip is positioned at a central portion of a surface facing the package substrate, and a plurality of chip pads are arranged in parallel in one direction, and the first and second chip pad rows, A third chip pad row that is located outside the end of the two chip pad row and in which a plurality of chip pads are arranged in the one direction;
The package substrate includes a plurality of openings disposed on a surface opposite to the surface on which the semiconductor chip is mounted, and an opening that faces the first, second, and third chip pad rows of the semiconductor chip outward. Bonding pads are arranged along the opening end of the opening on the first chip pad row side, and a plurality of bonding pads are arranged along the opening end of the opening on the second chip pad row side. A second bonding pad row;
A chip pad constituting the first chip pad row is electrically connected to a bonding pad constituting the first bonding pad row via a bonding wire;
A chip pad constituting the second chip pad row is electrically connected to a bonding pad constituting the second bonding pad row via a bonding wire;
A chip pad constituting the third chip pad row is electrically connected to a bonding pad constituting the first or second bonding pad row via a bonding wire;
The semiconductor device is characterized in that an angle of each bonding wire with respect to a direction orthogonal to the one direction is 45 ° or less.   2. The chip pads constituting the first and second chip pad rows are sequentially connected to bonding pads constituting the first and second bonding pad rows in the arrangement direction thereof. Semiconductor device.   3. The chip pads constituting the third chip pad row are alternately connected to the bonding pads constituting the first or second bonding pad row in the arrangement direction thereof. Semiconductor device.   The said 3rd chip pad row | line | column is arrange | positioned along with the extended line of the centerline between the said 1st chip pad row | line | column and the said 2nd chip pad row | line | column. The semiconductor device according to one item.   5. The semiconductor device according to claim 1, wherein the third chip pad row is disposed on both sides in one direction across the first and second chip pad rows. 6. .   6. The first and second bonding pads are provided at one end of a plurality of package wirings disposed on a surface opposite to a surface on which the semiconductor chip is mounted. The semiconductor device according to any one of the above. External connection terminals are respectively provided at the other ends of the plurality of package wirings,
The plurality of external connection terminals are located outside the first and second bonding pad rows, and are arranged side by side in the one direction and a direction orthogonal to the one direction. 6. The semiconductor device according to 6.   The semiconductor device according to claim 7, wherein the external connection terminal is a solder ball or an electrode pad.   The semiconductor device according to claim 1, wherein the opening is sealed with a sealing material.

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