JP2012015554A - Semiconductor device manufacturing method and multilayer semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multilayer semiconductor device and a manufacturing method of the device which has high reliability and inhibits warpage of the semiconductor device.SOLUTION: The semiconductor device comprises a semiconductor element 12 bonded on a substrate 11 by flip chip bonding, and underfill resin 13 fulfilled between the substrate 11 and the semiconductor element 12. On the outer periphery of the semiconductor element 12, bonding lands 14 are provided and all over the substrate 11 is encapsulated by resin 15. Openings 16 reaching the bonding lands 14 are formed on a top face of the resin 15.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a stacked semiconductor device in which two or more semiconductor packages are stacked and a manufacturing method thereof.

  As a semiconductor package technology for realizing high integration and multi-functionalization of a semiconductor device, a technology for three-dimensionally stacking a plurality of semiconductor packages each mounting a logic circuit element and a memory circuit element has attracted attention. Such a three-dimensional stacked semiconductor device is called a package on package (hereinafter abbreviated as PoP) or a stack package.

  According to the PoP, a combination of a logic circuit and a memory circuit can be arbitrarily selected according to the application, and since these elements are three-dimensionally stacked, the effective area can be reduced. Therefore, it is mainly used for a small, thin and multifunctional device represented by a mobile phone.

  An example of a cross-sectional structure according to the prior art PoP is shown in FIG. The first semiconductor device 100 disposed in the lower stage includes a semiconductor element 12 flip-chip connected on a substrate 11 having a connection land 14 on the outer periphery, and an underfill resin 13 is interposed between the substrate and the semiconductor element. Filled. Ball electrodes 17 are formed on the back surface of the substrate 11 as external connection terminals.

  The second semiconductor package 200 disposed in the upper stage includes the semiconductor element 12 connected to the substrate 11 by wire bonding, and is sealed with a resin 15. The first semiconductor device 100 and the second semiconductor package 200 are joined via the solder bumps 19 and configured as PoP.

  In addition, the prior art regarding this invention is disclosed by patent document 1, patent document 2, and patent document 3, for example.

  Patent Document 4 discloses a technique related to a pin grid array (PGA) type package in which a semiconductor package is entirely sealed with a resin, and a plurality of holes extending from the package surface to the inner lead frame surface are formed. Has been. Furthermore, a configuration is disclosed in which a plurality of packages are stacked via conductive bumps provided in the holes. The hole is provided to provide a multi-pin package with excellent mass productivity, and is a technology related to a PGA type package. Therefore, the semiconductor element is mounted on the tab and formed on the thin substrate according to the present invention. Is not provided.

JP 2004-289002 A JP 2002-252326 A JP 2004-172157 A JP-A-6-268101

  In the above prior art, the following problems have occurred.

  In order to realize the small size and thinning required for PoP, it is necessary to thin the substrate and semiconductor element which are components of the package.

  However, the rigidity of the substrate depends on its thickness, and the rigidity becomes lower as it becomes thinner. If the rigidity of the substrate is lowered, warping is likely to occur. In addition, the board | substrate used here shall include the thing which has a wiring layer which connects the connection terminal of a some surface and a back surface, and also includes an interposer.

  FIG. 11 is a cross-sectional view for explaining problems in the prior art. FIG. 11A shows the first semiconductor package 100 and the second semiconductor package 200 before being stacked and connected. Here, in the first semiconductor package, the semiconductor element 12 is flip-chip connected to the substrate 11 having the connection land 14, and the gap between the substrate 11 and the semiconductor element 12 is filled with the underfill resin 13. As an example, the second semiconductor package shows a semiconductor element 12 connected by wire bonding.

  In general, in the manufacturing process of a semiconductor device, the entire and outer periphery of the semiconductor element 12 are sealed with a resin for protection. In the curing process after resin formation, shrinkage stress is generated, and the substrate 11 of the first semiconductor package 100 is warped as shown in FIG.

  Therefore, since the warp has occurred in the first semiconductor package 100, the first semiconductor package 100 and the second semiconductor package 200 are connected via a conductor, for example, a solder bump 19, as shown in FIG. In the case of stacked connection, a defect such as a defective connection portion 27 occurs between the conductive bump 19 and the connection land 14 of the first semiconductor package 100, and the reliability as a stacked semiconductor device is significantly reduced. There was a problem.

  According to the present invention, there is provided a stacked semiconductor device in which two or more semiconductor packages are stacked, wherein a first semiconductor package other than the semiconductor package disposed at the uppermost stage includes a semiconductor element mounted on a substrate and Having a resin formed on the substrate, having a plurality of openings from the resin upper surface to a connection land on the substrate, having an external connection terminal on the back surface of the substrate, and further, in the opening There is provided a stacked semiconductor device characterized in that a conductor for connecting to a second semiconductor package stacked on the first semiconductor package is formed.

  A method of manufacturing a stacked semiconductor device in which two or more semiconductor packages are stacked, wherein a semiconductor element is mounted on a substrate having a connection land in a first semiconductor package other than the semiconductor package disposed in the uppermost stage. A step of forming a resin on the substrate, a step of forming a plurality of openings from the top surface of the resin to the connection land, a step of forming an external connection terminal on the back surface of the substrate, There is provided a method for manufacturing a stacked semiconductor device, comprising a step of stacking and connecting a second semiconductor package on one semiconductor package.

  In the stacked semiconductor device and the manufacturing method thereof according to the present invention, the resin is formed on the substrate on which the semiconductor element is mounted in the first semiconductor package, and the opening from the resin upper surface to the connection land on the substrate is formed. Have. Since the occurrence of warping of the substrate is suppressed in the first semiconductor package, it is avoided that problems such as poor connection occur in the bump bonding portion when bonding to the second semiconductor package via a conductor. It is done. Therefore, the connection reliability in the stacked semiconductor device is significantly improved.

  ADVANTAGE OF THE INVENTION According to this invention, the curvature of a laminated semiconductor device can be suppressed and the laminated semiconductor device excellent in reliability and its manufacturing method can be provided.

1A and 1B are a cross-sectional view and a plan view of a semiconductor device according to a first embodiment of the invention. 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention. It is process sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing and the top view of a semiconductor device for demonstrating the prior art example relevant to the 1st Embodiment of this invention. 1A and 1B are a cross-sectional view and a plan view of a semiconductor device according to a first embodiment of the invention. It is process sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing of the semiconductor device which shows the 3rd Embodiment of this invention. It is sectional drawing of the semiconductor device which shows the 4th Embodiment of this invention. It is sectional drawing of the semiconductor device which concerns on the 5th Embodiment of this invention. It is sectional drawing of the semiconductor device which concerns on a prior art. It is sectional drawing of the semiconductor device which concerns on a prior art.

  Hereinafter, each embodiment of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1A is an example of a cross-sectional structure of PoP. The first semiconductor package 100 and the second semiconductor package 200 are stacked and connected. In this embodiment, since the semiconductor device has a two-layer structure, the second semiconductor package 200 is a semiconductor package arranged at the top. Here, the first semiconductor package 100 has a semiconductor element 12 flip-chip connected on a substrate 11, and an underfill resin 13 is filled between the substrate 11 and the semiconductor element 12. A bonding land 14 is provided on the outer periphery of the semiconductor element 12, and the entire area of the substrate 11 except for the semiconductor element 12 forming part is sealed with a resin 15. The resin 15 may be formed so as to cover the entire area of the substrate 11 including the semiconductor element 12 portion. However, in consideration of thinning as a stacked semiconductor device, the resin 15 is formed of a semiconductor element as shown in FIG. It is preferable to form on the substrate 11 excluding 12 parts and to expose the back surface of the semiconductor element 12.

  An opening 16 is formed from the upper surface of the resin 15 to the bonding land 14. In the figure, the opening 16 has a tapered shape, but the shape is not limited to this. For example, the upper surface and the lower surface of the opening may have substantially the same diameter. Ball electrodes 17 that are external connection terminals are formed on the back surface of the substrate 11. The openings 16 are not necessarily formed on all the connection lands 14 on the substrate 11.

  The structure of the second semiconductor package 200 is not particularly limited, and may be, for example, a flip chip BGA (ball grid array) or a tape BGA. The first semiconductor package 100 and the second semiconductor package 200 are connected by a conductor on the back surface of the second semiconductor package, for example, a solder bump 19. FIG. 1B is a plan view of the first semiconductor package 100.

  FIG. 2 shows another example of the cross-sectional structure of PoP. The lower first semiconductor package 100 is the same as the first semiconductor package described with reference to FIG. The second semiconductor package 200 is a semiconductor device in which the substrate 11 and the semiconductor element 12 are connected by wire bonding. The first semiconductor package 100 and the second semiconductor package 200 are electrically connected by a conductor, for example, a solder bump 19, of the opening 16 formed in the first semiconductor package 100.

  Note that the types and combinations of upper and lower packages or the number of stacked semiconductor packages are not limited to this, and are appropriately selected depending on the application.

  Next, a method for manufacturing a semiconductor device according to the present invention will be described with reference to FIG.

  As shown in FIG. 3A, the semiconductor element 12 is mounted on the substrate 11 of the first semiconductor package 100 via a solder ball 18 by flip chip connection. A connection land 14 is formed on the substrate 11. Further, as shown in FIG. 3B, the gap between the substrate 11 and the semiconductor element 12 is filled with the underfill resin 13.

  Next, as shown in FIG. 3C, the substrate 11 is sealed with a resin 15. The resin sealing does not necessarily need to be performed separately from the filling of the underfill resin 13 described with reference to FIG.

  Further, as shown in FIG. 3C, when the entire region of the substrate 11 is resin-sealed, an opening 16 extending from the upper surface of the resin 15 to the bonding land 14 on the substrate is provided. The opening 16 is arranged and formed in advance so as to match the position and size of the connecting portion on the back surface of the second semiconductor package 200 stacked in the upper stage.

  As an example of a method for providing the opening 16, resin sealing to the upper surface of the substrate 11 is performed by transfer sealing using a mold (not shown), and at that time, a desired opening shape is formed in a connection land portion of the mold. There is a method in which an opening is formed by providing opposed convex portions so that resin does not flow into the convex portions.

  Subsequently, as shown in FIG. 3D, ball electrodes 17 which are external connection terminals are formed on the back surface of the semiconductor device.

  Next, as shown in FIG. 3E, the second semiconductor package 200 is connected to the connection land 14 of the first semiconductor package 100 via the conductor on the back surface, for example, the solder bump 19. The solder bumps 19 of the second semiconductor package 200 are fitted into the openings 16 of the first semiconductor package 100. Note that the structure of the second semiconductor package 200 used here is not particularly limited, and may be, for example, a flip chip BGA or a tape BGA.

  Subsequently, as shown in FIG. 3F, by performing reflow, the solder bumps 19 of the second semiconductor package 200 are melted, and the shape thereof conforms to the shape of the opening 16 of the first semiconductor package 100. To do. The first semiconductor package 100 and the second semiconductor package 200 are electrically joined to complete PoP.

  According to the present embodiment, since the occurrence of warpage is suppressed in the first semiconductor package 100, when bonding to the second semiconductor package 200 through the conductor 19, connection is made at the bump bonding portion. The occurrence of defects such as defects can be avoided. In addition, since the connection strength is maintained, problems associated with mounting the package on the motherboard are also eliminated.

  In general, when manufacturing such a semiconductor device, in particular, the first semiconductor package 100, a matrix substrate 20 arranged in a lattice shape is used as a substrate instead of individual pieces prepared for each semiconductor element. It is done.

  4A and 4B show a plan view and a cross-sectional view of a conventional matrix substrate 20, respectively. As shown in the figure, in the matrix substrate 20, there are cases where defective portions 21 are mixed in the substrate. Such defective portions 21 are present randomly in the matrix substrate 20, and the semiconductor element 12 is not mounted on the portions. FIG. 4 shows an example in which semiconductor elements are flip-chip connected.

  In such a case, as shown in FIG. 4B, when the entire substrate is viewed, random irregularities corresponding to the mounting / non-mounting portions of the semiconductor element are generated. Therefore, when forming a ball electrode as an external connection terminal (ball mount) or separating from the matrix substrate 20 into a semiconductor package, a specially devised dedicated tool is required, etc. I had to devise.

  In general, when the ball mount or the package is separated, the matrix substrate 20 is fixed and held by vacuum suction. However, when there is a defective portion 21 in the matrix substrate 20 and the semiconductor element 12 is not mounted, a vacuum leakage occurs due to a step difference from the mounted portion, making it difficult to stably hold the substrate (FIG. 4B). )reference). In order to stably hold, it is necessary to suck a region where a semiconductor element is not mounted, and a dedicated suction jig subjected to high-precision processing is required.

  Further, when the semiconductor device is divided into individual pieces, a step is generated between the semiconductor element mounting portion and the non-mounting portion, which causes a problem in cutting.

  In the semiconductor device according to the present invention, even when there is a part where the semiconductor element is not mounted on the matrix substrate, the entire substrate is resin-sealed smoothly, so that it is affected by a randomly generated defective part on the substrate. There is no. FIG. 5A and FIG. 5B are a plan view and a cross-sectional view, respectively, of the matrix substrate according to the present invention. Since the entire area of the matrix substrate 20 is sealed with the resin 15, unevenness due to the presence or absence of the semiconductor element 12 does not occur (FIG. 5B). Thereby, there is a manufacturing merit that there is no need to prepare a specially devised special tool.

(Second Embodiment)
This embodiment differs from the first example in that the first semiconductor package is formed by wire bonding.

  A method for manufacturing a semiconductor device according to the present invention will be described with reference to FIG.

  As shown in FIG. 6A, the semiconductor element 12 is mounted on the substrate 11 of the first semiconductor 100 and connected by wires. A connection land 14 is formed on the substrate 11.

  Next, the entire area of the substrate 11 is sealed with the resin 15. As shown in FIG. 6B, when the entire substrate 11 is resin-sealed, an opening 16 is provided from the upper surface of the resin 15 to the bonding land 14 on the substrate. The opening 16 is arranged and formed in advance so as to match the position and size of the connecting portion on the back surface of the second semiconductor package 200 stacked in the upper stage.

  As an example of the method of providing the opening 16, resin sealing onto the substrate 11 of the first semiconductor package is performed by transfer sealing using a mold (not shown), and at this time, a desired connection land portion of the mold is desired. There is a method of forming an opening portion by providing a protrusion portion corresponding to the shape of the opening portion so that resin does not flow into the protrusion portion.

  Subsequently, as shown in FIG. 6C, ball electrodes 17 that are external connection terminals are formed on the back surface of the first semiconductor package 100.

  Next, as shown in FIG. 6D, the second semiconductor package 200 is connected to the connection land 14 of the first semiconductor package 100 via the conductor on the back surface, for example, the solder bump 19. The solder bumps 19 of the second semiconductor package 200 are fitted into the openings 16 of the first semiconductor package 100. The second semiconductor package 200 is formed by wire bonding, for example.

  Subsequently, as shown in FIG. 6E, by performing reflow, the solder bumps 19 of the second semiconductor package 200 are melted, and the shape thereof becomes the shape of the opening 16 of the first semiconductor package 100. Fits. The first semiconductor package 100 and the second semiconductor package 200 are electrically joined to complete PoP.

(Third embodiment)
This embodiment is characterized in the step of stacking the second semiconductor package on the first semiconductor package. Accordingly, the other manufacturing steps are the same as those in the first embodiment or the second embodiment, and thus description thereof is omitted.

  As shown in FIG. 7A, a conductive material such as a solder paste 23 is embedded in the opening 16 using the squeegee 24 through the screen mask 22 on the first semiconductor package 100 having the opening 16.

  As shown in FIG. 7B, the solder bumps 19 on the back surface of the second semiconductor package 200 are arranged on the opening of the first semiconductor package 100 and stacked.

  Subsequently, as shown in FIG. 7C, the solder bumps 19 and the solder paste 23 are dissolved by the reflow process, and the connecting portions are integrated.

  In the present embodiment, the solder paste 23 or the like is embedded in the opening 16 of the first semiconductor package, so that the bonding with the second semiconductor package located on the upper portion can be made more reliable, and the mounting yield as PoP. Improvements can be made.

(Fourth embodiment)
This embodiment is characterized in the step of stacking the second semiconductor package on the first semiconductor package. Accordingly, the other manufacturing steps are the same as those in the first embodiment or the second embodiment, and thus description thereof is omitted.

  FIG. 8 shows a cross-sectional structure of PoP in which the first semiconductor package 100 and the second semiconductor package 200 are stacked. Before the two semiconductor devices are stacked, an adhesive, for example, a thermosetting adhesive 25 is applied to the back surface of the second semiconductor package except for the conductor bumps, for example, 19 parts of the solder bumps. The thermosetting adhesive 25 is present at the stacked interface between the first semiconductor device 100 and the second semiconductor package 200, and exhibits the function of integrating the two semiconductor devices.

  Accordingly, when attention is paid to the solder bumps 19 of the second semiconductor package 200, the semiconductor device has the same structure as if the underfill resin was injected by the resin 15 and the thermosetting adhesive 25 of the first semiconductor package 100. The joint reliability can be improved.

(Fifth embodiment)
This embodiment is characterized in the step of stacking the second semiconductor package on the first semiconductor package. Accordingly, the other manufacturing steps are the same as those in the first embodiment or the second embodiment, and thus description thereof is omitted.

  As shown in FIG. 9A, the first semiconductor package 100 is constituted by semiconductor elements 12 that are flip-chip connected. A film having a heat radiation function, for example, a heat radiation paste 26 is applied to the back surface of the semiconductor element 12.

  As illustrated in FIG. 9B, when the second semiconductor package 200 is stacked on the first semiconductor package 100, the heat generated from the first semiconductor package 100 is generated by the heat radiation paste 26, and the second semiconductor package 200. To be dissipated. That is, according to this embodiment, the second semiconductor package 200 functions as a heat sink of the first semiconductor package 100. Therefore, according to the present embodiment, heat generated in the first semiconductor device 100 can be effectively dissipated, and connection reliability can be further improved.

DESCRIPTION OF SYMBOLS 11 Board | substrate 12 Semiconductor element 13 Underfill resin 14 Connection land 15 Resin 16 Opening part 17 Ball electrode 18 Solder ball 19 Conductor (solder bump)
20 matrix substrate 21 defective portion 22 screen mask 23 solder paste 24 squeegee 25 thermosetting adhesive agent 26 heat radiation paste 27 poor connection portion 100 first semiconductor package 200 second semiconductor package

A step of preparing a substrate having a plurality of connection lands formed on the surface and a plurality of connection terminals formed on the back surface opposite to the surface; and a step of disposing a semiconductor element on the surface of the substrate And a plurality of openings exposing the connection lands on the bottom surface, forming a resin that is not formed on the back surface side of the substrate and is formed on the surface of the substrate, and In the step of forming the resin, the resin flows into the convex portion of the resin-sealed mold by a resin-sealed mold having a convex portion facing the connection land formed on the surface of the substrate. There is provided a method of manufacturing a semiconductor device in which the resin is formed so as not to exist .

Claims (13)

A stacked semiconductor device in which two or more semiconductor packages are stacked,
The first semiconductor package other than the semiconductor package arranged at the top is
Having a semiconductor element mounted on a substrate and a resin formed on the substrate;
Having a plurality of openings from the resin upper surface to the connection land on the substrate;
An external connection terminal on the back surface of the substrate;
Further, a conductor for connecting to a second semiconductor package stacked on the first semiconductor package is formed in the opening. The stacked semiconductor device according to claim 1, wherein the conductor formed in the opening is a solder paste. An upper surface of the first semiconductor package;
Having an adhesive between the lower surface of the second semiconductor package;
The stacked semiconductor device according to claim 1, wherein the semiconductor packages are fixed to each other through the adhesive. In the stacked semiconductor device in which the semiconductor elements of the first semiconductor package are flip-chip connected,
2. The stacked semiconductor device according to claim 1, wherein a film having a heat dissipation function is formed between a back surface of the semiconductor element and a bottom surface of the second semiconductor package. The stacked semiconductor device according to claim 4, wherein the film is a heat radiation paste. A method of manufacturing a stacked semiconductor device in which two or more semiconductor packages are stacked,
A step of mounting a semiconductor element on a substrate having a connection land by a first semiconductor package other than the semiconductor package disposed at the uppermost stage;
Forming a resin on the substrate;
Forming a plurality of openings from the resin upper surface to the connection land;
A method of manufacturing a stacked semiconductor device, comprising: forming an external connection terminal on a back surface of the substrate; and stacking and connecting a second semiconductor package on the first semiconductor package. In the step of stacking and connecting a second semiconductor package on the first semiconductor package,
The method of manufacturing a stacked semiconductor device according to claim 6, further comprising a step of adapting a conductor formed on a back surface of the second semiconductor package to an opening of the second semiconductor package. In the step of stacking and connecting a second semiconductor package on the first semiconductor package,
The method for manufacturing a stacked semiconductor device according to claim 6, further comprising a step of filling the opening with a conductor. 9. The method for manufacturing a stacked semiconductor device according to claim 8, wherein the conductor filled in the opening is a solder paste. In the step of stacking and connecting a second semiconductor package on the first semiconductor package,
10. The method of manufacturing a stacked semiconductor device according to claim 6, further comprising a step of fixing the upper surface of the first semiconductor package and the lower surface of the second semiconductor package with an adhesive. In the step of stacking and connecting a second semiconductor package on the first semiconductor package,
The method for manufacturing a stacked semiconductor device according to claim 10, further comprising a step of applying the adhesive material to a region other than a region where the conductor on the back surface of the second semiconductor package is formed. In the step of stacking and connecting a second semiconductor package on the first semiconductor package,
12. The method for manufacturing a stacked semiconductor device according to claim 6, further comprising a step of forming a film having a heat dissipation function on the back surface of the flip-chip connected semiconductor element. 13. The method of manufacturing a semiconductor device according to claim 12, wherein the film having a heat dissipation function is a heat dissipation paste.

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