JP2012009617A - Semiconductor device manufacturing method, copper alloy for wiring, and semiconductor device - Google Patents

Abstract

The yield and reliability of a semiconductor device are improved.
A Cu film 5b on a barrier metal film 3b other than a portion embedded in a wiring recess is removed by chemical mechanical polishing. Then, a layer 6b made of an additive element is formed on the Cu film 5b in the wiring recess. The additive element is diffused from the layer 6b into the Cu film 5b, and the Cu surface, the boundary of the Cu crystal grain, and the interface where the concentration of the additive element is higher than the inside of the Cu crystal grain at and near the grain boundary. While being formed, oxygen in the Cu film 5b is gettered to the layer 6b. Thereafter, the excessive layer 6b is removed, and the barrier metal film 3b on the insulating film is further removed.
[Selection] Figure 2

Description

  The present invention relates to a method for manufacturing a semiconductor device having copper wiring, a copper alloy for wiring, and a semiconductor device.

Aluminum (Al) or an Al alloy has been widely used as a wiring material for semiconductor devices, and a silicon oxide film (SiO ₂ ) has been widely used as an interlayer insulating film material. However, with the progress of miniaturization and speeding up of semiconductor devices, copper (Cu), which has a lower resistance as a wiring material, and a low dielectric constant, which is a lower dielectric constant, can be used to improve signal transmission delay in wiring. Dielectric constant films, such as SiOCH films, have been used.

When forming a Cu wiring, a damascene method is generally used because it is difficult to process by dry etching. The damascene method is a method of forming a Cu wiring by forming a groove on an insulating film formed on a semiconductor substrate, burying Cu in the groove, and polishing excess Cu other than the wiring groove. In order to prevent diffusion of Cu into the insulating film and corrosion of Cu, it is necessary to provide a barrier metal layer around Cu.
Below, the manufacturing method of a general Cu wiring is demonstrated using FIG.

  FIG. 10A shows a lower layer wiring on which an upper layer wiring is formed. The lower layer wiring has a structure in which a cap insulating film 6a is formed on the SiOCH film 1a as an insulating film, and a Cu wiring 5a is embedded in a wiring groove or wiring hole in which a barrier metal film 4a is formed inside. The lower layer wiring can also be formed by the same process as the upper layer wiring described below.

  First, as shown in FIG. 10B, an insulating film 1b made of a SiOCH film is formed on the lower wiring. Next, as shown in FIG. 10C, wiring grooves or wiring holes are formed in the insulating film 1b by lithography and anisotropic etching. Subsequently, as shown in FIG. 10D, a barrier metal film 3b, which is a conductor film, is formed on the wiring groove or wiring hole, and Cu 4b is embedded in the wiring groove or wiring hole. Next, excess Cu 4b and the barrier metal film 3b outside the wiring trench or wiring hole are removed by chemical mechanical polishing (CMP) (FIG. 10E). On this, a cap insulating film 6b, which is an insulator, is formed, and as shown in FIG. 10 (f), the lower and side surfaces are covered with the barrier metal film 3b and the upper surface is covered with the cap insulating film 6b. A wiring structure is formed.

  Silicon nitride (SiN), silicon carbonitride (SiCN), or the like is used as a barrier insulating film covering the Cu wiring surface. Generally, the relative dielectric constant of these films is as high as 5.0 or more, and the effective wiring is effective. It is difficult to reduce the dielectric constant and thus improve the signal transmission delay in the wiring. In order to reduce the effective dielectric constant of wiring, studies have been made to apply a film having a lower relative dielectric constant as a barrier insulating film. However, in that case, since the Cu diffusion preventing effect is insufficient or the adhesiveness with Cu is insufficient, there is a problem in reliability that electromigration (EM) resistance is deteriorated and disconnection is likely to occur. . Furthermore, the water resistance of the film deteriorates as the dielectric constant of the barrier insulating film decreases, so that moisture in the manufacturing process permeates through the barrier insulating film, and Cu on the Cu wiring surface under the barrier insulating film is oxidized. It becomes unstable. When the Cu surface is oxidized and destabilized, Cu is more easily diffused, and the EM resistance is further deteriorated. In addition, due to the effect of Cu surface oxidation, Cu on the surface is liable to diffuse to the barrier insulating film / insulating film interface due to electric field drift, so that there is a problem of reliability that TDDB (Time Dependent Dielectric Breakdown) resistance deteriorates. . Here, the barrier insulating film / Cu interface is a main diffusion path of copper atoms in EM and TDDB, and is the weakest interface in terms of reliability.

  In order to improve the EM reliability, a metal cap technique using a metal film instead of an insulating film as a cap film on the Cu surface has been studied. As a method for forming the metal cap layer, a Cu (Chemical Vapor Deposition) method (for example, see Patent Document 1) or a method by electroless plating (for example, see Patent Document 2) is selectively used. A method of forming a metal cap layer only on the wiring has been studied.

  Further, in Patent Document 3, in order to suppress electromigration, in the surface of the polycrystalline copper alloy constituting the copper wiring and in the vicinity of the surface, and in the crystal grain boundary and in the vicinity of the grain boundary constituting the polycrystalline copper alloy, It is disclosed that the concentration of the additive element is higher than that inside the crystal grains.

JP 2001-319928 A Special table 2003-505882 gazette International Publication No. 04/053971 Pamphlet

  However, in the selective growth process on the Cu wiring by the CVD or electroless plating, there is a possibility that the selection is essentially broken. In this case, the leakage between wiring due to the formation of metal on the insulating film Deterioration of inter-wiring TDDB resistance becomes a problem.

  In addition, in order to reduce the parasitic capacitance between wirings, carbon (C) is introduced to lower the polarizability, and pores are further introduced into the film to reduce the relative dielectric constant to 2.6 or less. Porous) An SiOCH film is about to be used, but when such a porous film is exposed on the surface, if the wafer surface is exposed to a CVD raw material or an electroless plating solution, the metal in the CVD raw material or the plating solution As the molecules diffuse into the porous film, the insulating properties and reliability are significantly degraded.

  Furthermore, when a porous SiCOH film is used as the insulating film, moisture during the CMP process is accumulated in the vacancies when the SiOCH film is exposed during CMP when forming the Cu wiring by the damascene method. There was a problem that the Cu surface was corroded.

A method of manufacturing a semiconductor device according to the present invention includes a step of forming an insulating film on a substrate on which a semiconductor element is formed,
Forming a recess for wiring comprising at least one of a groove and a hole in the insulating film;
Forming a barrier metal film for preventing Cu diffusion on the insulating film including the inner surface of the recess;
Forming a Cu film on the barrier metal film so as to be embedded in the recess;
Removing the Cu film on the barrier metal other than the portion embedded in the recess by chemical mechanical polishing;
Forming a layer of an additive element on the Cu film in the recess;
The additive element is diffused from the layer of the additive element into the Cu film, and the concentration of the additive element is higher than the inside of the Cu crystal grain at the Cu surface, the grain boundary of the Cu crystal grain, and the position near the grain boundary. Forming a high interface and its vicinity, and gettering oxygen in the Cu film to the layer of the additive element;
Removing a layer of excess additive elements;
Removing the barrier metal film on the insulating film;
It is characterized by having.

  According to the present invention, by adding a different element at a high concentration to the Cu surface, the Cu wiring surface and the vicinity of the surface, which are EM diffusion paths, are stabilized, and Cu migration along the Cu wiring surface is suppressed. it can. For this reason, the reliability of the wiring of the semiconductor device is improved. In addition, when an element that is more reducible and more easily oxidized than Cu is used as an additive element, the Cu surface and the Cu interior are cleaned by the gettering action of oxygen and impurities present in the Cu surface and Cu. . The oxygen present in the Cu surface and Cu diffuses during the heat treatment and may oxidize the underlying barrier metal. In this case, the adhesion between Cu and the barrier metal deteriorates, adversely affecting the reliability of the wiring. . Gettering the oxygen present in the Cu surface and Cu also suppresses the oxidation of the barrier metal and is effective in improving the reliability of the Cu wiring. Furthermore, even after the removal of the barrier metal on the insulating film, the high concentration of the additive element remains on the Cu surface, so that even if the surface is exposed to an oxidizing atmosphere such as moisture, the additive element is oxidized. Since the stable layer is formed, migration of Cu along the surface of the Cu wiring can be suppressed, and the reliability of the wiring of the semiconductor device is improved. Also, when a porous SiCOH film having a large pore diameter is used as the inter-wiring insulating film, moisture is easily taken into the film, and the adjacent Cu wiring surface is easily exposed to moisture in an oxidizing atmosphere. The surface becomes more unstable, pit and hillock defects occur, and this is a factor that greatly deteriorates the product yield of semiconductor devices. In the present invention, the Cu surface can be stabilized before the barrier metal is removed and the porous SiCOH film is exposed, so that the yield and reliability of the semiconductor device are improved.

The copper alloy for wiring according to the present invention is composed of a polycrystalline copper alloy containing Cu (copper) as a main component and containing an additive element,
The concentration of the additive element is higher in the surface of the polycrystalline copper alloy and in the vicinity of the surface, and in the crystal grain boundary of the crystal grains constituting the polycrystalline copper alloy and in the vicinity of the grain boundary than in the crystal grains,
Furthermore, a barrier metal is formed in the periphery, and the concentration of the additive element is higher than the inside of the crystal grain at the interface with the barrier metal and in the vicinity of the interface,
The thickness of the surface layer having a high concentration of the additive element is less than 30 nm,
The barrier metal located at the interface with the polycrystalline copper alloy is not oxidized.

  According to the present invention, the migration of Cu along the surface of the Cu wiring can be suppressed by introducing an additive element at a high concentration on the surface of the Cu wiring, which is an EM diffusion path of the wiring, and in the vicinity of the surface. Can improve the reliability. Also, by distributing the additive element at a higher concentration near the crystal grain boundary and interface than in the Cu grains, it is possible to effectively suppress Cu migration at the grain boundary / interface while suppressing an increase in wiring resistance. Can do. Further, since the barrier metal is not oxidized, deterioration of the adhesion between Cu and the barrier metal is suppressed, thereby improving the yield and reliability of the semiconductor device.

  A semiconductor device according to the present invention is characterized in that a metal wiring made of the copper alloy for wiring according to any one of claims 8 to 14 is formed on a substrate on which a semiconductor element is formed.

  According to the present invention, the yield and reliability of a semiconductor device can be improved.

It is sectional drawing shown to process order of 1st Embodiment of the manufacturing method of the semiconductor device which concerns on this invention. It is sectional drawing shown to process order of 1st Embodiment of the manufacturing method of the semiconductor device which concerns on this invention. It is a figure which shows the process following FIG. It is sectional drawing shown to process order of 2nd Embodiment of the manufacturing method of the semiconductor device which concerns on this invention. It is sectional drawing shown to process order of 2nd Embodiment of the manufacturing method of the semiconductor device which concerns on this invention. FIG. 4 is a diagram illustrating a process following FIG. 3. It is sectional drawing shown to process order of 3rd Embodiment of the manufacturing method of the semiconductor device which concerns on this invention. It is sectional drawing shown to process order of 3rd Embodiment of the manufacturing method of the semiconductor device which concerns on this invention. FIG. 6 is a diagram showing a step following FIG. 5. It is sectional drawing shown to process order of the modification of 1st Embodiment of the manufacturing method of the semiconductor device which concerns on this invention. It is sectional drawing shown to process order of the modification of 1st Embodiment of the manufacturing method of the semiconductor device which concerns on this invention. FIG. 8 is a diagram showing a step following FIG. 7. It is sectional drawing shown to process order of the modification of 1st Embodiment of the manufacturing method of the semiconductor device which concerns on this invention. FIG. 9 is a diagram illustrating a process following the process in FIG. 8. It is sectional drawing which shows the manufacturing process of general Cu wiring.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

  Before describing the present invention in detail, the meaning of terms in the present application will be described.

  The insulating film is, for example, a film (interlayer insulating film) that isolates and isolates the wiring material. A low dielectric constant insulating film refers to a material having a relative dielectric constant lower than that of a silicon oxide film (relative dielectric constant 4.5) in order to reduce the capacitance between multilayer wirings connecting semiconductor elements. In particular, as the porous insulating film, for example, a material obtained by making a silicon oxide film porous to reduce the relative dielectric constant, an HSQ (Hydrogen Silsesquioxane) film, and an organic silica such as SiOCH or SiOC There are those in which the relative permittivity is reduced by making the system material porous. It is desired to further reduce the dielectric constant of these films.

  The damascene wiring refers to a buried wiring formed by embedding a metal layer in a groove of an interlayer insulating film formed in advance and removing an excess metal layer other than the inside of the groove by, for example, CMP. For example, when damascene wiring is formed of a copper layer, a wiring structure in which the side and bottom surfaces of the copper layer are covered with a barrier metal and the upper surface of the copper layer is covered with an insulating barrier film is generally used.

  The CMP method is a method of flattening the unevenness on the wafer surface generated during the multilayer wiring formation process by polishing the wafer by bringing the slurry into contact with a rotating polishing pad while flowing the slurry on the wafer surface. In wiring formation by the damascene method, in particular, after a metal is buried in a wiring groove or a via hole (wiring hole), it is used for removing a surplus metal portion and obtaining a flat wiring surface.

  The barrier metal refers to a conductive film having a barrier property that covers the side and bottom surfaces of the wiring in order to prevent a metal element constituting the wiring from diffusing into the interlayer insulating film and the lower layer. For example, when the wiring is made of a metal element mainly composed of Cu, a refractory metal such as tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), tungsten carbonitride (WCN), and nitriding thereof A thing etc. or those laminated films are used. In recent years, ruthenium (Ru) has been studied as a barrier metal film for fine wiring because of its low specific resistance and direct Cu plating on ruthenium.

  The barrier insulating film is an insulating film that is formed on the upper surface of the copper wiring layer and has a function of preventing Cu oxidation and diffusion of Cu into the insulating film, and also serves as an etching stop layer during processing. Conventionally, SiN films, SiCN films, SiC films, and the like have been used.

  The metal cap film is a metal film that is formed on the upper surface of the copper layer and has a function of preventing Cu oxidation and Cu diffusion into the insulating film. For example, CoWP and CoWB are being studied. Improvement of wiring signal transmission delay due to the elimination of the barrier insulating film and improvement of wiring reliability such as electromigration (EM) resistance and stress migration (SM) are expected.

  A semiconductor substrate is a substrate on which a semiconductor device is configured. In particular, an SOI (Silicon on Insulator) substrate, a TFT (Thin film transistor), a liquid crystal manufacturing substrate, etc. Including the substrate.

  A hard mask refers to an insulating film that serves as a protective layer to be stacked on an interlayer insulating film when it is difficult to perform direct CMP due to a decrease in strength due to the lower dielectric constant of the interlayer insulating film. Since the hard mask has a relatively high dielectric constant, in order to reduce the effective dielectric constant, the hard mask may be removed during CMP to expose the low dielectric constant film.

  In the plasma CVD method, for example, a gaseous raw material is continuously supplied to a reaction chamber under reduced pressure, molecules are excited by plasma energy, and a continuous film is formed on the substrate by a gas phase reaction or a substrate surface reaction. It is a technique to form.

  As the PVD method, a normal sputtering method may be used. However, in order to improve the embedding characteristics, the film quality, and the uniformity of the film thickness within the wafer surface, a sputtering method with high directivity can be used. For example, there are a long throw sputtering method, a collimated sputtering method, an ionized sputtering method, and the like. When sputtering an alloy, a metal film other than the main component is previously contained in the metal target at a solid solubility limit or less, so that the formed metal film can be used as an alloy film. In the present invention, it can be used when forming a Cu seed layer and a barrier metal layer when a copper wiring layer is formed mainly by a damascene method.

(First embodiment)
Hereinafter, embodiments of the present invention will be specifically described with reference to the accompanying drawings. First, a first embodiment of the present invention will be described. FIGS. 1A to 1E and FIGS. 2A to 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the first embodiment in the order of steps.

  FIG. 1 (a) shows a lower layer wiring on which an upper layer wiring is formed. This lower layer wiring includes an insulating film 1a, a barrier metal 3a, and polycrystalline Cu 5a, a Cu wiring surface having a high additive element concentration and a surface vicinity 7a, and a crystal grain boundary / barrier metal interface having a high additive element concentration and its vicinity 8a. It is composed of a Cu wiring and a barrier insulating film 9a. Although this portion can also be formed using the same process as the upper layer wiring shown below, in this specification, a method for manufacturing the upper layer wiring will be described for the sake of convenience.

  First, as shown in FIG. 1B, an insulating film 1b is formed on the entire surface of the lower layer wiring. As the insulating film 1b, for example, organic silica (SiOCH) can be used. Next, as shown in FIG. 1C, wiring grooves and wiring holes (hereinafter also referred to as openings) are formed in the insulating film 1b. This step can be performed, for example, by lithography and anisotropic etching. When the wiring hole is formed, etching is performed to such an extent that the lower copper wiring layer is exposed on the bottom surface of the wiring hole.

  Next, as shown in FIG. 1D, a barrier metal film 3b is formed on the surface including the opening. As the barrier metal film 3b, for example, Ta, TaN, TiN, WCN, Ru, or the like can be used. Thereafter, Cu 4b is formed using, for example, a plating method so as to be embedded in the wiring groove and the wiring hole. Next, as shown in FIG. 1E, a heat treatment is performed for growing embedded Cu crystal grains. This heat treatment is performed at a low temperature of 300 ° C. or lower. Preferably it is 150 degrees C or less. This heat treatment for Cu grain growth can be omitted. By this treatment, Cu4b is changed to polycrystalline Cu5b having large crystal grains. In addition, by setting the temperature of this heat treatment to 150 ° C. or less, it is possible to prevent the barrier metal film 3b from being oxidized by the surface of the Cu4b serving as the plating layer and oxygen in the Cu4b.

  Thereafter, as shown in FIG. 2A, excess Cu 5b other than the wiring trench and the wiring hole is removed by CMP. Thereby, polycrystalline Cu 5a is embedded in the wiring groove and the wiring hole. At this time, the barrier metal film 3b on the insulating film 1b is left without being removed.

  Next, as shown in FIG. 2B, an element layer 6b to be added to Cu is formed on the Cu surface. The layer 6b is formed by, for example, a sputtering method. Thereafter, as shown in FIG. 2 (c), a heat treatment for diffusing the additive element in Cu is performed. As this heat treatment, for example, the treatment is performed at a temperature of 200 ° C. to 400 ° C. for 30 seconds to 1 hour in an inert gas or reducing gas atmosphere.

By this heat treatment, an additive element is added to Cu. The additive element layer 6b is a layer containing at least one element selected from the group consisting of water-soluble metals such as Ti, Zr, Hf, and Al. These additive elements are elements having a solid solubility limit in the Cu film of 1 atomic% or less and a large diffusion coefficient at the Cu crystal grain boundary. By adding this additive element into the Cu film, it is possible to introduce the additive element at a high concentration into the crystal grain boundary in the Cu film and in the vicinity of the crystal grain boundary, or in the Cu crystal grain / barrier metal interface and in the vicinity of the interface 8b. it can. Specifically, the concentration of the additive element inside the Cu crystal grains (for example, the center) is 0.1 atomic% or less. The concentration of the additive element in the grain boundary of the Cu crystal grains and in the vicinity of the grain boundary is 2 to 1000 times, more specifically 10 to 100 times the concentration of the additive element in the crystal grains. Further, since the additive element diffuses from the Cu surface, a layer 7b of a high concentration additive element is also formed on the Cu surface.
In addition, the heat treatment simultaneously cleanses the Cu surface and the Cu interior by gettering the Cu surface and oxygen inside the Cu to the layer of the additive element.

  Next, as shown in FIG. 2D, the excessive additive element layer 6b and the barrier metal film 3b are removed by CMP. At this time, the amount of CMP polishing is controlled so that the high-concentration additive element layer 7b remains on the surface of Cu5b. The removal of the excessive additive element layer 6b and the removal of the barrier metal film 3b can be performed in the same process. The remaining high-concentration additive element layer 7b has a thickness of, for example, less than 30 nm. By doing so, since the high-concentration impurity-added layer 7b having high resistance is formed only on the wiring surface, the Cu wiring surface, which is the Cu diffusion path, is stabilized while suppressing an increase in the resistance of the entire wiring. As a result, the reliability of the wiring can be improved effectively.

  Next, as shown in FIG. 2E, a barrier insulating film 9b for preventing corrosion and diffusion of Cu is formed on the entire surface by plasma CVD. For example, SiCN can be used as the barrier insulating film 9b.

  By repeating the steps shown in FIG. 1B to FIG. 2E, an upper wiring layer can be further laminated. In this embodiment, the dual damascene method for forming the wiring groove and the wiring hole at the same time has been described. However, only the wiring groove or the single damascene method for forming only the wiring hole is used for forming the wiring recess. The same applies. The additive element layer 6b may be a layer containing at least one element selected from the group consisting of Cr, Co, Ru, Sn, Ni, Mg, Mn, and W.

  As described above, according to the present embodiment, when forming the layer 6b of the additive element, the barrier metal film 3b is not removed from the insulating film 1b. Then, after the high concentration additive element layer 7b is formed on the surface of Cu5b, the barrier metal film 3b is removed. For this reason, it can suppress that Cu5b is exposed to oxidizing atmospheres, such as a water | moisture content, before an additional element is introduce | transduced into Cu5b. Further, at the stage of removing the barrier metal film 3b, since the high concentration additive element layer 7b is formed on the surface of the Cu 5b, even if the surface is exposed to an oxidizing atmosphere such as moisture, Oxidized, and a stable layer of oxide of the additive element is formed on and near the surface of the polycrystalline copper alloy. For this reason, Cu migration along the surface of the Cu wiring can be suppressed, and the reliability of the wiring of the semiconductor device is improved. This effect is particularly remarkable when the insulating film 1b is a film that easily absorbs water, such as a porous film.

(Second Embodiment)
A method of manufacturing a semiconductor device according to the second embodiment of the present invention will be described with reference to FIGS. 3 (a) to 3 (e) and FIGS. 4 (a) to 4 (e).

  In the manufacturing method of the second embodiment, when excess Cu is removed by CMP, a recess is formed in the wiring trench by overpolishing Cu in the wiring trench by setting the CMP processing time longer than usual. Except for this point, the second embodiment is the same as the first embodiment. As a result, the same effects as those of the first embodiment can be obtained, and the layer 6b of the additive element remains on the Cu surface even after removal of the barrier metal by CMP. A metal cap made of the additive element layer 6b is formed on the wiring surface, further improving the stability of the wiring surface and suppressing the migration of Cu on the wiring surface, thereby further improving the reliability. .

  FIG. 3A shows the lower layer wiring on which the upper layer wiring is formed. This lower layer wiring includes an insulating film 1a, a barrier metal 3a, and polycrystalline Cu 5a, a Cu wiring surface having a high element concentration and the vicinity of the surface 7a, a crystal grain boundary / barrier metal interface having a high additive element concentration and its vicinity 8a, and A Cu wiring made of an additive element layer 6a formed on the surface, and a barrier insulating film 9a. Although this portion can also be formed using the same process as the upper layer wiring shown below, in this specification, a method for manufacturing the upper layer wiring will be described for the sake of convenience.

  First, as shown in FIG. 3B, an insulating film 1b is formed on the entire surface of the lower layer wiring. As the insulating film 1b, for example, organic silica (SiOCH) can be used. Next, as shown in FIG. 3C, wiring grooves and wiring holes (hereinafter also referred to as openings) are formed in the insulating film 1b. This step can be performed, for example, by lithography and anisotropic etching. When the wiring hole is formed, etching is performed to such an extent that the lower copper wiring layer is exposed on the bottom surface of the wiring hole.

  Next, as shown in FIG. 3D, a barrier metal film 3b is formed on the surface including the opening. As the barrier metal film 3b, for example, Ta, TaN, TiN, WCN, Ru, or the like can be used. Thereafter, Cu 4b is formed using, for example, a plating method so as to be embedded in the wiring groove and the wiring hole. Next, as shown in FIG. 3E, heat treatment is performed for growing embedded Cu crystal grains. This heat treatment is performed at a low temperature of 300 ° C. or lower. Preferably it is 150 degrees C or less. This heat treatment for Cu grain growth can be omitted. By this treatment, Cu4b is changed to Cu5b having large crystal grains.

  Thereafter, as shown in FIG. 4A, excess Cu other than the wiring trench and the wiring hole is removed by CMP. Thereby, the polycrystalline Cu 5a is embedded in the wiring groove and the wiring hole. At this time, a recess is formed in the wiring groove by setting a CMP processing time longer than usual to partially remove Cu inside the wiring groove. At this time, the barrier metal film 3b on the insulating film is left without being removed.

  Next, as shown in FIG. 4B, an element layer 6b to be added to Cu is formed on the Cu surface. Thereafter, as shown in FIG. 4C, heat treatment for diffusing additive elements in Cu is performed. As this heat treatment, for example, the treatment is performed at a temperature of 200 ° C. to 400 ° C. for 30 seconds to 1 hour in an inert gas or reducing gas atmosphere.

By this heat treatment, an additive element is added to Cu. The additive element layer 6b is a layer containing at least one element selected from the group consisting of Ti, Zr, Hf, and Al. These additive elements are elements having a solid solubility limit in the Cu film of 1 atomic% or less and a large diffusion coefficient at the Cu crystal grain boundary. By adding this additive element to the Cu film, An additive element can be introduced at a high concentration in the crystal grain boundary and in the vicinity of the crystal grain boundary, or in the Cu crystal grain / barrier metal interface and in the vicinity of the interface 8b. Specifically, the concentration of the additive element inside the Cu crystal grains (for example, the center) is 0.1 atomic% or less. The concentration of the additive element in the grain boundary of the Cu crystal grains and in the vicinity of the grain boundary is 2 to 1000 times, more specifically 10 to 100 times the concentration of the additive element in the crystal grains. Further, since the additive element diffuses from the Cu surface, a layer 7b of a high concentration additive element is also formed on the Cu surface.
In addition, the heat treatment simultaneously cleanses the Cu surface and the Cu interior by gettering the Cu surface and oxygen inside the Cu to the layer of the additive element.

  Next, as shown in FIG. 4D, the excessive additive element layer 6b and the barrier metal film 3b are removed by CMP. At this time, the CMP polishing amount is controlled so that the additive element layer 6b remains on the wiring surface. By simultaneously removing the excess additive element layer 6b and the barrier metal film 3b, the manufacturing process can be simplified.

  Next, as shown in FIG. 4E, a barrier insulating film 9b for preventing corrosion and diffusion of Cu is formed on the entire surface by plasma CVD. For example, SiCN can be used as the barrier insulating film 9b.

  By repeating the steps shown in FIG. 3B to FIG. 4E, an upper wiring layer can be further laminated. In this embodiment, the dual damascene method for forming the wiring groove and the wiring hole at the same time has been described. However, only the wiring groove or the single damascene method for forming only the wiring hole is used for forming the wiring recess. The same applies. The additive element layer 6b may be a layer containing at least one element selected from the group consisting of Cr, Co, Ru, Sn, Ni, Mg, Mn, and W.

(Third embodiment)
A method of manufacturing a semiconductor device according to the third embodiment of the present invention will be described with reference to FIGS. 5 (a) to 5 (e) and FIGS. 6 (a) to 6 (d).

  The structure of the third embodiment is different from the structure of the second embodiment in that the barrier insulating film 9b is not used. As a result, the same effects as those of the first embodiment can be obtained, and the oxidation and corrosion of Cu can be prevented by forming a metal cap made of a stable additive element layer 6b on the Cu surface. For this reason, the barrier insulating film 9b becomes unnecessary. Since the effective dielectric constant of the Cu wiring is reduced by not providing the barrier insulating film 8b, the transmission delay can be improved.

  FIG. 5 (a) shows a lower layer wiring on which an upper layer wiring is formed. This lower layer wiring includes an insulating film 1a, a barrier metal 3a, and polycrystalline Cu 5a, a Cu wiring surface having a high element concentration and the vicinity of the surface 7a, a crystal grain boundary / barrier metal interface having a high additive element concentration and its vicinity 8a, and It is constituted by a Cu wiring made of an additive element layer 6a formed on the surface. Although this portion can also be formed using the same process as the upper layer wiring shown below, in this specification, a method for manufacturing the upper layer wiring will be described for the sake of convenience.

  First, as shown in FIG. 5B, an insulating film 1b is formed on the entire surface of the lower layer wiring. As the insulating film 1b, for example, organic silica (SiOCH) can be used. Next, as shown in FIG. 5C, wiring grooves and wiring holes (hereinafter also referred to as openings) are formed in the insulating film 1b. This step can be performed, for example, by lithography and anisotropic etching. When the wiring hole is formed, etching is performed to such an extent that the lower copper wiring layer is exposed on the bottom surface of the wiring hole.

  Next, as shown in FIG. 5D, a barrier metal film 3b is formed on the surface including the opening. As the barrier metal film 3b, for example, Ta, TaN, TiN, WCN, Ru, or the like can be used. Thereafter, Cu 4b is formed using, for example, a plating method so as to be embedded in the wiring groove and the wiring hole. Next, as shown in FIG. 5E, a heat treatment is performed for growing embedded Cu crystal grains. This heat treatment is performed at a low temperature of 300 ° C. or lower. Preferably it is 150 degrees C or less. This heat treatment for Cu grain growth can be omitted.

  Thereafter, as shown in FIG. 6A, excess Cu other than the wiring trench and the wiring hole is removed by CMP. Thereby, polycrystalline Cu 5a is embedded in the wiring groove and the wiring hole. At this time, a recess is formed in the wiring groove by setting a CMP processing time longer than usual to partially remove Cu inside the wiring groove. At this time, the barrier metal film 3b on the insulating film is left without being removed.

  Next, as shown in FIG. 6B, an element layer 6b to be added to Cu is formed on the Cu surface. Thereafter, as shown in FIG. 6C, heat treatment for diffusing the additive element in Cu is performed. As this heat treatment, for example, the treatment is performed at a temperature of 200 ° C. to 400 ° C. for 30 seconds to 1 hour in an inert gas or reducing gas atmosphere.

   By this heat treatment, an additive element is added to Cu. The additive element layer 6b is a layer containing at least one element selected from the group consisting of Ti, Zr, Hf, and Al. These additive elements are elements having a solid solubility limit in the Cu film of 1 atomic% or less and a large diffusion coefficient at the Cu crystal grain boundary. By adding this additive element to the Cu film, The additive element can be introduced at a high concentration into the crystal grain boundary and the vicinity of the crystal grain boundary, or the Cu crystal grain / barrier metal interface and the interface vicinity 8b. Specifically, the concentration of the additive element inside the Cu crystal grains (for example, the center) is 0.1 atomic% or less. The concentration of the additive element in the grain boundary of the Cu crystal grains and in the vicinity of the grain boundary is 2 to 1000 times, more specifically 10 to 100 times the concentration of the additive element in the crystal grains. Further, since the additive element diffuses from the Cu surface, a layer 7b of a high concentration additive element is also formed on the Cu surface. In addition, the heat treatment simultaneously cleanses the Cu surface and the Cu interior by gettering the Cu surface and oxygen inside the Cu to the layer of the additive element.

  Next, as shown in FIG. 6D, the excessive additive element layer 6b and the barrier metal film 3b are removed by CMP. At this time, the CMP polishing amount is controlled so that the additive element layer 6b remains on the wiring surface. The removal of the excess additive element layer 6b and the removal of the barrier metal film 3b are performed in the same process, whereby the manufacturing process can be simplified.

  By repeating the steps shown in FIG. 5B to FIG. 6D, an upper wiring layer can be further laminated. In this embodiment, the dual damascene method for forming the wiring groove and the wiring hole at the same time has been described. However, only the wiring groove or the single damascene method for forming only the wiring hole is used for forming the wiring recess. The same applies. The additive element layer 6b may be a layer containing at least one element selected from the group consisting of Cr, Co, Ru, Sn, Ni, Mg, Mn, and W.

  7A to 7I, FIGS. 8A to 8F, and FIGS. 9A to 9D are modified examples of the method of manufacturing the semiconductor device according to the first embodiment of the present invention. It is sectional drawing which shows these process order. In this modification, after the first wiring layer is formed by the single damascene method, a connection hole for the second wiring layer and the first wiring layer is formed on the upper portion by the dual damascene method. This will be described in detail below.

First, as shown in FIG. 7A, an insulating film 21, an inter-wiring insulating film 22, and a hard mask (SiO ₂ film) 23 are sequentially formed. Here, first, a SiO ₂ film 21 having a thickness of, for example, 300 nm is formed on a silicon substrate (not shown). Next, a porous SiOCH film 22 having a thickness of, for example, 80 nm and a relative dielectric constant of, for example, 2.55 is formed by plasma CVD as an inter-wiring insulating film in the first wiring layer. Subsequently, as a hard mask for covering the surface of the porous low dielectric constant film, an SiO ₂ film 23 having a thickness of, for example, 80 nm is similarly laminated by the plasma CVD method.

  Next, as shown in FIG. 7B, a wiring trench is formed in the above-described laminated insulating film by lithography and dry etching. Thereafter, as shown in FIG. 7C, a barrier metal film 24 in which a TaN film and a Ta film are laminated in this order on the entire surface of the substrate by an ionization sputtering method, and a Cu thin film having a thickness of, for example, 40 nm are used as a seed film. Then, Cu 25 is embedded by electrolytic plating using this Cu film as an electrode.

Next, as shown in FIG. 7D, for Cu grain growth, heat treatment is performed at 150 ° C. for 30 minutes in a nitrogen (N ₂ ) atmosphere, for example. Thereby, Cu25 changes to polycrystalline Cu26 with large crystal grains. Thereafter, as shown in FIG. 7E, excess Cu is removed by CMP.

  Next, as shown in FIG. 7F, a 20 nm-thickness Ti film (additive element layer) 27 is formed on the entire surface by sputtering.

  Subsequently, as shown in FIG. 7G, heat treatment is performed at 350 ° C. for 30 minutes in a nitrogen atmosphere to diffuse Ti into the Cu from the Cu surface. Here, since Ti diffuses through the Cu crystal grain boundary and hardly diffuses in the bulk, the layer 28 near the Cu surface and the Cu crystal grain boundary near 29 contain a large amount of Ti. A structure in which Ti is hardly mixed is formed.

Next, as shown in FIG. 7H, the excessive Ti film (added element layer) 27 and the barrier metal film 24 in which the TaN film and the Ta film are laminated in this order are simultaneously removed by CMP. Further, the hard mask (SiO ₂ film) 23 is removed, and the surface of the porous SiOCH film 22 is exposed. At this time, the layer 28 to which Ti is added at a high concentration remains in the vicinity of the Cu surface.

Next, as shown in FIG. 7I, a SiCN film 30 having a thickness of, for example, 30 nm is formed as a barrier insulating film by a plasma CVD method. Next, as a wiring interlayer insulating film in the via and the second wiring layer, a porous SiOCH film 31 having a relative dielectric constant of, for example, 2.55 is formed by plasma CVD with a thickness of, for example, 200 nm. On top of this, a SiO ₂ film 32 having a thickness of, for example, 80 nm is formed by a CVD method as a hard mask.

Next, as shown in FIG. 8A, a part of the SiO ₂ film 32 and the porous SiOCH film 31 are sequentially removed by lithography and anisotropic dry etching using the SiCN film 30 as an etching stopper. A main portion of the via hole between the first and second wiring layers is formed.

Subsequently, as shown in FIG. 8B, a part of the SiO ₂ film 32 and the porous SiOCH film 31 are removed by lithography and anisotropic etching. Thereby, the main part of the wiring groove of the second wiring layer is formed, and at the same time, the SiCN film 30 at the bottom of the via hole is removed to expose the upper connection surface of the first wiring layer. At this time, the organic stripping solution is used to remove etching residues in the via holes and trenches, and remove CuO and Cu ₂ O from the surface of the wiring layer exposed at the via bottom.

  Next, as shown in FIG. 8C, a TaN film and a Ta film are formed by ionized sputtering so as to cover the inner surface of the wiring groove of the second wiring layer and the via hole between the first and second wiring layers. A barrier metal film 33 and a Cu thin film having a thickness of, for example, 40 nm are formed in this order. Thereafter, Cu 34 is embedded by electrolytic plating using this as a seed electrode. This procedure is the same as the formation of the first wiring layer shown in FIG.

Next, as shown in FIG. 8D, for the grain growth of Cu 34, for example, heat treatment is performed at 150 ° C. for 30 minutes in a nitrogen (N ₂ ) atmosphere. Thereafter, as shown in FIG. 8E, excess Cu is removed by CMP. Thereby, Cu35 with large crystal grains is formed.

  Next, as shown in FIG. 8F, a 20 nm-thickness Ti film (additive element layer) 36 is formed on the entire surface by sputtering.

  Subsequently, as shown in FIG. 9A, heat treatment is performed at 350 ° C. for 30 minutes in a nitrogen atmosphere to diffuse Ti into the Cu from the Cu surface. Here, since Ti diffuses through the Cu crystal grain boundary and hardly diffuses in the bulk, a large amount of Ti is contained in the layer 37 near the Cu surface and in the vicinity of the Cu crystal grain boundary 38. A structure in which Ti is hardly mixed is formed.

Next, as shown in FIG. 9B, the excess Ti film (added element layer) 36 and the barrier metal film 33 of the TaN film and the Ta film are simultaneously removed by CMP, and further a hard mask (SiO ₂ The film) 32 is removed, and the surface of the porous SiOCH film 31 is exposed. At this time, a layer 37 to which Ti is added at a high concentration remains in the vicinity of the Cu surface.

Next, as shown in FIG. 9C, a SiCN film 39 having a thickness of, for example, 30 nm is formed as a barrier insulating film by plasma CVD. Next, as shown in FIG. 9D, a SiO ₂ film is formed as the cover film 40. Although not shown, Ti, TiN, and Al are sequentially formed by sputtering after opening a joint portion with the second wiring layer by lithography and etching in the cover film 40. Next, the Al / TiN / Ti laminated film is processed into an electric measurement pad pattern by lithography and etching. As described above, a two-layer wiring can be formed.

  As mentioned above, although embodiment of this invention was described with reference to drawings, these are the illustrations of this invention, Various structures other than the above are also employable.

1a Insulating film 1b Insulating film 3a Barrier metal 3b Barrier metal film 4a Barrier metal film 4b Cu
5a Polycrystalline Cu
5b Polycrystalline Cu
6a Additive element layer 6b Additive element layer 9a Barrier insulating film 9b Barrier insulating film 21 SiO ₂ film 22 Porous SiOCH film 23 SiO2 film 24 Barrier metal film 25 Cu
26 Cu
27 Ti film 28 Layer 29 Cu grain boundary vicinity 30 SiCN film 31 Porous SiOCH film 32 SiO2 film 33 Barrier metal film 34 Cu
35 Cu
46 Ti film 37 Layer 38 Cu grain boundary vicinity 39 SiCN film 40 Cover film

Claims (15)

Forming an insulating film on the substrate on which the semiconductor element is formed;
Forming a recess for wiring comprising at least one of a groove and a hole in the insulating film;
Forming a barrier metal film for preventing Cu diffusion on the insulating film including the inner surface of the recess;
Forming a Cu film on the barrier metal film so as to be embedded in the recess;
Removing the Cu film on the barrier metal other than the portion embedded in the recess by chemical mechanical polishing;
Forming a layer of an additive element on the Cu film in the recess;
The additive element is diffused from the layer of the additive element into the Cu film, and the concentration of the additive element is higher than the inside of the Cu crystal grain at the Cu surface, the grain boundary of the Cu crystal grain, and the position near the grain boundary. Forming a high interface and its vicinity, and gettering oxygen in the Cu film to the layer of the additive element;
Removing a layer of excess additive elements;
Removing the barrier metal film on the insulating film;
A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 1,
No heat treatment at a temperature higher than 150 ° C. is applied between the step of forming a Cu film on the barrier metal and the step of forming a layer made of an additive element on the Cu film in the recess. A method for manufacturing a semiconductor device. In the manufacturing method of the semiconductor device according to claim 1 or 2,
A method of manufacturing a semiconductor device, wherein the step of removing the excess additive element layer and the step of removing the barrier metal film on the insulating film are performed in the same step by chemical mechanical polishing. In the manufacturing method of the semiconductor device according to claim 1,
A method of manufacturing a semiconductor device, wherein the step of forming a layer made of an additive element on the Cu film in the recess is formed by a sputtering method. In the manufacturing method of the semiconductor device according to claim 1,
A method of manufacturing a semiconductor device, wherein the step of forming a layer made of an additive element on the Cu film in the recess uses a water-soluble metal. In the manufacturing method of the semiconductor device according to any one of claims 1 to 5,
The method for manufacturing a semiconductor device, wherein the additive element is at least one element selected from the group consisting of Ti (titanium), Zr (zirconium), Hf (hafnium), and Al (aluminum). In the manufacturing method of the semiconductor device according to any one of claims 1 to 5,
The additive element is selected from the group consisting of Cr (chromium), Co (cobalt), Ru (ruthenium), Sn (tin), Ni (nickel), Mg (magnesium), Mn (manganese), and W (tungsten). A method for manufacturing a semiconductor device, wherein the semiconductor device is at least one element selected from the above. It consists of a polycrystalline copper alloy containing Cu (copper) as a main component and containing an additive element,
The concentration of the additive element is higher in the surface of the polycrystalline copper alloy and in the vicinity of the surface, and in the crystal grain boundary of the crystal grains constituting the polycrystalline copper alloy and in the vicinity of the grain boundary than in the crystal grains,
Furthermore, a barrier metal is formed in the periphery, and the concentration of the additive element is higher than the inside of the crystal grain at the interface with the barrier metal and in the vicinity of the interface,
The thickness of the surface layer having a high concentration of the additive element is less than 30 nm,
A copper alloy for wiring, wherein the barrier metal at the interface of the polycrystalline copper alloy is not oxidized. In the copper alloy for wiring according to claim 8,
The copper alloy for wiring, wherein the additive element is at least one element selected from the group consisting of Ti, Zr, Hf, and Al. In the copper alloy for wiring according to claim 8 or claim 9,
A copper alloy for wiring, wherein an oxide of at least one element selected from the group consisting of Ti, Zr, Hf, and Al is formed on and near the surface of the polycrystalline copper alloy . In the copper alloy for wiring according to claim 8,
A copper alloy for wiring, wherein the additive element is at least one element selected from the group consisting of Cr, Co, Ru, Sn, Ni, Mg, Mn, and W. In the copper alloy for wiring according to claim 8 or claim 11,
An oxide of at least one element selected from the group consisting of Cr, Co, Ru, Sn, Ni, Mg, Mn, and W is formed on and near the surface of the polycrystalline copper alloy. A copper alloy for wiring. In the copper alloy for wiring according to any one of claims 8 to 12,
The concentration of the additive element in the crystal grains is 0.1 atomic% or less, and
The copper alloy for wiring, wherein the concentration of the additive element in the grain boundary of the crystal grain and in the vicinity of the grain boundary is 2 to 1000 times the concentration of the additive element in the crystal grain. In the copper alloy for wiring according to claim 13,
A copper alloy for wiring, wherein the concentration of the additive element in the grain boundary of the crystal grain and in the vicinity of the grain boundary is 10 to 100 times the concentration of the additive element in the crystal grain. 15. A semiconductor device, wherein a metal wiring made of a copper alloy for wiring according to claim 8 is formed on a substrate on which a semiconductor element is formed.

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