JP2012063790A - Display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display device capable of responding to two kinds of display modes including an analog display (moving image display) and a digital display (still image display) with a single display device, and that achieves remarkably low power consumption in a display system.SOLUTION: A display device comprises a first display circuit for performing an analog display, and a second display circuit for performing a digital display, in which, when switching to stop the analog display, a drain signal line 61 and the first display circuit are disconnected based on a mode setting signal DH inputted from the outside, and the power supply to unnecessary circuits (a DA converter 310, an operational amplifier 311 and a timing controller 305) is stopped in response to a stop control signal LA generated by delaying a mode setting signal DH.

Description

  The present invention relates to a display device, and more particularly to a display device suitable for use in a portable display device.

  In recent years, portable display devices such as mobile TVs and mobile phones have been required as market needs. In response to such demands, research and development has been actively conducted to cope with the reduction in size, weight, and power consumption of display devices.

  FIG. 6 shows a circuit configuration diagram of one display pixel of a liquid crystal display device according to a conventional example. A gate signal line 51 and a drain signal line 61 intersect with each other on an insulating substrate (not shown), and a TFT 65 connected to both signal lines 51 and 61 is provided in the vicinity of the intersection. . The source 11 s of the TFT 65 is connected to the display electrode 80 of the liquid crystal 21.

  Further, an auxiliary capacitor 85 for holding the voltage of the display electrode 80 for one field period is provided. One terminal 86 of the auxiliary capacitor 85 is connected to the source 11 s of the TFT 65, and the other electrode 87 is connected to each electrode 87. A common potential is applied to the display pixels. Here, when a scanning signal is applied to the gate signal line 51, the TFT 65 is turned on, and an analog video signal is transmitted from the drain signal line 61 to the display electrode 80 and held in the auxiliary capacitor 85. A video signal voltage applied to the display electrode 80 is applied to the liquid crystal 21, and the liquid crystal 21 is aligned according to the voltage, whereby a liquid crystal display can be obtained. Therefore, a display can be obtained regardless of a moving image or a still image. When a still image is displayed on such a liquid crystal display device, for example, an image of a dry cell is displayed as a battery remaining amount display for driving the mobile phone on a part of the liquid crystal display unit of the mobile phone.

  However, in the liquid crystal display device having the above-described configuration, even when a still image is displayed, the TFT 65 is turned on by a scanning signal and a video signal is sent to each display pixel as in the case of displaying a moving image. There was a need to rewrite. For this reason, driver circuits for generating drive signals such as scanning signals and video signals, and external LSIs for generating various signals for controlling the operation timing of the driver circuits always operate, and thus always consume large power. It was. For this reason, a mobile phone or the like having only a limited power source has a drawback that the usable time is shortened.

  On the other hand, Patent Document 1 discloses a liquid crystal display device including a static memory in each display pixel. Describing a part of the publication, this liquid crystal display device, as shown in FIG. 7, retains a digital video signal in a memory in which two-stage inverters INV1 and INV2 are positively fed back, that is, a static memory. By using it as a circuit, power consumption is reduced. Here, according to the binary digital video signal held in the static memory, the switch element 24 controls the resistance value between the reference line Vref and the display electrode 80 and adjusts the bias state of the liquid crystal 21. . On the other hand, an AC signal Vcom is input to the common electrode. Ideally, this apparatus does not require a refresh to the memory if there is no change in the display image as in a still image.

JP-A-8-194205

  As described above, the conventional liquid crystal display device is suitable for displaying a full-color moving image corresponding to an analog video signal. On the other hand, a liquid crystal display device having a static memory for holding a digital video signal is suitable for displaying a still image with a low gradation and reducing power consumption.

  However, since both liquid crystal display devices have different video signal sources, full color moving image display and still image display cannot be realized simultaneously in one display device. In addition, when a still image is displayed on a liquid crystal display device having a static memory, no attempt has been made to reduce the power consumption of an external LSI that outputs various control signals to the liquid crystal display device.

  Therefore, an object of the present invention is to support two types of display, full color moving image display and low power consumption still image display, with one display device (for example, one liquid crystal display panel). It is possible.

  Another object of the present invention is to significantly reduce power consumption of the entire display system including an external LSI externally attached to the display device.

The display device according to the present invention includes a plurality of gate signal lines arranged in one direction on a substrate, a gate driver that sequentially supplies a scanning signal to the gate signal lines, and a plurality arranged in a direction intersecting the gate lines. A drain signal line, a drain driver that sequentially selects the drain signal line, supplies a video signal to the drain signal line, a timing control circuit that supplies a timing control signal to the gate driver or / and the drain driver, and a matrix And a display electrode that is selected by a scanning signal from the gate signal line and is supplied with a video signal from the drain signal line,
A DA conversion circuit for converting an input digital video signal into an analog video signal, and the analog video signal converted by the DA conversion circuit are sequentially supplied to the display electrodes via the drain signal line to perform analog display. And a second display circuit that performs digital display by supplying a voltage corresponding to the input digital video signal held by the holding circuit to the display electrode. And comprising
When switching to stop the analog display, the analog display is generated by disconnecting the drain signal line from the first display circuit and delaying the mode setting signal based on a mode setting signal input from the outside. The supply of power supply voltage to the DA converter circuit is stopped in response to a stop control signal.

  According to the display device of the present invention, one display panel selects two types of display: full-color moving image display in the analog display mode and still image display with a low number of gradations corresponding to low power consumption in the digital display mode. It becomes possible to do.

  In particular, when the digital display mode is selected, not only the operation to unnecessary circuits is stopped, but also the power supply is stopped, so that the power consumption of the entire display device can be greatly reduced. .

  Accordingly, even when the display device of the present invention is used for a portable television or a mobile phone using a limited power source such as a battery, the display can be performed for a long time because of low power consumption.

It is a circuit block diagram of the liquid crystal display device which concerns on embodiment of this invention. It is a circuit block diagram of the switching circuit of the video signal which concerns on embodiment of this invention. It is another circuit block diagram of the liquid crystal display device which concerns on embodiment of this invention. FIG. 4 is a timing chart of the liquid crystal display device according to the embodiment of the present invention. It is sectional drawing of a reflection type liquid crystal display device. It is a circuit block diagram of the liquid crystal display device which concerns on a prior art example. It is another circuit block diagram of the liquid crystal display device which concerns on a prior art example.

Next, a display device according to an embodiment of the present invention will be described. FIG. 1 shows a circuit configuration diagram when the display device of the present invention is applied to a liquid crystal display device.

  A DFF 301 includes flip-flops 302 and 303. When the digital display mode switching signal DH input to the first stage flip-flop 302 becomes “H (high)”, the flip-flop 302 sends the mode switching signal MD in synchronization with the vertical period end signal Vend from the timing controller 305. Output.

  Further, the flip-flop 303 outputs a stop control signal LA in synchronization with the next vertical period end signal Vend. The mode switching signal MD and stop control signal LA control the operation of each circuit described later.

  The timing controller 305 is based on the system clock CLK, the horizontal synchronization signal Hsync, and the vertical synchronization signal Vsync, and controls the panel control signal PC, the vertical period end signal Vend, and the alternating current for driving the counter electrode of the liquid crystal stored in the display panel 100 to be inverted. The drive signal FRP and the operation clock DACCLK of the DA converter 310 are output. Here, the panel control signal PC includes a horizontal start pulse STH and a vertical start pulse STV which are trigger signals for the panel scanning signal.

  The AND gate 306 outputs a signal for stopping the operation of the timing controller 305. The stop control signal LA and the digital display mode switching signal DH are input to the AND gate. Therefore, the timing controller 305 stops operating when both signals are “H” (in the digital display mode). Further, when the digital display mode switching signal DH becomes “L”, the stop state is canceled and the analog display mode can be returned.

  In addition, an oscillator 307 is provided independently of the timing controller 305. The oscillator 307 serves as a signal source of the AC drive signal in the digital display mode, and has an AC drive signal having a longer period than the signal period (usually one horizontal period) of the AC drive signal FRP output from the timing controller 305. Is generated.

  Here, in the digital display mode, as will be described later, the digital video signal is held by a static holding circuit, and a configuration is adopted in which a signal applied to the display electrode is selected according to the holding signal. Since there is no risk of attenuation of the video signal due to leakage of the auxiliary capacitor as in the analog display mode, a relatively low frequency AC drive signal is sufficient. The signal period is preferably one vertical period (corresponding to 60 Hz) or more in order to reduce power consumption.

The output of the oscillator 307 and the AC drive signal FRP output from the timing controller 305 are switched by the switching circuit SW3 according to the mode switching signal MD, amplified by the operational amplifier 308, and then input to the counter electrode terminal COM.
The output signal of the oscillator 307 is inverted in phase by the inverter circuit 309 and further amplified by the operational amplifier 315 and then input to the signal terminal LSIG. These two opposite-phase signal pairs are used to display “white” or “black” in the digital display mode as described later.

  The DA converter 310 converts R, G, B digital video signal data input from the outside into an analog video signal. Here, each of the R, G, B digital video signal data usually has an 8-bit configuration. The analog video signal DA-converted from the most significant bit and further amplified by the operational amplifier 311 is input to the switching circuit SW1. Both signals are switched by the switching circuit SW1 in accordance with the mode switching signal MD and output to the R, G, B terminals of the display panel 100.

  In this embodiment, since a holding circuit for holding digital video signal data in the display panel 100 described later has a 1-bit configuration, only the most significant bit is output. If the circuit has a multi-bit configuration, it can be changed to a configuration that outputs a multi-bit digital video signal corresponding to the multi-bit configuration.

  Further, the switching circuit SW2 outputs “H” or “L” to the terminal LVDD of the display panel 100 according to the mode switching signal MD. In response to this, the display panel 100 is switched to an analog display mode (LVDD = “L”) and a digital display mode (LVDD = [H]) as described later.

  The power supply circuit 320 generates power supply voltages VDD1, VDD2 (for example, 5V), VCC1, VCC2 (for example, 8 to 10V), VEE1, VEE2 (for example, −4 to −5V) based on the power input. The power output lines 321, 322, and 323 of the power supply circuit 320 are provided with switching circuits SW 4, SW 5, and SW 6, which open and close according to the output of the AND gate 306 and supply VDD 1, VCC 1, and VEE 1 to a predetermined circuit. It is configured to be controllable.

  Here, when the output of the AND gate 306 becomes “H”, the switching circuits SW4, SW5, and SW6 are opened, and the circuits to which the power supply voltages VDD1, VCC1, and VEE1 are supplied, that is, the DA converter 310, the operational amplifier 311 and the timing controller 305. The power supply to the internal driver of the display panel 100 is stopped.

  Next, the operation of the display device having the above-described configuration will be described with reference to the timing chart of FIG. When the digital display mode switching signal DH is switched to “H”, the mode switching signal MD rises to “H” in synchronization with the rising of the vertical period signal Vend generated at the timing when the vertical period ends.

  Then, the terminal LVDD rises to “H” by the switching circuit SW3, and the display panel 100 is switched to the digital display mode. At the same time, the switching circuit SW1 is switched to output the most significant bit digital video signal data to the R, G, B terminals. Further, the AC drive signal (signal input to the counter electrode terminal COM) is switched to a low frequency by the switching circuit SW2. Thus, digital video signal data is written in one field of the display panel 100 over one vertical period (a period until the next Vend rises).

  When one vertical period for writing ends and the next signal Vend arrives, the stop control signal LA rises in synchronization therewith. Then, the output of the AND gate 306 rises to “H”, and based on this, the operation of the timing controller 305 is stopped. In other words, various panel control signals PC and output signals such as the operation clock DACCLK to the DA converter 310 are fixed. Thereby, the operation of the DA converter 310 is also stopped.

  Further, when the output of the AND gate 306 rises to “H”, the switching circuits SW4, SW5, SW6 are opened, and the power supply to the DA converter 310, the operational amplifier 311, the timing controller 305, and the internal driver of the display panel 100 is stopped. The

  As described above, according to the present invention, not only the operation of unnecessary circuits in the digital display mode is stopped, but also the supply of the power supply voltage is stopped. Electric power can be reduced. The effect is about 1/5 of the case where the operation is merely stopped.

  Next, when returning to the analog display mode, the digital display mode switching signal DH is switched to “L”. Then, since the output of the AND gate 306 becomes “L”, the timing controller 305 starts the operation again. When the mode switching signal MD falls to “L”, the switching circuit SW1 switches to output an analog video signal. At the same time, the switching circuit SW2 is switched to output the AC drive signal FRP from the timing controller 305 to the terminal COM. Further, the switching circuit SW3 is switched to the VEE side, and the display panel 100 is set to the normal analog display mode.

  Further, when the output of the AND gate 306 becomes “L”, the switching circuits SW4, SW5, SW6 are closed, and the power supply to the DA converter 310, the operational amplifier 311, the timing controller 305, and the internal drivers of the display panel 100 is resumed. . Thus, the display panel 100 returns to the normal analog display mode.

  Next, the circuit configuration of the display panel 100 will be described in detail with reference to FIG. On the insulating substrate 10, a plurality of gate signal lines 51 connected to a gate driver 50 for supplying a scanning signal are arranged in one direction, and a plurality of drain signal lines 61 are arranged in a direction intersecting with the gate signal lines 51. Is arranged.

  Sampling transistors SP1, SP2,..., SPn are turned on according to the timing of the sampling pulse output from the drain driver 60, and the data signal of the data signal line 62 is supplied to the drain signal line 61. Here, the data signal of the data signal line 62 is a digital video signal or an analog video signal supplied in accordance with the switching of the switching circuit SW1 outside the display panel 100 described above (FIG. 1).

  The liquid crystal display panel 100 is configured by a plurality of display pixels 200 which are selected by a scanning signal from the gate signal line 51 and are supplied with a data signal from the drain signal line 61 arranged in a matrix.

  Hereinafter, a detailed configuration of the display pixel 200 will be described. In the vicinity of the intersection of the gate signal line 51 and the drain signal line 61, a circuit selection circuit 40 including a P-channel TFT 41 and an N-channel type 42 is provided. Both drains of the TFTs 41 and 42 are connected to the drain signal line 61, and both gates thereof are connected to the selection signal line 88. One of the TFTs 41 and 42 is turned on in response to a selection signal from the selection signal line 88. Further, as will be described later, a circuit selection circuit 43 is provided in a pair with the circuit selection circuit 40. Here, the selection signal line 88 is a signal line wired from the terminal LVDD of the display panel 100.

  The circuit selection circuits 40 and 43 can select and switch between an analog video signal display (corresponding to a full-color moving image) and a digital video display (low power consumption, corresponding to a still image), which will be described later. In addition, a pixel selection circuit 70 including an N-channel TFT 71 and an N-channel TFT 72 is disposed adjacent to the circuit selection circuit 40. The TFTs 71 and 72 are connected in series with the TFTs 41 and 42 of the circuit selection circuit 40, respectively, and a gate signal line 51 is connected to both gates thereof. The TFTs 71 and 72 are configured such that both are turned on simultaneously in accordance with the scanning signal from the gate signal line 51.

  In addition, an auxiliary capacitor 85 for holding an analog video signal is provided. One electrode 86 of the auxiliary capacitor 85 is connected to the source 71 s of the TFT 71. The other electrode 87 is connected to a common auxiliary capacitance line 88 and supplied with a bias voltage VSC. When the gate of each TFT of the circuit selection circuit 70 is opened and an analog video signal is applied to the liquid crystal 21, the signal must be held for one field period. However, with only the liquid crystal 21, the voltage of the signal gradually increases with time. It will decline. If it does so, it will appear as display unevenness and a good display cannot be obtained. Therefore, an auxiliary capacitor 85 is provided to hold the voltage for one field period.

  A P-channel TFT 44 of the circuit selection circuit 43 is provided between the auxiliary capacitor 85 and the liquid crystal 21, and is configured to be turned on / off simultaneously with the TFT 41 of the circuit selection circuit 43.

  A holding circuit 110 and a signal selection circuit 120 are provided between the TFT 72 of the pixel selection circuit 70 and the display electrode 80 of the liquid crystal 21. The holding circuit 110 includes two inverter circuits that are positively fed back, and constitutes a static memory that holds a digital binary value.

  The signal selection circuit 120 is a circuit that selects a signal in accordance with a signal from the holding circuit 110, and includes two N-channel TFTs 121 and 122. Since complementary output signals from the holding circuit 110 are applied to the gates of the TFTs 121 and 122, the TFTs 121 and 122 are turned on and off in a complementary manner.

  Here, when the TFT 122 is turned on, the AC drive signal (signal B) is selected, and when the TFT 121 is turned on, the counter electrode signal VCOM (signal A) is selected, and a voltage is applied to the liquid crystal 21 via the TFT 45 of the circuit selection circuit 43. It is supplied to the display electrode 80 to be applied. Here, the counter electrode signal VCOM (signal A) corresponds to the signal from the oscillator 307 described above, and the signal B corresponds to a signal obtained by inverting the output of the oscillator 307 described above.

  To summarize the above-described configuration, a circuit (first display device) including a TFT 71 as a pixel selection element and an auxiliary capacitor 85 for holding an analog video signal, a TFT 72 as a pixel selection element, and a binary digital video signal. A holding circuit 110 for holding and a circuit (second display device) including the signal selection circuit 12 are provided in one display pixel 200, and circuit selection circuits 40 and 43 for selecting these two circuits are provided. Is provided.

  Next, peripheral circuits of the liquid crystal panel 200 will be described. A panel driving LSI 91 is provided on an external circuit board 90 which is a separate substrate from the insulating substrate 10 of the liquid crystal panel 200. A vertical start signal STV is input to the gate driver 50 from the panel driving LSI 91 of the external circuit board 90, and a horizontal start signal STH is input to the drain driver 60. A video signal is input to the data line 62. Here, the panel driving LSI 91 corresponds to the timing controller 305 described above.

Next, a method for driving the display panel having the above-described configuration will be described with reference to FIGS. FIG. 4 is a timing chart when the liquid crystal display device is selected in the digital display mode.
(1) In the case of the analog display mode When the analog display mode is selected according to the mode switching signal MD (“L”), the switching circuit SW1 sets the state in which the analog video signal is output to the data signal line 62. At the same time, the potential of the circuit selection signal line 88 becomes “L”, and the TFTs 41 and 44 of the circuit selection circuits 40 and 43 are turned on.

  Further, the sampling transistor SP is turned on according to the sampling signal based on the horizontal start signal STH, and the analog video signal of the data signal line 62 is supplied to the drain signal line 61.

  A scanning signal is supplied to the gate signal line 51 based on the vertical start signal STV. When the TFT 71 is turned on according to the scanning signal, the analog video signal Sig is transmitted from the drain signal line 61 to the display electrode 80 and held in the auxiliary capacitor 85. A video signal voltage applied to the display electrode 80 is applied to the liquid crystal 21, and the liquid crystal 21 is aligned according to the voltage, whereby a liquid crystal display can be obtained.

In this analog display mode, the video signal voltage is sequentially input, which is suitable for displaying a full-color moving image. However, the LSI 91 and the drivers 50 and 60 of the external circuit board 90 are constantly consuming power to drive them.
(2) Digital display mode When the digital display mode is selected according to the mode signal switching signal MD (“H”), the digital video signal is set to be output to the data signal line 62 and the circuit is selected. The potential of the signal line 88 becomes “H”, and the holding circuit 110 becomes operable. Further, the TFTs 41 and 44 of the circuit selection circuits 40 and 43 are turned off, and the TFTs 42 and 45 are turned on.

  Further, start signals STV and STH are input to the gate driver 50 and the drain driver 60 from the panel driving LSI 91 (timing controller 305) of the external circuit board 90. In response to this, sampling signals are sequentially generated, and the sampling transistors SP1, SP2,..., SPn are sequentially turned on in accordance with the respective sampling signals to sample the digital video signal Sig and supply it to each drain signal line 61.

  Here, the first row, that is, the gate signal line 51 to which the scanning signal G1 is applied will be described. First, the TFTs of the display pixels P11, P12,... P1n connected to the gate signal line 51 by the scanning signal G1 are turned on for one horizontal scanning period.

  When attention is paid to the display pixel P11 in the first row and first column, the digital video signal S11 sampled by the sampling signal SP1 is inputted to the drain signal line 61. When the TFT 72 is turned on by the scanning signal G 1, the drain signal D 1 is input to the holding circuit 110.

  The signal held by the holding circuit 110 is input to the signal selection circuit 120, the signal selection circuit 120 selects the signal A or the signal B, the selected signal is applied to the display electrode 80, and the voltage Is applied to the liquid crystal 21.

  By scanning from the gate signal line 51 to the gate signal line 51 in the last row in this way, scanning for one screen (one field period), that is, writing of a digital signal by all dot scanning is completed, and writing to the holding circuit 110 is completed. One screen corresponding to the digital video signal is displayed.

  Here, when one screen is displayed, as described above, based on the stop control signal LA, to unnecessary circuits such as the gate driver 50, the drain driver 60, the external panel driving LSI 91 (timing controller 305), and the like. The voltage supply is stopped and their driving is stopped.

  The holding circuit 110 is always driven by supplying the voltages VDD and VSS, and the low-frequency AC drive signal VCOM (for example, 60 Hz) is applied to the counter electrode 32 of the liquid crystal 21, and the signals A and B are supplied to the selection circuit 120. Supply. That is, when the liquid crystal display panel 100 is normally white (NW), the same AC drive signal VCOM as that of the counter electrode 32 is applied to the signal A and the signal B is applied to the signal B. Is applied with an AC drive signal having a phase opposite to that of the signal A.

  At this time, when “H (high)” is input to the drain signal line 61 as a digital video signal to the holding circuit 110, “L” is input to the first TFT 121 in the signal selection circuit 120. Therefore, the first TFT 121 is turned off, and “H” is input to the other second TFT 122, so that the second TFT 122 is turned on.

  Then, the signal B is selected, and the voltage of the signal B having the opposite phase to the counter electrode 32 is applied to the liquid crystal display electrode 80, and the liquid crystal rises due to the electric field. Therefore, the normally white display panel displays black. Can be observed.

  When “L” is input to the drain signal line 61 as a digital video signal to the holding circuit 110, “H” is input to the first TFT 121 in the signal selection circuit 120. Is turned on, and “L” is input to the other second TFT 122, so that the second TFT 122 is turned off. Then, the signal A is selected and the signal A is applied to the liquid crystal. That is, since a signal having the same phase as that of the counter electrode 32 is applied, an electric field is not generated and the liquid crystal does not stand up. Therefore, the display can be observed as a white display on a normally white display panel.

  In this digital display mode, it can be displayed as a still image by writing and holding one screen, and driving of each driver 50, 60 and LSI 91 and power supply are stopped, so power consumption is greatly reduced. can do.

  The display device of the present invention is preferably applied to a reflective liquid crystal display device among liquid crystal display devices. The device structure of this reflective liquid crystal display device will be described with reference to FIG.

  As shown in FIG. 5, on one insulating substrate 10, a gate insulating film 12 is formed on a semiconductor layer 11 made of polycrystalline silicon and formed into an island, and above the semiconductor layer 11, the gate insulating film 12 is formed. A gate electrode 13 is formed thereon.

  A source 11 s and a drain 11 d are formed in the lower semiconductor layer 11 located on both sides of the gate electrode 13. An interlayer insulating film 14 is deposited on the gate electrode 13 and the gate insulating film 12, and a contact hole 15 is formed at a position corresponding to the drain 11d and a position corresponding to the source 11s. The drain 11 d is connected to the drain electrode 16, and the source 11 s is connected to the display electrode 19 through a contact hole 18 provided in the planarization insulating film 17 provided on the interlayer insulating film 14.

  Each display electrode 19 formed on the planarization insulating film 17 is made of a reflective material such as aluminum (Al). An alignment film 20 made of polyimide or the like for aligning the liquid crystal 21 is formed on each display electrode 19 and the planarization insulating film 17.

  On the other insulating substrate 30, a color filter 31 exhibiting each color of red (R), green (G), and blue (B), a counter electrode 32 made of a transparent conductive film such as ITO (Indium Tin Oxide), And the alignment film 33 which orientates the liquid crystal 21 is formed in order. When color display is not used, the color filter 31 is not necessary.

  The periphery of the pair of insulating substrates 10 and 30 thus formed is adhered with an adhesive sealing material, and the liquid crystal 21 is filled in the gap formed thereby, thereby completing the reflective liquid crystal display device.

  As indicated by the dotted arrows in the figure, the external light incident from the viewer 1 side enters from the counter electrode substrate 30 in order, is reflected by the display electrode 19, is emitted to the viewer 1 side, and the display is viewed by the viewer 1. Can be observed.

  Thus, the reflective liquid crystal display device is a method of observing the display by reflecting external light, and unlike the transmissive liquid crystal display device, it is not necessary to use a so-called backlight on the side opposite to the viewer side. Does not require power to turn on its backlight. Therefore, the display device of the present invention is preferably a reflective liquid crystal display device that does not require a backlight and is suitable for low power consumption.

  In the above-described embodiment, the case where the counter electrode voltage and the voltages of the signals A and B are applied during the entire dot scan period of one screen has been described, but the present invention is not limited thereto. It is not necessary to apply these voltages during this period. However, in order to reduce power consumption, it is preferable not to apply.

  In the above-described embodiment, the case where a 1-bit digital data signal is input in the digital display mode has been described. However, the present invention is not limited thereto, and even in the case of a multi-bit digital data signal. It is possible to apply. By doing so, multi-gradation display can be performed. At that time, it is necessary to set the number of holding circuits and signal selection circuits according to the number of input bits.

  In the above-described embodiment, the case where a still image is displayed on a part of a liquid crystal display panel has been described. However, the present application is not limited thereto, and a still image can be displayed on all display pixels. Thus, the present invention has a characteristic effect of the present invention.

  In the above-described embodiment, the case of the reflective liquid crystal display device has been described. However, by disposing a transparent electrode in a region excluding the TFT, the holding circuit, the signal selection circuit, and the signal wiring in one pixel, the transmissive liquid crystal It can also be used for a display device.

301 DFF
305 timing controller 306 AND gate 310 DA converter 320 power supply circuit 10 insulating substrate 13 gate 21 liquid crystal 40 circuit selection circuit 43 circuit selection circuit 50 gate driver 51 gate signal line 60 drain driver 61 drain signal line 70 pixel selection circuit 85 auxiliary capacitor 110 Holding circuit 120 Signal selection circuit

Claims (6)

A plurality of gate signal lines arranged in one direction on the substrate;
A gate driver for sequentially supplying scanning signals to the gate signal lines;
A plurality of drain signal lines arranged in a direction crossing the gate line;
A drain driver that sequentially selects the drain signal line and supplies a video signal to the drain signal line; a timing control circuit that supplies a timing control signal to the gate driver or / and the drain driver;
In a display device having a display electrode arranged in a matrix and selected by a scanning signal from the gate signal line and supplied with a video signal from the drain signal line,
A DA conversion circuit for converting an input digital video signal into an analog video signal;
A first display circuit for performing analog display by sequentially supplying the analog video signal converted by the DA conversion circuit to the display electrode via the drain signal line;
A holding circuit for holding the input digital video signal, and a second display circuit for supplying a voltage corresponding to the input digital video signal held by the holding circuit to the display electrode and performing digital display,
When switching to stop the analog display, the analog display is generated by disconnecting the drain signal line from the first display circuit and delaying the mode setting signal based on a mode setting signal input from the outside. The display device is characterized in that the supply of power supply voltage to the DA converter circuit is stopped in response to a stop control signal.   An amplifier circuit for amplifying the analog video signal; and when switching to stop the analog display, the control circuit stops supplying power supply voltage to the amplifier circuit in response to the stop control signal. The display device according to claim 1.   2. The control circuit according to claim 1, wherein when switching to stop the analog display, the control circuit stops supply of power supply voltage to the gate driver and / or drain driver in accordance with the stop control signal. Display device.   2. The display device according to claim 1, wherein when switching to stop the analog display, the control circuit stops supply of a power supply voltage to the timing control circuit in accordance with the stop control signal. The timing control circuit outputs a first AC drive signal supplied to the counter electrode of the liquid crystal of the display panel, and generates a second AC drive signal having a longer period than the first AC drive signal. An oscillator,
The display device according to claim 1, further comprising: a switching circuit that switches from the first AC drive signal to the second AC drive signal when switching to stop the analog display.    The display device according to claim 4, wherein the period of the second AC drive signal is one vertical period or more.

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