JP2002333864A - Display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display device, in which designing of a drive circuit for low power consumption is made possible, by reducing power consumption in a digital display mode. SOLUTION: In this display device, a counter-electrode amplifier 82 for amplifying an AC drive signal, which is supplied to counter electrodes amplifies an AC drive signal FRP at a first slew rate in an analog display mode and amplifies the AC drive signal FRP at a second slew rate which is lower than the first slew rate in the digital display mode. As a result, power consumption in a digital display mode is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly to a display device suitable for a portable display device.

[0002]

2. Description of the Related Art In recent years, portable display devices such as portable televisions and portable telephones have been demanded as market needs. In response to such demands, research and development have been actively conducted to reduce the size, weight, and power consumption of the display device.

FIG. 8 shows a circuit configuration diagram of one display pixel of a liquid crystal display device according to a conventional example. On an insulating substrate (not shown),
The gate signal line 51 and the drain signal line 61 are formed to intersect with each other, and a pixel selection thin film transistor 72 connected to the signal lines 51 and 61 is provided near the intersection. Hereinafter, the thin film transistor is abbreviated as TFT. The source 11 s of the pixel selection TFT 72 is connected to the display electrode 80 of the liquid crystal 21.
It is connected to the. The counter electrode 32 of the liquid crystal 21 is supplied with a counter electrode voltage VCOM.

An auxiliary capacitor 85 for holding the voltage of the display electrode 80 for one field period is provided.
One terminal 86 of the auxiliary capacitor 85 is connected to the pixel selection TFT 7.
2 is connected to the source 11s, and a common potential is applied to the other electrode 87 to each display pixel.

Here, a scanning signal (H
When the (level) is applied, the pixel selection TFT 72 is turned on, an analog video signal is transmitted from the drain signal line 61 to the display electrode 80, and is held in the auxiliary capacitance 85. A video signal voltage applied to the display electrode 80 is applied to the liquid crystal 21 and the liquid crystal 21 is oriented according to the voltage, whereby a liquid crystal display can be obtained.

Therefore, liquid crystal display can be performed regardless of a moving image and a still image. When a still image is displayed on such a liquid crystal display device, for example, an image of a dry battery is displayed on a part of the liquid crystal display section of the mobile phone as a remaining battery level display for driving the mobile phone.

However, in the liquid crystal display device having the above-described configuration, even when a still image is displayed, the pixel selection TFT is selected by a scanning signal in the same manner as when displaying a moving image.
It has been necessary to turn on 72 and rewrite the video signal to each display pixel.

For this reason, a driver circuit for generating drive signals such as a scanning signal and a video signal and an external LSI for generating various signals for controlling the operation timing of the driver circuit always operate, so that a large amount of power is always consumed. Was. For this reason, a mobile phone or the like having only a limited power supply has a drawback that its usable time is shortened.

On the other hand, a liquid crystal display device having a static memory for each display pixel is disclosed in Japanese Patent Laid-Open No. 8-19420.
No. 5. The liquid crystal display device will be described with reference to a part of the publication. As shown in FIG. 9, a memory in which two-stage inverters INV1 and INV2 are positively fed back is provided.
That is, power consumption is reduced by using a static memory as a digital video signal holding circuit.

Here, the switch element 24 controls a resistance value between the reference line Vref and the display electrode 80 in accordance with the binary digital video signal held in the static memory,
The bias state of the liquid crystal 21 is adjusted. On the other hand, the common electrode voltage VCOM is input to the common electrode. Ideally, the present device does not require refreshing to the memory if there is no change in the displayed image like a still image.

[0011]

As described above, the conventional liquid crystal display device is suitable for displaying a full-color moving image corresponding to an analog video signal. On the other hand, a liquid crystal display device including a static memory for holding a digital video signal is suitable for displaying a still image with a low gradation and reducing power consumption.

However, since the two liquid crystal display devices use different video signal sources, they cannot be realized simultaneously in one display device.

Accordingly, the present applicant has proposed a display device capable of selecting two types of display, an analog display mode (normal display mode) and a digital display (display mode using a static memory). FIG. 10 shows a configuration of a display device studied by the present inventors. The digital video signal that has been subjected to the predetermined signal processing in the signal processing circuit 1 is converted into a DA converter 3,
The signal is input to the liquid crystal display panel 100 through the amplifier 4.
The digital video signal written to the static memory is input to the amplifier 4 without passing through the DA converter 3.
It is input to the liquid crystal display panel 100.

That is, in the analog display mode, the analog video signal is sequentially supplied to the display electrodes, and in the digital display mode, the digital video signal is written in the static memory, and the signal corresponding to the digital video signal held in the static memory. Is supplied to the display electrode.

The counter electrode amplifier 81 amplifies the AC drive signal FRP output from the timing controller 6 and supplies it to the counter electrode of each display pixel in the liquid crystal display panel 100 as the counter electrode voltage VCOM. However, when the same counter amplifier 81 is used in the analog display mode and the digital display mode, there is a problem that the power consumption in the digital display mode is high and the power consumption cannot be reduced.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a display device which can reduce power consumption in a digital display mode and can design a drive circuit with low power consumption.

[0017]

A display device according to the present invention displays a first display circuit for supplying an analog video signal to a display electrode and a signal corresponding to a digital video signal held in a static holding circuit. A second display circuit for supplying the electrode, a circuit selection circuit for selectively selecting the first display circuit and the second display circuit, and a counter electrode provided to face the display electrode with an AC drive signal And a counter electrode amplifier whose amplification capability is variably controlled, wherein the amplification capability of the counter electrode amplifier is reduced when the second display circuit is selected.

In the counter-electrode AC drive system for supplying an AC drive signal to the counter electrode, in the analog display mode using the first display circuit, for example, 1H cycle (one horizontal cycle)
Is supplied to the counter electrode. In the digital display mode using the second display circuit, a digital video signal is held by a static holding circuit, and a signal corresponding to the digital video signal held in the static holding circuit is supplied to a display electrode. Since the configuration is adopted, there is no fear of the video signal being attenuated. Therefore, it is sufficient to apply an AC drive signal having a relatively low frequency, for example, a 1 V cycle (one vertical cycle) to the counter electrode.

This makes it possible to reduce the power consumption of the oscillator that generates the AC drive signal. In the present invention, in addition, in the digital display mode, the amplification capability (slew rate) of the counter electrode amplifier is reduced. As a result, power consumption can be further reduced.

This counter electrode amplifier can be constituted by an amplifier (for example, an operational amplifier) whose slew rate is variably controlled according to a control signal. This is a variable slew rate amplifier in which a control transistor whose ON resistance is variably controlled by a control signal is provided in a current path from a high potential side potential to a low potential side potential of the amplifier. In the digital display mode by the control signal,
It is possible to reduce the slew rate of the counter electrode amplifier and reduce power consumption.

The counter electrode amplifier comprises a first amplifier and a second amplifier having different slew rates, and a first amplifier and a second amplifier.
And the second amplifier may be switched by a switch. In digital display mode,
Switching to an amplifier having a lower slew rate of the counter electrode amplifier makes it possible to reduce power consumption.

[0022]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a circuit configuration of a display device according to the present embodiment.

The signal processing circuit 1 performs various signal processing such as contrast adjustment and brightness adjustment on a digital video signal input from the outside. The digital video signal subjected to the signal processing is converted into an analog video signal by the DA converter 3 and then input to the amplifier 4.

This analog video signal is amplified by an analog amplifier provided in the amplifier 4. On the other hand, in the digital display mode, after the digital video signal is subjected to signal processing by the signal processing circuit 1, the digital video signal is output to the liquid crystal display panel 100 through the level shifter provided in the amplifier 4 without passing through the DA converter 3. You.

Based on the system clock CLK from the oscillator 5, the horizontal synchronizing signal Hsync and the vertical synchronizing signal Vsync, the timing control circuit 6 controls the panel drive signal PC, the signal processing circuit 1, the DA converter 3, and the counter electrode amplifier 82. Outputs control signal.

The counter electrode amplifier 82 is a counter electrode 3 of the liquid crystal 21.
2 is a circuit for amplifying the AC drive signal FRP to be supplied to the power supply 2. The timing control circuit 6 supplies an AC drive signal FRP and a slew rate control signal TRC to the counter electrode amplifier 82. The signal cycle of the AC drive signal FRP is configured to be switchable by the mode switching signal MD so as to be one horizontal period in the analog display mode and one vertical period or more in the digital display mode.

Thus, the power consumption of the signal source in the digital display mode is reduced. Specifically, for example, two oscillators having different oscillation periods are prepared, and these are switched and output according to the mode switching signal MD.

The counter electrode amplifier 82 amplifies the AC drive signal FRP at the first slew rate in the analog display mode in accordance with the slew rate control signal TRC as described later.
In the digital display mode, the AC drive signal FRP is amplified at a second slew rate lower than the first slew rate. Here, the slew rate is a characteristic value corresponding to the amplifying ability of the amplifier. Normally, the voltage level at the rise (fall) of the signal is 10% to 90%, the potential difference is dV, and the time required for the rise (fall) is Assuming that dt, slew rate is defined by the formula: dV / dt (V / μsec).

As will be described later, in the digital display mode, a digital video signal is held by a static holding circuit, and a signal corresponding to the digital video signal held in the static holding circuit is supplied to the display electrode. Since there is no danger of the video signal being attenuated, it is sufficient to apply an AC drive signal of a relatively low frequency, for example, a 1 V cycle (one vertical cycle) to the counter electrode. Therefore, in the digital display mode, there is no problem even if the slew rate of the counter electrode amplifier 82 is reduced, and power consumption can be reduced.

The white / black voltage generating circuit 7 responds to a signal from the timing control circuit 6 to display a white signal (signal B described later) and a black signal (signal A described later) used in the digital display mode. Output to panel 100.

FIG. 2 shows an example of a circuit configuration of the counter electrode amplifier 82. The counter electrode amplifier 82 uses a variable slew rate operational amplifier. The output of the operational amplifier OP is fed back to the inverting input terminal (-). The AC drive signal FRP whose bias level has been converted is applied to the non-inverting input terminal (+) of the operational amplifier. The slew rate of the operational amplifier OP can be controlled by a slew rate control signal TRC as described later.

More specifically, desired voltages (VL, VH) are created by resistors R1, R2, R3 connected between the power supply voltage Vdd and the ground voltage Vss. Then, the voltage (VH, VL) is selectively applied to the non-inverting input terminal (+) of the operational amplifier through the switch SW1 that switches according to the AC drive signal FRP. The AC drive signal FRP output from the timing control circuit 6 is, for example, (0 V, 3.3
V), according to the configuration described above, the bias level of the AC drive signal FRP is adjusted according to the standard of the liquid crystal display panel 100 by converting this signal into a signal of (VL, VH). can do.

FIG. 3 shows a first configuration example of the operational amplifier OP described above. 3, an operational amplifier OP includes a pair of differential transistors T1 and T2 (N-channel TFT), transistors T3 and T4 (P-channel TFT) forming a current mirror, and a pair of differential transistors T1 and T2.
And a transistor T5 (N
And an output stage T6 ((P-channel TFT), T7 (N-channel TFT).
5, a slew rate control signal TRC is applied to the gate of T7.

When the voltage of the slew rate control signal TRC increases, the on-resistance of the transistors T5 and T7 decreases, so that a large amount of current flows through the operational amplifier OP, and the slew rate increases. Conversely, the slew rate control signal TR
When the voltage of C decreases, the on-resistance of the transistors T5 and T7 decreases, so that the current in the operational amplifier OP decreases, and the slew rate decreases. Therefore, in the digital display mode, the timing control circuit 6 lowers the voltage of the slew rate control signal TRC, thereby lowering the slew rate of the operational amplifier OP and reducing power consumption.

FIG. 4 shows a second circuit configuration example of the counter electrode amplifier 82. In the figure, a first operational amplifier OP1 having a first slew rate and a second operational amplifier OP1 having a second slew rate
An operational amplifier OP2 is provided, and an AC drive signal FRP whose bias level is converted is applied to the non-inverting input terminals (+) of the operational amplifiers OP1 and OP2. More specifically, similarly to the first circuit configuration example, the power supply voltage V
Desired voltages (VL, VH) are created by resistors R1, R2, R3 connected between dd and the ground voltage Vss. And
Switch S that switches according to AC drive signal FRP
Through W1, voltages (VH, VL) are selectively applied to the non-inverting input terminals (+) of the first operational amplifier OP1 and the second operational amplifier OP2.

The first operational amplifier OP1 and the second operational amplifier O
The output of P2 can be switched by a switch SW2 that switches according to the slew rate control signal TRC. Therefore, in the analog display mode, the slew rate control signal TRC is set to “H” (or “L”) to select the first operational amplifier OP1, and in the digital display mode, the slew rate control signal TRC is set to “L” (or By switching to “H”) and switching to the second operational amplifier OP2, the slew rate can be reduced and power consumption can be reduced.

Next, the configuration of the liquid crystal display device, in particular, the detailed configuration of the liquid crystal display panel 100 will be described with reference to the circuit diagram of FIG.

On the insulating substrate 10, a plurality of gate signal lines 51 connected to a gate driver 50 for supplying a scanning signal are provided.
Are arranged in one direction, and these gate signal lines 51
A plurality of drain signal lines 61 are arranged in a direction intersecting with.

The drain signal line 61 is connected to the sampling transistors SP1, SP2 and SP2 in accordance with the timing of the sampling pulse output from the drain driver 60.
, SPn are turned on, and the data signal (analog video signal or digital video signal) of the data signal line 62 is supplied.

The liquid crystal display panel 100 includes a gate signal line 5
A plurality of display pixels 200 which are selected by the scanning signal from 1 and to which the data signal from the drain signal line 61 is supplied are arranged in a matrix.

Hereinafter, a detailed configuration of the display pixel 200 will be described. In the vicinity of the intersection between the gate signal line 51 and the drain signal line 61, a circuit selection circuit 40 including a P-channel TFT 41 and an N-channel TFT 42 is provided. Both drains of the TFTs 41 and 42 are connected to a drain signal line 61, and both gates thereof are connected to a circuit selection signal line 88. One of the TFTs 41 and 42 is turned on in response to a selection signal from a circuit selection signal line 88. Further, a circuit selection circuit 43 is provided in a pair with the circuit selection circuit 40 as described later.

Thus, it is possible to selectively switch between an analog display mode (corresponding to a full-color moving image) and a digital display mode (low power consumption, corresponding to a still image), which will be described later. Further, a pixel selection circuit 70 including an N-channel TFT 71 and an N-channel TFT 72 is arranged adjacent to the circuit selection circuit 40. Pixel selection TFT7
Reference numerals 1 and 72 denote circuit selection TFTs of the circuit selection circuit 40, respectively.
Gates 41 and 42 are connected in cascade, and a gate signal line 51 is connected to both gates. Pixel selection T
The FTs 71 and 72 are configured so that both are turned on at the same time according to the scanning signal from the gate signal line 51.

An auxiliary capacitor 85 for holding an analog video signal is provided. One electrode 86 of the auxiliary capacitance 85 is connected to the source of the pixel selection TFT 71. The other electrode 87 is connected to a common auxiliary capacitance line SCL, and is supplied with a bias voltage Vsc. Pixel selection TF
When an analog video signal is applied to the liquid crystal 21 by opening the gate of T71, the signal must be held for one field period, but the voltage of the signal is gradually reduced with the passage of time only with the liquid crystal 21. Then,
Appearing as display unevenness, it is impossible to obtain a good display. Therefore, an auxiliary capacitor 85 is provided to hold the voltage for one field period.

Between the storage capacitor 85 and the liquid crystal 21,
A P-channel TFT 44 of the circuit selection circuit 43 is provided, and is turned on and off simultaneously with the TFT 41 of the circuit selection circuit 43. In addition, T of the pixel selection circuit 70
A static memory circuit 110 and a signal selection circuit 120 are provided between the FT 72 and the display electrode 80 of the liquid crystal 21.

The static memory circuit 110 includes first and second inverter circuits IN forming a positive feedback loop.
V1 and INV2. First inverter circuit INV
The input of 1 is connected to the source 11s of the pixel selection TFT 72, and the output is input to the second inverter circuit INV2. The output of the second inverter circuit INV2 is connected to the input of the first inverter circuit INV1.

In the digital display mode, the potential of the circuit selection signal line 88 becomes "H" and the gate signal line 5
When the one scanning signal becomes “H”, the static memory circuit 110 becomes writable.

The signal selection circuit 120 is a circuit for selecting a signal in accordance with the digital video signal held in the static memory circuit 110, and includes two N-channel TFs.
It is composed of T121 and T122. TFT 121, 1
Complementary output signals from the static memory circuit 110 are applied to the gates of the gates 22 respectively.
The FTs 121 and 122 turn on and off complementarily.

When the TFT 122 is turned on, the common electrode voltage V
When COM (signal B) is selected and the TFT 121 is turned on, a signal (signal A) having an opposite phase to the signal B is selected,
The voltage is supplied to the display electrode 80 that applies a voltage to the liquid crystal 21 via the TFT 45 of the circuit selection circuit 43. Here, it is assumed that the AC drive signal from the above-described counter electrode amplifier 82 is supplied to the counter electrode 32 of the liquid crystal 21 as the counter electrode voltage VCOM.

Next, the peripheral circuit of the display pixel 200 will be described. The driver scan LSI is provided on the insulating substrate 10 of the display pixel 200 and the external circuit substrate 90 which is another substrate.
91 are provided. The vertical start signal STV is output from the driver scan LSI 91 of the external circuit board 90.
Is input to the gate driver 50, and the horizontal start signal S
TH is input to the drain driver 60. Further, a video signal is input to the data signal line 62.

Next, a method of driving the display device having the above-described configuration will be described with reference to FIGS. FIG.
FIG. 6 is a timing chart when the liquid crystal display device is selected to be in the digital display mode. (1) In the case of the analog display mode When the analog display mode is selected in accordance with the mode switching signal MD, the analog video signal is output to the data signal line 62 through the DA converter 3 and the amplifier 4 described above. At the same time, the circuit selection signal line 88 becomes “L”, and the TFTs 41 and 44 of the circuit selection circuits 40 and 43 are turned on.

Further, the sampling transistor SP according to the sampling signal based on the horizontal start signal STH
Is turned on, and the analog video signal of the data signal line 62 is supplied to the drain signal line 61.

A scanning signal is supplied to the gate signal line 51 based on the vertical start signal STV. When the TFT 71 is turned on in response to the scanning signal, the drain signal line 6
1 transmits the analog video signal Sig to the display electrode 80 and is held in the auxiliary capacitance 85. Display electrode 80
Is applied to the liquid crystal 21,
A liquid crystal display can be obtained by orienting the liquid crystal 21 according to the voltage.

Here, the AC drive signal from the counter electrode amplifier 82 described above is supplied to the counter electrode 32 of the liquid crystal 21, and the cycle is switched to, for example, one horizontal period.

This analog display mode is suitable for displaying a full-color moving image. (2) Digital display mode When the digital display mode is selected in accordance with the mode switching signal MD, the digital signal is set to be output to the data signal line 62 and the circuit selection signal line 8 is set.
8 becomes “H” and the static memory circuit 1
10 becomes operable.

Here, the digital video signal is input to the data signal line 62 through the amplifier 4 after the signal processing is performed by the signal processing circuit 1 as described above.

The TFTs 4 of the circuit selection circuits 40, 43
1 and 44 are turned off, and the TFTs 42 and 45 are turned on. Also, the driver scan L of the external circuit board 90 is used.
Start signals STV and STH are input from the SI 91 to the gate driver 50 and the drain driver 60, respectively. Sampling signals are sequentially generated in response thereto, and the sampling transistors SP1, SP2,..., SPn are sequentially turned on in accordance with the respective sampling signals to sample the digital video signal Sig and supply it to each drain signal line 61.

Here, the first row, that is, the gate signal line 51 to which the scanning signal G1 is applied will be described. First, the TFTs of the display pixels P11, P12,... P1n connected to the gate signal line 51 are turned on by the scanning signal G1 for one horizontal scanning period.

Focusing on the display pixel P11 in the first row and first column, the digital video signal S11 sampled by the sampling signal SP1 is input to the drain signal line 61. Then, the scanning signal G1 becomes “H” and the TFT 7
When 0 is turned on, the drain signal D1 is written to the static memory circuit 110.

In this digital display mode, the level of the digital video signal S11 is a binary output of a high potential (VH) and a low potential (VL). Therefore, writing can be performed by setting the threshold value of the static memory circuit 110 between the high potential (VH) and the low potential (VL).

The signal held by the static memory circuit 110 is input to the signal selection circuit 120, and the signal selection circuit 120 selects the signal A or the signal B.
The selected signal is applied to the display electrode 80, and the voltage is applied to the liquid crystal 21. Thus, the gate signal line 51
, The scanning for one screen (one field period) is completed.

Thereafter, the static memory circuit 110
(Display of a still image) based on the data held in. In the digital display mode, the supply of the voltage to the gate driver 50, the drain driver 60, and the external driver scan LSI 91 is stopped, and the driving thereof is stopped. The voltages VDD and VSS are always supplied to the static memory circuit 110, the AC drive signal is supplied to the counter electrode 32, and the signals A and B are supplied to the signal selection circuit 120. The voltage is not applied to the other gate driver 50, drain driver 60, and external LSI 91. Thereby, one screen can be held and displayed as a still image.

When the liquid crystal display panel 100 is normally white (NW), the same signal as the common electrode voltage VCOM (= AC drive signal) supplied to the common electrode 32 is supplied as the signal B, and the signal A is supplied to the signal A. Supplies a signal having the opposite phase to the signal B.

In this digital display mode, the cycle of the AC drive signal is switched to a relatively long cycle (for example, one vertical period or more), thereby reducing power consumption. Along with this, by decreasing the slew rate of the counter electrode amplifier 82 that amplifies the AC drive signal supplied to the counter electrode 32,
Further, power consumption can be reduced.

When “H (high)” as a digital video signal is input to the drain type signal line 61 to the static memory circuit 110, “L” is input to the first TFT 121 in the signal selection circuit 120. Therefore, the first TFT 121 is turned off, and the other second TFT 1
Since “H” is inputted to the second TF, the second TF
T122 is turned on.

Then, the signal B is selected, and the voltage of the signal B is applied to the liquid crystal. That is, the same counter electrode voltage VCOM as that of the counter electrode 32 is applied, no electric field is generated, and N
On the W display panel, white display can be observed.

On the other hand, when “L” is input to the static memory circuit 110 as a digital video signal on the drain signal line 61, the first T
Since “H” is input to the FT 121, the first
TFT 121 is turned on, and the other second TFT 12
Since "L" is input to the second TFT, the second TFT
122 turns off. Then, signal A is selected,
The voltage of the signal A is applied to the liquid crystal 21. That is, since the signal A has an opposite phase to the counter electrode voltage VCOM, an electric field is generated, and the liquid crystal rises due to the electric field, so that the NW display panel can be observed as a black display.

The display device of the present invention is preferably applied to a reflection type liquid crystal display device among liquid crystal display devices. Therefore, the device structure of the reflection type liquid crystal display device will be described with reference to FIG.

As shown in FIG. 7, one of the insulating substrates 10
On the semiconductor layer 11 made of polycrystalline silicon,
A gate insulating film 12 is formed thereon, and a gate electrode 13 is formed on the gate insulating film 12 above the semiconductor layer 11.

In the lower semiconductor layer 11 located on both sides of the gate electrode 13, a source 11s and a drain 11d are formed. An interlayer insulating film 14 is deposited on the gate electrode 13 and the gate insulating film 12, and a contact hole 15 is formed at a position corresponding to the drain 11d and a position corresponding to the source 11s. The drain 11d is connected to a drain electrode 16, and the source 11s is connected to a display electrode 19 via a contact hole 18 provided in a planarization insulating film 17 provided on the interlayer insulating film 14.

Each display electrode 19 formed on the flattening insulating film 17 is made of a reflective material such as aluminum (Al). An alignment film 20 made of polyimide or the like for aligning the liquid crystal 21 is formed on each of the display electrodes 19 and the flattening insulating film 17.

On the other insulating substrate 30, red (R),
A color filter 3 that exhibits green (G) and blue (B) colors
1. Counter electrode 32 made of a transparent conductive film such as ITO (Indium Tin Oxide), and alignment film 33 for aligning liquid crystal 21
Are formed in order. When color display is not performed, the color filter 31 is unnecessary.

The pair of insulating substrates 1 thus formed
The periphery of 0, 30 is adhered with an adhesive sealing material, and the gap formed thereby is filled with the liquid crystal 21 to complete the reflection type liquid crystal display device.

As shown by the dotted arrow in the figure, external light incident from the observer 1 side sequentially enters from the counter electrode substrate 30,
The light is reflected by the display electrode 19 and emitted to the observer 1 side, so that the display can be observed by the observer 1.

As described above, the reflection type liquid crystal display device is a system for observing a display by reflecting external light, and it is necessary to use a so-called backlight on the side opposite to the observer side like a transmission type liquid crystal display device. Therefore, power for lighting the backlight is not required. Therefore, it is preferable that the display device of the present invention is a reflective liquid crystal display device which does not require a backlight and is suitable for low power consumption.

In the above embodiment, the case where a 1-bit digital data signal is input in the digital display mode has been described. However, the present invention is not limited to this. It is possible to apply even in the case of. Thus, multi-tone display can be performed. At that time, it is necessary to set the number of holding circuits and signal selection circuits according to the number of input bits. Further, the signal processing of the signal processing circuit 1 needs to be changed.

[0076]

According to the display device of the present invention, a digital display can be selected from two types of display, an analog display mode (normal display mode) and a digital display (display mode using a static memory). Power consumption in the mode can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram illustrating a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a first circuit configuration of a counter electrode amplifier 82.

FIG. 3 is a circuit diagram showing a configuration of a counter electrode amplifier 82 in FIG.

FIG. 4 is a circuit diagram showing a second circuit configuration of the counter electrode amplifier 82.

FIG. 5 is a circuit diagram showing a detailed configuration of a liquid crystal display panel.

FIG. 6 is a timing chart when a digital display mode is selected.

FIG. 7 is a sectional view of a reflection type liquid crystal display device.

FIG. 8 is a circuit configuration diagram of a liquid crystal display device according to a conventional example.

FIG. 9 is a circuit configuration diagram of a liquid crystal display device according to a conventional example.

FIG. 10 is a block diagram illustrating a configuration of a liquid crystal display device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Signal processing circuit 3 DA converter 4 Amplifier 5 Oscillator 6 Timing control circuit 7 White / black voltage generation circuit 21 Liquid crystal 32 Counter electrode 40, 43 Circuit selection circuit 41, 42 Circuit selection TFT 44, 45 Circuit selection TFT 50 Gate driver 51 Gate signal line 60 Drain driver 61 Drain signal line 62 Data signal line 70 Pixel selection circuit 71, 72 Pixel selection TFT 80 Display electrode 81, 82 Counter electrode amplifier 85 Auxiliary capacitance 88 Circuit selection signal line 100 Liquid crystal display panel 110 Static memory circuit 120 Signal selection circuit 200 Display pixel

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/20 624 G09G 3/20 624B 624C F-term (Reference) 2H093 NA31 NA41 NA51 NA34 NC34 ND06 ND39 5C006 AA01 AA02 AC25 AC26 AF71 AF82 BB16 BC03 BC06 BC12 BC13 BC16 BC20 BF09 BF24 BF25 FA47 5C080 AA06 AA10 BB05 DD26 EE17 FF11 GG12 JJ02 JJ03 JJ04 KK07

Claims (10)

[Claims] A first display circuit that supplies an analog video signal to a display electrode; and a second display circuit that supplies a signal corresponding to a digital video signal held in a static type holding circuit to the display electrode. A circuit selection circuit for selectively selecting the first display circuit and the second display circuit, and an AC drive signal supplied to a counter electrode provided opposite to the display electrode, and an amplification capability thereof. And a counter electrode amplifier variably controlled, wherein the amplification capability of the counter electrode amplifier is reduced when the second display circuit is selected. 2. The display device according to claim 1, wherein the counter electrode amplifier comprises an amplifier whose slew rate is variably controlled according to a control signal. 3. A control transistor whose on-resistance is variably controlled by the control signal in a current path from a high potential side potential to a low potential side potential of the amplifier. 4. The display device according to 3. 4. The display device according to claim 2, wherein the amplifier is a negative feedback type operational amplifier. 5. A counter amplifier comprising: a first amplifier and a second amplifier having different slew rates from each other; a switch for switching between the first amplifier and the second amplifier;
The display device according to claim 1, comprising: 6. The display device according to claim 5, wherein the first and second amplifiers are negative feedback type operational amplifiers. 7. A display element for performing display by a predetermined signal applied to a display electrode and a counter electrode, a first display circuit for supplying an analog video signal to the display electrode, and a static holding circuit A second display circuit for supplying a signal corresponding to the digital video signal to the display electrode,
A circuit selection circuit for selectively selecting the first display circuit and the second display circuit; a counter electrode amplifier for amplifying an AC drive signal and supplying the amplified signal to the counter electrode, and having an amplification capability variably controlled; A control circuit for switching a signal cycle of the AC drive signal, wherein when the second display circuit is selected, the cycle of the AC drive signal is switched to a long cycle and the slew rate of the counter electrode amplifier is reduced. A display device characterized in that: 8. The display device according to claim 7, wherein said counter electrode amplifier is a negative feedback type operational amplifier. 9. The control transistor according to claim 8, wherein a control transistor whose on-resistance is variably controlled by said control signal is provided in a current path from a high potential side potential to a low potential side potential of said operational amplifier. The display device according to the above. 10. The counter electrode amplifier comprises: a first operational amplifier and a second operational amplifier having different slew rates from each other;
8. A switch for switching between the first operational amplifier and the second operational amplifier.
The display device according to claim 1.