JP2012060091A - Semiconductor element, semiconductor device, and manufacturing method of semiconductor element - Google Patents

Abstract

An object is to provide a semiconductor element that uses an oxide semiconductor in a semiconductor region, can control a large current with high breakdown voltage, and is excellent in mass productivity. Another object is to provide a semiconductor device using the semiconductor element. Another object is to provide a method for manufacturing the semiconductor element.
A transistor including an oxide semiconductor in a semiconductor region and a semiconductor chip including a through electrode electrically connected to each of a gate electrode layer, a source electrode layer, and a drain electrode layer of the transistor are stacked, and the transistor is formed. By electrically connecting in parallel, a semiconductor element having a substantially long W length is provided.
[Selection] Figure 1

Description

The present invention relates to a semiconductor element, a semiconductor device using the semiconductor element, and a method for manufacturing the semiconductor element.

Note that in this specification, a semiconductor element refers to an element that functions by utilizing semiconductor characteristics, and includes a structure in which a plurality of transistors are integrated. In this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, an electronic component, and an electronic device are all semiconductor devices.

It is desirable that a semiconductor device used for a power converter, a so-called power device, has a high breakdown voltage and low loss. Conventionally, power devices using silicon semiconductors have been disclosed. However, in semiconductor elements using silicon, it is said that the physical characteristics have reached the limit of the theoretical value, and in order to realize a power device capable of controlling a higher withstand voltage and a larger current, There is a need to provide new semiconductor materials capable of improving characteristics and new structures of semiconductor devices.

As semiconductor materials that can improve various characteristics such as high breakdown voltage, high conversion efficiency, and high-speed switching instead of silicon semiconductors, for example, silicon carbide and gallium nitride are disclosed (Patent Document 1 and Patent Document 2). ).

JP 2010-129628 A JP 2010-171416 A

However, the film formation temperature of silicon carbide is about 1500 ° C. and the film formation temperature of gallium nitride is about 1100 ° C. These compound semiconductors are extremely high in film formation temperature, and it is difficult to increase the size of the substrate. There is a problem that is low.

The present invention has been made under such a technical background. Therefore, it is an object of the present invention to provide a semiconductor element that has a high breakdown voltage, can control a large current, and is excellent in mass productivity. Another object is to provide a semiconductor device using the semiconductor element, and to provide a method for manufacturing the semiconductor element.

In order to achieve the above object, the present inventor has focused on an oxide semiconductor.

Since an oxide semiconductor exhibits a wide band gap, it has a higher breakdown voltage than silicon or the like, and has a high breakdown resistance required for a semiconductor material for power devices.

In addition, since the deposition temperature of the oxide semiconductor film is approximately 700 ° C., the substrate can be increased in size. Further, the oxide semiconductor film can be manufactured by a sputtering method, a wet method (for example, a printing method) or the like, and is excellent in mass productivity because a doping step is unnecessary.

On the other hand, the mobility of an oxide semiconductor may not always be sufficient as a semiconductor material for a power device that allows a large current to flow. When a power device transistor is manufactured using a semiconductor material with low mobility, a large current cannot be flowed quickly, and there is a problem that the transistor generates heat when a large current is flowed.

As a means for solving such a problem, there is a method of increasing the W length (channel width) of a transistor.

However, when the W length of the transistor is increased, there is a problem that the area of the transistor increases and the area occupied by the transistor in the circuit increases. Further, when the area per transistor is increased, the number of transistors that can be manufactured per substrate is reduced. In addition, if a defect due to particles or the like is included even at one location, the reliability of the transistor is impaired. Therefore, in the case where the same number of defects due to particles or the like occurs per substrate, the larger the transistor area, the higher the probability of being defective.

Therefore, in order to solve the above problems, a semiconductor chip including one or more transistors using an oxide semiconductor having a wide band gap in a channel formation region and a through electrode that electrically connects the transistors is stacked. A transistor having a substantially long W length can be manufactured without enlarging the area of the element by electrically connecting the transistors through the through electrode in parallel.

That is, according to one embodiment of the present invention, a first transistor using an oxide semiconductor for a semiconductor layer and three through electrodes that are electrically connected to a gate electrode layer, a source electrode layer, and a drain electrode layer of the first transistor, respectively. A first substrate having an oxide semiconductor as a semiconductor layer, and three through holes electrically connected to the gate electrode layer, the source electrode layer, and the drain electrode layer of the second transistor, respectively. The first transistor and the second transistor are semiconductor elements that are electrically connected in parallel via respective through electrodes.

According to one embodiment of the present invention, by using an oxide semiconductor as a semiconductor material, a transistor having high breakdown voltage and low loss and characteristics suitable for a power device can be manufactured. In addition, since the oxide semiconductor film has a lower deposition temperature than other semiconductor materials for power devices, the substrate can be increased in size and a transistor with high productivity can be manufactured.

Further, according to one embodiment of the present invention, it is possible to increase the substantial W length without enlarging the area of the element by stacking the substrates and electrically connecting the transistors in parallel. It is possible to provide a semiconductor element capable of promptly flowing a large current necessary for a power device.

Another embodiment of the present invention is a semiconductor element using a through electrode that penetrates a substrate. In the stacking method using the through electrode, the length of the wiring drawn out from the electrode layer can be set freely, so that the length of the wiring can be set freely even if the substrate becomes large, generating heat from the wiring, Resistance can be reduced.

In the above semiconductor element, the oxide semiconductor is preferably formed of an oxide semiconductor having a band gap of 3 eV or more. As a result, a transistor with excellent withstand voltage can be provided.

In the semiconductor element, a silicon substrate is preferably used for the first substrate and the second substrate. By using a silicon substrate, even when semiconductor chips are stacked, deterioration of the semiconductor element due to heat can be prevented due to the excellent heat dissipation of silicon. In addition, since silicon has good workability, it is possible to easily perform drilling when forming the through electrode.

In the semiconductor element, an insulating substrate may be used for the first substrate and the second substrate. The use of an insulating substrate is preferable because it is not necessary to form an insulating film that prevents conduction between the through electrode and the substrate, and the process is simplified.

Another embodiment of the present invention is a semiconductor device using the above semiconductor element. As a result, a high-performance semiconductor device that can control a large current with a high breakdown voltage can be provided.

According to one embodiment of the present invention, a first transistor in a first region of a substrate and a second transistor in a second region of the substrate are manufactured, and a gate electrode layer and a source electrode layer of the first transistor are manufactured. A first semiconductor chip including a first region, and six through electrodes electrically connected to the gate electrode layer, the source electrode layer, and the drain electrode layer of the second transistor and the gate electrode layer, the source electrode layer, and the drain electrode layer of the second transistor; The first step of forming the second semiconductor chip having the second region by dividing the substrate, the first semiconductor chip and the second semiconductor chip are stacked, and the first transistor and the second semiconductor chip are stacked. This is a method for manufacturing a semiconductor device having a second step of electrically connecting the transistors in parallel through a through electrode. As a result, since a semiconductor element having a long W length can be manufactured without enlarging the area of the element, the semiconductor element can be efficiently manufactured without being affected by a substrate defect or the like.

Note that in this specification, a semiconductor chip includes a transistor that uses an oxide semiconductor for a semiconductor layer, and three through electrodes that are electrically connected to the gate electrode layer, the source electrode layer, and the drain electrode layer of the transistor, respectively. Having a substrate.

Further, in this specification and the like, the terms “upper” and “lower” do not limit that the positional relationship between the constituent elements is “directly above” or “directly below”. For example, the expression “a gate electrode layer over a gate insulating layer” does not exclude the case where another component is included between the gate insulating layer and the gate electrode layer. In addition, the terms “upper” and “lower” are merely expressions used for convenience of explanation, and include terms in which the top and bottom are interchanged unless otherwise specified.

Further, in this specification and the like, the terms “electrode” and “wiring” do not functionally limit these components. For example, an “electrode” may be used as part of a “wiring” and vice versa. Furthermore, the terms “electrode” and “wiring” include a case where a plurality of “electrodes” and “wirings” are integrally formed.

In addition, the functions of “source” and “drain” may be switched when transistors having different polarities are employed or when the direction of current changes in circuit operation. Therefore, in this specification, the terms “source” and “drain” can be used interchangeably.

According to one embodiment of the present invention, it is possible to provide a semiconductor element that has high breakdown voltage, can control a large current, and is excellent in mass productivity.
In addition, a semiconductor device using the semiconductor element can be provided. In addition, a method for manufacturing the semiconductor element can be provided.

10A and 10B illustrate a semiconductor element according to an embodiment. 8A and 8B illustrate a method for manufacturing a semiconductor element according to an embodiment. 8A and 8B illustrate a method for manufacturing a semiconductor element according to an embodiment. 8A and 8B illustrate a method for manufacturing a semiconductor element according to an embodiment. 10A to 10D illustrate a method for manufacturing a transistor according to an embodiment. FIG. 9 illustrates a converter circuit according to an embodiment.

Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in structures of the invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated.

(Embodiment 1)
In this embodiment, a structure and a manufacturing method of a semiconductor element of one embodiment of the present invention will be described with reference to FIGS.

1A and 1B illustrate an example of a structure of a semiconductor element of one embodiment of the present invention. FIG. 1B is a top view of a semiconductor element of one embodiment of the present invention. FIG. 1A is a cross-sectional view taken along the line P1-P2 in FIG.

One embodiment of the present invention is a semiconductor element manufactured by stacking a plurality of semiconductor chips as illustrated in FIG. The number of semiconductor chips to be stacked may be any number as long as it is two or more, and can be appropriately determined according to required performance. In this embodiment, a structure in which two semiconductor chips are stacked with a conductor interposed therebetween will be described. As shown in FIG. 1A, the semiconductor element has a structure in which a semiconductor chip 100a and a semiconductor chip 100b are connected to each other through a conductor 207.

<Configuration of semiconductor chip>
Next, the semiconductor chip will be described with reference to FIG. A semiconductor chip 100a illustrated in FIGS. 1A and 1B includes one transistor 130a, a through electrode 120a electrically connected to the gate electrode layer 111a of the transistor 130a, and a through electrode electrically connected to the source electrode layer 106a. Three through electrodes of a through electrode 122a electrically connected to the electrode 121a and the drain electrode layer 107a are provided. Further, as shown in FIG. 1A, the semiconductor chip 100b includes a transistor 130b and three through electrodes. In this embodiment mode, all transistors included in the semiconductor chip have the same configuration. Note that the structure of the semiconductor chip of one embodiment of the present invention is not limited to this, and one semiconductor chip may include a plurality of transistors.

<Structure of transistor>
In the transistor included in the semiconductor chip of this embodiment, an oxide semiconductor is used for a semiconductor layer.

The structure of the transistor 130a is described below. The transistor 130b has a structure similar to that of the transistor 130a. In order to avoid overlapping description, the description of the structure of the transistor 130a is used for the description of the transistor 130b.

In this embodiment, a structure in which a semiconductor chip includes a top-gate / top-contact transistor is described as an example; however, a structure of a transistor that can be used for a semiconductor element of one embodiment of the present invention is There is no limitation, and a bottom gate type structure or a top gate type structure may be used. Furthermore, a bottom contact structure or a top contact structure may be used.

In FIG. 1A, a transistor 130a includes a base film 103a covering the silicon substrate 101a, an island-shaped oxide semiconductor layer 105a over the base film 103a, and a pair of electrodes in contact with the oxide semiconductor layer 105a. The source electrode layer 106a and the drain electrode layer 107a, the oxide semiconductor layer 105a, the gate insulating layer 109a formed so as to cover the source electrode layer 106a and the drain electrode layer 107a, and the oxide semiconductor layer over the gate insulating layer 109a The gate electrode layer 111a overlaps with the channel formation region 105a, and the protective insulating layer 113a covers the gate electrode layer 111a and the gate insulating layer 109a. The source wiring 116a is electrically connected to the source electrode layer 106a through an opening formed in the gate insulating layer 109a, and the drain wiring 117a is connected to the drain electrode layer through an opening formed in the gate insulating layer 109a. It is electrically connected to 107a.

Note that although a silicon substrate is used as the substrate in this embodiment, there is no particular limitation on a substrate on which a semiconductor chip is manufactured. A silicon substrate is excellent in workability, and can be suitably used because it is easy to make a hole when forming a through electrode. Furthermore, due to the excellent heat dissipation of silicon, deterioration of a semiconductor element due to heat can be prevented even when transistors are stacked. Note that when an insulating substrate made of an insulator is used, a step of forming the insulating film 201 for preventing conduction between the through electrode and the substrate becomes unnecessary. Insulating substrates include glass substrates such as barium borosilicate glass and alumino borosilicate glass, insulating resin substrates (organic insulating substrates) such as BCB (benzocyclobutane) and epoxy, ceramic substrates, quartz substrates, and sapphire substrates. Etc. can be used.

<Configuration of through electrode>
The semiconductor chip is provided with a through electrode in a region that does not overlap with the transistor. The gate electrode layer 111a is electrically connected to the through electrode 120a, the source electrode layer 106a is electrically connected to the through electrode 121a, and the drain electrode layer 107a is electrically connected to the through electrode 122a (FIG. 1 ( (See B)

Each through electrode is exposed on the upper surface of the semiconductor chip and the lower surface of the semiconductor chip.

<Electrical connection>
As already described, the semiconductor element is an element in which the semiconductor chip 100a and the semiconductor chip 100b are connected. Specifically, the through electrodes connected to the gate electrode layer, the through electrodes connected to the source electrode layer, and the through electrodes connected to the drain electrode layer are electrically connected by the conductor 207, respectively. That is, the transistor 130a and the transistor 130b are electrically connected in parallel.

As described above, the semiconductor element of this embodiment is electrically connected to the first transistor using an oxide semiconductor for the semiconductor layer, the gate electrode layer, the source electrode layer, and the drain electrode layer of the first transistor. A first substrate having three through electrodes, a second transistor using an oxide semiconductor as a semiconductor layer, and a gate electrode layer, a source electrode layer, and a drain electrode layer of the second transistor, respectively, The second substrate having three through electrodes to be connected is laminated. Further, the first transistor and the second transistor are electrically connected in parallel through the respective through electrodes.

In the semiconductor element of this embodiment, since transistors are connected in parallel by through electrodes, the substantial W length can be increased without increasing the area of the transistor, and the semiconductor element having high mobility Can be provided.

In addition, since the semiconductor element of this embodiment uses an oxide semiconductor for a semiconductor layer, it has a characteristic that a high current can be controlled with a high breakdown voltage. Therefore, it is suitable for a semiconductor device such as a power device that handles a large current.

Note that this embodiment can be combined with any of the other embodiments described in this specification as appropriate.

(Embodiment 2)
In this embodiment, a method for manufacturing the semiconductor element exemplified in Embodiment 1 will be described with reference to FIGS.

The manufacturing method of a semiconductor element consists of two steps. Specifically, a plurality of transistors and through electrodes that are electrically connected to the gate electrode layer, the source electrode layer, and the drain electrode layer of the transistors are formed over the silicon substrate 101 (see FIG. 4A). ), A first step (see FIG. 4B) for dividing the silicon substrate 101 to fabricate the semiconductor chip 100, and a plurality of semiconductor chips 100 are stacked (see FIG. 4C) to penetrate each other. It consists of the 2nd step (refer FIG.4 (D)) which connects an electrode.

That is, the first transistor in the first region of the substrate and the second transistor in the second region of the substrate are manufactured, and the gate electrode layer, the source electrode layer, and the drain electrode layer of the first transistor are electrically connected to each other. Three through electrodes that are electrically connected to each other are formed in the first region, and three through electrodes that are electrically connected to the gate electrode layer, the source electrode layer, and the drain electrode layer of the second transistor are respectively formed in the second region. , A first step of forming a first semiconductor chip having a first region and a second semiconductor chip having a second region by dividing a substrate, a first semiconductor chip and a second semiconductor chip This is a method for manufacturing a semiconductor element having a second step of stacking semiconductor chips and electrically connecting a first transistor and a second transistor in parallel via a through electrode.

<First step>
A plurality of transistors using an oxide semiconductor for a semiconductor layer are formed over a silicon substrate 101. Note that details of a manufacturing method of the transistor will be described in Embodiment 3.

Subsequently, a through electrode for connecting the transistors is manufactured.

A process for manufacturing the through electrode will be described with reference to FIGS. Note that FIGS. 2 and 3 illustrate only a manufacturing process of the through electrode 122 that is electrically connected to the drain electrode layer 107 of the transistor. For the through electrode that is electrically connected to the source electrode layer or the gate electrode layer 111, the drain electrode layer 107 is illustrated. It is manufactured in the same process as the through electrode 122 that is electrically connected to the electrode, and the description and illustration are omitted.

As shown in FIG. 2B, a via 200 for embedding the through electrode 122 is formed. The via 200 penetrates the protective insulating layer 113, the gate insulating layer 109, and the base film 103 in an opening that reaches the upper surface of the drain wiring 117 in the protective insulating layer 113 and a region that does not overlap with the transistor, and forms a recess in the silicon substrate 101. It consists of an opening (see FIG. 2B). The via 200 is formed using etching or laser when a silicon wafer is used as the substrate, and is formed using sand blasting or laser because it is difficult to perform anisotropic etching when glass is used. To do.

Next, as shown in FIG. 2C, an insulating film 201 (oxide film or nitride film) is formed on the silicon substrate 101 by heat-treating the substrate. In this embodiment, an oxide film is formed by performing thermal oxidation treatment on the silicon substrate 101. The thermal oxidation treatment is preferably performed by adding halogen in an oxidizing atmosphere. For example, by performing thermal oxidation treatment on a single crystal silicon substrate in an oxidizing atmosphere to which chlorine (Cl) is added, a chlorine-oxidized oxide film can be formed. Note that when an insulating substrate made of an insulator is used as the substrate, heat treatment is unnecessary.

Note that in the case where an insulating film is formed over the gate electrode layer 111, the source wiring, and the drain wiring 117 by heat treatment of the substrate, the insulating film needs to be etched to expose the conductive layer.

Next, as illustrated in FIG. 2D, a conductive barrier film 203 is formed in the via 200. The conductive barrier film 203 functions as a protective film that prevents diffusion of metal from the wiring 205. The conductive barrier film 203 may be formed using one or more materials selected from tantalum nitride, titanium nitride, tungsten nitride, tantalum carbide (TaC), and titanium carbide (TiC). Further, a three-dimensional amorphous barrier film having silicon may be used.

The conductive barrier film 203 can be formed using a film formation method such as a PVD method or a CVD method, or a sputtering method. For example, in the case of a titanium nitride film, nitrogen and argon may be used as a sputtering gas and formed at an output of 150 W. It has a polycrystalline structure, and the diffusion preventing function is improved by the presence of grain boundaries. At this time, a dense film can be formed and the barrier property can be improved by increasing the sputtering output, increasing the flow rate ratio of argon gas, or increasing the temperature of the substrate. . In this embodiment, a tantalum nitride film is used. The tantalum nitride film is a conductive film having a high barrier property, and when polishing in a later step is considered, a CMP method (Chemical-Mechanical-Polishing) is used. Since it can be easily processed, it is suitable for the conductive barrier film used in this embodiment.

Next, as illustrated in FIG. 2E, the wiring 205 is embedded in the via 200. A metal such as Cu, Ag, or Ni is used for the wiring. As a wiring method, a CVD method, a sputtering method, a remote plasma method, a plating method, or the like is used. By using the multi-chamber, the conductive barrier film and the wiring can be continuously formed without being exposed to the atmosphere. By performing continuous film formation in this manner, adhesion of impurities to the interface can be prevented and good film formation can be performed.

By etching, the conductive barrier film 203 and the wiring 205 are etched into a desired shape. Note that in the wiring embedding by plating, the wiring 205 can be selectively formed from the beginning.

Next, as illustrated in FIG. 3A, the protective layer 115 is formed over the wiring 205. The protective layer 115 can be formed by a plasma CVD method, a sputtering method, or the like. The protective layer 115 includes a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, an aluminum nitride film, an aluminum oxynitride film, an aluminum nitride oxide film, a hafnium oxide film, or a tantalum oxide. One or a plurality of films selected from a film and the like can be formed as a single layer or stacked.

Next, as illustrated in FIG. 3B, the wiring 205 is exposed on the upper surface and the lower surface. By polishing the protective layer 115 and the wiring 205 on the upper surface, the wiring 205 is exposed to the upper surface and the upper surface is planarized. On the lower surface, the substrate 101, the insulating film 201, and the conductive barrier film 203 are polished to expose the wiring 205 and planarize the lower surface. As the planarization treatment, polishing treatment or laser irradiation treatment can be performed. The polishing process and the laser beam irradiation process may be performed a plurality of times or in combination. Further, the order of processing is not limited and can be selected as appropriate. A lamp light irradiation process may be performed instead of the laser light irradiation process.

Since the wiring 205 was exposed on the upper and lower surfaces, the drain electrode layer 107 was conducted to the upper and lower surfaces of the semiconductor chip. As shown in FIG. 3B, the wiring 205 and the conductive barrier film 203 that connect the upper and lower surfaces of the transistor and each electrode layer are referred to as a through electrode 122.

Next, as illustrated in FIG. 3C, a conductor 207 is formed.

The conductor 207 is preferably formed using a conductive material having fluidity, such as a conductive paste containing conductive fine particles or conductive powder, or a conductive liquid containing conductive fine particles or conductive powder. By using such a conductive material, the conductor 207 can be formed by a droplet discharge method (including methods such as an inkjet method and a dispenser method), a printing method such as a screen printing method, and the like. . In these methods, the convex conductor 207 is formed at a necessary place without performing a film formation process in a complicated film formation apparatus such as a CVD apparatus or a sputtering apparatus, and an exposure process for forming a photomask. It is possible to form.

The conductive paste and the conductive liquid are conductive fine particles, a material in which conductive powder is dispersed, or a conductive material in which these are dissolved. For example, as the material of the conductive powder or conductive fine particles contained in the conductive liquid, for example, metals such as Ag, Au, Cu, Ni, Pt, Pd, Nd, and alloys of these metal materials (for example, Ag-Pd) ), Conductive oxide materials such as indium oxide and zinc oxide. Moreover, as a medium (solvent, dispersing agent) for dissolving or dispersing conductive powder or conductive fine particles, for example, a photocurable resin such as an ultraviolet curable resin, or a precursor material of a thermosetting resin Can be given. Examples of the ultraviolet curable resin include acrylic resins and epoxy resins. An example of the thermosetting resin is a polyimide resin.

Subsequently, the substrate 101 is cut and divided into individual semiconductor chips 100 (see FIG. 4B). For cutting, dicing, scribing, laser cutting, or the like can be used to selectively divide.

As described above, by fabricating a plurality of transistors on a substrate and then separating them, it is possible to sort them into non-defective transistors and defective transistors affected by particles, etc. Therefore, the semiconductor element can be efficiently manufactured.

The semiconductor chip 100 can be formed through the above steps.

<Second step>
Next, as shown in FIG. 3D, the cut semiconductor chips 100 are stacked one above the other and connected in parallel through the through electrode 122 and the conductor 207.

The semiconductor chip is electrically connected by bringing the conductor 207 and the through electrode exposed on the lower surface of the substrate into contact with each other so as to overlap each other. As a method for fixing the semiconductor chips, it is possible to fix the through electrodes to each other with solder or the like, and to fix them with a sealing resin in order to improve connection reliability. As the resin to be used, a photocurable resin, a thermosetting resin, a naturally curable resin, or the like can be used.

The number of semiconductor chips stacked above and below can be freely determined, and the number stacked may be changed according to the required performance.

As described above, the semiconductor element of this embodiment can be manufactured.

Since the semiconductor element of this embodiment uses an oxide semiconductor for a semiconductor layer, it has a characteristic that a high current can be controlled with a high breakdown voltage. Therefore, it is suitable for a semiconductor device such as a power device that handles a large current.

In the semiconductor element of this embodiment, transistors are connected in parallel by through electrodes, so that the substantial W length of the transistors can be increased and high mobility suitable for a power device is realized.

Note that this embodiment can be combined with any of the other embodiments described in this specification as appropriate.

(Embodiment 3)
In this embodiment, a method for manufacturing a transistor that can be applied to the semiconductor elements described in Embodiments 1 and 2 will be described with reference to FIGS.

In the transistor of this embodiment, an oxide semiconductor is used for a semiconductor layer. The oxide semiconductor used for the semiconductor layer in this embodiment is purified by removing hydrogen that is an n-type impurity from the oxide semiconductor so that impurities other than the main components of the oxide semiconductor are included as much as possible. The oxide semiconductor is an I-type (intrinsic) oxide semiconductor or an oxide semiconductor close to I-type (intrinsic).

Note that the number of carriers in the highly purified oxide semiconductor is extremely small, and the carrier concentration is less than 1 × 10 ¹⁴ / cm ³ , preferably less than 1 × 10 ¹² / cm ³ , and more preferably 1 × 10 ¹¹ / am ^3. Less than. In addition, since the number of carriers is small in this manner, the current in the off state (off current) is sufficiently small.

Specifically, in the transistor including the above-described oxide semiconductor layer, the leakage current density (off-current density) per channel width of 1 μm between the source and the drain in the off state is 3. 5 V, under temperature conditions during use (for example, 25 ° C.), 100 zA / μm (1 × 10 ⁻¹⁹ A / μm) or less, or 10 zA / μm (1 × 10 ⁻²⁰ A / μm) or less, 1 zA / μm (1 × 10 ⁻²¹ A / μm) or less.

In addition, in a transistor including a highly purified oxide semiconductor layer, the temperature dependence of on-state current is hardly observed, and the off-state current remains very small even in a high temperature state.

First, the base film 103 is formed on the substrate 101.

As the base film, for example, any one of a silicon oxide film, a silicon oxynitride film, a silicon nitride film, a silicon nitride oxide film, an aluminum nitride film, and an aluminum nitride oxide film is formed as a single layer or a plurality of layers are stacked. Can be used.

In this embodiment, a thermal oxidation treatment (here, a silicon oxide film) is formed as the base film 103 by performing thermal oxidation treatment on the silicon substrate.

If the thermal oxide film formed on the back surface (the surface on which the transistor is not formed) of the substrate 101 is unnecessary, it may be removed by etching or polishing.

Note that in this specification, an oxynitride is a substance having a higher oxygen content than nitrogen as a composition, and a nitrided oxide is a nitrogen content higher than oxygen as a composition. A substance. For example, silicon oxynitride refers to oxygen of 50 atomic% to 70 atomic%, nitrogen of 0.5 atomic% to 15 atomic%, silicon of 25 atomic% to 35 atomic%, and hydrogen of 0.1 atomic% The substance can be contained in the range of 10 atomic% or less. In addition, silicon nitride oxide refers to oxygen of 5 atomic% to 35 atomic%, nitrogen of 20 atomic% to 55 atomic%, silicon of 25 atomic% to 35 atomic%, and hydrogen of 10 atomic% to 30 atomic%. The substance can be included in the following ranges. However, the range of the said composition is a thing when it measures using Rutherford backscattering method (RBS: Rutherford Backscattering Spectrometry) and the hydrogen forward scattering method (HFS: Hydrogen Forward Scattering). Further, the content ratio of the constituent elements takes a value that the total does not exceed 100 atomic%.

In particular, by using an insulating film with high barrier properties such as a silicon nitride film, a silicon nitride oxide film, an aluminum nitride film, or an aluminum nitride oxide film as the base film 103, impurities in an atmosphere such as moisture or hydrogen Alternatively, impurities such as alkali metal and heavy metal contained in the substrate 101 can be prevented from entering the oxide semiconductor layer 105.

Note that impurities such as alkali metals such as Li and Na and alkaline earth metals such as Ca contained in the oxide semiconductor are preferably reduced. Specifically, Na detected by SIMS is 5 × 10 ¹⁶ / cm ³ or less, preferably 1 × 10 ¹⁶ / cm ³ or less, more preferably 1 × 10 ¹⁵ / cm ³ or less, and Li is 5 × 10 5 or less. ^{It is 15} / cm ³ or less, preferably 1 × 10 ¹⁵ / cm ³ or less, and K is 5 × 10 ¹⁵ / cm ³ or less, preferably 1 × 10 ¹⁵ / cm ³ or less.

Alkali metals and alkaline earth metals are malignant impurities for oxide semiconductors, and fewer are better. In particular, among alkali metals, Na diffuses into an Na ⁺ when the insulating film in contact with the oxide semiconductor is an oxide. In addition, in the oxide semiconductor, a bond between a metal and oxygen is analyzed or interrupted during the bond. As a result, the transistor characteristics are deteriorated (for example, normally-on, threshold shift to negative). In addition, it causes variation in characteristics. Such a problem becomes significant particularly when the concentration of hydrogen in the oxide semiconductor is sufficiently low. Therefore, when the concentration of hydrogen in the oxide semiconductor is 5 × 10 ¹⁹ / cm ³ or less, particularly 5 × 10 ¹⁸ / cm ³ or less, the alkali metal concentration is strongly required to be the above value. .

Next, an oxide semiconductor film is formed over the base film 103 by a sputtering method using a target for forming an oxide semiconductor. The oxide semiconductor film can be formed by a sputtering method in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas (typically argon) and oxygen mixed atmosphere.

Note that before the oxide semiconductor film is formed by a sputtering method, reverse sputtering that generates plasma by introducing argon gas is performed, so that a powdery substance (also referred to as particles or dust) attached to the base film 103 is removed. It is preferable to remove. Reverse sputtering is a method for modifying the surface by forming a plasma near the substrate by applying a voltage to the substrate side using an RF power source in an argon atmosphere. Note that nitrogen, helium, oxygen, or the like may be used instead of the argon atmosphere. Alternatively, an argon atmosphere may be used in which oxygen, nitrous oxide, or the like is added. Alternatively, an argon atmosphere may be used in which chlorine, carbon tetrafluoride, or the like is added.

Examples of the oxide semiconductor used for the oxide semiconductor film include an In—Sn—Ga—Zn—O-based oxide semiconductor that is a quaternary metal oxide and an In—Ga—Zn— that is a ternary metal oxide. O-based oxide semiconductor, In-Sn-Zn-O-based oxide semiconductor, In-Al-Zn-O-based oxide semiconductor, Sn-Ga-Zn-O-based oxide semiconductor, Al-Ga-Zn-O-based Oxide semiconductors, Sn-Al-Zn-O-based and In-Zn-O-based oxide semiconductors that are binary metal oxides, Sn-Zn-O-based oxide semiconductors, Al-Zn-O-based oxides It is a semiconductor, a Zn-Mg-O-based oxide semiconductor, a Sn-Mg-O-based oxide semiconductor, an In-Mg-O-based oxide semiconductor, an In-Ga-O-based oxide semiconductor, or a unitary metal oxide. In-O oxide semiconductor, Sn-O oxide semiconductor, Zn-O oxide semiconductor It can be used an oxide semiconductor such. Further, silicon oxide may be included in the oxide semiconductor film. By including silicon oxide (SiOx (X> 0)) that inhibits crystallization in the oxide semiconductor film, crystallization is suppressed when heat treatment is performed after the formation of the oxide semiconductor layer in the manufacturing process. can do. Note that the oxide semiconductor layer is preferably in an amorphous state and may be partially crystallized. Here, for example, an In—Ga—Zn—O-based oxide semiconductor means an oxide film containing indium (In), gallium (Ga), and zinc (Zn), and there is no particular limitation on the composition ratio. . Moreover, elements other than In, Ga, and Zn may be included.

As the oxide semiconductor film, a thin film represented by InMO ₃ (ZnO) _m (m> 0) can be used. Here, M represents one or more metal elements selected from Ga, Al, Mn, and Co. For example, M includes Ga, Ga and Al, Ga and Mn, or Ga and Co.

The oxide semiconductor of this embodiment is preferably an oxide semiconductor containing In, and more preferably an oxide semiconductor containing In and Ga. Since the oxide semiconductor layer is i-type (intrinsic), dehydration or dehydrogenation is effective. In this embodiment, the oxide semiconductor film is formed by a sputtering method using an In—Ga—Zn—O-based oxide semiconductor target for film formation.

As an example of an In—Ga—Zn—O-based oxide semiconductor film formation target, an oxide semiconductor film formation target containing In, Ga, and Zn (composition ratio: In ₂ O ₃ : Ga ₂ O ₃ : ZnO = 1: 1: 1 [molar ratio]) or the like can also be used. As a target for forming an oxide semiconductor film containing In, Ga, and Zn, In ₂ O ₃ : Ga ₂ O ₃ : ZnO = 1: 1: 2 [molar ratio], or In ₂ O ₃ : Ga ₂ A target having a composition ratio of O ₃ : ZnO = 1: 1: 4 [molar ratio] can also be used. The filling rate of the oxide semiconductor target for film formation is 90% to 100%, preferably 95% to 99.9%. By using an oxide semiconductor target for film formation with a high filling rate, the formed oxide semiconductor film becomes a dense film.

The substrate is held in a processing chamber kept under reduced pressure, a sputtering gas from which hydrogen and moisture are removed is introduced while removing residual moisture in the processing chamber, and an oxide semiconductor film is formed on the substrate 101 using the target. Is deposited. In order to remove moisture remaining in the treatment chamber, an adsorption-type vacuum pump is preferably used. For example, it is preferable to use a cryopump, an ion pump, or a titanium sublimation pump. The exhaust means may be a turbo pump provided with a cold trap. In the film formation chamber evacuated using a cryopump, for example, a compound containing a hydrogen atom (more preferably a compound containing a carbon atom) such as a hydrogen atom or water (H ₂ O) is exhausted. The concentration of impurities contained in the oxide semiconductor film formed in the chamber can be reduced. Further, the substrate may be heated when the oxide semiconductor film is formed.

Next, the oxide semiconductor film is processed into an island-shaped oxide semiconductor layer 105 through a first photolithography step. (See FIG. 5A). Further, a resist mask for forming the island-shaped oxide semiconductor layer 105 may be formed by an inkjet method. When the resist mask is formed by an ink-jet method, a manufacturing cost can be reduced because a photomask is not used.

Note that the etching of the oxide semiconductor film here may be either dry etching or wet etching, or both.

As an etching gas used for dry etching, a gas containing chlorine (chlorine-based gas such as chlorine (Cl ₂ ), boron chloride (BCl ₃ ), silicon chloride (SiCl ₄ ), carbon tetrachloride (CCl ₄ ), or the like) is preferable. .

In addition, a gas containing fluorine (fluorine-based gas such as carbon tetrafluoride (CF ₄ ), sulfur fluoride (SF ₆ ), nitrogen fluoride (NF ₃ ), trifluoromethane (CHF ₃ ), etc.), hydrogen bromide ( HBr), oxygen (O ₂ ), a gas obtained by adding a rare gas such as helium (He) or argon (Ar) to these gases, or the like can be used.

As the dry etching method, a parallel plate RIE (Reactive Ion Etching) method or an ICP (Inductively Coupled Plasma) etching method can be used.

As an etchant used for wet etching, a mixed solution of phosphoric acid, acetic acid, and nitric acid, or the like can be used. In addition, ITO07N (manufactured by Kanto Chemical Co., Inc.) may be used.

In addition, the etchant after the wet etching is removed by cleaning together with the etched material. The waste solution of the etching solution containing the removed material may be purified and the contained material may be reused. By recovering and reusing materials such as indium contained in the oxide semiconductor layer from the waste liquid after the etching, resources can be effectively used and costs can be reduced.

Etching conditions (such as an etchant, etching time, and temperature) are adjusted as appropriate depending on the material so that the material can be etched into a desired shape.

In this embodiment, the oxide semiconductor film is processed into the island-shaped oxide semiconductor layer 105 by a wet etching method using a mixed solution of phosphoric acid, acetic acid, and nitric acid as an etchant.

Next, first heat treatment is performed on the oxide semiconductor layer 105. The oxide semiconductor layer 105 is subjected to heat treatment in an atmosphere of oxygen, nitrogen, ultra-dry air (air with a water content of 20 ppm or less, preferably 1 ppm or less, preferably 10 ppb or less), or a rare gas (such as argon or helium). By applying, the oxide semiconductor layer 105 from which moisture and hydrogen are released is formed. The temperature of the first heat treatment is 250 ° C. or higher and 750 ° C. or lower, or 400 ° C. or higher and lower than the strain point of the substrate. For example, it may be performed at 500 ° C. for about 3 minutes to 6 minutes. When the RTA method is used for the heat treatment, dehydration or dehydrogenation can be performed in a short time, and thus the treatment can be performed at a temperature exceeding the strain point of the substrate.

Note that the heat treatment apparatus is not limited to an electric furnace, and may include a device for heating an object to be processed by heat conduction or heat radiation from a heating element such as a resistance heating element. For example, a rapid thermal annealing (RTA) apparatus such as a GRTA apparatus (Gas Rapid Thermal Anneal) apparatus or an LRTA (Lamp Rapid Thermal Anneal) apparatus can be used. The LRTA apparatus is an apparatus that heats an object to be processed by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, or a high pressure mercury lamp. The GRTA apparatus is an apparatus that performs heat treatment using a high-temperature gas. As the gas, an inert gas that does not react with an object to be processed by heat treatment, such as nitrogen or a rare gas such as argon, is used.

For example, as the first heat treatment, the substrate is moved into an inert gas heated to a high temperature of 650 ° C. to 700 ° C., heated for several minutes, and then moved to a high temperature by moving the substrate to a high temperature. GRTA may be performed from When GRTA is used, high-temperature heat treatment can be performed in a short time.

Note that in the first heat treatment, it is preferable that water, hydrogen, or the like be not contained in nitrogen or a rare gas such as helium, neon, or argon. Alternatively, the purity of nitrogen or a rare gas such as helium, neon, or argon introduced into the heat treatment apparatus is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (that is, the impurity concentration is 1 ppm). Or less, preferably 0.1 ppm or less).

In addition, after the oxide semiconductor layer is heated by the first heat treatment, high purity oxygen gas, high purity N ₂ O gas, or ultra dry air (CRDS (cavity ring down laser spectroscopy) method) is used in the same furnace. The amount of water measured using a dew point meter may be 20 ppm (air at dew point conversion of −55 ° C.) or less, preferably 1 ppm or less, preferably 10 ppb or less. It is preferable that water, hydrogen, and the like are not contained in the oxygen gas or N ₂ O gas. Alternatively, the purity of the oxygen gas or N ₂ O gas introduced into the heat treatment apparatus is 6 N or more, preferably 7 N or more (that is, the impurity concentration in the oxygen gas or N ₂ O gas is 1 ppm or less, preferably 0.1 ppm or less). It is preferable that By supplying oxygen, which is a main component material of the oxide semiconductor, which is simultaneously reduced by the impurity removal step by dehydration or dehydrogenation treatment by the action of oxygen gas or N ₂ O gas, the oxide The semiconductor layer is highly purified and electrically made I-type (intrinsic).

The first heat treatment of the oxide semiconductor layer can be performed on the oxide semiconductor film before being processed into the island-shaped oxide semiconductor layer. In that case, after the first heat treatment, the substrate is taken out of the heating apparatus and a photolithography process is performed.

The heat treatment that exerts the effects of dehydration and dehydrogenation on the oxide semiconductor layer 105 is performed by stacking the source electrode layer 106 and the drain electrode layer 107 over the oxide semiconductor layer 105 after forming the oxide semiconductor layer. After the gate insulating layer 109 is formed over the source electrode layer and the drain electrode layer, this may be performed.

Through the above steps, the concentration of hydrogen in the island-shaped oxide semiconductor layer can be reduced and high purity can be achieved. Accordingly, stabilization of the oxide semiconductor layer can be achieved. In addition, an oxide semiconductor layer with an extremely low carrier density and a wide band gap can be formed by heat treatment at a temperature lower than or equal to the glass transition temperature. Therefore, a transistor can be manufactured using a large-area substrate, and mass productivity can be improved. In addition, by using the highly purified oxide semiconductor layer with reduced hydrogen concentration, a transistor with high withstand voltage and extremely low off-state current can be manufactured. The heat treatment can be performed at any time after the oxide semiconductor film is formed.

Note that in the case of heating an oxide semiconductor film, a plate-like crystal may be formed on the surface of the oxide semiconductor film, depending on a material of the oxide semiconductor film and heating conditions. The plate-like crystal is preferably a single crystal having a c-axis orientation substantially perpendicular to the surface of the oxide semiconductor film. Note that in the case where the surface of the base film under the oxide semiconductor film has unevenness, the plate-like crystal becomes a polycrystalline body. Therefore, it is desirable that the underlying surface be as flat as possible.

In addition, the oxide semiconductor layer is formed in two steps, and the heat treatment is performed in two steps, so that the material of the base member can be formed regardless of the material such as oxide, nitride, or metal. An oxide semiconductor layer having a thick crystal region (single crystal region), that is, a c-axis aligned crystal region perpendicular to the film surface may be formed. For example, a first oxide semiconductor film with a thickness of 3 nm to 15 nm is formed and 450 ° C. to 850 ° C., preferably 550 ° C. to 750 ° C. in an atmosphere of nitrogen, oxygen, a rare gas, or dry air. 1 is performed, so that a first oxide semiconductor film having a crystal region (including a plate crystal) in a region including the surface is formed. Then, a second oxide semiconductor film thicker than the first oxide semiconductor film is formed, and a second heat treatment is performed at 450 ° C. to 850 ° C., preferably 600 ° C. to 700 ° C., Even if an oxide semiconductor film is used as a seed for crystal growth, crystal growth is performed upward, the entire second oxide semiconductor film is crystallized, and as a result, an oxide semiconductor layer having a thick crystal region is formed. Good.

Next, a conductive film to be the source electrode layer 106 and the drain electrode layer 107 is formed over the oxide semiconductor layer 105. As a material for the conductive film to be a source electrode and a drain electrode, an element selected from Al, Cr, Cu, Ta, Ti, Mo, W, an alloy containing the above elements as a component, or a combination of the above elements Alloy films and the like. Alternatively, a high melting point metal film such as Cr, Ta, Ti, Mo, or W may be laminated below or above the metal film such as Al or Cu. Moreover, heat resistance is improved by using an Al material to which an element for preventing generation of hillocks and whiskers generated in an Al film such as Si, Ti, Ta, W, Mo, Cr, Nd, Sc, and Y is added. Is possible.

The conductive film may have a single-layer structure or a stacked structure including two or more layers. For example, a single layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is laminated on an aluminum film, a titanium film, an aluminum film laminated on the titanium film, and a titanium film formed on the titanium film. Examples include a three-layer structure that forms a film.

The conductive film may be formed using a conductive metal oxide. Examples of the conductive metal oxide include indium oxide (In ₂ O ₃ ), tin oxide (SnO ₂ ), zinc oxide (ZnO), indium oxide tin oxide alloy (In ₂ O ₃ —SnO ₂ , abbreviated as ITO), An indium oxide-zinc oxide alloy (In ₂ O ₃ —ZnO) or a metal oxide material containing silicon or silicon oxide can be used.

In the case where heat treatment is performed after formation of the conductive film, it is preferable that the conductive film have heat resistance enough to withstand the heat treatment.

Next, a resist mask is formed over the conductive film by a second photolithography step, and selective etching is performed to form the source electrode layer 106 and the drain electrode layer 107, and then the resist mask is removed. (See FIG. 5B).

Ultraviolet, KrF laser light, or ArF laser light is used for light exposure for forming the resist mask in the second photolithography process. The channel length L of a transistor to be formed later is determined by the gap width between the lower end portion of the source electrode layer adjacent to the oxide semiconductor layer 105 and the lower end portion of the drain electrode layer. Note that in the case of performing exposure with a channel length L of less than 25 nm, it is preferable to perform exposure when forming a resist mask in a photolithography process using extreme ultraviolet (Extreme Ultraviolet) having an extremely short wavelength of several nm to several tens of nm. . Exposure by extreme ultraviolet light has a high resolution and a large depth of focus. Therefore, the channel length L of a transistor to be formed later can be 10 nm to 1000 nm, the operation speed of the circuit can be increased and the off-state current is extremely small, so that low power consumption can be achieved.

Note that each material and etching conditions are adjusted as appropriate so that the oxide semiconductor layer 105 is not removed as much as possible when the conductive film is etched.

In this embodiment mode, a titanium film is used as the conductive film, and the conductive film is wet-etched using ammonia overwater (31 wt% hydrogen peroxide solution: 28 wt% ammonia water: water = 5: 2: 2). Thus, the source and drain electrode layers 107 are formed. Alternatively, the conductive film may be dry-etched using a gas containing chlorine (Cl ₂ ), boron chloride (BCl ₃ ), or the like.

When the source electrode layer 106 and the drain electrode layer 107 are formed by the above patterning, a part of the exposed portion of the island-shaped oxide semiconductor layer 105 is etched, whereby a groove ( (Concave part) may be formed. Further, a resist mask for forming the source electrode layer 106 and the drain electrode layer 107 may be formed by an inkjet method. When the resist mask is formed by an ink-jet method, a manufacturing cost can be reduced because a photomask is not used.

In addition, in order to reduce the number of photomasks used in the photolithography process and the number of processes, the etching process may be performed using a resist mask formed by a multi-tone mask that gives transmitted light multistage intensity. A resist mask formed using a multi-tone mask has a shape with a plurality of thicknesses, and the shape can be further changed by etching. Therefore, the resist mask can be used for a plurality of etching steps for processing into different patterns. Therefore, a resist mask corresponding to at least two different patterns can be formed by using one multi-tone mask. Therefore, the number of exposure masks can be reduced, and the corresponding photolithography process can be reduced, so that the process can be simplified.

Next, plasma treatment using a gas such as N ₂ O, N ₂ , or Ar may be performed. Adsorbed water or the like attached to the surface of the oxide semiconductor layer 105 exposed by this plasma treatment is removed. Further, plasma treatment may be performed using a mixed gas of oxygen and argon.

Next, the gate insulating layer 109 is formed. The gate insulating layer 109 is formed by a single layer or a stack of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, a hafnium oxide layer, a tantalum oxide layer, or an aluminum oxide layer by a sputtering method or the like. Can be formed. Note that the gate insulating layer 109 is preferably formed by a sputtering method so that the gate insulating layer 109 does not contain a large amount of hydrogen. In the case of forming a silicon oxide film by a sputtering method, a silicon target or a quartz target is used as a target, and oxygen or a mixed gas of oxygen and argon is used as a sputtering gas.

An oxide semiconductor adversely affects characteristics when hydrogen is contained. Therefore, it is preferable that the gate insulating layer 109 in contact with the oxide semiconductor layer 105 contain as little impurities as possible such as hydrogen and oxygen. In the case of forming a silicon oxynitride film by a sputtering method, a silicon target or a quartz target is used as a target, and oxygen or a mixed gas of oxygen and argon is used as a sputtering gas.

As the oxide semiconductor of this embodiment, an oxide semiconductor (a highly purified oxide semiconductor) that is i-type or substantially i-type by removing impurities is used. Since such a highly purified oxide semiconductor is extremely sensitive to interface states and interface charges, the interface with the gate insulating layer 109 is important. Therefore, the gate insulating layer (GI) in contact with the highly purified oxide semiconductor is required to have high quality.

The gate insulating layer 109 may have a structure in which an insulating layer using a material having a high barrier property and an insulating film such as a silicon oxide film or a silicon oxynitride film with a low ratio of nitrogen contained are stacked. In this case, an insulating film such as a silicon oxide film or a silicon oxynitride film is formed between the insulating film having a barrier property and the oxide semiconductor layer. Examples of the insulating film having a high barrier property include a silicon nitride film, a silicon nitride oxide film, an aluminum nitride film, and an aluminum nitride oxide film. By using an insulating film having a barrier property, impurities in an atmosphere such as moisture or hydrogen, or impurities such as alkali metals and heavy metals contained in the substrate are formed in the oxide semiconductor layer, the gate insulating layer 109, and the like. It is possible to prevent entry into the vicinity. In addition, by forming an insulating film such as a silicon oxide film or a silicon oxynitride film with a low content of nitrogen so as to be in contact with the oxide semiconductor layer, the insulating film using a material having a high barrier property can be directly oxidized. The contact with the semiconductor layer can be prevented.

Note that second heat treatment may be performed after the gate insulating layer 109 is formed. The heat treatment is preferably performed at 200 ° C. or higher and 400 ° C. or lower (for example, 250 ° C. or lower and 350 ° C. or lower) in an atmosphere of nitrogen, ultra-dry air, or a rare gas (such as argon or helium). The gas should have a water content of 20 ppm or less, preferably 1 ppm or less, preferably 10 ppb or less. For example, heat treatment is performed at 250 ° C. for 1 hour in a nitrogen atmosphere. Alternatively, high temperature and short time RTA treatment may be performed as in the first heat treatment. By performing heat treatment after the gate insulating layer 109 containing oxygen is buried, even if oxygen vacancies are generated in the oxide semiconductor layer 105 by the first heat treatment, oxidation is performed from the gate insulating layer 109. Oxygen is supplied to the physical semiconductor layer 105. By supplying oxygen to the oxide semiconductor layer 105, oxygen vacancies serving as donors in the oxide semiconductor layer 105 can be reduced and the stoichiometric ratio can be satisfied. As a result, the oxide semiconductor layer 105 can be made closer to an I-type, variation in electrical characteristics of the transistor due to oxygen vacancies can be reduced, and electrical characteristics can be improved. The timing for performing the second heat treatment is not particularly limited as long as it is after the gate insulating layer 109 is formed.

Alternatively, oxygen vacancies serving as donors in the oxide semiconductor layer 105 may be reduced by performing heat treatment on the oxide semiconductor layer 105 in an oxygen atmosphere so that oxygen is added to the oxide semiconductor. The temperature of the heat treatment is, for example, 100 ° C. or higher and lower than 350 ° C., preferably 150 ° C. or higher and lower than 250 ° C. It is preferable that the oxygen gas used for the heat treatment under the oxygen atmosphere does not contain water, hydrogen, or the like. Alternatively, the purity of the oxygen gas introduced into the heat treatment apparatus is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (that is, the impurity concentration in oxygen is 1 ppm or less, preferably 0.1 ppm). Or less).

In this embodiment, second heat treatment (preferably 200 ° C. to 400 ° C., for example, 250 ° C. to 350 ° C.) is performed in an inert gas atmosphere or an oxygen gas atmosphere. For example, the second heat treatment is performed at 250 ° C. for 1 hour in a nitrogen atmosphere. When the second heat treatment is performed, part of the oxide semiconductor layer (a channel formation region) is heated in contact with the gate insulating layer 109.

Next, an opening reaching the top surfaces of the source electrode layer 106 and the drain electrode layer 107 is formed in the gate insulating layer 109 (see FIG. 5C). For example, the opening can be formed by performing the third photolithography step and etching the gate insulating layer 109. As the etching, either wet etching or dry etching may be used. From the viewpoint of fine processing, it is preferable to use dry etching.

Next, a conductive film is formed so as to fill the opening and cover the gate insulating layer 109. The conductive film can be formed using a film formation method such as a PVD method or a CVD method. As a material for the conductive film, a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, neodymium, or scandium, a conductive film using an alloy material containing these metal materials as a main component, or a nitride of these metals is used. Can do.

After the conductive film is formed, part of the conductive film is removed by a method such as etching, so that the source wiring 116 and the drain wiring 117 that are electrically connected to the gate electrode layer 111, the source electrode layer 106, and the drain electrode layer 107 are manufactured. (See FIG. 5D).

Note that a source wiring refers to a wiring for connecting at least one source electrode to another electrode.

Next, a protective insulating layer 113 is formed to cover the gate insulating layer 109, the gate electrode layer 111, the source wiring 116, and the drain wiring 117 (see FIG. 5E). As the protective insulating layer 113, for example, a silicon nitride film is formed using an RF sputtering method. The RF sputtering method is preferable as a method for forming the protective insulating layer because of its high productivity. As the protective insulating layer, an inorganic insulating film that does not contain impurities such as moisture and blocks entry of these from the outside is used, and a silicon nitride film, an aluminum nitride film, or the like is used. In this embodiment, the protective insulating layer 113 is formed using a silicon nitride film.

In this embodiment, as the protective insulating layer 113, the substrate 101 formed up to the gate electrode layer 111 is heated from 100 ° C. to 400 ° C., and a sputtering gas containing high-purity nitrogen from which hydrogen and moisture are removed is used. Then, a silicon nitride film is formed using a silicon semiconductor target. Even in this case, it is preferable to form the protective insulating layer 113 while removing residual moisture in the treatment chamber.

Through the above process, the transistor described in this embodiment is formed.

In the transistor of this embodiment, an oxide semiconductor is used for a semiconductor layer; therefore, a high current can be controlled with a high breakdown voltage. Therefore, it is suitable for a transistor used in a power device that handles a large current.

Note that this embodiment can be combined with any of the other embodiments described in this specification as appropriate.

(Embodiment 4)
In this embodiment mode, a voltage conversion circuit (DC-DC converter) which is an example of a semiconductor device of the present invention is described.

A converter circuit 301 illustrated in FIG. 6A is a booster circuit including a transistor 302, a coil 303, a diode 304, a capacitor 305, and a DC power supply 306.

Note that in this embodiment, the semiconductor element of one embodiment of the present invention can be used as the transistor 302 or the transistor 312, for example.

One terminal of the coil 303 is electrically connected to the anode of the DC power supply 306. The other terminal of the coil 303 is electrically connected to one of a source and a drain of the transistor 302. The other of the source and the drain of the transistor 302 is electrically connected to the cathode of the DC power supply 306 and one terminal of the capacitor 305. The other terminal of the capacitor 305 is electrically connected to the output terminal of the diode 304 and the output terminal OUT. Note that the cathode of the DC power supply 306, the other of the source and drain of the transistor 302, and one terminal of the capacitor 305 are grounded.

The transistor 302 functions as a switching element. The gate of the transistor 302 is connected to the control circuit of the converter circuit 301. The transistor 302 is turned on or off depending on a signal from the control circuit of the converter circuit 301.

When the transistor 302 that is a switching element is in an ON state, excitation energy is stored in the coil 303 by a current flowing into the coil 303.

When the transistor 302 is turned off, the excitation energy stored in the coil 303 is released. The voltage V2 resulting from the excitation energy released from the coil 303 is added to the voltage V1. Thereby, the converter circuit 301 functions as a booster circuit.

The longer the time during which the transistor 302 is on and the larger the energy stored in the coil 303, the larger power can be extracted.

A converter circuit 311 illustrated in FIG. 6B is a step-down circuit including a transistor 312, a coil 313, a diode 314, and a capacitor 315.

One of the source and the drain of the transistor 312 is electrically connected to the anode of the DC power supply 316. The other of the source and the drain of the transistor 312 is electrically connected to the output terminal of the diode 314 and one terminal of the coil 313. The input terminal of the diode 314 is electrically connected to the cathode of the DC power supply 316 and one terminal of the capacitor 315. An output terminal of the diode is electrically connected to the other of the source and the drain of the transistor 312 and one terminal of the coil 313. One terminal of the coil 313 is electrically connected to the other of the source and the drain of the transistor 312 and the output terminal of the diode 314. The other terminal of the coil 313 is electrically connected to the other terminal of the capacitor 315 and the output terminal OUT. Note that the cathode of the DC power supply 316, the input terminal of the diode 314, and one terminal of the capacitor 315 are grounded.

The transistor 312 functions as a switching element. The gate of the transistor 312 is connected to the control circuit of the converter circuit 311. The transistor 312 is turned on or off depending on a signal from the control circuit of the converter circuit 311.

When the transistor 312 which is a switching element is in an on state, excitation energy is stored in the coil 313 by the current of the step-down circuit flowing from the input to the output.

When the transistor 312 is turned off, the coil 313 generates an electromotive force in an attempt to maintain current, and the diode 314 is turned on. As a current flows through the diode 314, the voltage V2 decreases. Since the voltage V2 is lower than the voltage V1, the converter circuit 311 functions as a step-down circuit. Note that in this embodiment, for example, a field-effect transistor can be used as the transistor 312.

In this embodiment, as the coil 303 and the coil 313, wiring formed in a coil shape over a substrate can be used.

In this embodiment, for example, a Schottky barrier diode can be used as the diode 304 and the diode 314.

In this embodiment, as the capacitor 305 and the capacitor 315, for example, a capacitor having a first electrode, a second electrode, and a dielectric can be used.

The semiconductor element described in one embodiment of the present invention has a characteristic that a high current can be controlled with a high breakdown voltage because an oxide semiconductor is used for a semiconductor layer. Therefore, a circuit capable of driving a large current can be manufactured by using the voltage conversion circuit described in this embodiment mode.

In the semiconductor element described in one embodiment of the present invention, transistors are connected in parallel by through electrodes, so that a substantial W length of the transistor can be increased, and a high mobility semiconductor element suitable for a power device Can provide. Therefore, the driving speed of the circuit is increased by using the voltage conversion circuit shown in this embodiment mode.

Further, this embodiment can be freely combined with any of the other embodiments.

100 Semiconductor chip 100a Semiconductor chip 100b Semiconductor chip 101 Substrate 101a Substrate 103 Base film 103a Base film 105 Oxide semiconductor layer 105a Oxide semiconductor layer 106 Source electrode layer 106a Source electrode layer 107 Drain electrode layer 107a Drain electrode layer 109 Gate insulating layer 109a Gate insulating layer 111 Gate electrode layer 111a Gate electrode layer 113 Protective insulating layer 113a Protective insulating layer 115 Protective layer 116 Source wiring 116a Source wiring 117 Drain wiring 117a Drain wiring 120a Through electrode 121a Through electrode 122 Through electrode 122a Through electrode 130a Transistor 130b Transistor 200 Via 201 Insulating film 203 Conductive barrier film 205 Wiring 207 Conductor 301 Converter circuit 302 Transistor 303 Coil 3 4 the diode 305 the capacitor 306 DC power supply 311 converter circuit 312 transistor 313 coil 314 diode 315 capacitor 316 DC power supply

Claims (6)

A first substrate having a first transistor using an oxide semiconductor for a semiconductor layer, and three through electrodes electrically connected to the gate electrode layer, the source electrode layer, and the drain electrode layer of the first transistor, respectively When,
A second substrate having a second transistor using an oxide semiconductor for a semiconductor layer, and three through electrodes electrically connected to the gate electrode layer, the source electrode layer, and the drain electrode layer of the second transistor, respectively And stacking,
The semiconductor element in which the first transistor and the second transistor are electrically connected in parallel through respective through electrodes. The semiconductor element according to claim 1, wherein the oxide semiconductor has a band gap of 3 eV or more. The semiconductor element according to claim 1, wherein the first substrate and the second substrate are silicon substrates. 4. The semiconductor device according to claim 1, wherein the first substrate and the second substrate are insulating substrates. 5. The semiconductor device using the semiconductor element as described in any one of Claims 1 thru | or 4. Forming a first transistor in a first region of the substrate and a second transistor in a second region of the substrate;
Three through electrodes that are electrically connected to the gate electrode layer, the source electrode layer, and the drain electrode layer of the first transistor, respectively, are formed in the first region, and the gate electrode layer, the source electrode layer, and the second transistor of the second transistor Three through electrodes that are respectively electrically connected to the drain electrode layer are formed in the second region,
Forming a first semiconductor chip having the first region and a second semiconductor chip having the second region by dividing the substrate;
Laminating the first semiconductor chip and the second semiconductor chip;
A method for manufacturing a semiconductor device, comprising: a second step of electrically connecting the first transistor and the second transistor in parallel through the through electrode.

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