JP2012059880A - Method of manufacturing semiconductor device - Google Patents

Abstract

A semiconductor device manufacturing method capable of optimizing MOS transistors in both a memory cell region and a peripheral circuit region is provided.
A method of manufacturing a semiconductor device according to the present invention includes a MOS transistor including a gate electrode having a sidewall on a side wall in a memory cell region and a peripheral circuit region on a semiconductor substrate. And forming a silicon layer 10 on the upper surface of the semiconductor substrate 1 by selective epitaxial growth after forming the sidewalls, and after forming the silicon layer 10, at least the peripheral circuit region is covered with a mask 20b. Then, a step of thinning the sidewall 9c of the MOS transistor Tr1 in the memory cell region by etching is employed.
[Selection] Figure 7

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  In recent years, large-scale integrated circuits (hereinafter referred to as LSIs) in which a large number of MOS transistors are integrated on a single semiconductor chip have been adopted as main parts of computers and electrical equipment. In addition, among LSIs, for example, with the rapid miniaturization of elements such as DRAM (Dynamic Random Access Memory), the gate length of a MOS transistor is becoming shorter. Also, by integrating a large number of MOS transistors in the memory cell region, the distance between adjacent MOS transistors can be shortened. On the other hand, the shorter the gate length, the more problematic the transistor characteristics deteriorate due to the short channel effect of the MOS transistor.

  As one means for suppressing the short channel effect of such a MOS transistor, a silicon layer made of an epitaxial growth layer is formed on the impurity diffusion region of the MOS transistor, and the gate is formed by diffusing the impurity into the silicon layer. A method for preventing the reduction in length is known (Patent Document 1). An outline of this method will be described below with reference to FIGS.

  First, as shown in FIG. 10, gate electrodes (first gate electrode 6a and second gate electrode 6b) are formed in the memory cell region and the peripheral circuit region of the semiconductor substrate 1, respectively. Note that the memory cell region is a region where a memory element and a selection transistor (MOS transistor) are arranged, and the peripheral circuit region is a drive circuit for the selection transistor and amplification of data output from the memory element in the memory cell region. This is the area where the circuit is placed.

  First, element isolation 2 is formed on one surface of a semiconductor substrate 1 made of P-type single crystal silicon by the STI method. Next, one surface of the semiconductor substrate 1 is oxidized to form a gate insulating film 3. Next, a conductive film is formed on the gate insulating film 3 by sequentially depositing, for example, a polycrystalline silicon film containing an N-type impurity and a metal film. Next, an insulating film made of silicon nitride is formed over the conductive film. Next, the insulating film and the conductive film are etched to form a first gate electrode 6a including the first conductive film 4a and the first insulating film 5a in the memory cell region, and a second gate electrode in the peripheral circuit region. A second gate electrode 6b composed of the conductive film 4b and the second insulating film 5b is formed.

  Next, ion implantation of N-type impurities is performed on one surface of the semiconductor substrate 1 in the peripheral circuit region using the second gate electrode 6b as a mask to form a low-concentration impurity diffusion region 7. Next, a third insulating film 9 made of silicon nitride is formed so as to cover the first gate electrode 6a, the second gate electrode 6b, and the gate insulating film 3 by a CVD method.

  Next, as shown in FIG. 11, a first MOS transistor Tr1 and a second MOS transistor Tr2 are formed. First, the third insulating film 9 and the gate insulating film 3 are etched back, and the sidewalls (first sidewall 9a, first gate electrode 6a, second gate electrode 6b) are respectively formed on the sidewalls of the gate electrodes (first gate electrode 6a, second gate electrode 6b). A second sidewall 9b) is formed. Next, selective epitaxial growth is performed using the first sidewall 9a and the second sidewall 9b as a selection mask. Thereby, the first silicon layer 10a and the second silicon layer 10b are formed in the memory cell region and the peripheral circuit region of the semiconductor substrate 1, respectively.

  Next, using the gate electrodes (first gate electrode 6a, second gate electrode 6b) and sidewalls (first sidewall 9a, second sidewall 9b) as masks, the first silicon layer 10a and the second For example, N-type impurities such as arsenic are ion-implanted into the second silicon layer 10b. Thereafter, N-type impurities are thermally diffused to form a first impurity diffusion region 11 and a second impurity diffusion region 12 in the memory cell region and the peripheral circuit region of the semiconductor substrate 1, respectively. As described above, the source region and the drain region, which are partially stacked on the semiconductor substrate 1, are formed. Thereafter, contact plugs (not shown) are formed between the first sidewalls 9a of the adjacent first gate electrodes 6a by self-alignment using the first sidewalls 9a.

JP 2008-130756 A

  However, in the method of Patent Document 1, although reduction of the gate length is prevented, reduction of the diameter of the contact plug due to reduction of the distance D between the adjacent first MOS transistors Tr1 (first sidewalls 9a) is suppressed. I can't. Therefore, by integrating a large number of MOS transistors in the memory cell region, the diameter (width D) of the contact plug formed between the first sidewalls 9a is reduced. For this reason, the connection resistance of the contact plug increases.

On the other hand, as a method of suppressing an increase in connection resistance of the contact plug, a method of reducing the film thickness of the first sidewall 9a and maintaining the width D can be considered. However, since the first sidewall 9a is formed simultaneously with the second sidewall 9b, the first sidewall 9a and the second sidewall 9b are formed with the same film thickness. Therefore, if the first sidewall 9a is thinned, the film thickness of the second sidewall 9b is also thinned, and the short channel effect of the second MOS transistor Tr2 cannot be suppressed. Therefore, there is a problem in that the electrical characteristics of the second MOS transistor Tr2 are likely to be adversely affected and the semiconductor characteristics are deteriorated.
Thus, it has been difficult to optimize the MOS transistors (first MOS transistor Tr1 and second MOS transistor Tr2) in both the memory cell region and the peripheral circuit region.

  In order to solve the above problems, the present invention employs the following configuration. That is, the method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device including a MOS transistor including a gate electrode having a sidewall on a side wall in a memory cell region and a peripheral circuit region on a semiconductor substrate, A step of forming a silicon layer on the upper surface of the semiconductor substrate by a selective epitaxial growth method after forming the sidewall; and after forming the silicon layer, at least the peripheral circuit region is covered with a mask, and the memory cell is formed by etching. The method includes a step of thinning a sidewall of the MOS transistor in the region.

According to the method for manufacturing a semiconductor device of the present invention, at least the peripheral circuit region is covered with a mask and etched, so that the MOS film in the memory cell region is not changed without changing the thickness of the sidewall of the MOS transistor in the peripheral circuit region. The sidewall of the transistor can be thinned. For this reason, it is possible to suppress a reduction in the interval between the sidewalls of the adjacent MOS transistors in the memory cell region. Therefore, a contact plug having a sufficiently large diameter can be formed between adjacent MOS transistors in the memory cell region. For this reason, the connection resistance of the contact plug can be suppressed. Further, since the thickness of the sidewall of the MOS transistor in the peripheral circuit region is not changed, it is possible to prevent the MOS transistor in the peripheral circuit region from being shortened and the electrical characteristics from being deteriorated.
Further, by forming a silicon layer on the upper surface of the semiconductor substrate, impurities can be diffused into the silicon layer to form source / drain electrodes of the MOS transistor. For this reason, it is possible to prevent impurities from spreading too much into the semiconductor substrate, and it is possible to prevent the distance between adjacent source / drain electrodes from being reduced. In addition, since a part of the source / drain electrodes can be stacked on the semiconductor substrate, the short channel effect of the semiconductor device can be suppressed.
As described above, optimization of the MOS transistors in both the memory cell region and the peripheral circuit region can be realized. In addition, since the interval between the first MOS transistors can be reduced, miniaturization of the semiconductor device can be realized.

FIG. 1 is a cross-sectional process diagram illustrating a method of manufacturing a semiconductor device according to the present invention. FIG. 2 is a cross-sectional process diagram illustrating a method for manufacturing a semiconductor device according to the present invention. FIG. 3 is a cross-sectional process diagram illustrating a method for manufacturing a semiconductor device according to the present invention. FIG. 4 is a cross-sectional process diagram illustrating a method of manufacturing a semiconductor device according to the present invention. FIG. 5 is a cross-sectional process diagram illustrating a method of manufacturing a semiconductor device according to the present invention. FIG. 6 is a cross-sectional process diagram illustrating a method of manufacturing a semiconductor device according to the present invention. FIG. 7 is a cross-sectional process diagram illustrating a method of manufacturing a semiconductor device according to the present invention. FIG. 8 is a cross-sectional process diagram illustrating a method for manufacturing a semiconductor device according to the present invention. FIG. 9 is a cross-sectional process diagram illustrating a method of manufacturing a semiconductor device according to the present invention. FIG. 10 is a cross-sectional process diagram illustrating a conventional method of manufacturing a semiconductor device. FIG. 11 is a cross-sectional process diagram illustrating a conventional method of manufacturing a semiconductor device.

  Hereinafter, an example of a method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described with reference to the drawings. Note that the drawings referred to in the following description may show the features that are enlarged for convenience in order to make the features easier to understand, and the dimensional ratios of the respective components are not always the same as the actual ones. Absent. In addition, the raw materials, dimensions, and the like exemplified in the following description are merely examples, and the present invention is not limited to these, and can be appropriately modified and implemented without changing the gist thereof.

  The manufacturing method of the semiconductor device of this embodiment includes a step of forming MOS transistors (first MOS transistor Tr1, second MOS transistor Tr2), a step of covering the peripheral circuit region with a mask, and a MOS transistor in the memory cell region. This is roughly composed of a step of thinning the sidewall (first sidewall 9a) of the (first MOS transistor Tr1) and a step of forming the contact plug 22.

  First, as shown in FIG. 1, a first gate electrode 6a is formed in the memory cell region of the semiconductor substrate 1, and a second gate electrode 6b is formed in the peripheral circuit region. The memory cell region is a region where the storage element and the selection transistor (first MOS transistor Tr1) are arranged, and the peripheral circuit region is a drive circuit for the first MOS transistor Tr1 and a memory cell region storage. This is a region where an amplifier circuit for data output from the element is arranged.

First, a semiconductor substrate 1 made of a semiconductor containing a predetermined concentration of P-type impurities, such as silicon (Si), is prepared. Next, an element isolation 2 is formed by embedding an insulating film made of a silicon oxide film (SiO ₂ ) or the like on the surface of the semiconductor substrate 1 by STI (Shallow Trench Isolation). The memory cell region and the peripheral circuit region are electrically partitioned by element isolation 2.
Next, a gate insulating film 3 made of, for example, a 4 nm-thickness silicon oxide (SiO ₂ ) film is formed by thermal oxidation so as to cover the semiconductor substrate 1 and the element isolation 2.

Next, a gate insulating film 3 is covered by a CVD method using monosilane (SiH ₄ ) and phosphine (PH ₃ ) as a source gas for a polycrystalline silicon film having a thickness of 70 nm containing an N-type impurity such as phosphorus. To form. Next, a metal film having a thickness of 50 nm made of a refractory metal such as tungsten, tungsten nitride or tungsten silicide is laminated on the polycrystalline silicon film by sputtering. Thus, a conductive film made of a stacked body of the polycrystalline silicon film and the metal film is formed.

Next, an insulating film having a thickness of 70 nm made of silicon nitride (Si ₃ N ₄ ) or the like is formed so as to cover the conductive film by a CVD method using monosilane and ammonia (NH ₃ ) as source gases.

  Next, after applying a resist (not shown) on the insulating film, a photoresist pattern for forming gate electrodes (first gate electrode 6a and second gate electrode 6b) is formed by photolithography. Next, a first insulating film 5a and a second insulating film 5b made of the insulating film are formed by anisotropic etching using the photoresist pattern as a mask.

Next, the photoresist pattern is removed. Next, etching is performed using the first insulating film 5a and the second insulating film 5b as masks to form a first conductive film 4a and a second conductive film 4b made of the conductive film.
As described above, the first gate electrode 6a made of the first conductive film 4a and the first insulating film 5a is formed in the memory cell region, and the second gate electrode made of the second conductive film 4b and the second insulating film 5b. Gate electrode 6b is formed in the peripheral circuit region.

Next, as shown in FIG. 2, a low concentration impurity diffusion region 7 is formed. First, by an ion implantation method using the second gate electrode 6b as a mask, N-type impurities such as phosphorus are applied to the upper surface of the semiconductor substrate 1 in the peripheral circuit region at a concentration of 1 × 10 ^{13 to} 7 × 10 ¹³ cm ² . Introduce. The range of the impurity concentration of the low-concentration impurity diffusion region 7 mentioned here is an example, and the concentration outside this range may be used. Next, the N-type impurity is diffused by heat to form a low-concentration impurity diffusion region 7 around the second gate electrode 6b.

  Next, a third insulating film 9 made of silicon nitride having a film thickness of 30 nm to 40 nm is formed by CVD so as to cover the first gate electrode 6a, the second gate electrode 6b, and the gate insulating film 3.

  Next, as shown in FIG. 3, sidewalls (first sidewall 9a and second sidewall 9b) are formed. First, the third insulating film 9 is etched back, the upper surface of the first gate electrode 6a (first insulating film 5a), the upper surface of the second gate electrode 6b (second insulating film 5b), and the semiconductor substrate 1 The top surface is exposed. By this etch-back, the first sidewall 9a and the second sidewall 9b made of silicon nitride and having a thickness of 30 nm to 40 nm are respectively formed on the sidewalls of the first gate electrode 6a and the second gate electrode 6b. It is formed.

  Next, the gate insulating film 3 remaining on the upper surface of the semiconductor substrate 1 is removed by a wet etching process using dilute hydrofluoric acid.

  Next, the silicon layers (first silicon layer 10a and second silicon layer 10b) are formed on the upper surface of the semiconductor substrate 1 by selective epitaxial growth using the first sidewall 9a and the second sidewall 9b as a selective mask. Form. Here, the silicon layer formed in the memory cell region is the first silicon layer 10a, and the silicon layer formed on the peripheral circuit region (low-concentration impurity diffusion region 7) is the second silicon layer 10b.

Next, as shown in FIG. 4, a first impurity diffusion region 11 is formed in the memory cell region, and a second impurity diffusion region 12 is formed in the peripheral circuit region.
First, N-type impurities such as phosphorus are introduced into the first silicon layer 10a by ion implantation using the first gate electrode 6a and the first sidewall 9a as a mask.
Next, the impurities are diffused from the first silicon layer 10a into the semiconductor substrate 1 at a concentration of 5 × 10 ^{12 to} 5 × 10 ¹³ atoms / cm ² , and the impurities are diffused into the semiconductor substrate 1 below the first silicon layer 10a. One impurity diffusion region 11 is formed. The range of the impurity concentration of the first impurity diffusion region 11 shown here is an example, and the concentration outside this range may be used. The first impurity diffusion region 11 functions as a source / drain electrode of the first MOS transistor Tr1.
Thus, the first MOS transistor Tr1 is formed.

  At this time, it is possible to prevent the first impurity diffusion region 11 from spreading too much in the semiconductor substrate 1 by diffusing impurities into the semiconductor substrate 1 through the first silicon layer 10a. Therefore, it is possible to prevent the distance between the adjacent first impurity diffusion regions 11 from being reduced. For this reason, the shortening of the channel of the semiconductor device can be suppressed.

  The first region 10A composed of the first silicon layer 10a and the first impurity diffusion region 11 functions as a source / drain electrode of the first MOS transistor Tr1. Therefore, a part of the source region or the drain region (first silicon layer 10a) of the first MOS transistor Tr1 is stacked on the semiconductor substrate 1, and the short channel of the semiconductor device can be further suppressed. A region of the semiconductor substrate 1 adjacent to the first MOS transistor Tr1 via the gate insulating film 3 functions as a channel region of the first MOS transistor Tr1.

Next, an N-type impurity such as arsenic is introduced into the second silicon layer 10b by ion implantation using the second gate electrode 6b and the second sidewall 9b as a mask.
Next, the impurity is diffused from the second silicon layer 10b to the semiconductor substrate 1 at a concentration of × 10 ^{14 to} 5 × 10 ¹⁵ atoms / cm ² , and the second impurity is then added to the semiconductor substrate 1 below the second silicon layer 10b. The impurity diffusion region 12 is formed. Note that the impurity concentration range of the second impurity diffusion region 12 shown here is an example, and the impurity concentration may be outside this range as long as the impurity concentration is higher than that of the low concentration impurity diffusion region 7. By this impurity diffusion, the second impurity diffusion region 12 is formed in the formation region of the low-concentration impurity diffusion region 7. The second impurity diffusion region 12 functions as a source / drain electrode of the second MOS transistor Tr2, and the low concentration impurity diffusion region 7 functions as an LDD layer.
Thus, the second MOS transistor Tr2 is formed.

At this time, it is possible to prevent the second impurity diffusion region 12 from spreading too much in the semiconductor substrate 1 by diffusing impurities into the semiconductor substrate 1 via the second silicon layer 10b. Therefore, it is possible to prevent the distance between the adjacent second impurity diffusion regions 12 from being reduced. For this reason, the shortening of the channel of the semiconductor device can be suppressed.
Further, the short channel effect of the second MOS transistor Tr2 can be reduced by forming the second impurity diffusion region 12 after forming the low-concentration impurity diffusion region 7 to form the LDD structure.

  In addition, by diffusing impurities into the second silicon layer 10b, the second region 10B composed of the second silicon layer 10b and the second impurity diffusion region 12 becomes the source / drain electrode of the second MOS transistor Tr2. Function as. For this reason, a part of the source region or the drain region (second silicon layer 10b) of the second MOS transistor Tr2 is stacked on the semiconductor substrate 1, and the short channel of the semiconductor device can be suppressed. Note that a region of the semiconductor substrate 1 adjacent to the second MOS transistor Tr2 via the gate insulating film 3 functions as a channel region of the second MOS transistor Tr2.

  Next, the peripheral circuit region is covered with a mask. First, as shown in FIG. 5, a fourth insulating film 20 is formed so as to cover the semiconductor substrate 1, the element isolation 2 and the second MOS transistor Tr2 by, for example, the CVD method. At this time, the fourth insulating film 20 only needs to completely cover at least the peripheral circuit region, and may cover part or all of the memory cell region.

  Next, as shown in FIG. 6, the first MOS transistor Tr1 is exposed. First, using a photolithography method, a photoresist mask (not shown) is formed so as to cover the peripheral circuit region. At this time, if the photoresist mask does not cover the first MOS transistor Tr1, it may cover a part of the memory cell region.

Next, wet etching is performed using the photoresist mask as a mask to selectively remove the fourth insulating film 20.
For the wet etching at this time, for example, a chemical solution containing hydrofluoric acid (HF) can be used. In wet etching, it is desirable to appropriately control the time for performing wet etching so that the surface of the element isolation 2 is not excessively etched. By this wet etching, the fourth insulating film 20 is selectively removed, and a fourth insulating film 20b is formed.
After the wet etching, the photoresist mask is removed.

  As described above, the second MOS transistor Tr2 is covered with the fourth insulating film 20b, and the first MOS transistor Tr1 is exposed. At this time, the interval between the first sidewalls 9a of the adjacent first MOS transistors Tr1 is defined as D1.

Next, as shown in FIG. 7, the first sidewall 9a is thinned.
First, the side surface of the first sidewall 9a having a thickness of 30 nm to 40 nm is formed by wet etching using phosphoric acid (H ₃ PO ₄ ) heated to about 150 to 160 ° C. as a chemical solution using the fourth insulating film 20 b as a mask. For example, the first sidewall 9c having a thickness of 15 to 20 nm is formed.

  Here, the interval D2 between the adjacent first sidewalls 9c is larger than the interval D1 between the first sidewalls 9a. At this time, since the second MOS transistor Tr2 is covered with the fourth insulating film 20b, the second MOS transistor Tr2 is not affected by etching, and the film thickness remains 30 nm to 40 nm. Here, by using phosphoric acid as a chemical solution for wet etching, the first sidewall 9a made of silicon nitride is selectively thinned without etching the mask made of silicon oxide (fourth insulating film 20b). it can.

In thinning the first sidewall 9a, wet etching using phosphoric acid is preferable from the viewpoint of selectively etching silicon nitride, but silicon nitride using SF ₆ (sulfur hexafluoride) gas is preferable. Thinning by isotropic dry etching is also possible. When dry etching is used, for example, by mixing HBr gas or the like, the selectivity of silicon nitride can be improved and the first sidewall 9a can be thinned without damaging the silicon oxide.

  Further, the time required for wet etching or dry etching may be appropriately set according to the desired film thickness of the first sidewall 9c.

  Next, as shown in FIG. 8, a fifth insulating film 21 is formed. First, a fifth insulating film 21 made of silicon oxide or the like is formed with a thickness of, for example, about 600 nm so as to embed the first MOS transistor Tr1 and the fourth insulating film 20b. Next, the upper surface of the fifth insulating film 21 is planarized by CMP. At this time, the CMP conditions are adjusted so that the fourth insulating film 20b is not exposed.

  Next, as shown in FIG. 9, a contact plug 22 connected to the first silicon layer 10a is formed by self-alignment. First, a resist mask (not shown) is formed on the fifth insulating film 21 by photolithography. Next, etching is performed using the resist mask as a mask to form a contact hole 22a exposing the first region 10A (first silicon layer 10a). At this time, the pattern (diameter) of the photoresist contact hole 22a may be larger than the width D2. Even when the pattern (diameter) of the contact hole 22a is larger than the width D2, the contact hole 22a having the width D2 is formed between the adjacent first sidewalls 9c by self-alignment using the first sidewall 9c. This is because it can be formed between them.

  Next, a conductive film made of tungsten or the like is deposited so as to fill the contact hole 22 a and cover the upper surface of the fifth insulating film 21. Thereafter, the upper surface of the conductive film is polished by CMP until the fifth insulating film 21 is exposed. By this polishing, a contact plug 22 made of a conductive film filling the contact hole 22a is formed. Further, the contact plug 22 penetrates the fifth insulating film 21 and is connected to the first region 10A (first silicon layer 10a).

  Thereafter, a memory element and a bit wiring (not shown) are formed so as to be connected to each contact plug 22. Here, as the memory element, for example, when a DRAM is formed, a capacitor element can be exemplified. Thereafter, an interlayer insulating film (not shown), a contact plug (not shown) connected to the second MOS transistor Tr2, a wiring layer, and the like are formed, thereby completing the semiconductor device of this embodiment.

  According to the present invention, at least the peripheral circuit region is covered with a mask made of silicon oxide (fourth insulating film 20b) and etched, whereby the second MOS transistor (second MOS transistor Tr2) in the peripheral circuit region is etched. The first sidewall 9a of the MOS transistor (first MOS transistor Tr1) in the memory cell region can be thinned without changing the film thickness of the sidewall 9b.

  Further, by using phosphoric acid as an etching chemical, the first sidewall 9a made of silicon nitride can be selectively thinned without etching the mask made of silicon oxide (fourth insulating film 20b).

  For this reason, it is possible to suppress a reduction in the interval between the first sidewalls 9c of the adjacent first MOS transistors Tr1. For this reason, the contact plug 22 having a sufficiently large diameter (D2) can be formed between the adjacent first MOS transistors Tr1. For this reason, the connection resistance of the contact plug 22 can be suppressed. Further, since the film thickness of the second sidewall 9b of the second MOS transistor Tr2 is not changed, it is possible to prevent the second MOS transistor Tr2 from being shortened and the electrical characteristics from being deteriorated.

  As described above, optimization of the MOS transistors (first MOS transistor Tr1 and second MOS transistor Tr2) in both the memory cell region and the peripheral circuit region can be realized. In addition, since the reduction in the interval between the first sidewalls 9c can be suppressed, the interval between the first MOS transistors Tr1 can be reduced. For this reason, miniaturization of the semiconductor device can be realized.

  Further, by introducing impurities into the first silicon layer 10a and forming the contact plug 22 connected to the first silicon layer 10a, the first silicon layer 10a functions as a part of the contact plug 22. Can do. For this reason, the electrical resistance of the contact plug 22 can be reduced, and a decrease in the on-current of the first MOS transistor Tr1 can be suppressed.

  As described above, both the first MOS transistor Tr1 in the memory cell region and the second MOS transistor Tr2 in the peripheral circuit region can be optimized. Therefore, it is possible to realize miniaturization of the semiconductor device.

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Element isolation, 3 ... Gate insulating film, 4a ... 1st electrically conductive film, 4b ... 2nd electrically conductive film, 5a ... 1st insulating film, 5b ... 2nd insulating film, 6a ... 1st gate electrode, 6b ... 2nd gate electrode, 7 ... Low concentration impurity diffusion region, 9 ... 3rd insulating film, 9a ... 1st side wall, 9b ... 2nd side wall, 9c ... 1st 10a ... first silicon layer, 10b ... second silicon layer, 10A ... first region, 10B ... second region, 11 ... first impurity diffusion region, 12 ... second impurity diffusion. Regions 20, 20b ... fourth insulating film, 21 ... fifth insulating film, 22 ... contact plug, 22a ... contact hole, Tr1 ... first MOS transistor, Tr2 ... second MOS transistor, D1, D2 ... width

Claims (7)

A method of manufacturing a semiconductor device including a MOS transistor including a gate electrode having a sidewall on a side wall in a memory cell region and a peripheral circuit region on a semiconductor substrate,
After forming the sidewall,
A step of forming a silicon layer on the upper surface of the semiconductor substrate by selective epitaxial growth;
A method for manufacturing a semiconductor device, comprising: forming a silicon layer, covering at least the peripheral circuit region with a mask, and thinning a sidewall of a MOS transistor in the memory cell region by etching. The memory cell region includes a plurality of the MOS transistors,
After the step of thinning the sidewall,
2. The semiconductor according to claim 1, wherein a contact plug connected to the silicon layer by self-alignment is formed between the gate electrodes of the MOS transistors arranged adjacent to each other in the memory cell region. Device manufacturing method.   The method for manufacturing a semiconductor device according to claim 2, wherein the sidewall is made of silicon nitride.   The method of manufacturing a semiconductor device according to claim 3, wherein the mask is made of silicon oxide.   5. The method of manufacturing a semiconductor device according to claim 4, wherein the sidewall is thinned by wet etching using phosphoric acid. Before the step of covering the peripheral circuit region with a mask,
6. The method according to claim 1, further comprising the step of forming an impurity diffusion region to be a source / drain electrode of the MOS transistor by diffusing an impurity into the semiconductor substrate through the silicon layer. A manufacturing method of a semiconductor device given in any 1 paragraph. Before forming the silicon layer, a low concentration impurity diffusion region having a lower impurity concentration than the impurity diffusion region is formed in the peripheral circuit region,
7. The method of manufacturing a semiconductor device according to claim 6, wherein in the step of forming the impurity diffusion region, the impurity diffusion region is formed in the low concentration impurity diffusion region.

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