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JP2011129700A - Semiconductor device - Google Patents

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JP2011129700A
JP2011129700A JP2009286652A JP2009286652A JP2011129700A JP 2011129700 A JP2011129700 A JP 2011129700A JP 2009286652 A JP2009286652 A JP 2009286652A JP 2009286652 A JP2009286652 A JP 2009286652A JP 2011129700 A JP2011129700 A JP 2011129700A
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Junichi Matsuda
順一 松田
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Asahi Kasei Toko Power Devices Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To set a latchup voltage of a semiconductor device for ESD protection, using a latchup, to an arbitrary value. <P>SOLUTION: The semiconductor device 300 includes: a P-type substrate 301; an N type well region 302 formed on a surface of the P-type substrate 301; a P+ type diffusion region 303 and an N+ type diffusion region 304 on a surface of the N type well region 302; an oxide film 305 disposed on a boundary between the P type substrate 301 and N type well region 302; polysilicon 306 disposed on a part of the oxide film 305; and a P+ type diffusion region 307 and an N+ type diffusion region 308 on a surface of the P type substrate 301. A floating electrode 309 is disposed to be capacitively coupled to the polysilicon 306 and N type well region 302 respectively. The polysilicon 306 is grounded. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、半導体装置に関し、より詳細には、ＥＳＤ保護のための半導体装置に関する。   The present invention relates to a semiconductor device, and more particularly to a semiconductor device for ESD protection.

集積回路等を静電気放電（ＥＳＤ）によるサージ破壊から保護するための半導体装置が研究されている。たとえば、図１に示すものが挙げられる（非特許文献１参照）。半導体装置１００は、Ｐ型基板１０１と、Ｐ型基板１０１の表面に形成されたＮ型ウェル領域１０２と、Ｎ型ウェル領域１０２の表面上のＰ＋型拡散領域１０３及びＮ＋型拡散領域１０４と、Ｐ型基板１０１とＮ型ウェル領域１０２との境界上に配置された酸化膜１０５と、酸化膜１０５上のポリＳｉ１０６と、Ｐ型基板１０１の表面上のＰ＋型拡散領域１０７及びＮ＋型拡散領域１０８とを備える。   Semiconductor devices for protecting integrated circuits and the like from surge breakdown due to electrostatic discharge (ESD) have been studied. For example, what is shown in FIG. 1 is mentioned (refer nonpatent literature 1). The semiconductor device 100 includes a P-type substrate 101, an N-type well region 102 formed on the surface of the P-type substrate 101, a P + type diffusion region 103 and an N + type diffusion region 104 on the surface of the N-type well region 102, The oxide film 105 disposed on the boundary between the P-type substrate 101 and the N-type well region 102, the poly-Si 106 on the oxide film 105, the P + type diffusion region 107 and the N + type diffusion region on the surface of the P-type substrate 101 108.

第１のＰ＋型拡散領域１０３、Ｎ型ウェル領域１０２及びＰ型基板１０１が寄生ＰＮＰバイポーラトランジスタを形成し、Ｎ型ウェル領域１０２、Ｐ型基板１０１及びＮ＋型拡散領域１０８が寄生ＮＰＮバイポーラトランジスタを形成し、寄生ＰＮＰバイポーラトランジスタ及び寄生ＮＰＮバイポーラトランジスタがサイリスタを構成する。   The first P + type diffusion region 103, the N type well region 102 and the P type substrate 101 form a parasitic PNP bipolar transistor, and the N type well region 102, the P type substrate 101 and the N + type diffusion region 108 form a parasitic NPN bipolar transistor. The parasitic PNP bipolar transistor and the parasitic NPN bipolar transistor form a thyristor.

図１に記載されたＥＳＤ保護回路の動作原理は以下の通りである。
＜１＞通常動作電圧より高い電圧が印加電圧ＶCCとして印加されると、Ｎ型ウェル領域１０２とＰ型基板１０１との間に形成される空乏層内の電界は、酸化膜１０５上に設置されたポリＳｉ１０６により酸化膜１０５下近傍で高くなり、ポリＳｉ１０６がない場合よりも低い電圧でアバランシェ破壊を引き起こす。ここで、「通常動作電圧」とは、集積回路が正常に機能動作する電圧を意味する。
＜２−１＞アバランシェ破壊による電流（正孔）は、Ｐ型基板１０１のＰ＋型拡散領域１０７へ流れる（電流経路（１））。
＜２−２＞この電流がＰ型基板１０１内の抵抗（ＲPSUB）により電圧降下を発生させ、Ｐ型基板１０１内にある寄生ＮＰＮトランジスタのエミッタ／ベース間を順方向にバイアスする。
＜２−３＞この順方向バイアスにより、ＮＰＮトランジスタのベース電流が流れ始める。これによりコレクタ電流（電子）が流れる（電流経路（２））。
＜２−４＞このコレクタ電流はＮ型ウェル領域１０２内を流れ、Ｎ型ウェル領域内の抵抗（ＲNWell）により電圧降下を発生させる。
＜２−５＞この電圧降下が、Ｎ型ウェル領域１０２内にある寄生ＰＮＰトランジスタのエミッタ／ベース間を順方向にバイアスするので、ベース電流が流れ始める。これによりコレクタ電流（正孔）が流れる（電流経路（３））。
＜２−６＞このコレクタ電流がＰ型基板１０１内の電圧降下を更に上昇させ、ＮＰＮトランジスタのベース電流を増大させる。これにより正帰還動作に入る。Ｐ型基板１０１内の電圧降下がＰ型基板１０１内のＮ+／Ｐ基板間のビルトイン電圧ＶBISUBを超えた場合、またはＮ型ウェル領域１０２内の電圧降下がＮ型ウェル領域１０２内のＰ+／Ｎウェル間のビルトイン電圧ＶBIWellを超えた場合にラッチアップに至る。
＜３−１＞一方、アバランシェ破壊による電流（電子）は、Ｎウェル内のＮ+型拡散領域１０４（ＶCC）へも流れる（電流経路（１’））。
＜３−２＞この電流が上記＜２−４＞の電圧降下を更に増大させ、正帰還動作を加速する。つまり、アバランシェ破壊で発生した正孔電流と電子電流は、ともに正帰還する様に働いてラッチアップを起こす。 The operating principle of the ESD protection circuit described in FIG. 1 is as follows.
<1> When a voltage higher than the normal operating voltage is applied as the applied voltage V CC , an electric field in a depletion layer formed between the N-type well region 102 and the P-type substrate 101 is set on the oxide film 105. Due to the poly Si 106 thus formed, it becomes higher near the oxide film 105 and causes avalanche breakdown at a lower voltage than when there is no poly Si 106. Here, the “normal operating voltage” means a voltage at which the integrated circuit functions normally.
<2-1> A current (hole) due to avalanche breakdown flows to the P + type diffusion region 107 of the P type substrate 101 (current path (1)).
<2-2> This current causes a voltage drop due to the resistance (R PSUB ) in the P-type substrate 101, and the emitter / base of the parasitic NPN transistor in the P-type substrate 101 is biased in the forward direction.
<2-3> Due to this forward bias, the base current of the NPN transistor starts to flow. As a result, collector current (electrons) flows (current path (2)).
<2-4> This collector current flows in the N-type well region 102, and a voltage drop is generated by the resistance (R NWell ) in the N-type well region.
<2-5> Since this voltage drop biases the emitter / base of the parasitic PNP transistor in the N-type well region 102 in the forward direction, the base current starts to flow. Thereby, collector current (hole) flows (current path (3)).
<2-6> This collector current further increases the voltage drop in the P-type substrate 101 and increases the base current of the NPN transistor. As a result, a positive feedback operation starts. When the voltage drop in the P-type substrate 101 exceeds the built-in voltage V BISUB between the N + / P substrates in the P-type substrate 101, or the voltage drop in the N-type well region 102 becomes P in the N-type well region 102. When the built-in voltage V BIWell between + / N well is exceeded, latch-up is reached.
<3-1> On the other hand, current (electrons) due to avalanche breakdown also flows to the N + type diffusion region 104 (V CC ) in the N well (current path (1 ′)).
<3-2> This current further increases the voltage drop of <2-4> and accelerates the positive feedback operation. In other words, the hole current and the electron current generated by avalanche breakdown both act as positive feedback and cause latch-up.

小括すると、非特許文献１に記載されたＥＳＤ保護回路は、酸化膜上にポリＳｉを設置することにより、ポリＳｉが設置されないものに比べて低い電圧でアバランシェ破壊を引き起こすことにより、ラッチアップを発生させ、集積回路等をＥＳＤから保護することを可能にするものである。   In summary, the ESD protection circuit described in Non-Patent Document 1 is latch-up by causing avalanche breakdown at a lower voltage than that without poly-Si by placing poly-Si on the oxide film. And the integrated circuit or the like can be protected from ESD.

C. Duvvury, J. Rodriguez, C. Jones, and M. Smayling, ‘‘Device Integration for ESD Robustness of High Voltage Power MOSFETs,’’ IEDM Technical Digest, 1994, pp. 407-410C. Duvvury, J. Rodriguez, C. Jones, and M. Smayling, ‘‘ Device Integration for ESD Robustness of High Voltage Power MOSFETs, ’IEDM Technical Digest, 1994, pp. 407-410

しかしながら、図１に示す従来の半導体装置等では、高耐圧素子のＥＳＤ保護を十分に行うことができない。通常動作電圧としての印加電圧ＶccがＮ型ウェル領域１０２の反転電圧よりも高い場合、Ｎ型ウェル領域１０２のポリＳｉ１０６の下部分において通常動作電圧範囲でも反転が生じ、ラッチアップ動作に入ってしまうからである。 However, the conventional semiconductor device or the like shown in FIG. 1 cannot sufficiently perform ESD protection of the high breakdown voltage element. When the applied voltage V cc as the normal operation voltage is higher than the inversion voltage of the N-type well region 102, inversion occurs in the normal operation voltage range in the lower portion of the poly-Si 106 in the N-type well region 102, and the latch-up operation starts. Because it ends up.

本発明はこのような問題点に鑑みてなされたものであり、その目的は、素子への印加電圧Ｖccに応じて適当にラッチアップを発生させることによるＥＳＤ保護のための半導体装置を提供することにある。 The present invention has been made in view of such problems, and an object of the present invention is to provide a semiconductor device for ESD protection by appropriately generating latch-up according to the voltage Vcc applied to the element. There is.

このような目的を達成するために、本発明の第１の態様は、第２の導電型の基板と、前記第２の導電型の基板表面に形成された第１の導電型のウェル領域と、前記第１の導電型のウェル領域の表面上の第１及び第２の拡散領域と、前記第２の導電型の基板と前記第１の導電型のウェル領域との境界上に配置された酸化膜と、前記酸化膜の一部の上に配置された第１の電極と、前記第２の導電型の基板の表面上の第３及び第４の拡散領域と、前記第１の電極及び前記第１の導電型のウェル領域とそれぞれ容量結合するように配置された第２の電極とを備え、前記第１の電極は接地され、前記第１及び第３の拡散領域は第２の導電型であり、前記第２及び第４の拡散領域は第１の導電型であることを特徴とする半導体装置である。   In order to achieve such an object, a first aspect of the present invention includes a second conductivity type substrate, a first conductivity type well region formed on the surface of the second conductivity type substrate, and , Disposed on the boundary between the first and second diffusion regions on the surface of the first conductivity type well region, the second conductivity type substrate and the first conductivity type well region. An oxide film; a first electrode disposed on a portion of the oxide film; third and fourth diffusion regions on a surface of the second conductivity type substrate; the first electrode; A second electrode disposed so as to be capacitively coupled to the first conductivity type well region, the first electrode being grounded, and the first and third diffusion regions being a second conductive material. The semiconductor device is characterized in that the second and fourth diffusion regions are of the first conductivity type.

また、本発明の第２の態様は、第１の態様において、前記第２の電極と前記第１の電極および前記第１の導電型のウェル領域との間の容量結合の容量結合比は、通常動作電圧範囲において前記第２の電極と前記第１の導電型のウェル領域との間にかかる電圧が前記第１の導電型のウェル領域の反転電圧以下になるように設定されていることを特徴とする。   According to a second aspect of the present invention, in the first aspect, the capacitive coupling ratio of the capacitive coupling between the second electrode and the first electrode and the first conductivity type well region is as follows: The voltage applied between the second electrode and the first conductivity type well region in a normal operating voltage range is set to be equal to or lower than the inversion voltage of the first conductivity type well region. Features.

また、本発明の第３の態様は、第１の態様において、Ｖcc配線が前記第２の電極と容量結合するように配置されたことを特徴とする。 According to a third aspect of the present invention, in the first aspect, the Vcc wiring is disposed so as to be capacitively coupled to the second electrode.

また、本発明の第４の態様は、第１から第３のいずれかの態様において、前記半導体装置の平面図において、第１の電極と第１の導電型のウェル領域とが重複する領域が存在することを特徴とする。   According to a fourth aspect of the present invention, in any one of the first to third aspects, in the plan view of the semiconductor device, there is a region where the first electrode and the first conductivity type well region overlap. It is characterized by the existence.

本発明によれば、第１の電極および第１の導電型のウェル領域とそれぞれ容量結合するように配置された第２の電極を設けることにより、素子への印加電圧に応じて通常動作電圧範囲内ではラッチアップが発生せず、通常動作電圧を超えた場合にラッチアップを発生させることを可能にする。   According to the present invention, by providing the second electrode disposed so as to be capacitively coupled to the first electrode and the first conductivity type well region, the normal operating voltage range according to the voltage applied to the element. Latch-up does not occur in the circuit, and latch-up can be generated when the normal operating voltage is exceeded.

従来のＥＳＤ保護のための半導体装置およびラッチアップ動作を説明するための断面図である。It is sectional drawing for demonstrating the conventional semiconductor device and latch-up operation | movement for ESD protection. 本発明の第１の実施形態によるＥＳＤ保護のための半導体装置を示す断面図である。1 is a cross-sectional view showing a semiconductor device for ESD protection according to a first embodiment of the present invention. 本発明の第１の実施形態によるＥＳＤ保護のための半導体装置を示す平面図である。1 is a plan view showing a semiconductor device for ESD protection according to a first embodiment of the present invention; 本発明の第２の実施形態によるＥＳＤ保護のための半導体装置を示す図である。FIG. 6 is a diagram illustrating a semiconductor device for ESD protection according to a second embodiment of the present invention.

以下、図面を参照して本発明の実施形態を詳細に説明する。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

（第１の実施形態）
図２は、第１の実施形態によるＥＳＤ保護のための半導体装置を示す図である。半導体装置３００は、Ｐ型基板３０１と、Ｐ型基板３０１の表面に形成されたＮ型ウェル領域３０２と、Ｎ型ウェル領域３０２の表面上のＰ＋型拡散領域３０３及びＮ＋型拡散領域３０４と、Ｐ型基板３０１とＮ型ウェル領域３０２との境界上に配置された酸化膜３０５と、酸化膜３０５の一部の上に配置されたポリＳｉ３０６と、Ｐ型基板３０１の表面上のＰ＋型拡散領域３０７及びＮ＋型拡散領域３０８とを備える。フローティング電極３０９は、ポリＳｉ３０６及びＮ型ウェル領域３０２とそれぞれ容量結合するように配置されている。ポリＳｉ３０６は接地されている。Ｐ型基板３０１の表面の反転を防止するために酸化膜３０５の一部の上にのみポリＳｉ３０６が配置されている。図３は、本実施形態の半導体装置の平面図であり、図２はＡ−Ａ線に沿った図３の断面図である。 (First embodiment)
FIG. 2 is a diagram illustrating a semiconductor device for ESD protection according to the first embodiment. The semiconductor device 300 includes a P-type substrate 301, an N-type well region 302 formed on the surface of the P-type substrate 301, a P + type diffusion region 303 and an N + type diffusion region 304 on the surface of the N-type well region 302, An oxide film 305 disposed on the boundary between the P-type substrate 301 and the N-type well region 302, poly Si 306 disposed on a part of the oxide film 305, and P + type diffusion on the surface of the P-type substrate 301 A region 307 and an N + type diffusion region 308 are provided. The floating electrode 309 is disposed so as to be capacitively coupled to the poly Si 306 and the N-type well region 302, respectively. The poly Si 306 is grounded. In order to prevent the surface of the P-type substrate 301 from being inverted, the poly-Si 306 is disposed only on part of the oxide film 305. FIG. 3 is a plan view of the semiconductor device of this embodiment, and FIG. 2 is a cross-sectional view of FIG. 3 taken along the line AA.

フローティング電極３０９について詳述する。フローティング電極３０９と、ポリＳｉ３０６及びＮ型ウェル領域３０２との間の静電容量をそれぞれＣ1及びＣ2とすると、フローティング電極３０９と、ポリＳｉ３０６及びＮ型ウェル領域３０２との間の電圧Ｖ1及びＶ2はそれぞれ次式で表される。 The floating electrode 309 will be described in detail. Assuming that the capacitance between the floating electrode 309 and the poly-Si 306 and the N-type well region 302 is C 1 and C 2 , respectively, the voltage V 1 between the floating electrode 309 and the poly-Si 306 and the N-type well region 302 is V 1. And V 2 are respectively represented by the following equations.

Figure 2011129700
Figure 2011129700

Figure 2011129700
Figure 2011129700

ここで、Ｖccは第１のＰ＋型拡散領域３０３及び第１のＮ＋型拡散領域３０４への印加電圧である。静電容量Ｃ1及びＣ2は、フローティング電極３０９の大きさと、フローティング電極３０９とポリＳｉ３０６とのオーバーラップ（図３参照）に依存するパラメーターである。フローティング電極３０９の形成は、ポリＳｉ３０６が設けられるレイヤーとは異なるレイヤーに適当な大きさの金属領域を設けることにより行うことができる。したがって、いずれのレイヤーにフローティング電極３０９を形成するかによってフローティング電極３０９とポリＳｉ３０６及びＮ型ウェル領域３０２との間の距離が異なり、これも静電容量Ｃ1及びＣ2に影響を与える。 Here, V cc is a voltage applied to the first P + type diffusion region 303 and the first N + type diffusion region 304. Capacitances C 1 and C 2 are parameters that depend on the size of the floating electrode 309 and the overlap between the floating electrode 309 and the poly-Si 306 (see FIG. 3). The floating electrode 309 can be formed by providing a metal region having an appropriate size in a layer different from the layer in which the poly-Si 306 is provided. Accordingly, the distance between the floating electrode 309 and the poly-Si 306 and the N-type well region 302 differs depending on which layer the floating electrode 309 is formed on, and this also affects the capacitances C 1 and C 2 .

ここで、通常動作電圧範囲内としての印加電圧Ｖccが１５０Ｖの場合を考える。図１に示した従来のＥＳＤ保護のための半導体装置では、Ｎ型ウェル領域３０２の反転電圧が例えば４０Ｖであると、酸化膜３０５下において反転が生じてしまい、通常動作電圧範囲内でもラッチアップが発生してしまう。しかし、例えばＶ1＝１２０Ｖ、Ｖ2＝３０Ｖとなるように容量結合比Ｃ1／Ｃ2を設定してフローティング電極３０９を設けると、フローティング電極３０９とＮ型ウェル領域３０２との間にかかる電圧をＮ型ウェル領域３０２の反転電圧以下に抑えることができ、通常動作電圧範囲内でのラッチアップが発生しない。したがって、容量結合比Ｃ1／Ｃ2を変えることによりラッチアップ発生電圧を自在に制御することができる。 Here, consider a case where the applied voltage V cc is 150 V within the normal operating voltage range. In the conventional semiconductor device for ESD protection shown in FIG. 1, when the inversion voltage of the N-type well region 302 is 40 V, for example, inversion occurs under the oxide film 305, and latch-up is performed even within the normal operating voltage range. Will occur. However, if the floating electrode 309 is provided with the capacitive coupling ratio C 1 / C 2 set such that V 1 = 120 V and V 2 = 30 V, for example, the voltage applied between the floating electrode 309 and the N-type well region 302 Can be suppressed below the inversion voltage of the N-type well region 302, and latch-up does not occur within the normal operating voltage range. Therefore, the latch-up generation voltage can be freely controlled by changing the capacitive coupling ratio C 1 / C 2 .

（第２の実施形態）
図４は、第２の実施形態によるＥＳＤ保護のための半導体装置を示す図である。半導体装置４００は、第１の実施形態の半導体装置３００と概ね同一であるが、Ｖcc配線４１０がフローティング電極３０９と容量結合している点が異なる。 (Second Embodiment)
FIG. 4 is a diagram illustrating a semiconductor device for ESD protection according to the second embodiment. The semiconductor device 400 is substantially the same as the semiconductor device 300 of the first embodiment, except that the Vcc wiring 410 is capacitively coupled to the floating electrode 309.

Ｖcc配線４１０がフローティング電極３０９と容量結合すると、静電容量Ｃ2の実効容量がＣ2＋Ｃ3に増加し、フローティング電極３０９とＮ型ウェル領域３０２との間の電圧Ｖ2を低減することができる。したがって、印加電圧Ｖccがより高電圧になっても電圧Ｖ2を反転電圧以下に抑えることができ、高耐圧化が図れる。 When the V cc wiring 410 is capacitively coupled to the floating electrode 309, the effective capacitance of the capacitance C 2 increases to C 2 + C 3 , and the voltage V 2 between the floating electrode 309 and the N-type well region 302 is reduced. Can do. Therefore, even when the applied voltage V cc becomes higher, the voltage V 2 can be suppressed to the inversion voltage or less, and a high breakdown voltage can be achieved.

加えて、当該容量結合により、ノイズによる本ＥＳＤ保護装置の誤動作を抑えることができる。Ｖcc配線４１０がフローティング電極３０９を静電シールドし、それによりフローティング電極３０９が他からのノイズの影響を受け難いからである。 In addition, the capacitive coupling can suppress malfunction of the ESD protection device due to noise. This is because the Vcc wiring 410 electrostatically shields the floating electrode 309 so that the floating electrode 309 is hardly affected by noise from others.

３００ 半導体装置
３０１ Ｐ型基板（「第２の導電型の基板」に対応）
３０２ Ｎ型ウェル領域（「第１の導電型のウェル領域」に対応）
３０３ 第１のＰ＋型拡散領域（「第１の拡散領域」に対応）
３０４ 第１のＮ＋型拡散領域（「第２の拡散領域」に対応）
３０５ 酸化膜
３０６ ポリＳｉ （「第１の電極」に対応）
３０７ 第２のＰ＋型拡散領域（「第３の拡散領域」に対応）
３０８ 第２のＮ＋型拡散領域（「第４の拡散領域」に対応）
３０９ フローティング電極（「第２の電極」に対応）
４００ 半導体装置
４１０ Ｖcc配線 300 Semiconductor device 301 P-type substrate (corresponding to “second conductivity type substrate”)
302 N-type well region (corresponding to “well region of first conductivity type”)
303 first P + type diffusion region (corresponding to “first diffusion region”)
304 First N + type diffusion region (corresponding to “second diffusion region”)
305 Oxide film 306 Poly-Si (corresponding to “first electrode”)
307 Second P + type diffusion region (corresponding to “third diffusion region”)
308 Second N + type diffusion region (corresponding to “fourth diffusion region”)
309 Floating electrode (corresponding to “second electrode”)
400 Semiconductor device 410 V cc wiring

Claims (4)

第２の導電型の基板と、
前記第２の導電型の基板表面に形成された第１の導電型のウェル領域と、
前記第１の導電型のウェル領域の表面上の第１及び第２の拡散領域と、
前記第２の導電型の基板と前記第１の導電型のウェル領域との境界上に配置された酸化膜と、
前記酸化膜の一部の上に配置された第１の電極と、
前記第２の導電型の基板の表面上の第３及び第４の拡散領域と、
前記第１の電極及び前記第１の導電型のウェル領域とそれぞれ容量結合するように配置された第２の電極と
を備え、
前記第１の電極は接地され、前記第１及び第３の拡散領域は第２の導電型であり、前記第２及び第４の拡散領域は第１の導電型であることを特徴とする半導体装置。 A second conductivity type substrate;
A first conductivity type well region formed on the surface of the second conductivity type substrate;
First and second diffusion regions on the surface of the well region of the first conductivity type;
An oxide film disposed on a boundary between the substrate of the second conductivity type and the well region of the first conductivity type;
A first electrode disposed on a portion of the oxide film;
Third and fourth diffusion regions on the surface of the substrate of the second conductivity type;
A second electrode disposed so as to be capacitively coupled to the first electrode and the well region of the first conductivity type, respectively.
The first electrode is grounded, the first and third diffusion regions are of a second conductivity type, and the second and fourth diffusion regions are of a first conductivity type. apparatus. 前記第２の電極と前記第１の電極および前記第１の導電型のウェル領域との間の容量結合の容量結合比は、通常動作電圧範囲内では前記第２の電極と前記第１の導電型のウェル領域との間にかかる電圧が前記第１の導電型のウェル領域の反転電圧以下になるように設定されていることを特徴とする請求項１に記載の半導体装置。   A capacitive coupling ratio of capacitive coupling between the second electrode, the first electrode, and the first conductivity type well region is such that the second electrode and the first conductivity are within a normal operating voltage range. 2. The semiconductor device according to claim 1, wherein a voltage applied to a well region of a type is set to be equal to or lower than an inversion voltage of the well region of the first conductivity type. Ｖcc配線が前記第２の電極と容量結合するように配置されたことを特徴とする請求項１に記載の半導体装置。 2. The semiconductor device according to claim 1, wherein a Vcc wiring is disposed so as to be capacitively coupled to the second electrode. 前記半導体装置の平面図において、第１の電極と第１の導電型のウェル領域とが重複する領域が存在することを特徴とする請求項１から３のいずれかに記載の半導体装置。   4. The semiconductor device according to claim 1, wherein in the plan view of the semiconductor device, there is a region where the first electrode and the well region of the first conductivity type overlap each other.
JP2009286652A 2009-12-17 2009-12-17 Semiconductor device Withdrawn JP2011129700A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110828426A (en) * 2018-08-10 2020-02-21 世界先进积体电路股份有限公司 Semiconductor structure and electrostatic protection device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110828426A (en) * 2018-08-10 2020-02-21 世界先进积体电路股份有限公司 Semiconductor structure and electrostatic protection device
CN110828426B (en) * 2018-08-10 2024-03-05 世界先进积体电路股份有限公司 Semiconductor structures and electrostatic protection devices

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